Architecture: TMS320C54x
Architecture: TMS320C54x
Architecture: TMS320C54x
Emulator interrupt
pin/disable all outputs
11.4.2 Architecture of
TMS320C54x Processors
The TMSS200>Nprocessors employ an
advanced. modified Harvard architecture
essing power by providing tour pairs of separate bus
proc
rOgram mory. The 4 pairs or S'internal buses of stnuctures three nairs for data memory a
for program mem
TMS320C54x processors
rocessors are.
PB Program Bus
PAB Program Address BusTogram memory bus to read opcode and immediate operana
CB CBus
CAB C Address Bus Two independent data memory buses to Havvoa
DB:DBus read two data
simultaneously from memory
DAB D Address Bus
EB E Bus
Data memory bus to write data in data memory
EAB E Address Bus
n 1MS520C54x processors, the separate program and data memory spaces allow simultaneous access
to program instructions and data, providing a high degree of parallelism. For example. two read and one write
operations can be performed in a single cycle. Special instructions with parallel load/store and multipiy
accumulate fully utilize this architecture. In addition, data can be transferred between data and program
memory spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations
that can be performed in a single machine cycle. In addition, the TM$320C54x processors include the control
mechanisms to manage interrupts repeated operations and function calls.
The simplified internal architecture of TMS320C54xprocessor is shown in fig 11.14. The architectue
can be broadly divided into three major areas. They are CPU (Central Processing Unit), on-chip memory unit
and on-chip peripherals.
The functional units ofCPU are 40-bit ALU (Arithmetic Logic Unit), two numbers of 40-bit accumulators
(ACCA and ACCB), barrel shifter, 17x 17-bit multiplier, 40-bit adder, CSSU (Compare, Select and Store Unit)
exponent encoder, status registers, data address generation unit, program address generation unit and system
control interface.
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38
m--f--
p
Chapter 11 -Digital Signal Processors
.Barrelshifter 11. 52
. 17x17-bitmultiplier
.40-bitadder
. Compare, Select and Store Unit (CSSU)
.Exponentencoder
.Data address generation unit
Program address generation unit
Accumulators
The CPU has two 40-bit accumulators referred to as accumulator A (ACCA) and accumulator
B(ACCB). The accumulators can act as source/destination for the ALU and the multiplier/adder. Also, any
of the accumulators can be used as temporary storage for the other.
Barrel Shifter
The 40-bit barrel shifter can perform 0 to 31 bits left shift, 0 to 16 bits right shit and along with
exponent encoder can normalize the accumulator content. The shift informations are specified in the shift
cOunt field of the instruction, the shift count field of status register I or in T-register. The shift and normalize
operations of barrel shifter can be used to realize the following operations.
before an ALU operation
Prescaling of the memory/accumulator operand
value
Logical or arithmetic shifting of accumulator
Normalizing the accunmulator
in memory
Postscaling the accumulator before storing
Digital Signal PrOCessng
11. 53
buses (DB and
16-biv32-biv40-bit onerands which are input from data
Shifter can handle
CB buses) or from accumulators. The output ofshifter can be loaded in ALU or bus.
Multiplier/Adder
unit consists of 17 17-bit multiplier, 40-bit adder, signed/unsigned input control
ne muiplier/adder x
The inputs to CSSU for comparision are from accumulator and the output is stored in data memory.
The status of comparision is also stored in LSB of TRN register and TC bit of status register 0.
Exponent Encoder
For implementation of floating
point arithmetic in fixed point processors like TMS320C54x, require
separation of exponent and mantissa of the floating point data.
The exponent encoder is an
application-specific hardware device dedicated to extract the exponent
value from floating point data in the accumulators
and store in T-register.
The "EXPsrc" instruction is used to extract the
exponent and save in T-register. The "NORM src, dst"
instruction is used to normalize the accumulator
using the exponent in T-register as count value.
Data Address Generation Unit
RESET
BIT NAME VALUE FUNCTIOON
to select AR for indirect addressing
15-13 ARP Auxiliary register pointer
stores the results of ALU test bit operations
12 TC Test/control flag bit which
indicates a carry or borrow in ALU operation
11 C Carry bit which
Indicates an overtlow in ALU operation with destination as ACCA
10 OVA Overflow flag for ACCA.
Overflow flag for ACCB. Indicales an overilow in ALU operation with destination as ACCB
OVB
pointer to specity the current data memory page
8-0 Data-memory page
DP
15 14 13 12 11 10 9 87 6 432
DP
ARP
T oVAov
Fig 11.15: Format of status register 0 (STO) of TMS320C54xprocessor
10 0 Always 0
5 CMPT Compatibility mode bit. Determines the compatibility mode for the ARP
15 14 13 12 11 10 9
8 76 5 210
BRAF CPL XF HM
INTM oVM SxM cis FRCT CMPT ASM
14 E T Temporary register
15 F TRN Transition register
Auxiliary register 0 - Auxiliary register 7
16-23 10-17 ARO-AR7
24 18 SP Stack pointer
31 IF Reserved
TMS320C54x Processors
11.4.4 On-Chip Memory in and they
consists of three different types of on-chip memory
The TMS320C54x family of processors Dual-Access RAM (DARAM). The various
Single-Access RAM (SARAM) and
are mask-programmable ROM, which are listed in table I1.21.
will have different capacity on-chip memory
of
members of TMS320C54x
11. 57
iharwivnviurerennsrd
On-chip ROM
2k to 48k words.
TMS320C54x have internal maskable ROM ofsize
The various models of processors
and in some processors
In majority of the processors, the
on-chipROM is mapped to program-memory space
or excluding
a part of ROM can be mapped to data-memory space.
The processor has an option for including
address space.
the on-chip ROM addresses in the processor program memory
store the program code and
data for a specific
The main purpose of internal ROM is to permanently the content
The processor has an option of boot loading
application during manufacturing of the chip itself. ROM can be
ROM to internal/extermal RAM during power-ON reset. The content of the on-chip
of on-chip
to the program code. This feature provide security
protected so that any external device cannot have access
for proprietary algorithms.
On-chip DARAM
The TMS320C54x family of processors has 5k to 10k words of on-chip DARAM which are organized
into blocks as shown below.
.TMS320C541 :Sk words organized as 5 blocks ofIk words each
The TMS320C548/549 processors has 24k words of on-chip SARAM which are organized as three
blocks of 8k words. Upon reset, the SARAM is mapped to data memory space and after reset the processor
has provision to map the SARAM into program memory space.
11.4.5 On-Chip Peripberals of TMS320C54x Processors
The various on-chip peripherals available in TMS320C54x family of processors are,
Software-programmable wait-state generator
Programmable bank switching
Parallel 1Oports
Chapter
-
11. 58
DMA controller
.HostPort Interface (HPI)
.Serial ports (Standard, TDM, BSP and McBSP)
.General purpose 1O pins
Timer
The
multichannel byffered serialport
(McBSP) is an enhanced buffered serial
port can that support
multichannel transmit and receive up to 128 channels. The advanced features ofMcBSP are wide data sizes
from8-bit to 32-bit, p-law and A-law companding and programmable internal clock and frame synchronization.
Genera-Purpose 10 Pins
TheTMS320C54x family of processors has two general-purpose 1O pins and they are branch control
input pin, BIO and external flag output pin, XF.
The BIO pin can be used to monitor the status of peripheral devices. A branch instruction can be
conditionally executed depending upon the state ofthe BlIO input. The BIO pin is an alternative to interrupt,
when the interrupts are dedicated to time-critical applications.
The XF pin can be used to signal external devices. The XF pin is controlled using software. At reset
the XF pin is set high. The SSBX instruction is used to set XF pin and RSBX instruction is used to reset XF
pin.
Timer
The on-chip timer in TMS320C54x processors is a 16-bit timer with a4-bit
prescaler. The tùmer can be
used to initiate any time-based event through interrupt. The timer has a count
register, which is loaded with
a count value and at every clock cycle the timer count is decremented
by 1. At the end of the count an
interrupt is generated. The timer has a control register to control its operations like start, stop, restart and
disable.
4.6 Addressing
The addressing mode refer to the method of
ction, The
instruction. The TMS320C54x
specifying the operand or the data to be operated by the
processors supports the following seven
addressing modes.
1 Immediate addressing
2 Absolute addressing
3 Accumulator addressing (
4. Direct addressing v)
S. Indirect addressing
6. Memory-mapped register addressing
7. Stack addressing
Example
LD #1Ch, ASM ;Load the immediate 5-bit constant (ICh) in ASM ield of status register1
LD # 12Ah, DP :Load the immediate 9-bit constant (12Ah) in DP field of status register 0
LD#37A5h, 16,A Shift the long immediate (16-bit) constant by 16-bit and load in accumulator A
Absolute Addressing
In absolute addressing, the 16-bit address ofthe operand is directly specified in the instruction. This
addressing can be used to address an operand in all the three address spaces of the processor (ie., address
anoperand in program memory, data memory and IO ports). Inthe instruction listed in table 11.22, the syntax
used for absolute addrsssing are pmad, dmad and PA. In assembly language programs, the l6-bit address is
specified as a 16-bit constant without # symbol.
Example
MVKD SF3Bh, "AR2 Movethe data from data memory addressed by the instruction (address =5F38h
to anotherdata memory localion addressed by AR2
MVPD 3FCAh, "AR4 Move the data from program memory addressed by the instruction
(address 3FCAh} to data memory location addressed by AR4
=
Move the data from the l0 port addressed by the instruction (address = 7C20h)
PORTR 7C20h, *ARI
to data memory location addressed by ARI
Accumulator Addressing
In accumulator addressing, the content of accumulator is the address of the operand/data in program
memory.
11.61 Digital Signal Processing
Example:
EADA AR3 : Read the content of program memory addressed by accumulator A and store in data
Example:
ADD 6Ch, A Add the content of memory directly addressed by the instruction laddress - 6Ch)tothe
:accumulator A
57h) from the
SUB 57h, B Subtract the content of memory directily addressed by the instruction laddress =
:accumulatorB
Indirect Addressing
In the indirect addressing mode, the data memory address is specified by the content of one of the
the data
eight auxiliary registers, ARO-AR7. The AR (Auxiliary Register) currently used for accessing
is
operand is fetched. The syntax used for modifying the content of AR are listed in table 11.21.
In the instruction set listed in table 11.22, the syntax used to represent indirect addressing is Smem
Xmem/Ymem. In the assembly language programs, the syntax listed in table 11.21 are used.
SYNTAX MODIFICATION OF AR
ARx AR unaltered
Example
LD AR3, A Load the content of
memory addressed by AR3 in accumulator A
LD AR3- A Same as above, but after
loading decrement AR3
LD AR3+ A Same as above, but after
loading increment AR3
LD AR3-0, A Same as above, but
after loading decrement AR3 using ARO
LD AR3+0, A Same as above, but after
loading increment AR3 ARO using
Memory-Mapped Register Addressing
In memory-mapped register addressing, the address of the memory-mapped register is specified as
direct or indirect address in the instruction.
The memory-mapped registers are mapped to page-0 of data memory address and so can be accessed
by using only 7-bit address. In direct addressing, the 7 bits are directly specified in the instruction as a 7-bit
constant without # symbol. In indirect addressing, the lower 7 bits of auxiliary
register will be the address of
memory-mapped register. In this addressing nmode, the memory-mapped registers are accessed without atfecting
the content of DP (Data Pointer) or SP (Stack Pointer).
Example
LDM 06h, A : Load the content of MMR directly addressed by the instruction (address = 06h) in
accumulator A
STLMA, 1Eh Store the content of accumulator A in MMR directly addressed by the instruction
(address= IEh)
Stack Addressing
In stack addressing mode, the data memory address is the content of Stack Pointer (SP).
to/from stack.
11.63
Digital Signal Processing
Note : Stack memory is a
portion of data memory reserved by user/system designed for stack operations.
Example:
PSHM ICh: Decrement SP by 2 and push the content of MMR addressed by the instruction
laddress=1Ch} to stack memory addressed by SP
POPM ICh : Popthetop of stack
polnted by SP to MMR addressed by the Instruction (address=1Chl,
:then SP is Incremented by 2.
clock cycles.