5.4. Functional Modes of Digital Signal Processor: Rohini College of Engineering & Technology

ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY
5.4. FUNCTIONAL MODES OF DIGITAL SIGNAL PROCESSOR

TMS320C54xx processors retain in the basic Harvard architecture of their
predecessor, TMS320C25, but have several additional features, which improve their
performance over it. Fig.5.4.1 shows a functional block diagram of TMS320C54xx
processors. They have one program and three data memory spaces with separate buses,
which provide simultaneous accesses to program instruction and two data operands and
enables writing of result at the same time.
Part of the memory is implemented on-chip and consists of combinations of
ROM, dual-access RAM, and single-access RAM. Transfers between the memory
spaces are also possible.
The central processing unit (CPU) of TMS320C54xx processors consists of a 40-
bit arithmetic logic unit (ALU), two 40-bit accumulators, a barrel shifter, a 17x17
multiplier, a 40-bit adder, data address generation logic (DAGEN) with its own
arithmetic unit, and program address generation logic (PAGEN). These major
functional units are supported by a number of registers and logic in the architecture.
A powerful instruction set with a hardware-supported, single-instruction repeat
and block repeat operations, block memory move instructions, instructions that pack
two or three simultaneous reads, and arithmetic instructions with parallel store and load
make these devices very efficient for running high-speed DSP algorithms.
Several peripherals, such as a clock generator, a hardware timer, a wait state
generator, parallel I/O ports, and serial I/O ports, are also provided on-chip. These
peripherals make it convenient to interface the signal processors to the outside world. In
these following sections, we examine in detail the various architectural features of the
TMS320C54xx family of processors.
Bus Structure:
The performance of a processor gets enhanced with the provision of multiple
buses to provide simultaneous access to various parts of memory or peripherals. The
54xx architecture is built around four pairs of 16-bit buses with each pair consisting of
an address bus and a data bus.As shown in Fig.5.4.1, these are The program bus pair
EE8591-DIGITAL SIGNAL PROCESSING

Figure 5.4.1.Functional architecture for TMS320C54xx processors.

[Source: ‘Lonnie C.Ludeman ,”Fundamentals of Digital Signal Processing”]
(PAB, PB); which carries the instruction code from the program memory. Three data
bus pairs (CAB, CB; DAB, DB; and EAB, EB); which interconnected the various units

within the CPU. In Addition the pair CAB, CB and DAB, DB are used to read from the
data memory, while the pair EAB, EB; carries the data to be written to the memory.
The ‘54xx can generate up to two data-memory addresses per cycle using the two
auxiliary register arithmetic unit (ARAU0 and ARAU1) in the DAGEN block. This
enables accessing two operands simultaneously.
Central Processing Unit (CPU):
The ‘54xx CPU is common to all the ‘54xx devices. The ’54xx CPU contains a
40-bit arithmetic logic unit (ALU); two 40-bit accumulators (A and B); a barrel shifter;
a 17 x 17-bit multiplier; a 40-bit adder; a compare, select and store unit (CSSU); an
exponent encoder(EXP); a data address generation unit (DAGEN); and a program
address generation unit (PAGEN).
Figure 5.4.2.Functional diagram of the central processing unit


Accumulators
Accumulators A and B store the output from the ALU or the multiplier/adder
block and provide a second input to the ALU. Each accumulators is divided into three
parts: guards bits (bits 39-32), high- order word (bits-31-16), and low-order word (bits
15- 0), which can be stored and retrieved individually. Each accumulator is memory-
mapped and partitioned. It can be configured as the destination registers. The guard bits
are used as a head margin for computations.
Barrel shifter:
Barrel shifter provides the capability to scale the data during an operand read or
write. No overhead is required to implement the shift needed for the scaling operations.
The’54xx barrel shifter can produce a left shift of 0 to 31 bits or a right shift of 0 to 16
bits on the input data. The shift count field of status registers ST1, or in the temporary
register T. Figure 4.3 shows the functional diagram of the barrel shifter of
TMS320C54xx processors. The barrel shifter and the exponent encoder normalize the
values in an accumulator in a single cycle. The LSBs of the output are filled with0s, and
the MSBs can be either zero filled or sign extended, depending on the state of the sign-
extension mode bit in the status register ST1. An additional shift capability enables the
processor to perform numerical scaling, bit extraction, extended arithmetic, and
overflow prevention operations.
Multiplier/adder unit:
The kernel of the DSP device architecture is multiplier/adder unit. The
multiplier/adder unit of TMS320C54xx devices performs 17 x 17 2’s complement
multiplication with a 40-bit addition effectively in a single instruction cycle.
In addition to the multiplier and adder, the unit consists of control logic for integer and
fractional computations and a 16-bit temporary storage register, T. Figure 4.4 show the
functional diagram of the multiplier/adder unit of TMS320C54xx processors.
The compare, select, and store unit (CSSU) is a hardware unit specifically incorporated
to accelerate the add/compare/select operation. This operation is essential to implement
the Viterbi algorithm used in many signal-processing applications

Figure 4.3.Functional diagram of the barrel shifter

The exponent encoder unit supports the EXP instructions, which stores in the T
register the number of leading redundant bits of the accumulator content. This
information is useful while shifting the accumulator content for the purpose of scaling.

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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

5.4. FUNCTIONAL MODES OF DIGITAL SIGNAL PROCESSOR

EE8591-DIGITAL SIGNAL PROCESSING

Figure 5.4.1.Functional architecture for TMS320C54xx processors.

EE8591-DIGITAL SIGNAL PROCESSING

Figure 5.4.2.Functional diagram of the central processing unit

EE8591-DIGITAL SIGNAL PROCESSING

EE8591-DIGITAL SIGNAL PROCESSING

Figure 4.3.Functional diagram of the barrel shifter

EE8591-DIGITAL SIGNAL PROCESSING

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