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BCA501-T DATA COMMUNICATION AND NETWORKS

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2 Blue Print – Question paper pattern
3 • Unit wise Questions
• TMAQ – Important Tutor Mark Assignment Question
4 Bangalore University Question Paper
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BCA 501T DATA COMMUNICATION & NETWORKS

BCA501T: DATA COMMUNICATIONS AND NETWORKS
Total Teaching Hours : 60 No of Hours / Week : 04

Unit – I
Introduction: Communication Network and services, Approaches to Network Design, Network
Functions and Network Topology, Message ,packet and circuit Switching , Internet, Packet
Switching ; Key factors in Communication Network Evolution ; Layered Architecture and
Applications – Examples of Layering , OSI Reference Model, TCP/IP Model Telnet FTP and
IP Utilities. Digital Transmission: Digital Representation of Information: Properties of digital
transmission: Characterization of Communication Channels Frequency Domain and Time
Domain : Fundamental limits in Digital Communication – The NyquistSignalling rate, The
Shannon channel capacity : Line coding , Modems & digital Modulations
[ 12 Hours ]
Unit - II
Transmission Systems: properties of media and digital transmission Systems – Twisted Pair ,
Coaxial Cable, Optical Fibre, Radio Transmission Intrared Light Error detection and
correction – Error detection , Two – dimensional parity checks , Internet checksum ,
Polynomial code; standardized Polynomial codes , Error detecting capability of a polynomial
code, Multiplexing – frequency – Division , Time – Division , SONET; Wavelength Division
Multiplexing Circuit switches; Telephone network , signalling Traffic and Overload control in
Telephone networks – Concentration, Routing Control, Overload controls Cellular Telephone
Networks, Satellite Cellular networks. [ 12 Hours ]
Unit – III
Peer –to-Peer Protocols:- Peer-to peer Protocols and service models ARQ Protocols stop and
wait , Go –back-N Selective Repeat , Transmission efficiency of ARQ Protocols, Other
adaptation functions , - Sliding window flow control Timing Recovery in Synchronous
Services Reliable Stream Service, Data Link Control, HDLC, PPP ; Statistical Multiplexing.
[ 12 Hours ]
Unit - IV
Local Area Networks and Medium access Control Protocols:- Multiple access
communications; Local Area network – LAN Structure, MAC Sublayer, Logical link
control layer, Random Access protocols ALOHA , Slotted ALOHA, CSMA, CSMA/CD,
Scheduling approaches to medium access control – Reservation Systems, polling , Token
passing rings, comparison of Random access & Scheduling access control Comparison of
Radom access & SHEDULING MEDIUM access controls; Channelization – FDMA,
TDMA, CDMA; [ 12 Hours ]
Unit - V
LAN Standard –Ethernet and IEF, 802.3 LAN Standard ; Token Ring and IEEE 8025 LAN
standard , FDDI, Wireless LAN’s and IEEE 802.11 Standards; LAN Bridges – Transparent
Bridges , Source Routing Bridges , Mixed – media Bridges. Packet Switching Networks :-
Network services & Internal Network Operation; Packet Network Topology; Datagrams &
VIRTUAL circuits ; structure of switch/ Router, Connectionless packet switching ; Virtual –
Circuit packet switching ; Overview of Routing and congestion in packet networks – Routing
algorithms classification , Routing tables, shortest path routing algorithms, Flooding ,
Hierarchical routing , Distance vector routing
Link state routing , congestion control algorithms. [ 12 Hours ]
Text Books:
1.Stallings, “Data and Computer Communications”, 7thEdition,Pearson Education, 2012
Reference Books:
1. Andrew S Tanenbaim, “Computer Networks”, 4th Edition, Pearson Education.
2. BehrouzFerouzan, Introduction to Data Communication & Networking TMH, 1999. 3.
Larry &Peterson & Bruce S Davis; Computer networks Second Edition , Morgan
Kaufman, 2000.
BCA501T: DATA COMMUNICATIONS AND NETWORKS

BLUE PRINT
Question paper pattern for theory has four sections :
Section – A :Contains 12 questions, out of which a student has to answer 10 questions. Each
question carries 2 marks ( 10 x 2 = 20 )
Section – B :Contains 5 full questions includes sub-question as (a) & (b). Each full question
carries 10 marks (5 x 10 = 50)
Section – C: Contains 5 full questions includes sub-question as (a) & (b). Each full question
Section – D :Contains 2 questions out of which a student has to answer 1 questions. Each
question carries 1 marks (1 x 10 = 10 )
SECTION A SECTION B
CHAPTER SECTION C SECTION D
2 MARKS 10 MARKS
15 MARKS 10 MARKS
Introduction to data
communication 1
networks
Network architecture
and switching 1
I
techniques
Layered architecture 1 1 1
1
and applications
Data and signals 1 1
Encoding 1 1
1
Transmission Media 1
II Multiplexing 1 1
Error Detection And
1 1
Correction
Peer to Peer Protocols 1 1
III Medium Access Control 1
1 1
Protocols
1
IV Local Area Networks 1 1
Packet Switching 1
V Networks and 1 1
Congestion Control
5 2
TOTAL 12 8
ANSWER ANSWER ANSWER ANSWER

ANY 10 ANY 5 ANY 3 ANY 1
45 10
TOTAL MARKS 20 25
SECTION – A ( 2 Marks)
UNIT-I
[Nov / Dec 2016]
1. Write any two examples of data communication modes?
2. Expand NIC and TCP
3. What is a switch?
4. Write any two difference between analog and digital signals?
[Nov / Dec 2017]

5. Define SNR?
6. What is modem?
7. What is FTP?
8. What do you mean by IP utility? Give an example.
9. What is Network Topology? List out any two network topologies.
10. Define attenuation
11. Write any two differences between analog and digital signals.
[Nov / Dec 2018]

12. What is telnet? How it differs from FTP?
13. What is meant by protocol and internet protocol suite?
14. Define encoding and decoding.
15. Define datagram and packet.
16. Define bit rate and baud rate.
[TMAQ – Important Tutor Mark Assignment Questions]

1. What is Network Topology? List any two types of Topology.
2. What are the types of network?
3. Expand SMTP and SNMP.
4. Define computer network.
5. What are the different characteristics for analog signals?
6. Compare LAN and WAN.
7. What is protocol? Give 2 examples.
SECTION – A (2 Marks)
UNIT-II
[Nov / Dec 2015]
1. Define multiplexing?
[Nov / Dec 2016]
2. What is cellular telephone network?
[Nov / Dec 2017]
3. What do you mean by Nyquist signaling rate? Explain.
1. Define SNR.
2. What is digital to digital encoding?
3. What is difference between UTP and STP cables?
4. What is TFTP?
5. Define NETSTAT command.
6. What is Shannon capacity formula?
UNIT-III
[Nov / Dec 2016]
1. Expand HDLC and PPP?
2. What is framing?

1. What is pipelining?
2. Differentiate between single hop and End-to-End.
3. What is polling?
4. What is piggybacking?
5. Define checksum.
6. What is ALOHA?
7. Compare FDMA, TDMA.
UNIT-IV
[Nov / Dec 2016]
1. What is the use of repeaters?
2. Expand FDDI and CSMA
[Nov / Dec 2017]
3.What is reservation?
4.What do you mean by centralized pooling?
1. What is FDDI?
2. List the features of CSMA/CD.
3. What are the essential components of LAN?
4. What are the functions of data link sub layer?
5. Compare various standards of Ethernet.
UNIT-V
[Nov / Dec 2016]
1. What is Ethernet?
2. What is meant by choke pocket?
3. What are the two types of LAN standards?
[Nov / Dec 2017]
4. What is flooding?
[Nov / Dec 2018]
6. What do you mean by IEEE 802.11 standards?
7. What do you mean by flooding? Explain.
8. What is the difference between Ethernet and fast Ethernet?
1. Explain different types of bridges.
2. Define routing.
3. What is bridge?
4. What is hierarchical routing?
5. What is fragmentation?
SECTION – B (10 Marks)
UNIT-I
[Nov / Dec 2016]
1. Explain types of transmission modes?
2. Compare mesh topology with star topology?
6. Differentiate datagrams with virtual circuits.
[Nov / Dec 2017]
7. Explain packet switching.
8. Explain Shannon capacity.
7. Illustrate the use of function overloading with example.
[Nov / Dec 2018]
14. Explain circuit switching.
15. How many layers are there in TCP\IP model? Mention the function of each layer.

1. Explain packet switching techniques.
2. Write a note on various technology?
3. What is multiplexing? What are the different types of multiplexing?
4. What is pulse code modulation?
5. With a neat diagram, explain TELNET.
6. Explain TCP/IP architecture.
7. Explain the properties of digital transmission systems.
8. Explain circuit switching and packet switching techniques.
UNIT-II
[Nov / Dec 2016]
1. Explain concept of checksum?
2. Explain types of errors?
[Nov /Dec2017]
3.What is multiplexing? Explain TDM
4. Differentiate connectionless and connection oriented services.
[Nov / Dec 2018]

16. Explain twisted pair cable as transmission medium.
18. Explain 2-dimensional parity check for error detection.
19. Explain the difference between connection and connectionless services.
1. Explain the concept of checksum.
2. Explain the types of errors.
3. Define time domain and frequency domain with the representation of any 2 frequency
signals.
4. Write a short notes on a) Infrared waves
5. Explain CRC with example.
6. Explain SONET multiplexing.

UNIT-III
[Nov / Dec 2016]
1. Explain the structure of HDLC frames
[Nov / Dec 2018]
2. Explain HDLC frame structure

1. Explain pulse code modulation.
2. Explain selective repeat ARQ.
3. Explain in detail the 1-persistant, p-persistent and non-persistent CSMA protocols.
4. How go back ‘n’ is different from selective repeat method?
5. Write the signal waveforms when 101101 is transmitted suing line coding
(a)Polar NRZ b) Bipolar
6. Explain Go Back N ARQ.
UNIT-IV
[Nov / Dec 2016]
1. Explain CSMA protocols.
[Nov / Dec 2017]

1. Illustrate CSMA
2. Describe FDDI.
3. Explain structure of HDLC frame.
1. Briefly explain peer-to-peer protocols and service models.
2. Explain the following scheduling schemes.
(i) Reservation systems (ii) polling
3. Explain transition phases in PPP.
4. Explain the architecture of IEEE 802.11.
5. Explain the architecture of IEEE 802.5.
SECTION – B ( 10 Marks )
UNIT-V
[Nov / Dec 2016]
1. Explain the following (a) congestion control.
[Nov / Dec 2017]
1. Describe FDDI
2. Write Bellman Ford Algorithm.
[Nov / Dec 2018]
3.Explain the role of the following network devices:
2.Describe FDDI.

1. Explain congestion control algorithms.
2. Explain token bucket algorithm.
3. Explain Dijkstraw’s algorithm.
4. Explain flooding algorithms.
5. Explain leaky bucket algorithm.
6. Write short note on choke packets.
7. Write short note on distance vector routing.
SECTION – C (15 Marks)
UNIT-I
[Nov / Dec 2016]
1.a) Explain the types of network?
b) Explain the functions of OSI model layers?
[Nov / Dec 2017]

2. Explain OSI reference model with a neat diagram.
3. What is digital modulation? Explain the digital modulation techniques.
[Nov / Dec 2018]

4. Explain digital representation of information

UNIT-II
[Nov / Dec 2016]

1.Explain the following?
A) Pulse Code Modulation (PCM).
B) SONET
c.coaxial cable
[Nov / Dec 2017]

2. Illustrate polynomial code with an example
3. Describe twisted pair cable.
4. Explain SONET.
[Nov / Dec 2018]

5) Write note on polynomial code with suitable exam
6. Explain optical fibre as transmission medium
UNIT-III
[Nov / Dec 2016]

1.Explain the following?
a) CRC method
b) Stop –and-wait –ARQ algorithm
[Nov / Dec 2017]
2. Describe selective repeat ARQ.
[Nov / Dec 2018]
3. Explain stop and wait ARQ with a neat diagram.
4. Explain sliding window method of flow control.
5.What do you mean by peer-to-peer protocol? Compare

UNIT-IV
[Nov / Dec 2016]

1. a) Write short notes on ALOHA protocol.
b) Explain CSMA protocols.
[Nov / Dec 2017]

2.Explain FDMA, TDMA and CDMA
[Nov / Dec 2018]
3.Explain ALOHA and slotted ALOHA

4. Explain frequency division multiple access and time division multiple access
5. Explain LLC and MAC sub layers of data link layer.
UNIT-V
[Nov / Dec 2016]
1. Explain Dijikstra’s algorithm
[Nov / Dec 2017]

2. What is a bridge? Explain the various types of bridges
3. Illustrate the two sublayer of data link layer
4.I llustrate open-loop congestion control
[Nov / Dec 2018]

5.Explain different types of bridges in computer
SECTION – D (10 Marks)

UNIT-I
[Nov / Dec 2016]
1.Compare packet switching with circuit switching.
[Nov / Dec 2017]
2.Explain TCP/IP model with a neat diagram.
[Nov / Dec 2018]
3.Explain OSI reference model in detail.

UNIT-II
[Nov / Dec 2016]
4.IIlustrate polar line encoding scheme.

UNIT-V
[Nov / Dec 2016]
2.Explain the following:
a) Modems
b).Congestion control.
[Nov / Dec 2018]
3. Explain any routing algorithms.
1. Explain the working of FTP.
2. Explain AM, FM and PM.
3. Write a note on guided transmission media.
4. Explain IEEE 802.4 Token ring format.
5. Write a note on switches?
6. What are different scheduling approaches? Compare them.
7. Discuss MAC sub layer and logical link control sub layer.
8. Explain Cyclic Redundancy check method for error detection.
9. Explain sliding window protocols.
10. What is the difference between datagram and virtual algorithms.
11. Describe digital to analog conversion.
12. What is Hamming code?
13. Explain scheduling algorithms?
14. Write a short notes on shortest path algorithm?
15. Explain the working and frame format of token ring.
16. Write algorithm of CRC method of error detection with an example.
17. Explain the characteristic s of co-axial cable with neat diagram? What are the
advantages of co-axial over twisted pair.
18. Explain selective Repeat ARQ.
19. Explain the concept of checksum.
20. Explain the flooding algorithm.
Section -A
Unit-1
1. Write any two examples of data communication modes?
• Simplex mode: Ex: T.V transmission
• Half-duplex mode: Ex: Internet browsing
• Full-duplex mode: Ex: Telephone communication
2. Expand NIC and TCP
• NIC: network interface cards
• TCP: transmission control protocol
3. What is a switch?
A network switch is a hardware device that channels incoming data from multiple input
ports to a specific output port that will take it toward its intended destination. It is a small
device that transfers data packets between multiple network devices such as computers,
routers… A switch network consists of several devices interlinked by a series of nodes
called switch.
4. Write any two difference between analog and digital signals?

Analog signal Digital signal
An Analog signal is a continuous wave that A digital signal is a discrete wave that
changes over a time period. carries information in binary form.
Analog signal has no fixed range. Digital signal has a finite numbers i.e. 0
and 1.
5. Define SNR?
SNR is ratio of the signal power to the noise power
SNR= Average signal power
Average noise power
6. What is modem?
Modem is abbreviation for Modulator – Demodulator. Modems are used for data transfer
from one computer network to another computer network through telephone lines.
7. What is FTP?
FTP is application protocol used to transfer a file from one computer to another .it is intended
to operate across different computers even when they are running different operating system.
8. What do you mean by IP utility? Give an ex.
IP provides several handy tools or utilities for troubleshooting, investigating, and analyzing
the network
Examples:
➢ PING
➢ TRACE ROUTE.
9. What is Network Topology? List out any two network topologies.

Network Topologies define layout, virtual shape or structure of network, not only physically
but also logically.
Examples
➢ Bus topology
➢ Star topology
10. Define attenuation?

Attenuation, when a signal travel through transmission media it loses some of its energy in
overcoming the resistance of the medium. To compensate attenuation, amplifier are used to
strengthen the signal.
11.Write any two differences between analog and digital signals.
ANALOG SIGNALS DIGITAL SIGNALS
a) An analog signal is a continuous wave that a)A digital signal is a discrete wave that
changes over a time period. carries information in binary form
b) An analog signal is represented by a sine b) A digital signal is represented by square
wave. waves.
12. What is telnet? How it differs from FTP ?

TELNET is a terminal network . It is a TCP\IP protocol which provides a means of accessing
resources on a remote computer where the initiated computer is treated as local to the remote
computer.
FTP provides access to files only. It is driven either by command line interpreter or graphical
user interface.
13. What ismeant by protocol and internet protocol suite ?
In telecommunication, a communication protocol is a system of rules that allow two or more
entities of a communications system to transmit information via any kind of variation of a
physical quantity.
Internet protocol is one of the major protocols in the TCP\IP protocols suite. It works at the
internet layer of the TCP\IP model.
14. Define encoding and decoding.

Encoding is the process by which information from a source is converted into symbols to be
communicated.
Decoding is the reverse process, converting these code symbols back into information
understandable by a receiver.
15.Define datagram and packet.

Datagram is a basic transfer unit associated with a packet switched network it provides a
connectionless communication service across a packet switched network.
Packet is a unit of data made into a single package that travels along a given network path.
16. Define bit rate and baud rate.

Bit rate is the number of bits transmitted per second.
Baud rate is the number of signal units transmitted per second
17. Define multiplexing?

Multiplexing is a method by which multiple analog or digital signals are combined into one
signal over a shared medium. ... For example, in telecommunications, several telephone calls
may be carried using one wire.
18. What is cellular telephone network?

A cellular network or mobile network is a communication network where the last link
is wireless. The network is distributed over land areas called "cells", each served by at least
one fixed-location transceiver, but more normally, three cell sites or base transceiver stations.
19. What do you mean by Nyquist signaling rate ? explain.

The Nyquist frequency, named after electronic engineer Harry Nyquist, is half of the
sampling rate of a discrete signal processing system.The Nyquist rate is twice the maximum
component frequency of the function being sampled.
Formula : C = 2 * B * log2 M
20. Expand HDLC and PPP?
HDLC – high level data link control
PPP – point to point protocol
21. What is framing?
A frame is a digital data transmission unit in computer networking and telecommunication.
A frame typically includes frame synchronization features consisting of a sequence of bits or
symbols that indicate to the receiver the beginning and end of the payload data within the
stream of symbols or bits it receives.
22. What is the use of repeaters?

A network device used to regenerate or replicate a signal. Repeaters are used in transmission
systems to regenerate analog or digital signals distorted by transmission loss.
Analog repeaters frequently can only amplify the signal while digital repeaters can reconstruct
a signal to near its original quality.
23. Expand FDDI and CSMA

• FDDI – Fiber Distributed Data Interface.
• CSMA- Carrier Sense Multiple Access.
24. What is reservation?
The Resource Reservation Protocol (RSVP) is a transport layer protocol designed
to reserve resources across a network using the integrated services model. ... RSVP can be used
by hosts and routers to request or deliver specific levels of quality of service (QoS) for
application data streams.
25. What do you mean by centralized pooling?
A central controller transmits polling messages to stations according to a certain order
Ethernet is the traditional technology for connecting wired local area networks (LANs),
enabling devices to communicate with each other via a protocol-- a set of rules or common
network language.
27.What is meant by choke pocket?
A choke packet is used in network maintenance and quality management to inform a specific
node or transmitter that its transmitted traffic is creating congestion over the network. This
forces the node or transmitter to reduce its output rate.
28.What are the two types of LAN standards?
(I) Ethernet or IEEE 802.3 standard
(II) Token bus or IEEE 802.4 standard
29. What is flooding?
Flooding is a simple routing technique in computer networks where a source or node sends
packets through every outgoing link. Flooding, which is similar to broadcasting, occurs when
source packets (without routing data) are transmitted to all attached network nodes.
Ethernet is the traditional technology for connecting wired local area networks (LANs),
enabling devices to communicate with each other via a protocol-- a set of rules or common
network language.
31.What do you mean by IEEE 802.11 standards?
IEEE 802.11 refers to the set of standards that define communication for wireless LANs
(wireless local area networks, or WLANs). The technology behind 802.11 is branded to
consumers as Wi-Fi. As the name implies, IEEE 802.11 is overseen by the IEEE, specifically
the IEEE LAN/MAN Standards Committee (IEEE 802).
32. What do you mean by flooding? Explain.
In a network, flooding is the forwarding by a router of a packet from any node to every
other node attached to the router except the node from which the packet arrived. The
Internet's Open Shortest Path First (OSPF) protocol, which updates router information in
a network, uses flooding.
33. What is the difference between Ethernet and fast Ethernet?
ETHERNET FAST ETHERNET
Offers 100 Mbps speed. Provide 1 Gbps speed.
Generate more delay. Less comparatively.
Simple Complicated and create more errors.
Can cover distance up to 10 km. Has the limit of 70 km.
Successor of 10-Base-T Ethernet. A successor of fast Ethernet.

Section B (5marks)
1. Explain types of transmission modes?
Ans:Transmission mode refers to the mechanism of transferring of data between two devices
connected over a network. It is also called Communication Mode. These modes direct the
direction of flow of information. There are three types of transmission modes. They are:
1. Simplex Mode
2. Half duplex Mode
3. Full duplex Mode
Simplex mode : In this type of transmission mode, data can be sent only in one direction
i.e. communication is unidirectional. We cannot send a message back to the sender.
Unidirectional communication is done in Simplex Systems where we just need to send a
command/signal, and do not expect any response back.
Examples of simplex Mode are loudspeakers, television broadcasting, television and
remote, keyboard and monitor etc.
Half duplex mode : Half-duplex data transmission means that data can be transmitted
in both directions on a signal carrier, but not at the same time
Full duplex mode : In full duplex system we can send data in both the directions as it is
bidirectional at the same time in other words, data can be sent in both directions
simultaneously.
2. Compare mesh topology with star topology?
Mesh topology Star topology
It contains at least two nodes with two The peripheral nodes are connected to
or more paths between them. the central node(ex. hub, switch or
router).
Information is directly routed from one All the information is routed from the
device to another. central network connection.
Expensive due to extensive cabling. Cost is Comparatively less
Quite complex Simple0
Highly robust Intermediate
3. Differentiate datagrams with virtual circuits

Virtual circuits Datagrams
1.It is connection-oriented simply meaning that 1.It is connectionless service. There is no need for
there is a reservation of resources like buffers, reservation of resources as there is no dedicated
CPU, bandwidth, etc. for the time in which the path for a connection session.
newly setup VC is going to be used by a data
transfer session.
2. First packet goes and reserves resources for the 2. All packets are free to go to any path on any
subsequent packets which as a result follow the intermediate router which is decided on the go by
same path for the whole connection time dynamically changing routing tables on routers.
3. Since all the packets are going to follow the 3. Since every packet is free to choose any path,
same path, a global header is required only for the all packets must be associated with a header with
first packet of the connection and other packets proper information about the source and the
generally don’t require global headers. upper layer data.
4. Since data follows a particular dedicated path, 4. The connectionless property makes data
packets reach inorder to the destination. packets reach the destination in any order, means
they need not reach in the order in which they
were sent.
5. In Virtual Circuit Switching, it is sure the all 5. Datagram networks are not reliable as Virtual
the packets will definitely reach to the Destination. Circuits.
No packet will discard due to unavailability of
resources.
4. Explain packet switching.
Packet switching is a method of grouping data that is transmitted over a digital network
into packets. Any message exceeding the maximum-defined length of the packet is broken
up into packets. Packet switching overcomes the drawbacks of circuit switching and
message switching. Packets are made of a header,user data, trailer. Data in the header are
used by networking hardware to direct the packet to its destination where the payload is
extracted and used by application software Each packet contains header, user data and
trailer. The header specifies the beginning of a packet and contains control information like
source and destination addresses, packet number, priority codes etc. the user data contains
information. The trailer contains a cyclic redundancy checksum used for error detection
and correction.
5. Explain Shannon capacity.

Transmission channels are noisy. The presence of noise can corrupt one or more bits. If
data rate is increased, then more bits will occur in the interval of a noise spike, and hence
more errors will occur. Claude Shannon introduced a formula, called Shannon capacity, to
determine the theatrical highest data rate for a noisy channel.
C = B * log2 (1+SNR)
Where,
C is the capacity of the channel in bits per second
B is the bandwidth of the channel
SNR is the Signal-to-noise Ratio.
6. Explain circuit switching.
In circuit switching a dedicated physical connection is established between the source and
destination and then data is transmitted. Communication via circuit switching involves
three phases.Circuit establishment: Before any data can be transmitted, an end to end
dedicated connection is established.
Data transfer: once the connection is established data is transmitted on the link.
Circuit disconnect: After the data transmission is completed, the circuit is terminated and
the resources are deallocated
Advantages:
• Data is transmitted without delays.
• This method suitable for long continuous transmission.
Disadvantages:
• Long connection establishment delay
• Network does not provide flow control or error control.
7. How many layers are there in TCP\IP model? Mention the function of each layer.
TCP/IP means Transmission Control Protocol and Internet Protocol. It is the network
model used in the current Internet architecture as well. Protocols are set of rules which
govern every possible communication over a network. These protocols describe the
movement of data between the source and destination or the Internet. These protocols offer
simple naming and addressing schemes. TCP/IP that is Transmission Control Protocol and
Internet Protocol was developed by Department of Defence Project Research Agency
(ARPA, later DARPA) as a part of a research project of network interconnection to
connect remote machines
Host-to-network layer
• Lowest layer of the all.
• Protocol is used to connect to the host, so that the packets can be sent over it.
• Varies from host to host and network to network. It is equivalent to the combination
of physical and datalink layer.
Internet layer
• Selection of a packet switching network which is based on a connectionless
internetwork layer is called a internet layer.
• It is the layer which holds the whole architecture together.
• It helps the packet to travel independently to the destination.
• Order in which packets are received is different from the way they are sent.
• IP (Internet Protocol) is used in this layer.
Transport layer
• It decides if data transmission should be on parallel path or single path.
• Functions such as multiplexing, segmenting or splitting on the data is done by
transport layer.
• The applications can read and write to the transport layer.
• Transport layer adds header information to the data.
• Transport layer breaks the message (data) into small units so that they are
handled more efficiently by the network layer. Transport layer also arrange the
packets to be sent, in sequence.
Application layer
• TELNET is a two-way communication protocol which allows connecting to a
remote machine and run applications on it.
• FTP (File Transfer Protocol) is a protocol, that allows File transfer amongst
computer users connected over a network. It is reliable, simple and efficient.
• SMTP (Simple Mail Transport Protocol) is a protocol, which is used to transport
electronic mail between a source and destination, directed via a route.
• DNS (Domain Name Server) The Domain Name System (DNS) is a hierarchical
decentralized naming system for computers, services, or other resources
connected to the Internet or a private network.
•
8. Explain concept of checksum?
• A checksum is an error-detection method the transmitter computes a numerical
value according to the number of set or unset bits in a message and sends it along
with each message frame.
• At the receiver end, the same checksum function (formula) is applied to the message
frame to retrieve the numerical value. If the received checksum value matches the
sent value, the transmission is considered to be successful and error free. A
checksum may also be known as a hash sum.
• A mismatched checksum shows that the entire message has not been transmitted.
TCP/IP and User Datagram Protocol (UDP) provide a checksum count as one of
their services.
• The procedure of generating checksums from messages is called a checksum
function and is performed using a checksum algorithm. Efficient checksum
algorithms produce different results with large probabilities if messages are
corrupted. Parity bits and check digits are special checksum cases suitable for tiny
blocks of data. Certain error-correcting codes based on checksums are even capable
of recovering the original data.
9. Explain types of errors?
• Whenever bits flow from one point to another, they are subject to unpredictable
changes because of interference. This interference can change the shape of the
signal.
There are three types of errors.
1.single bit
2.multiple bit
3.burst error
• The term single-bit error means that only 1 bit of a given data unit (such as a byte,
character, or packet) is changed from 1 to 0 or from 0 to 1.
• The following figure shows the effect of a single-bit error on a data unit. To
understand the impact of the change, imagine that each group of 8 bits is an ASCII
character with a 0 bit added to the left. In the figure 00000010 (ASCII STX) was
sent, meaning start of text, but 00001010 (ASCII LF) was received, meaning line
feed.
Burst Error:
The term burst error means that 2 or more bits in the data unit have changed from 1 to
0 or from 0 to 1.The following figure shows the effect of a burst error on a data unit. In
this case, 0100010001000011 was sent, but 0101110101100011 was received. Note that a
burst error does not necessarily mean that the errors occur in consecutive bits. The
length of the burst is measured from the first corrupted bit to the last corrupted bit.
Some bits in between may not have been corrupted.
Multiple bit error: multiple bit error means that two or more non-consecutive bits in
the data unit have changed from 1 to 0 or from 0 to 1
10. What is multiplexing? Explain TDM
• Multiplexing is the set of techniques that allows the simultaneous transmission of
multiple signals across a single data link.
TDM (Time division multiplexing)
• Time-division multiplexing (TDM) is a method of putting multiple data streams in a
single signal by separating the signal into many segments, each having a very short
duration. ... The composite signal thus contains data from multiple senders.
• Time-division multiplexing is used primarily for digital signals, but may be applied
in Analog multiplexing in which two or more signals or bit streams are transferred
appearing simultaneously as sub-channels in one communication channel, but are
physically taking turns on the channel.
11. Differentiate connectionless and connection oriented services
NO CONNECTION-ORIENTED SERVICE CONNECTION-LESS SERVICE
Connection-oriented service is related Connection-less service is related to the

1.
to the telephone system. postal system.
Connection-oriented service is
preferred by long and steady Connection-less Service is preferred by
2.
communication. bursty communication.
Connection-oriented Service is
3.
necessary. Connection-less Service is not compulsory.
4.
Connection-oriented Service is feasible. Connection-less Service is not feasible.
In connection-oriented Service, In connection-less Service, Congestion is

5.
Congestion is not possible. possible.
Connection-oriented Service gives the Connection-less Service does not give the
6.
guarantee of reliability. guarantee of reliability.
12. Explain twisted pair cable as transmission medium.

• A twisted pair can be used as a balanced line, which as part of a balanced circuit can
greatly reduce the effect of noise currents induced on the line by coupling of electric
or magnetic fields. The idea is that the currents induced in each of the two wires are
very nearly equal. The twisting ensures that the two wires are on average the same
distance from the interfering source and are affected equally. The noise thus
produces a common-mode signal which can be cancelled at the receiver by detecting
the difference signal only, the latter being the wanted signal.
• Shielded twisted pair: Shielded twisted pair is a special kind of copper telephone
wiring used in some business installations. An outer covering or shield is added to
the ordinary twisted pair telephone wires; the shield functions as a ground.
• Unshielded twisted pair :Unshielded twisted pair (UTP) cables are found in
many Ethernet networks and telephone systems. For indoor telephone applications,
UTP is often grouped into sets of 25 pairs according to a standard 25-pair colour
code originally developed by AT&T Corporation.
Advantages
• Cheapest form of cable available for networking purposes.
• Easy to handle and install.
13. Explain 2-dimensional parity check for error detection.
• When a large amount of data is to be transmitted two dimensional parity checks can be
employed. In this method, the data words are arranged one above another and is
organized in a form of two dimensional binary matrix. For each row and column of the
matrix parity-check bit is calculated.
• A message consisting of n characters with 8-bits per character will now become n+1
character with 9-bits per character and is transmitted.
• The whole matrix is then sent to the receiver. At the receiver end, the sum of the bits in
the block of data is added again, and if the calculated sum is different than what was
transmitted, then an error is indicated. Then the original block must be transmitted or
written again. This scheme can detect up to three errors that occur anywhere in the
table.
1100111 1011101 0111001 0101001

• Ex: Original data
1100111 1
Row
1011101 1
parities
0111001 0
0101001 1
0101010 1 column parities
11001111 10111011 01110010 0101001 01010101
14. Explain the difference between connection and connectionless services.
S.NO CONNECTION-ORIENTED SERVICE CONNECTION-LESS SERVICE
Connection-oriented service is related Connection-less service is related to the

1. to the telephone system. postal system.
Connection-oriented service is
preferred by long and steady Connection-less Service is preferred by
2. communication. busty communication.
Connection-oriented Service is Connection-less Service is not

3. necessary. compulsory.
Connection-oriented Service is
4. feasible. Connection-less Service is not feasible.
In connection-oriented Service, In connection-less Service, Congestion is

5. Congestion is not possible. possible.
Connection-oriented Service gives the Connection-less Service does not give the
6. guarantee of reliability. guarantee of reliability.
In connection-oriented Service, In connection-less Service, Packets do not

7. Packets follow the same route. follow the same route.
15. Explain the structure of HDLC frames
An HDLC frame is structured as follows:

FLAG ADDRESS CONTROL INFORMATION FCS FLAG
8 bits 8 bits 8 / 16 bits variable 8 8 bits
FRAME FIELDS
FLAG
• The flag field of an HDLC frame is an 8-bit sequence with the bit pattern
01111110, same as PPP flag field which indicates the beginning and end of the
frame.
ADDRESS
• The second field of an HDLC frame contains the address of the secondary
station. If a primary station created the frame, it contains a to address. If a
secondary creates the frame, it contains a from address.
CONTROL
• The control field is used for flow and error control. It also determines the type of
the frame
INFORMATION FIELD
• The information field contains the user’s data from the network layer or
management information.
FCS FIELD:
• The frame check sequence is the HDLC error detection field. It contains either a
2 or 4-byte CRC
16. Illustrate CSMA
Carrier Sense Multiple Access with collision avoidance(CSMA/CA) was invented for
this network. Collisions are avoided through the use of three CSMA/CA strategies:
✓ Interface space(IFS): In this method when a station senses the channel id idle, it
does not send immediately. It waits for a period of time called the Inter-frame
space. Even though the channel may appear idle when it is sensed, a distant
station may have already started transmitting.
✓ Contention Window: The contention window is an amount of time divided into
slots. A station that is ready to send chooses a random number of slots as its
wait time. The number of slots in the window changes according to the binary
exponential back-off strategy
✓ Acknowledgement: With all these precautions, there may be collision resulting
in destroyed data. The positive acknowledgement and the time-out timer can
help the receiver has received the frame.
17. Describe FDDI
• FDDI uses dual-ring architecture with traffic on each ring flowing in opposite
directions. The dual rings consist of a primary and a secondary ring. During normal
operation, the primary ring is used for data transmission, and the secondary ring
remains idle. When the frames are transmitted through the primary ring at each and
every station the destination address is checked, if it matches then it stops at the
destination else will be transferred through the ring again until exact address is
matched got. If there is any break in the ring, unlike Token-Ring, the frame takes
opposite direction of flow and is transmitted on the secondary ring.
18. Write Bellman Ford Algorithm

The Bellman Ford algorithm calculates the shortest path to all nodes in the graph from a
single source. The principle states that “Each neighbor of source node knows the shortest
path to the destination node.
The steps involved in bellman ford algorithm is:
1. Intially mark all the nodes except source as infinity.
2. And the distance to destination Dd=0.
3. Find minimum distance to the destination through neighbours: for each i=/d D i-
minj(cij+Dj), for all j=/i
4. Repeat step 2 until destination is reached.
Consider the following figure. Suppose we want to find the shortest path from node 2 to
node 6
To reach destination from node 2, we must go through either node1, node4, node5.
Suppose the shortest path from node 1(through node 3), node4 and node 5 to the
destination node 6 are 3,3,2.
➢ Then for the packet from node 2 through node 1, the total distance is(3+3)=6
➢ Similarly, for the packet from node 2 through node 4 and node 5 are (1+3)=4 and
(4+2)=6 respectively
Then the shortest distance according to Bellman ford algorithm from node 2 to
destination node 6 is through node 4.
Example
Let us understand the algorithm with following example graph. The images are taken
from this source.
Let the given source vertex be 0. Initialize all distances as infinite, except the distance to
source itself. Total number of vertices in the graph is 5, so all edges must be processed 4
times.
Let all edges are processed in following order: (B, E), (D, B), (B, D), (A, B), (A, C), (D,
C), (B, C), (E, D). We get following distances when all edges are processed first time.
The first row in shows initial distances. The second row shows distances when edges (B,
E), (D, B), (B, D) and (A, B) are processed. The third row shows distances when (A, C) is
processed. The fourth row shows when (D, C), (B, C) and (E, D) are processed.
The first iteration guarantees to give all shortest paths which are at most 1 edge long.
We get following distances when all edges are processed second time (The last row
shows final values).
The second iteration guarantees to give all shortest paths which are at most 2 edges
long. The algorithm processes all edges 2 more times. The distances are minimized after
the second iteration, so third and fourth iterations don’t update the distances.
19. Explain the role of the following network devices:
• Hub
• Switch
• Bridge
• Router
• Repeater
• Hub – A hub is basically a multiport repeater. A hub connects multiple wires
coming from different branches, for example, the connector in star topology which
connects different stations. Hubs cannot filter data, so data packets are sent to all
connected devices.
• Switch – A switch is a multiport bridge with a buffer and a design that can boost its
efficiency (large number of ports imply less traffic) and performance. Switch is data
link layer device. The switch can perform error checking before forwarding data,
that makes it very efficient as it does not forward packets that have errors
and forward good packets selectively to correct port only.
• Bridge – A bridge operates at data link layer. A bridge is a repeater, with add on
functionality of filtering content by reading the MAC addresses of source and
destination.
• Routers – A router is a device like a switch that routes data packets based on their
IP addresses. Router is mainly a Network Layer device. Routers normally connect
LANs and WANs together and have a dynamically updating routing table based on
which they make decisions on routing the data packets. Router divide broadcast
domains of hosts connected through it.
• Repeater – A repeater operates at the physical layer. Its job is to regenerate the
signal over the same network before the signal becomes too weak or corrupted so as
to extend the length to which the signal can be transmitted over the same network.
An important point to be noted about repeaters is that they do not amplify the
signal. When the signal becomes weak, they copy the signal bit by bit and regenerate
it at the original strength. It is a 2 port device.
Section-C
1. A) Explain the types of network?
LAN
• LAN refers to a group of computers that all belong to the same organization and that
are linked within a small geographic area using a network and often the same
technology (the most widespread being Ethernet).
• A local area network is a network in its simplest form. Data transfer speeds over a local
area network can reach up to 10 Mbps, such as for an Ethernet network, and 1 gbps, as
with FDDI or Gigabit Ethernet. A local area network can reach as many as 100, or even
1000, users. MAN
• MANs connect multiple geographically close LANs (over an area of up to several dozen
miles) to one another at high speeds. Thus, a MAN lets two remote nodes communicate
as if they were part of the same local area network.A MAN is made from switches or
routers connected to one another with high-speed links (usually fibre optic cables).
WANs
• A WAN connects multiple LANs to one another over great geographic distances. The
speed available on a WAN varies depending on the cost of the connections, which
increases with distance, and may be low.WANs operate using routers, which can
"choose" the most appropriate path for data to take to reach a network node.
The most well-known WAN is the Internet.
b) Explain OSI reference model with a neat diagram. Repeated [Nov-Dec 2018]
Layer 1: The Physical Layer
1. Physical Layer is the lowest layer of the OSI Model.

2. It activates, maintains and deactivates the physical connection.
3. It is responsible for transmission and reception of the unstructured raw data over
network.
4. Voltages and data rates needed for transmission is defined in the physical layer.
5. It converts the digital /analog bits into electrical signal or optical signals.
6. Data encoding is also done in this layer.
Layer 2: Data Link Layer
1. Data link layer synchronizes the information which is to be transmitted over the
physical layer.
2. The main function of this layer is to make sure data transfer is error free from one node
to another, over the physical layer.
3. Transmitting and receiving data frames sequentially is managed by this layer.
4. This layer sends and expects acknowledgements for frames received and sent
respectively. Resending of non-acknowledgement received frames is also handled by this
layer.
5. This layer establishes a logical layer between two nodes and also manages the Frame
traffic control over the network. It signals the transmitting node to stop, when the frame
buffers are full.
Layer 3: The Network Layer
1. Network Layer routes the signal through different channels from one node to other.
2. It acts as a network controller. It manages the Subnet traffic.
3. It decides by which route data should take.
4. It divides the outgoing messages into packets and assembles the incoming packets into
messages for higher levels.
Layer 4: Transport Layer
1. Transport Layer decides if data transmission should be on parallel path or single path.
2. Functions such as Multiplexing, Segmenting or Splitting on the data are done by this
layer
3. It receives messages from the Session layer above it, convert the message into smaller
units and passes it on to the Network layer.
4. Transport layer can be very complex, depending upon the network requirements.
Transport layer breaks the message (data) into small units so that they are handled more
efficiently by the network layer.
Layer 5: The Session Layer

1. Session Layer manages and synchronize the conversation between two different
applications.
2. Transfer of data from source to destination session layer streams of data are marked
and are resynchronized properly, so that the ends of the messages are not cut
prematurely and data loss is avoided
Layer 6: The Presentation Layer
1. Presentation Layer takes care that the data is sent in such a way that the receiver will
understand the information (data) and will be able to use the data.
2. While receiving the data, presentation layer transforms the data to be ready for the
application layer.
3. Languages(syntax) can be different of the two communicating systems. Under this
condition presentation layer plays a role of translator.
4. It performs Data compression, Data encryption, Data conversion etc.
Layer 7: Application Layer
1. Application Layer is the topmost layer.
2. Transferring of files disturbing the results to the user is also done in this layer. Mail
services, directory services, network resource etc are services provided by application
layer.
3. This layer mainly holds application programs to act upon the received and to be sent
data.
DIAGRAM OF OSI MODEL
3.What is digital modulation? Explain the digital modulation techniques.

DM stands for Digital Modulation and is a generic name for modulation techniques that uses
discrete signals to modulate a carrier wave.
Three types of digital modulation
• Amplitude Modulation (AM)

• Frequency Modulation (FM)
• Phase Modulation (PM)
Amplitude Modulation
Amplitude modulation was developed in the beginning of the 20th century. It was the earliest
modulation technique used to transmit voice by radio. This type of modulation technique is
used in electronic communication. In this modulation, the amplitude of the carrier signal varies
in accordance with the message signal, and other factors like phase and frequency remain
constant.
Frequency Modulation
In this type of modulation, the frequency of the carrier signal varies in accordance with the
message signal, and other parameters like amplitude and phase remain constant. Frequency
modulation is used in different applications like radar, radio and telemetry, seismic
prospecting and monitoring new-borns for seizures via EEG, etc.
Phase Modulation
In this type of modulation, the phase of the carrier signal varies in accordance with the
message signal. When the phase of the signal is changed, then it affects the frequency. So, for
this reason, this modulation is also comes under the frequency modulation.
4. Explain digital representation of information.
Applications that run over networks involve the transfer of information of various types. Some
of them may involves blocks of text characters like e-mail and others involve stream of
information such as telephony.
Information can be classified into two broad categories
1. Block oriented information: this occurs naturally in form of a single block. These
blocks of information range from a few bytes to several hundred kilobytes and
occasionally several megabytes. Normal files of this form usually contain fair amount of
redundancies. Hence, data compression utilities such as compress, zip and other
methods are used to encode the original information into blocks which will now take
fewer bits to transfer and less disk storage space.
2. Stream information: this id produced continuously and must be transmitted as it is
produced. These signals are analog signals that are digitalized before transmission. The
first step in digitalizing and analog signal is to obtain sample values of the signal every
T seconds. The second step is quantizing each of the sample values. The last step is to
convert them into digital signals. Video signals are succession of pictures that gives
illusion to the human eye the appearance of continuous motion.
Transmission of digital signals

1. Baseband transmission: Base band is defined as one that uses digital signaling , which
is inserted in the transmission channel as voltage pulses .
2. Broadband transmission: These systems use analog signaling to transmit information
using a carrier of high frequency.
Transmission impairment
1. Attenuation: When a signal travels through a medium it loses some of its energy in
overcoming the resistance of the medium. To compensate attenuation, amplifiers are
used to strengthen the signal.
2. Distortion: It means that the signal changes its form or shape. It can occur in a
composite signal made of different frequencies.
3. Noise: It is the disturbance in the medium caused due to heat, crosstalk, spike in
energy, lighting. Noise corrupts the signal.
5. Explain the following?
A) Pulse Code Modulation (PCM).
• A signal is pulse code modulated to convert its analog information into a binary
sequence, i.e., 1s and 0s. The output of a PCM will resemble a binary sequence. The
following figure shows an example of PCM output with respect to instantaneous values
of a given sine wave.
• Instead of a pulse train, PCM produces a series of numbers or digits, and hence this
process is called as digital. Each one of these digits, though in binary code, represent
the approximate amplitude of the signal sample at that instant.
• In Pulse Code Modulation, the message signal is represented by a sequence of coded
pulses. This message signal is achieved by representing the signal in discrete form in
both time and amplitude.
B) SONET
• Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy
(SDH) are standardized multiplexing protocols that transfer multiple digital bit streams
over optical fiber using lasers or light-emitting diodes (LEDs). Lower data rates can also
be transferred via an electrical interface. The method was developed to replace the
Plesiochronous Digital Hierarchy (PDH) system for transporting larger amounts of
telephone calls and data traffic over the same fiber without synchronization problems.
SONET generic criteria are detailed in Telcordia Technologies Generic Requirements
document GR-253-CORE.Generic criteria applicable to SONET and other transmission
systems (e.g., asynchronous fiber optic systems or digital radio systems) are found in
Telcordia GR-499-CORE.
• SONET and SDH, which are essentially the same, were originally designed to transport
circuit mode communications (e.g., DS1, DS3) from a variety of different sources, but
they were primarily designed to support real-time, uncompressed, circuit-switched
voice encoded in PCM format.The primary difficulty in doing this prior to
SONET/SDH was that the synchronization sources of these various circuits were
different. This meant that each circuit was actually operating at a slightly different rate
and with different phase. SONET/SDH allowed for the simultaneous transport of many
different circuits of differing origin within a single framing protocol. SONET/SDH is
not itself a communications protocol per se, but a transport protocol.
Co-coaxial cable
• Coaxial cable is a type of copper cable specially built with a metal shield and other
components engineered to block signal interference. It is primarily used by cable TV
companies to connect their satellite antenna facilities to customer homes and businesses.
It is also sometimes used by telephone companies to connect central offices to telephone
poles near customers. Some homes and offices use coaxial cable, too, but its widespread
use as an Ethernet connectivity medium in enterprises and data centres has been
supplanted by the deployment of twisted pair cabling.
5. Illustrate polynomial code with an example.Repeated [Nov-Dec 2018]
Polynomial codes are used extensively in error detection and correction. Polynomial codes can
be easily implemented using shift-register circuits. A k-bit data-word can be represented as a
polynomial with k terms ranging from x k-1 to x0 as
I(x)= ik-1xk-1 + ik-2 xk-2 +………….+i1 x +I0 .
For example, let’s take a 8-bit message 10011010. The corresponding polynomial is
represented
M(x) = 1.x7 +0.x6 + 0.x5 +1.x4 + 1.x3 + 0.x2 + 1.x1 + 0.x0
=x7 + x4 + x3+ x1
•
• Polynomial codes involve generating check bits in the form of a cyclic redundancy
check(CRC). For these reasons they are also known as CRC codes.
• When applying the CRC method, both the sender and the receiver must agree upon a
common generator polynomial G(x). To compute the checksum for frame with M bits,
corresponding to the polynomial M(x), the frame M must be longer than the generator
polynomial. The polynomial M(x)is divided by G(x) to generate checksum. The
checksum, is appended at the end of the frame, in such a way that the transmitted
polynomial is completely divisible by G(x). if there is no remainder, it indicates no
transmission error.
• The most common CRC is the CCITT CRC-16 and CRC-32 used for many today’s
applications.
CRC-16=X16+X15+X2+1
CRC-CCITT=X16+X12+X5+1
CRC-32=X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+1
7. Describe twisted pair cable.

A twisted-pair cable is a cable made by intertwining two separate insulated wires.
There are two twisted pair types:
• Shielded twisted pair
• Unshielded twisted pair
A STP (Shielded Twisted Pair) cable has a fine wire mesh surrounding the wires to protect the
transmission a UTP (Unshielded Twisted Pair) cable does not. Shielded cable is used in older
telephone networks, as well as network and data communications to reduce outside
interference. The illustration gives an example of how the inside of these looks.
ADVANTAGES
• Electrical noise going into or coming from the cable can be prevented.
• Crosstalk is minimize.
• Cheapest form of cable available for networking purposes.
• Easy to handle and install.
DISADVANTAGES
• It is incapable carrying a signal over long distances without the use of repeaters only
because of high attenuation.
• It is not suitable for broadband applications only because of its low bandwidth capabilities
8.Explain SONET.
Synchronous optical networking (SONET) is a standardized digital communication protocol
that is used to transmit a large volume of data over relatively long distances using a fiber optic
medium. With SONET, multiple digital data streams are transferred at the same time over
optical fiber using LEDs and laser beams.
PHYSICAL CONFIGURATION
1. STS Multiplexer:
• Performs multiplexing of signals
• Converts electrical signal to optical signal
2. STS De-multiplexer:
• Performs de-multiplexing of signals
• Converts optical signal to electrical signal
3. Regenerator:
It is a repeater, that takes an optical signal and regenerates (increases the strength) it.
4. Add/Drop Multiplexer:
It allows to add signals coming from different sources into a given path or remove a
signal.
10. Explain optical fibre as transmission medium
• Optical fibre transmission systems were introduced in 1970. It offered greater advantages
over copper based digital transmission systems.
• A thin flexible fibre with a glass core through which light signals can be sent.
• Fibre optic cable has the ability to transmit signals over much longer distances.
• Optical fibre are immune to interference and cross talk
• A fibre optic cable is made of centre glass core surrounded by a concentric layer of
glass(cladding).
• The information is transmitted thru the glass core in the form of light.
• An important characteristic of fibre optic is refraction. Refraction is the characteristic of a
material to either pass or reflect the light. When a light passes thru the medium, it bends as it
passes from one medium to another.
•Wave length Division Multiplexing is an effective approach to explore the bandwidth that is
available in optical fibre. In WDM multiple wave length are used to carry several information
simultaneously over the same fibre.
Advantages
• It supports higher bandwidth
• It runs greater distance.
• Electromagnetic noise cannot affect fibre optic cables
• Usage of glass makes more resistant than copper
Disadvantages
• Installation and maintenance is difficult.
• Unidirectional light propagation. Two fibres are used for bidirectional propagation
• The cable and the interfaces are more expensive.
11. Explain the following?
a) CRC method
• Error detection mechanism in which a special number is appended to a block of data in
order to detect any changes introduced during storage (or transmission). The CRe is
recalculated on retrieval (or reception) and compared to the value originally
transmitted, which can reveal certain types of error. For example, a single corrupted bit
in the data results in a one-bit change in the calculated CRC, but multiple corrupt bits
may cancel each other out.
• A CRC is derived using a more complex algorithm than the simple CHECKSUM,
involving MODULO ARITHMETIC (hence the 'cyclic' name) and treating each input
word as a set of coefficients for a polynomial.
• CRC is more powerful than VRC and LRC in detecting errors.
• It is not based on binary addition like VRC and LRC. Rather it is based on binary
division.
• At the sender side, the data unit to be transmitted IS divided by a predetermined
divisor (binary number) in order to obtain the remainder. This remainder is called
CRC.
• The CRC has one bit less than the divisor. It means that if CRC is of n bits, divisor is of
n+ 1 bit.
• The sender appends this CRC to the end of data unit such that the resulting data unit
becomes exactly divisible by predetermined divisor i.e. remainder becomes zero.
• For example, if data to be transmitted is 1001 and predetermined divisor is 1011. The
procedure given below is used:
• String of 3 zeroes is appended to 1011 as divisor is of 4 bits. Now newly formed

data is 1011000.
1. Data unit 1011000 is divided by 1011.
2. During this process of division, whenever the leftmost bit of dividend or remainder is 0, we
use a string of Os of same length as divisor. Thus in this case divisor 1011 is replaced by 0000.
3. At the receiver side, data received is 1001110.
4. This data is again divided by a divisor 1011.
5. The remainder obtained is 000; it means there is no error.

b) Stop –and-Wait –ARQ algorithm
Characteristics
• Used in Connection-oriented communication.
• It offers error and flow control
• It is used in Data Link and Transport Layers
• Stop and Wait ARQ mainly implements Sliding Window Protocol concept with Window
Size 1
Useful Terms:
• Propagation Delay: Amount of time taken by a packet to make a physical journey from
one router to another router.
Propagation Delay = (Distance between routers) / (Velocity of propagation)
• RoundTripTime (RTT) = 2* Propagation Delay
• TimeOut (TO) = 2* RTT
• Time To Live (TTL) = 2* TimeOut. (Maximum TTL is 180 seconds)
Simple Stop and Wait
Sender:
Rule1) Send one data packet at a time.

Rule 2)Send next packet only after receiving acknowledgement for previous.
Receiver:
Rule 1) Send acknowledgement after receiving and consuming of data packet.
Rule 2) After consuming packet acknowledgement need to be sent (Flow Control).
12. Describe selective repeat ARQ.
Selective repeat protocol, also called Selective Repeat ARQ (Automatic Repeat reQuest), is a
data link layer protocol that uses sliding window method for reliable delivery of data frames. ...
The size is half the maximum sequence number of the frame
Features required for Selective Repeat ARQ
• To support Go-Back-N ARQ, a protocol must number each PDU which is sent. (PDUs
are normally numbered using modulo arithmetic, which allows the same number to be
re-used after a suitably long period of time. The time period is selected to ensure the
same PDU number is never used again for a different PDU, until the first PDU has "left
the network" (e.g. it may have been acknowledged)).
• The local node must also keep a buffer of all PDUs which have been sent, but have not
yet been acknowledged.
• The receiver at the remote node keeps a record of the highest numbered PDU which has
been correctly received. This number corresponds to the last acknowledgement PDU
which it may have sent.
Recovery of lost PDUs using Selective Repeat ARQ
The recovery of a corrupted PDU proceeds in four stages:
• First, the corrupted PDU is discarded at the remote node's receiver.

• Second, the remote node requests retransmission of the missing PDU using a control
PDU (sometimes called a Selective Reject). The receiver then stores all out-of-sequence
PDUs in the receive buffer until the requested PDU has been retransmitted.
• The sender receives the retransmission request and then transmits the lost PDU(s).
• The receiver forwards the retransmitted PDU, and all subsequent in-sequence PDUs
which are held in the receive buffer.
14. Explain sliding window method of flow control.
In this protocol (and the next), the sliding window is an abstract concept that defines the
range of sequence numbers that is the concern of the sender and receiver. In other words, the
sender and receiver need to deal with only part of the possible sequence numbers. The range
which is the concern of the sender is called the send sliding window; the range that is the
concern of the receiver is called the receive sliding window.
The send window is an imaginary box covering the sequence numbers of the data frames which
can be in transit. In each window position, some of these sequence numbers define the frames
that have been sent; others define those that can be sent. The window at any time divides the
possible sequence numbers into four regions.
• The first region, from the far left to the left wall of the window, defines the sequence
numbers belonging to frames that are already acknowledged. The sender does not worry
about these frames and keeps no copies of them.
• Defines the range of sequence numbers belonging to the frames that are sent and have an
unknown status. The sender needs to wait to find out if these frames have been received or
were lost. We call these outstanding frames.
• The third range, white in the figure, defines the range of sequence numbers for frames
that can be sent; however, the corresponding data packets have not yet been received from
the network layer.
• Finally, the fourth region defines sequence numbers that cannot be used until the window
slides, as we see next.
The window itself is an abstraction; three variables define its size and location at any time. We
call these variables (send window, the first outstanding frame), Sn (send window, the next
frame to be sent), and Size (send window, size). The variable Sf defines the sequence number of
the first (oldest) outstanding frame.
The variable Sn holds the sequence number that will be assigned to the next frame to be sent.
Finally, the variable Size defines the size of the window, which is fixed in our protocol.
The send window is an abstract concept defining an imaginary box of size 2m ~ 1 with three
variables: Sf Sm and Size'
How a send window can slide one or more slots to the right when an acknowledgment arrives
from the other end. As we will see shortly, the acknowledgments in this protocol are
cumulative, meaning that more than one frame can be acknowledged by an ACK frame.
Frames 0, I, and 2 are acknowledged, so the window has slid to the right three slots. Note that
the value of Sf is 3 because frame 3 is now the first outstanding frame.
15.What do you mean by peer-to-peer protocol? Compare PPP and HDLC.
Peer to Peer Protocol:

one of the most common protocols for point-to-point access is the Point-to-Point Protocol
(PPP). Today, millions of Internet users who need to connect their home computers to the
server of an Internet service provider use PPP. The majority of these users have a traditional
modem; they are connected to the Internet through a telephone line, which provides the
services of the physical layer. But to control and manage the transfer of data, there is a need
for a point-to-point protocol at the data link layer. PPP is by far the most common.
BASIS FOR
HDLC PPP
COMPARISON
Expands to High-level Data Link Layer Protocol Point-to-Point Protocol
Type of protocols Bit-oriented protocol Byte oriented protocol
Used in Only synchronous media Synchronous as well as

asynchronous media
Authentication No provision of authentication Provides authentication
Dynamic addressing Does not offer dynamic addressing. Dynamic addressing is used.
Implemented in Point-to-point and multipoint Only point-to-point

configurations. configurations.
Compatibility with other Can not be operated with non-Cisco Interoperable with non-Cisco
protocols devices. devices also.
Unit 4
16 .a) Write short notes on ALOHA protocol.
ALOHA is a system for coordinating and arbitrating access to a shared communication

Networks channel. It was developed in the 1970s by Norman Abramson and his
colleagues at the University of Hawaii. The original system used for ground based radio
broadcasting, but the system has been implemented in satellite communication systems.
A shared communication system like ALOHA requires a method of handling collisions

that occur when two or more systems attempt to transmit on the channel at the same
time. In the ALOHA system, a node transmits whenever data is available to send. If
another node transmits at the same time, a collision occurs, and the frames that were
transmitted are lost. However, a node can listen to broadcasts on the medium, even its
own, and determine whether the frames were transmitted.
Aloha means "Hello". Aloha is a multiple access protocol at the datalink layer and
proposes how multiple terminals access the medium without interference or collision.
There are two different versions of ALOHA
Pure ALOHA
• In pure ALOHA, the stations transmit frames whenever they have data to send.
• When two or more stations transmit simultaneously, there is collision and the frames
are destroyed.
Slotted ALOHA
• Slotted ALOHA was invented to improve the efficiency of pure ALOHA as chances of
collision in pure ALOHA are very high.
• In slotted ALOHA, the time of the shared channel is divided into discrete intervals
called slots.
• The stations can send a frame only at the beginning of the slot and only one frame is
sent in each slot.
b) Explain CSMA protocols.
o CSMA is a network access method used on shared network topologies such as Ethernet to
control access to the network. Devices attached to the network cable listen (carrier sense)
before transmitting. If the channel is in use, devices wait before transmitting. MA (Multiple
Access) indicates that many devices can connect to and share the same network. All devices
have equal access to use the network when it is clear.
CSMA works on the principle that only one device can transmit signals on the network,
otherwise a collision will occur resulting in the loss of data packets or frames. CSMA works
when a device needs to initiate or transfer data over the network. Before transferring, each
CSMA must check or listen to the network for any other transmissions that may be in
progress. If it senses a transmission, the device will wait for it to end. Once the transmission is
completed, the waiting device can transmit its data/signals. However, if multiple devices access
it simultaneously and a collision occurs, they both have to wait for a specific time before
reinitiating the transmission process.
17.Explain FDMA, TDMA and CDMA
• Frequency division multiple access(FDMA): In FDMA, the available bandwidth of the
channel is divided into frequency bands and each frequency band is allocated to different
stations. Each station on demand is allocated a predetermined band to send its all the time.
To prevent station interference the allocated bands are separated from one another by
small guard bands.
• Time division multiple access (TDMA) : In TDMA, the stations take turns to share the
entire bandwidth of the channel. Each station is allocated a time slot during which it can
transmit data for the complete bandwidth. Since TDMA transmissions are slotted, the
receiver must be synchronized with the sender. Each station needs to know the beginning of
its slot and the location of its slot for transmission.
• Code division multiple access(CDMA): In TDMA and FDMA data transmission from
different stations are clearly separated either by time or by frequency. Code division
multiple access is a digital wireless technology that uses spread spectrum techniques.
CDMA does not assign a specific frequency to each user. Instead, every station uses the full
available spectrum.
18.Explain ALOHA and slotted ALOHA
• ALOHA is a system for coordinating and arbitrating access to a shared communication
Networks channel. It was developed in the 1970s by Norman Abramson and his colleagues
at the University of Hawaii. The original system used for ground based radio
broadcasting, but the system has been implemented in satellite communication systems.
• A shared communication system like ALOHA requires a method of handling collisions
that occur when two or more systems attempt to transmit on the channel at the same time.
• In the ALOHA system, a node transmits whenever data is available to send. If another
node transmits at the same time, a collision occurs, and the frames that were transmitted
are lost. However, a node can listen to broadcasts on the medium, even its own, and
determine whether the frames were transmitted.
• There are two different versions of ALOHA
Pure ALOHA
• In pure ALOHA, the stations transmit frames whenever they have data to send.
• When two or more stations transmit simultaneously, there is collision and the
frames are destroyed.
Slotted ALOHA
• Slotted ALOHA was invented to improve the efficiency of pure ALOHA as
chances of collision in pure ALOHA are very high.
• In slotted ALOHA, the time of the shared channel is divided into discrete
intervals called slots.
• The stations can send a frame only at the beginning of the slot and only one
frame is sent in each slot.
20.Explain LLC and MAC sub layers of data link layer.
The data link layer is divided into two sublayers namely LLC (Logical Link Control) and MAC
(Media Access Control).
Logical Link Control (LLC) sublayer provides the logic for the data link. Thus, it
controls the synchronization, flow control, and error checking functions of the data link
layer.
Media Access Control (MAC) sublayer provides control for accessing the transmission
medium. It is responsible for moving data packets from one network interface card
(NIC) to another, across a shared transmission medium. Physical addressing is handled
at the MAC sublayer. MAC is also handled at this layer. This refers to the method used
to allocate network access to computers and prevent them from transmitting at the
same time, causing data collisions. Common MAC methods include Carrier Sense
Multiple Access/Collision Detection (CSMA/CD), used by Ethernet networks,
Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA), used by AppleTalk
networks, and token passing, used by Token Ring and Fiber Distributed Data Interface
(FDDI) networks.
Unit 5
21. Explain the following:
a) Dijikstra’s algorithm
o Dijkstra's algorithm is a step-by-step process we can use to find the shortest path
between two vertices in a weighted graph. This algorithm enables us to find
shortest distances and minimum costs, making it a valuable tool.
b) Token bucket algorithm.
• The token bucket algorithm is based on an analogy of a fixed capacity bucket into
which tokens, normally representing a unit of bytes or a single packet of predetermined
size, are added at a fixed rate.
• When a packet is to be checked for conformance to the defined limits, the bucket is
inspected to see if it contains sufficient tokens at that time. If so, the appropriate
number of tokens, e.g. equivalent to the length of the packet in bytes, are removed
("cashed in"), and the packet is passed, e.g., for transmission.
• The packet does not conform if there are insufficient tokens in the bucket, and the
contents of the bucket are not changed. Non-conformant packets can be treated in
various ways:
Algorithm
• A token is added to the bucket every seconds
• The bucket can hold at the most tokens. If a token arrives when the bucket is full, it is
discarded.
• When a packet (network layer PDU) of n bytes arrives,
• if at least n tokens are in the bucket, n tokens are removed from the bucket, and the
packet is sent to the network.
• if fewer than n tokens are available, no tokens are removed from the bucket, and the
packet is considered to be non-conformant.
22. What is a bridge? Explain the various types of bridges.Repeated [Nov-Dec 2018]
• It is type of computer network device that provides interconnection with other bridge
network that uses same protocol
Types of bridges:
• Transparent bridges: The term transparent refers to the fact that stations are
completely unaware of the presence of bridges in the network. When a transparent is
added or removed from the system, reconfiguration of the stations in unnecessary.
• Source Routing Bridges: Source routing bridges were developed by the IEEE 802.5
Committee and are primarily used to interconnect token-ring networks. Unlike
transparent bridges where filtering frames, forwarding and blocking functions are
implemented in bridges, source routing bridges put these burden on the end stations.
The main idea of source routing is that each station should determine the route to the
destination when it wants to send a frame and therefore include the route information
in the header of the frame.
24.Illustrate open-loop congestion control
Open-loop policies, policies are applied to prevent congestion before it happens. In these
mechanisms, congestion control is handled by either the source or destination.
• Admission control: Admission control is a quality-of-service mechanism that computes
the resource requirements of a network flow and determines whether the resources are
available for the flow. If the QoS of the new flow can be satisfied without violating QoS
of existing flow, the flow is accepted; otherwise, the flow is rejected.
• Traffic shaping: one of the main causes of congestion is that traffic is often bursty data.
When a source tries to send packets; it may not know exactly what its traffic flow looks
like. if the source wants to ensure that the traffic flow conforms to the parameters of
QoS, it should alter its traffic flow
25.Explain different types of bridges in computer networks.
There are three types of bridges
1. Transparent bridges: The term transparent refers to the fact that stations are
completely unaware of the presence of bridges in the network. When a transparent is
added or removed from the system, reconfiguration of the stations is unnecessary.
A transparent bridge performs the following 3 basic functions:
A. Forwards frames from one LAN to another
B. Learns where stations are attached to the LAN
C. Prevents loops in the topology
2. Source Routing bridges: It was developed by the IEEE 802.5 committee an are primarily
used to interconnect token ring networks Unlike transparent bridges where filtering
frames, forwarding and blocking functions are implemented in bridges, source routing
bridges put these burden on the end stations. The main idea of this is that reach station
should determine the route to the destination when it wants to send a frame and therefore
include the route information in the header of the frame. thus the problem boils down to
finding good routes efficiently.
The solution is to first find all the paths from source to destination then calculate the
distance for all the route the less distance path will be taken for transferring the frame
from source to destination
As an example, if S1 wants to send a frame to S2, then a possible route is
a. LAN 1 – B1 – LAN 2 – B4 – LAN 4
b. LAN 1 – B2 – LAN 3 – B5 – LAN 4
c. LAN 1 – B2 – LAN 3 – B3 LAN 2 – B4 – LAN 4
d. LAN 1 – B2 – LAN3 – B6 – LAN 5 – B7 LAN 4
2. Mixed Media Bridges: Bridges that interconnect LAN of different type are referred to
as Mixed Media Bridge. This type of interconnection is not simple. Mixed media bridges
can be discussed in terms of the interconnection of Ethernet and token ring LAN. These
two LAN differ in their frame structure, their operation and their speed, and the bridge
needs to take these difference into accounts.
Section D
26. Compare packet switching with circuit switching.
Packet switching Circuit switching
1. Packet switching is connectionless which 1. Circuit switching is a type of networking
means the data is transmitted into small units protocol in which a dedicated channel is
called packets and a dynamic route is established between two end points in a network
established for each pack for the duration of a transmission. Data transfer
takes place after the circuit is established
2.Data is divided into small units called packets 2. A physical path is established which is
with each packet carrying small header dedicated to a single connection between the two
containing signalling information end points.
3.Dynamic route is established for each packet 3. Data transmission takes place after the circuit
which carries the routing information. is established for the duration of the
transmission.
4.Each data packet may take a different route to 4. A dedicated routing path is followed
reach the destination, making it flexible throughout the transmission and no other user
throughout the session. is allowed to use the circuit.
5. There is no end to end reservation of links. 5. It follows a uniform path throughout the
session.
6.Each data packet carries the signalling 6. Data doesn’t carry the signalling information
information containing source and destination and moves on its own.
addresses in the packet header.
7.It’s mainly used for data and voice 7. It’s ideal for voice communication and the
communication, and the delay is not uniform. delay is uniform.
34. Explain TCP/IP model with a neat diagram.
TCP/IP model layers
TCP/IP functionality is divided into four layers, each of which include specific protocols.
• The application layer provides applications with standardized data exchange. Its protocols
include the Hypertext Transfer Protocol (HTTP), File Transfer Protocol (FTP), Post Office
Protocol 3 (POP3), Simple Mail Transfer Protocol (SMTP) and Simple Network
Management Protocol (SNMP).
• The transport layer is responsible for maintaining end-to-end communications across the
network. TCP handles communications between hosts and provides flow control,
multiplexing and reliability. The transport protocols include TCP and User Datagram
Protocol (UDP), which is sometimes used instead of TCP for special purposes.
• The network layer, also called the internet layer, deals with packets and connects
independent networks to transport the packets across network boundaries. The network
layer protocols are the IP and the Internet Control Message Protocol (ICMP), which is
used for error reporting.
• The physical layer consists of protocols that operate only on a link -- the network
component that interconnects nodes or hosts in the network. The protocols in this layer
include Ethernet for local area networks (LANs) and the Address Resolution Protocol
(ARP).
35. Explain OSI reference model in detail.
The model is proposed by the ISO (International Standards Organization). It is called ISO-
OSI (Open Systems Interconnection) Reference Model because it deals with connecting
open systems. The OSI Reference Model has 7 layers.
a. Physical Layer:
• It is concerned with the actual physical attachment to the network i.e. it deals with the
means of connecting two nodes in a network.
• It deals with transmitting raw bits over the communication channel.
• The design issues here deal with mechanical, electrical, timing interfaces and the
physical transmission medium which lies below the physical layer.
b. Data Link Layer:
• It breaks the data into frames and passes it to the network layer. It also does:
• Error Control: To control transmission errors.
• Flow Control: To prevent the drowning of slow receiver by fast transmitter.
• Access Control: Control access to the shared channel. A special section of the DLL
called the Medium Access Control sub layer deals with this.
c. Network Layer:
• It has the responsibility of preforming source to destination delivery of packets. It
focuses on:
• Dynamic routing
• Congestion control
• Quality of service
• Addressing
• Integration of heterogeneous networks.
e. Transport Layer:
• It deals withControl of data flow in the network.
• Ensuring no loss of data.
• Ensuring that destination is not inundated with data.
• Ensuring that all pieces arrive correctly at the other end.
• It is a true end to end layer.
e. Session Layer: Its features are:
• Dialogue Control: Keeping track of whose turn it is to transmit.
• Token management: Preventing two parties from attempting the same critical operation
at the same time.
• Synchronization: Check pointing long transmissions to allow them to continue from
where they were after a crash.
f. Presentation Layer: It is concerned with the following:
• Syntax of information.
• Semantics of information.
• Compression
• Encoding of information.
g. Application Layer: Application layer provide user interface and support for services
like:
• E-mail.
• Remote file access.
• File transfer
• Shared database management.
Advantages of OSI Reference Model:
• OSI Model distinguish between the services, interfaces and protocols.
• Protocols of OSI Model are very well hidden.
• They can be replaced by new protocols as technology changes.
• Supports connection oriented as well as connectionless service.
Disadvantages of OSI Reference Model:
i. Model was devised before the invention of protocols.
ii. Fitting of protocols is a tedious task.
36. Illustrate polar line encoding scheme.
A: Non Return to Zero (NRZ)

NRZ Codes has 1 for High voltage level and 0 for Low voltage level. The main behavior of
NRZ codes is that the voltage level remains constant during bit interval. The end or start of a
bit will not be indicated and it will maintain the same voltage state, if the value of the previous
bit and the value of the present bit are same.
The following figure explains the concept of NRZ coding.
If the above example is considered, as there is a long sequence of constant voltage level and
the clock synchronization may be lost due to the absence of bit interval, it becomes difficult
for the receiver to differentiate between 0 and 1.
There are two variations in NRZ namely −
NRZ - L (NRZ – LEVEL)
There is a change in the polarity of the signal, only when the incoming signal changes from 1
to 0 or from 0 to 1. It is the same as NRZ, however, the first bit of the input signal should have
a change of polarity.
NRZ - I (NRZ – INVERTED)
If a 1 occurs at the incoming signal, then there occurs a transition at the beginning of the bit
interval. For a 0 at the incoming signal, there is no transition at the beginning of the bit
interval.
NRZ codes has a disadvantage that the synchronization of the transmitter clock with the
receiver clock gets completely disturbed, when there is a string of 1s and 0s. Hence, a separate
clock line needs to be provided.
Bi-phase Encoding
The signal level is checked twice for every bit time, both initially and in the middle. Hence, the
clock rate is double the data transfer rate and thus the modulation rate is also doubled. The
clock is taken from the signal itself. The bandwidth required for this coding is greater.
There are two types of Bi-phase Encoding.
• Bi-phase Manchester
• Differential Manchester
Bi-phase Manchester
In this type of coding, the transition is done at the middle of the bit-interval. The transition for
the resultant pulse is from High to Low in the middle of the interval, for the input bit 1. While
the transition is from Low to High for the input bit 0.
Differential Manchester
In this type of coding, there always occurs a transition in the middle of the bit interval. If
there occurs a transition at the beginning of the bit interval, then the input bit is 0. If no
transition occurs at the beginning of the bit interval, then the input bit is 1.
The following figure illustrates the waveforms of NRZ-L, NRZ-I, Bi-phase Manchester and
Differential Manchester coding for different digital inputs.
37.Explain the following:
a) Modems:Modem is abbreviation for Modulator – Demodulator. Modems are used for data
transfer from on computer network to another computer network through telephone lines. The
computer network works in digital mode, while analog technology is used for carrying
massages across phone lines.
Modulator converts information from digital mode to analog mode at the transmitting end
and demodulator converts the same from analog to digital at receiving end. The process of
converting analog signals of one computer network into digital signals of another computer
network so they can be processed by a receiving computer is referred to as digitizing.
Types of Modems
• Modems can be of several types and they can be categorized in a number of ways.
• Categorization is usually based on the following basic modem features:
1. Directional capacity: half duplex modem and full duplex modem.
2. Connection to the line: 2-wire modem and 4-wire modem.
3. Transmission mode: asynchronous modem and synchronous modem.
b).Congestion control.Congestion is an important issue that can arise in packet switched
network. Congestion is a situation in Communication Networks in which too many packets are
present in a part of the subnet, performance degrades. Congestion in a network may occur
when the load on the network (i.e. the number of packets sent to the network) is greater than
the capacity of the network (i.e. the number of packets a network can handle.). Network
congestion occurs in case of traffic overloading.
38. Explain any routing algorithms.
Routing is process of establishing the routes that data packets must follow to reach the
destination. In this process, a routing table is created which contains information regarding
routes which data packets follow. Various routing algorithm are used for the purpose of
deciding which route an incoming data packet needs to be transmitted on to reach
destination efficiently.
Classification of Routing Algorithms: The routing algorithms can be classified as follows:
1.Adaptive Algorithms –These are the algorithms which change their routing decisions
whenever network topology or traffic load changes. The changes in routing decisions are
reflected in the topology as well as traffic of the network. Also known as dynamic routing,
these make use of dynamic information such as current topology, load, delay, etc. to select
routes. Optimization parameters are distance, number of hops and estimated transit time.
2.Non-AdaptiveAlgorithms–These are the algorithms which do not change their routing
decisions once they have been selected. This is also known as static routing as route to be
taken is computed in advance and downloaded to routers when router is booted.
Further these are classified as follows:
(a) Flooding – Flooding is the static routing algorithm. In this algorithm, every incoming
packet is sent on all outgoing lines except the line on which it has arrived.
(b) Random walk – In this method, packets are sent host by host or node by node to one
of its neighbours randomly. This is highly robust method which is usually implemented
by sending packets onto the link which is least queued.
SOLUTION BANK
BCA 502T SOFTWARE ENGINEERING

BCA502T : SOFTWARE ENGINEERING
Unit - I
Introduction: Software Products and Software process, Process models: Waterfall modal, Evolutionary
Development, Bohemia’s Spiral model, Overview of risk management, Process Visibility,
Professional responsibility. Computer based System Engineering: Systems and their environment,
System Procurement, System Engineering Process, System architecture modelling. Human Factors,
System reliability Engineering. Requirements and Specification: The requirement Engineering
Process, The Software requirement document, Validation of Evolution of requirements, Viewpoint –
oriented & method based analysis , system contexts , Social 7 organizational factors . Data flow ,
Semantic, Objects, models , Requirement Specification, Non functional requirement.[ 12 Hours ]
Unit - II
Software Prototyping: Prototyping in software process, Prototyping techniques, User interface
prototyping. Software Design: Design Process, Design Strategies, Design Quality , System Structuring
control models, Modular decomposition , Domain Specific architecture.[ 12 Hours ]
Unit - III
Object Oriented& function oriented design: Objects, object Classes and inheritance Object
identification, An object oriented design example, Concurrent Objects, Data flow design Structural
decomposition, Detailed Design, A Comparison of design Strategies.User interface design: Design
Principles, User System interaction, Information Presentation, User Guidance, Interface Evaluation.
[ 12 Hours ]
Unit - IV
Software Reliability and reusability : Software reliability metrics , Software reliability Specification ,
Statistical testing ,Reliability Growth modeling, Fault avoidance & tolerance, Exception handling &
defensive programming , Software development with reuse, Software’ development for reuse ,
Generator based reuse, Application System Portability.[ 12 Hours ]
Unit - V
Software Verification and Validation : The testing Process , Test Planning & Strategies, Black Box ,
Structural, interface testing , Program inspections , Mathematically based verification, Static analysis
tools, Clean room software development. Management Issues: Project management, Quality
management, Software cost estimation, Softwaremaintenance. [ 12 Hours ]
Text book
1. Ian Sommerville – Software Engineering, 9th Edition, Pearson Education Ltd, 2010.
Reference Books
1. Roger S. Pressman – Software Engineering, A Practitioner’s approach, 7th Edition,
McGRAW-HILL Publication, 2010.
2. Pankaj Jalote, “An integrated approach to Software Engineering”, 3rd Edition, Narosa
Publishing House, 2013.
BCA502T : SOFTWARE ENGINEERING
BLUE PRINT
Question paper pattern for theory has two sections :
Section – A :Contains 12 questions, out of which a student has to answer 10 questions. Each question
carries 2 marks ( 10 x 2 = 20 )
Section – B :Contains 8 full questions, out of which 5 question to be answered. Each full question
Section – C :Contains 5 full questions with sub questions(a) & (b), out of which 3 questions to be
answered. Each full question carries 15 marks (3x 15 = 45)
Section – D :Contains 2 full questions, out of which 1 question to be answered. Each full question
SECTION SECTION SECTION SECTION

UNIT CHAPTER A B B D
2 MARKS 5 MARKS 15 MARKS 15 MARKS
Introduction: Software Products
I 4 2 1 1
and Software process,
II Software Prototyping 1 1 1
Object Oriented& function

III 2 2 1
oriented design
Software Reliability and
IV 2 1 1
reusability
Software Verification and
V 3 2 1
Validation 1
TOTAL 12 8 5
2
ANSWER ANSWER ANSWER ANSWER
ANY 10 ANY 5 ANY 3 ANY 1
10
TOTAL MARKS 20 25
45
UNIT-I
[ Nov / Dec 2015 ]
1. What is software product ? Name two types of software product.
2. What is the difference between software engineering and system engineering?
3. What is system decommissioning ?
4. Define volatile requirement.
5. What are functional requirement? Give example.
[ Nov / Dec 2016 ]
6. What is customized software product? Give an example.
7. What is COTS?
8. What is feasibility study?
[ Nov / Dec 2017 ]
9. Define system.
10. What are the two types of software products?
11. Define SRS
[ Nov / Dec 2018 ]
12. Define Software engineering?
[ TMAQ - Important Tutor Mark Assignment Questions ]

13. Define SDLC. List the different phases of SDLC.
14. What are the goals of software engineering?
15. What are the characteristics of software process?
16. Differentiate between generic product & customized product.
17. What are the characteristics of software?
18. Differentiate between product & process in software engineering.
19. Name different types of SDLC models.
20. What is system integration ? Explain the two types of system integration.
21. What are non-functional requirement? Give example.
22. Define DFD. Explain different symbols.
UNIT-II
[ Nov / Dec 2015 ]
1. Define cohesion and coupling.
2. Define prototype
[ Nov / Dec 2016 ]
Define coupling
3. Define object class.
[ Nov / Dec 2017]
Define cohesion.
4. Define Evolutionary prototyping.
[ Nov / Dec 2018]
What is coupling? Mention any two types.
5. What is loose coupling?
6. What is tight coupling?
7. Difference between generic model and reference model.
8. What is software design?
9. What are the objectives of prototyping?
10. Why software design is important?
11. Define throw-away prototyping.
UNIT-III
[ Nov / Dec 2015 ]
1. Write any two characteristics of GUI.
2. What is object oriented design.
[ Nov / Dec 2016 ]
3. What are OOD and OOP?
4. What is user interface design?
[ Nov / Dec 2017 ]
5. Define object and class.
What are the characteristics of GUI.
[ Nov / Dec 2018 ]
What are OOD and OOP?
6. What are the advantages of GUI.

7. Name the different styles of user-system interaction.
8. What are advantages and disadvantages of command languages?
9. Explain two types of interface evaluation.
10. Define object.
11. Define object class.
UNIT-IV
[ Nov / Dec 2015 ]
1. Define reliability. Mention its types.
[ Nov / Dec 2016 ]
2. Difference between fault and failure.
[ Nov / Dec 2017 ]
3. Define reliability.
[ Nov / Dec 2017 ]
4. What is fault detection and recovery?
5. Define risk.
6. What is software product line?
7. Define software reliability.
8. Define hardware reliability.
9. Define software reliability metrics.
10. What is RGM?
11. What are the factors on which reliability depends?
UNIT-V
[ Nov / Dec 2015 ]
1. What is test case ? Give one example for test case.
2. What is quality assurance? What is the purpose of quality assurance?
3. List different phases of project management.
[ Nov / Dec 2016 ]
4. What do you mean by cyclometic complexity?
5. Define quality planning.
6. What is software maintenance?
[ Nov / Dec 2017 ]
7. Differentiate between verification and validation/
8. What is test case?
[ Nov / Dec 2018 ]
9. Define equivalence class portioning.
Define quality assurance.
10. Define project management
Differentiate between verification and validation.
1. Define Black box testing.
2. What are the advantages and disadvantages of V-model.
3. Define quality assurance.
4. Explain the importance of standards.
SECTION – B( 5 Marks)
UNIT-I
[ Nov / Dec 2015 ]
1. Discuss the challenges of software engineer.
2. Explain system procurement process in detail.
[ Nov / Dec 2016 ]
Discuss the challenges of software engineer.
3. Explain the phases of requirement elicitation and analysis process.
[ Nov / Dec 2017 ]
4. Explain water fall model with its advantages and disadvantages.
5. What are volatile requirements? Explain the classification of volatile requirements.
[ Nov / Dec 2018 ]
6. Describe system procurement process.
7. Explain the IEEE structure of SRS document.

1. Explain spiral model with advantages and disadvantages.
2. What is data flow diagram? Explain various notations using in data flow model with an
example.
3. Explain different requirement validation check.
4. What is SDLC ? Explain the different phases of SDLC with neat diagram.
5. Describe system architectural modeling with an example.
6. What is software process? What are the activities of software process?
UNIT-II
[ Nov / Dec 2015 ]
1. Explain Prototyping model.
[ Nov / Dec 2016 ]
2. Describe in detail the design principle
[ Nov / Dec 2017 ]
3. Explain two types of prototyping with advantages and disadvantages
[ Nov / Dec 2018 ]
4. Describe design principles
UNIT-III
[ Nov / Dec 2015 ]
1. Describe any two styles of use interaction
[ Nov / Dec 2016 ]
2. What are the methods of object identification with an example
[ Nov / Dec 2017 ]
3. Explain different phases of user system interaction
[ Nov / Dec 2018 ]
4. Write a short note on Data flow design, structural decomposition.
UNIT-IV
[ Nov / Dec 2015 ]
1. Explain different types of software reliability metrics.
2. What are the different types of interface errors
[ Nov / Dec 2016 ]
3. Write a note on system reliability engineering.
4. Discuss hardware and software reliability metrics.
[ Nov / Dec 2017 ]
5. Give the classification of failures with examples
6. What is fault tolerance? Explain the two approaches of software fault tolerance.
[ Nov / Dec 2018 ]
7. Write a short note on reliability growth modeling.
UNIT-V
[ Nov / Dec 2015 ]
1. Write a note on black box testing
[ Nov / Dec 2016 ]
2. Explain thread testing with a diagram
[ Nov / Dec 2017 ]
3. Difference between Black box and white box testing
[ Nov / Dec 2018 ]
4. Explain the content of test plan
SECTION –C , D & E
UNIT-I
[ Nov / Dec 2015 ]
1. Explain Spiral model with neat diagram. Discuss advantages and disadvantages.
2. Explain requirement elicitation and analysis process.
3. Explain IEEE structure of SRS
4. Write SRS for library system.
[ Nov / Dec 2016 ]
5. Explain water fall model with a neat diagram. Mention its merits and demerits
[ Nov / Dec 2017 ]
6. Explain system engineering process with a neat diagram.
[ Nov / Dec 2018 ]
7. Explain the fundamental process activities involved in SDLC with neat diagram.
UNIT-IV & UNIT V
[ Nov / Dec 2015 ]
1. Explain quality control in detail.
[ Nov / Dec 2016 ]
2. Write a note on Risk management
3. Write a note on COCOMO model.
[ Nov / Dec 2017]
4. Explain different types of software maintenance.
5. Explain the contents of test plan template.
[ Nov / Dec 2018]
1. Explain clean room software development process.
2. Explain software reuse.
3. Explain types of cohesion.
4. Explain function oriented design.
1.Explain waterfall model with its advantages and disadvantages?
Waterfall model was developed by Royce in 1970. this model is also referred as linear
sequential model or classical life cycle model. This model suggests a systematic, sequential
approach to software development that begins at system level and progresses through
analysis, design, development, coding, testing and maintenance.
Advantages of waterfall model:

• Easy to understand and implement.
• Widely used and known
• Identifies deliverables and milestones
• The waterfall model redeems the software development process of the code and fix
problems
• It allows for communication between customer and developer and specifies what will
be delivered when and at what cost.
Disadvantages:
• The waterfall model requires the user to define system requirements early in the
project.
• This model is rigid because it assumes that a phase is fully complete before another one
commences.in reality two or more phases may proceed in parallel.
• Interaction with the user takes place right in the beginning while firming up
requirements and then at the time of implementation. this leaves a huge gap in-
between phases and does not in any way build a method of cross checking user
requirements.
2. Explain IEEE structure of SRS document.
The IEEE standards recognize the fact that different projects may require their requirements
to be organized differently, that is no method that is suitable for all projects. It provides
different ways of structuring the SRS. The first two sections of SRS are the same in all of
them. IEEE suggests the following structure for requirements document.
1.Introduction
1.1 Purpose of the requirement’s document
1.2 Scope of the product
1.3 Definitions, acronyms and abbreviations
1.4 References to supporting documents
1.5 Overview of rest of SRS
2.General description
2.1 Product perspective
2.2 Product functions
2.3 User characteristics
2.4 General constraints
2.5 Assumptions and dependencies.
3.Functional requirements
4.Non-functional requirements
5.System architecture
6.System models
7.Appendices
3. Explain the phases of requirement elicitation and analysis process.

The phases of requirement elicitation and analysis include:
• Requirements discovery
• Requirement classification and organization
• Requirement prioritization and negotiation
• Requirements specification
Requirement discovery: This is the process of interacting with stakeholders of the system to
discover their requirements. Domain requirements from stakeholders and documentation are
also discover during this activity.
Requirements classification and organization:This activity takes the unstructured collection

of requirements, groups related requirements, and organizes them into coherent clusters.
Requirements prioritization and negotiation: Inevitably, when multiple stakeholders are

involved, requirements will conflict. This activity is concerned with prioritizing requirements
and finding and resolving requirements conflicts through negotiation.
Requirements specification:The requirements are documented and input into the next round
of the spiral. Formal or informal requirements documents may be produced.
4. Explain prototyping model.

• The prototyping model is a systems development method in which a prototype is built,
tested and then reworked as necessary until an acceptable outcome is achieved from
which the complete system or product can be developed.
Step 1: Requirements gathering and analysis : A prototyping model starts with requirement
analysis. In this phase, the requirements of the system are defined in detail. During the
process, the users of the system are interviewed to know what is their expectation from the
system.
Step 2: Quick design. The second phase is a preliminary design or a quick design. In this
stage, a simple However, it is not a complete design. It gives a brief idea of the system to the
user. The quick design helps in developing the prototype .design of the system is created.
Step 3:, Building Prototype an actual prototype is designed based on the information gathered
from quick design. It is a small working model of the required system.
Step 4: Engineer Product. In this stage, the proposed system is presented to the client for an
initial evaluation. It helps to find out the strength and weakness of the working model.
Comment and suggestion are collected from the customer and provided to the developer.
Step 5: Refining prototype.If the user is not happy with the current prototype, you need to
refine the prototype according to the user's feedback and suggestions.
Step 6: Customer evaluation. Once the final system is developed based on the final
prototype, it is thoroughly tested and deployed to production. The system
undergoes routine maintenance for minimizing downtime and prevent large-scale
failures.
5. Explain evolutionary prototyping with an example.

Evolutionary Prototyping –
In this method, the prototype developed initially is incrementally refined on the basis of
customer feedback till it finally gets accepted. In comparison to Rapid Throwaway
Prototyping, it offers a better approach which saves time as well as effort. This is because
developing a prototype from scratch for every iteration of the process can sometimes be very
frustrating for the developers.
Advantages –
• The customers get to see the partial product early in the life cycle. This ensures a greater
level of customer satisfaction and comfort.
• New requirements can be easily accommodated as there is scope for refinement.
• Missing functionalities can be easily figured out.
• Flexibility in design.
Disadvantages –
• Costly w.r.t time as well as money.
• There may be too much variation in requirements each time the prototype is evaluated
by the customer.
• It is very difficult for the developers to accommodate all the changes demanded by the
customer.
• Developers in a hurry to build prototypes may end up with sub-optimal solutions.
6. Explain the principles of software design.

Software design is both a process and a model. The design process is a sequence of steps that
enable the designer to describe all aspects of the software to be build.
• Top-Down or Bottom-up
• Problem Partitioning
• Abstraction
• Modularity
1. Problem Partitioning: Problem partitioning is a method of adopting the principle
of divide and conquer to get the solution to the problem.
2. Abstraction: Abstraction is the method of describing a program function. High
level of abstraction states the solution to the problem. Low level abstraction deals
with procedural details. Types of abstraction are : Data abstraction, Procedural
Abstraction
andControl Abstraction
3. Modularity: Software is divide into separately named and addressable components,

often called modules that are integrated to satisfy problem requirements. Module
contains instructions, processing logic and data structures.
• Top-Down and Bottom-Up Strategies: Top-Down takes the whole software system
as one entity and then decomposes it to achieve more than one sub system or
component based on some characteristics until the lowest level of system in the top-
down hierarchy is achieved.
The bottom-up design model starts with most specific and basic components. It keeps
creating higher level components until the desired system is not evolved as one single
component.
7. Explain function oriented design with example.

A function-oriented design strategy relies on decomposing the system into a set of
interacting functions with a centralized system state shared by these functions.
General Procedure :
1. Start with a high level description of what the software / program does.
Refine each part of the description one by one by specifying in greater
details the functionality of each part. These points lead to Top-Down
Structure.
2. Problem in Top-down design method
3. Solution to the problem
The various activities in a function oriented design process are :
(b) Data-flow design : This shows how data passes through the system and is
transformed by each system functions.
(c) Structural decomposition : Model illustrates how functions are decomposed
into sub-functions using graphical structure charts.
(d) Detailed data description : Describe the entities in the design and their
interfaces. These descriptions may be recorded in a data dictionary.
8. Explain different types of cohesion with example.

Cohesion measures the semantic strength of relationship between components within a
functional unit.
Several levels of cohesion can be identified in necessary order of strength, these are :
(a) Coincidental cohesion : The parts of a component are not related but simply
bundled into a single component.
Ex : Module miscellaneous functions such as : use customer record, display
customer record, read transaction record.
(b) Logical cohesion : Components that perform similar functions such as input,
error handling and so on are put together in a single document.
Ex : if record-type is student then
display student record
else if record-type is staff then
display staff record
(c) Temporal cohesion : A temporally cohesive module is one whose elements are
functions that are related in time.
Ex :Set counter to 0, Open student file, Clear error message variable, initialize
array.
(d) Communicational Cohesion : All of the elements of a component operate on the

same input data or produce the same output data.
Ex : Use customer account, find customer name, find customer loan balance etc.
(e) Procedural cohesion : A procedurally cohesive module is on whose elements are

involved m different activities but the activities are sequential.
Ex : Use out record, write out record, read in record, pad numeric fields to
zero.
(f) Functional cohesion :Each part of the component is necessary for the execution
of a single function.
Ex: Compute cosine of angle, Read transaction record, Assign seat to airline
passanger.
9. Explain five types of user system interaction
A user interface, also sometimes called a human-computer interface, comprises both
hardware and software components. It handles the interaction between the user and the
system.There are different ways of interacting with computer systems which have
evolved over the years. There are five main types of user interface:
• command line (cli)
• graphical user interface (GUI)
• menu driven (mdi)
• form based (fbi)
• natural language (nli)
Command Line Interface

Command line interfaces are the oldest of the interfaces,It involves the computer
responding to commands typed by the operator. This type of interface has the
drawback that it requires the operator to remember a range of different commands
and is not ideal for novice users.
Graphical UI
Graphical user interfaces (GUI) are sometimes also referred to as WIMP because they
use Windows, Icons, Menus and Pointers. Operators use a pointing device (such as a
mouse, touchpad or trackball) to control a pointer on the screen which then interacts
with other on-screen elements.
Menu Driven
A menu driven interface is commonly used on cash machines (also known as automated
teller machines ( ATM's), ticket machines and information kiosks (for example in a
museum). They provide a simple and easy to use interface comprised of a series of
menus and sub-menus which the user accesses by pressing buttons, often on a touch-
screen device.
Form Based
A form-based interface uses text-boxes, drop-down menus, text areas, check boxes,
radio boxes and buttons to create an electronic form which a user completes in order to
enter data into a system. This is commonly used on websites to gather data from a user,
or in call centres to allow operators to quickly enter information gathered over the
phone.
Natural language
A natural language interface is a spoken interface where the user interacts with the
computer by talking to it. Sometimes referred to as a 'conversational interface', This is
the kind of interface used by the popular iPhone application
called Siri and Cortana in Windows
10. What is fault tolerance ? Explain the two approaches to software fault tolerance.
This strategy assumes that residual faults remain in the system. Facilities are provided
in the software to allow operation to continue when these faults cause system failures.
Two approaches to software fault tolerance are:
1) N-version programming: using a common specification, the software system is
implemented in a number of different teams. These versions are executed in
parallel. Their outputs are compared using a voting system and inconsistent
outputs are rejected. At least 3 versions of the system should be available.
2)Recovery Blocks: this is a finger grain approach to fault tolerance. Each program
component is executed successfully. It also includes alternative code, which allows the
system to back-up and repeat the computation if the test detects a failure. Unlike N-
version programing, the implementation is different rather than independent
implementation of the same specification. They are executed in a sequence rather than
independent implementation of the same specification. They are executed in sequence
in sequence rather than in parallel.
11. Explain the different types of software reliability matrices.

Software reliability metrics are units of measure for system reliability. System reliability is
measured by counting the number of operational failures and relating these to demands
made on the system at the time of failure.
The metrics are :
(a) Rate of occurrence of failures (ROCOF) –This is a measure of the frequency of
occurrence in which unexpected behaviour is likely to occur.
(b) Mean Time to Failure (MTTF) – MTTF is the average time between two successive
failures observed over a large number of failures.
(c) Mean Time to Repair(MTTR) –Once the failure occurs, some time is required to fix
the error that is nothing but mean time to repair.
(d) Mean Time between Failure(MTBF) – This metrics is the combination of MTTF and
MTTR. Thus as MTBF of 300 hours indicates that once the failure occurs the next
failure is expected to occur only after 300 hours.
(e) Probability of Failure on Demand(POFOD) – Unlike the other metrics explained above
this metrics does not explicitly involved in the time measurements. POFOD metrics
measures the systems falling when a service request is made.
(f) AVAIL :The availability of system is a measure of how well the system is available for
the use over a given time.
12. What is reliability growth modelling ? Explain its types.

A GRM is a mathematical model. It explains how software reliability improves as the errors
are detected and repaired. The model can be used to predict when a particular level of
reliability can’t be attained. Thus RGM can be used to determine when to stop testing to
attain a given reliability.
Software reliability growth models have been grouped into two classes of models - concavel
and S-shaped. These two model types are shown in Figure 2-2. The most important thing
about both models is that they have the same asymptotic behavior, i.e., the defect detection
rate decreases as the number of defects detected (and repaired) increases
Although several different growth models have been proposed.
There are two types of steps function model as follows:
• Equal step Function

• Random step function
1.Equal Step Function: The model has been designed by Jelinki and Moranda. In this model it
is assumed that the reliability increases by a constant-increment each time an error is
detected and repaired.
The demerit of this model is that it assumes that all defects contribute equally to the reliability
growth. However in reliability some defects are simple and some are more complex. Hence the
reliability also varies.
2. Random step Function: This model has been designed by little wood and Verall. The model
allows for negative reliability growth to reflect the fact that when a repair is carried out it
may introduce additional errors.
The model explains that as the errors are repaired the average improvement in reliability per
repair decreases. Therefore, contribution of errors to reliability improvement is random
variable.
13. Explain COCOMO model in detail.

Cocomo (Constructive Cost Model) is a regression model based on LOC, i.e number of Lines
of Code. It is a procedural cost estimate model for software projects and often used as a
process of reliably predicting the various parameters associated with making a project such
as size, effort, cost, time and quality. It was proposed by Barry Boehm in 1970 and is based on
the study of 63 projects, which make it one of the best-documented models.
Bohem’sCocomo model takes three forms :
• Model 1 : Basic Cocomo model : This model is the starting point for project estimation
which computes software development effort & cost as function of program size expressed
in estimated lines of code.
Basic cocomo model provides an approximate estimation of software costs and is given by
E = a (KLOC) b
PRODUCT COMPLEXITY A B
Simple 2.4 1.05
Moderate 3.0 1.12
Embedded 3.6 1.20
• Model 2: Intermediate Cocomomodel :Intermediate cocomo makes use of cost drives and
their multiples to estimate the cost.Model utilizes 15 drives such as product attribute,
hardware attribute, personal attribute, project attribute etc for cost estimation. Ex:
Computers, skilled professional, administrative staff etc.
b
E = (a (KLOC) ) * EAF
• Model 3: Complete Cocomo model :Complex systems are made up of sub-systems, each
parameter of a module must be summed up to get complete cost estimation. There are six
phases in this model they are :
• Planning and requirements
• System design
• Detailed design
• Module code and test
• Integration and test
• Cost Constructive model
14. Explain various levels of testing

Testing process is the creation of a test strategy or plan device to test the system. The
stages/levels of testing process are :
(a) Unit Testing : Individual components are tested to ensure that they operate correctly.
Each component is tested independently without referring other system.
(b) Module Testing : A module is a collection of dependent components such as an object
class, an abstract data type or some collection of procedures and functions.
(c) Integration Testing : This phase involves collection of modules which have been
integrated into sub-systems. Sub-systems may be independently designed and
implemented.
(d) System Testing : The sub-systems are integrated to make-up the entire system. It is
also concerned with validating that the system meets its functional and non-functional
requirements.
(e) Acceptance Testing : This is the final stage in the testing process before the system is
accepted for operational use.
15. Differentiate between Black box and White box testing

Software Testing can be majorly classified into two categories:
1. Black Box Testing is a software testing method in which the internal structure/ design/
implementation of the item being tested is known to the tester
2. White Box Testing is a software testing method in which the internal structure/ design/
implementation of the item being tested is not known to the tester.
BLACK BOX TESTING WHITE BOX TESTING
• It is a way of software testing in • It is a way of testing the software in

which the internal structure or the which the tester has knowledge about
program or the code is hidden and the internal structure r the code or the
nothing is known about it. program of the software.
• It is mostly done by software

• It is mostly done by software testers. developers.
• It is functional test of the software. • It is structural test of the software.
• This testing can be initiated on the

basis of requirement specifications • This type of testing of software is
document. started after detail design document.
• No knowledge of programming is • It is mandatory to have knowledge of

required. programming.
• It is the behavior testing of the

software. • It is the logic testing of the software.
• It is applicable to the higher levels • It is generally applicable to the lower

of testing of software. levels of software testing.
• It is also called closed testing. • It is also called as clear box testing.
• It is least time consuming. • It is most time consuming.
Example: search something on google by

using keywords Example: by input to check and verify loops
16. Write a note on risk management.

Risk management is a process that is used to minimize or eradicate risk before it can harm
the productivity of a software project. With only 28% of software projects finishing on time
and within budget. Risk and management of risk play an important role in software
development.
There are several types of risk that can occur during a software development project. This
include:
Generic Risks Generic threats across all projects.
For ex., Requirements change, loss of team members, loss of
funding.
Product-Specific Risks High level risks associated with the type of product being developed.
For ex., Availability of testing resources.
Project Risk Affect project schedule of resources
Product Risk Affect quality of performance of software
Business Risk Affect the viability of the software
There are also specific risks associated with team members, customers, tools, technology, time
estimation and team size. Many of these risks can be minimized by the development
methodology used for the project. There are many different tools that can be used to analyze
the risk apparent in a project and that can help to choose the best way to minimize or
eliminate the risk.
17. Explain evolutionary and throw-away prototyping.
EVOLUTIONARY PROTOTYPING: An approach to system development where an initial

prototype is produced and refined through a number of stages to the final system.
Advantages:
• Accelerated delivery of the system: rapid delivery and deployment are

sometimes more important than functionality or long-term software
maintainability.
• User engagement with the system: not only is the system more likely to meet
user requirements, they are more likely to commit to the use of the system.
Disadvantages:
• Management problem:
Existing management processes assume a waterfall model of development.
Specialist skills are required which may not be available in all development
teams.
• Maintenance problems:
Continual change tends to corrupt system structure so long-term maintenance
is expensive
Contractual problems.
THROW-AWAY PROTOTYPING: A prototype which is usually a practical implementation

of the system is produced to help discover requirements problems and then discarded. The
system is then developed using some other development process.
Advantages:
• The speed with each prototype is put together.
• It also focuses the user on only one aspect of the system so keeping their
feedback precise.
Disadvantages:
• One disadvantage with throw-away prototyping is that developers may be
pressurized by the users to deliver it as a final system.
• Another issue is that in throw-away prototype, all the efforts put in one loft
unlike evolutionary prototype.
18. Describe system procurement process in detail.
• System procurement is a process of acquiring a system for an organization to meet
some identified need.
• The contractor or sub-contractor minimizes the number of organization which the
procurer must deal with. The sub-contractor design and build parts of the system to a
specification produced by the principal contractor. Once completed these different
parts are integrated by the principal contractor. They are then delivered to the
customer by buying the system. The procurement of large hardware or software
system is usually based around some principal contractor.
• Depending on the contract the procurer may allow the principal contractor a free
choice of sub-contractor or may require principal contractor to choice sub-contractor
from an approved list.
19. Write a note on reliability engineering.
• Reliability is a complex concept which should always be considered at the level of

systems rather than at the individual component level. The components in the system
reliability namely, Hardware reliability, Software reliability, software reliable and
operator reliably.
A. Hardware reliability: What is the

probability of a hardware component
failing and how long does it take to
replace/repair that component.
B. Software reliability: How likely is that a software component will produce an incorrect
output? Software failure is usually distinct from hardware failure. In that software does not
ware out. It can continue to work even after an incorrect result has been produced.
3.Operator reliability: How likely is that the operator of a system will make an error?
20. Explain thread testing with a diagram.

• Thread testing is normally applied for testing real time application program. It is also
called event based system. Since it is an event based approach; tests are based on the
events which trigger system actions. Thread testing strategy which may be used after
processed or objects have been individually tested and integrated into sub-systems.
Consider the real time system made up of five interacting processes shown in the figure:
Some processes accept inputs from their own environment and generate output to that
environment. These inputs may be from sensors, keyboards or some other computer systems.
Similarly, outputs may be to control lines, other computer or user terminals. Inputs from the
environment are labeled with an “I” and output with an “O”. As part of the testing process,
the system should be analyzed to identify as many threads as possible.
21 .Explain the methods for object identification?
Step 1 BY MEANS OF NATURAL LANGUAGE GRAMMATICAL NOTATIONS:

using this methodology we can refer objects and its supported attributes as
“nouns” and finally various operations associated with these objects as “verbs”
Step 2 BY MEANS OF BEHAVIORAL APPROACH: in this mechanism considering

the system’s behavior is of prime focus. If possible all the participating entities
of a given system are assigned with a specific behavior. Hence ,in this way the
entities which are performing specific roles can be treated as objects of that
system
Step 3 BY MEANS OF SCENARIO BASED ANALYSIS PROCESS: in this

mechanism, a scenario of a given system is built and is analyzed deeply. Hence
during analysis of this system ,various objects and its specifications can be
easily determined
Step 4 BY USING FOLLOWING SPECIFICATION

Usage of events such as request/reply
Usage of interactions such as meetings
Usage of tangible entities such as car etc
Usage of locations such as offices
Usage of organizational units such as companies
22. What are volatile requirements? Explain the classification of volatile requirements.
Volatile requirements are unstable requirements and are likely to change during the system
development process or after the system has been put into (operational) use.
Classification of volatile requirements are:
Types Description
Mutable Requirements that changes due to the system environment in

requirements which the organization is operating
Emergent Requirements that emerge as the customers understanding of

requirements the system develops during the system development
Consequential Requirements that result from the introduction of the

requirements computer system. Introducing the computer system may
change the organizations processes and open up new ways of
working.
Compatibility Requirements that depend on other systems or business

requirements process within an organization.
23. Explain the different phases of system design process with a diagram?
System design is concerned with how the system functionality is to be provided by the
components of the system. The different phases are:
• Partition requirements: analyze the requirement and organize them into related
groups.
• Identify subsystems: identify sub system that can individually or collectively meet the
requirements. group of requirements are usually related to sub systems so this activity
and requirement partitioning may be carried out together.
• Assign requirements to sub system: assign the requirements to each identified sub
systems .in principle this should be straight forward if the requirements partitioning is
used to drive the sub system identification. in practice there is never a clean match
between requirements partitions and identified sub systems. limitations of COTS sub
system may mean that requirements have to be modified
• Specify subsystem functionality: the specific functions provided by each sub system are
specified. This may be seen as a part of the system design phase or if the subsystem is a
software system, part of the system requirement specification activity for that system.
relationship between sub system should also be identified at this stage.
• Define sub system interface: define the interfaces that are provided and expected by
each subsystems. once these interfaces have been agreed parallel development of the
subsystem becomes possible.
24. Explain types of software maintenance.
In a software lifetime, type of maintenance may vary based on its nature. It may be just a
routine maintenance tasks as some bug discovered by some user or it may be a large event in
itself based on maintenance size or nature. Following are some types of maintenance based on
their characteristics:
• Corrective maintenance: this includes modifications and updations done in order to

correct or fix problems, which are either discovered by user or concluded by user
error reports.
• Adaptive maintenance: this includes modifications and updations done in order to
correct or fix product up-to date and tuned to the ever changing world of technology
and business environment.
• Perfective maintenance: this includes modifications and updates done in order to keep
the software usable over long period of time. It includes new features, new user keep
the software usable over long period of time. It includes new features, new user
requirements for refining the software and improve its reliability and performance.
• Preventive maintenance: this includes modifications and updations to prevent future
problems of the software. It aims to attend problems, which are not significant at this
moment but may cause serious issues in future.
corrective Enhancement
Proactive Preventive Perfective
Reactive Corrective Adaptive
25. Discuss the Challenges of Software Engineer.

The software engineering discipline has been faced with a number of challenges over the
years, including those related to quality, management and cost estimation. Although
numerous approaches, including methods and frameworks have been introduced and adopted
as industry standards and/or best practices that have mitigated many of these issues. The
discipline is still faced with a number of challenges, and future challenges are also bound to
appear.
There are 3 challenges. They are :
1.The legacy Challenge
2.the heterogeneity challenge
3.The delivery challenge
4.Changing requirements
5.Schedule Optimism
• The legacy challenge: The majority of software systems which are in use today were
developed many years ago yet they perform critical business functions. The legacy
challenge is the challenge of maintaining and updating this software in such a way that
excessive costs are avoided and essential business services continue to be delivered.
• The heterogeneity challenge: Increasingly, systems are required to operate as

distributed systems across networks that include different types of computers and with
different kinds of support systems. The heterogeneity challenge is the challenge of
developing techniques to build dependable software which is flexible enough to cope
with this heterogeneity.
• The delivery challenge: Many traditional software engineering techniques are time-
consuming to deliver a quality software. However business operation today change
very frequently, so supporting software must also change rapidly. Software time
should be reduced without compromising on quality of a software product.
26. Write a shot note on user interface design.

System users often judge a system by its interface rather than its functionality. A poorly
designed interface can cause a user to make catastrophic errors. The poor user interface
design is the reason why many software systems are never used. Most users of business
systems interact with these systems through graphical user interfaces (GUI’s). In some cases,
legacy text-based interfaces are still used.
• GUI characteristics
Characteristics Description
Windows Multiple windows allow different information to be displayed

simultaneously on the user’s screen.
Icons represents different types of information. On some systems,

Icons
icons represent files; on others, icons represent processes.
Commands are selected from a menu rather than typed in a

Menus
command language.
A pointing device such as a mouse is used for selecting choices

Pointing
from a menu or indicating items of interest in a window.
Graphics Graphical elements can be mixed with text on the same display.
• Advantages of GUI
• They are easy to learn and use. Users without experience can learn to use the
system quickly.
• The user may switch quickly from one task to another and can interact with
several different applications. Information remains visible in its own window
when attention is switched.
• Fast, full-screen interaction is possible anywhere on the screen.
27. Explain Spiral Model in Detail.

• The Spiral Life Cycle Model is a type of iterative software development model which is
generally implemented in high risk projects. It was first proposed by Bohem in 1988.
• The spiral model is similar to the incremental model, with more emphasis placed on
risk analysis. In this system development method, it combines the best features of both,
waterfall model and prototype model. Each loop in the spiral represents a phase of the
software process. Thus, the innermost loop might be concerned with system feasibility,
the next loop with requirements definition, the next loop with system design and so on.
Each phase of Spiral Model is divided into four quadrants as shown in the above figure. The
functions of these four quadrants are :
• Objectives determination and identify alternative solutions: Requirements are

gathered from the customers and the objectives are identified, elaborated and analyzed
at the start of every phase.
• Identify and resolve Risks: During the second quadrant all the possible solutions are
evaluated to select the best possible solution. Then the risks associated with that
solution is identified and the risks are resolved using the best possible strategy
• Develop next version of the Product: During the third quadrant, the identified features
are developed and verified through testing. At the end of the third quadrant, the next
version of the software is available.
• Review and plan for the next Phase: In the fourth quadrant, the Customers evaluate
the so far developed version of the software. In the end, planning for the next phase is
started.
Advantages of Spiral Model:

• Risk Handling: Spiral Model is the best development model to follow due to the risk
analysis and risk handling at every phase.
• Good for large projects: It is recommended to use the Spiral Model in large and
complex projects.
• Flexibility in Requirements: Change requests in the Requirements at later phase can
be incorporated accurately by using this model.
• Customer Satisfaction: Customer can see the development of the product at the early
phase of the software development and thus, they habituated with the system by using
it before completion of the total product.
Disadvantages of Spiral Model:
• Complex: The Spiral Model is much more complex than other SDLC models.
• Expensive: Spiral Model is not suitable for small projects as it is expensive.
• Too much dependable on Risk Analysis: The successful completion of the project is very
much dependent on Risk Analysis. Without very highly experienced expertise, it is
going to be a failure to develop a project using this model.
• Difficulty in time management: As the number of phases is unknown at the start of the
project, so time estimation is very difficult
28. Explain the contents of test plan.
The test plan is the document which is created before the testing process. It includes the type
of testing that will be performed, high level scope of the project, the environmental
requirements of the testing process, what automated testing tools will be used the schedule of
each test, when it will start and end etc.
Test plan identifier
• Provide a unique for the document.
Introduction:
• Provide an overview of the test plan.
• Specify the goals
• Specify any constraints.
References:
• List the related documents, with links to them if available, including the
following:
1. Project plan
2. Configuration management Plan
Test Items:
• List the test items and their versions.
Features to be tested:
• List the features of the software/product to be tested.
• Provide references to the requirements and/or Design specifications of the
features to be tested.
Features not to be Tested:
• List the features of the software/product which will not be tested.
• Specify the reasons these features won’t be tested.
Approach:
• Mention the overall approach to testing.
• Specify the testing levels, testing types, and the testing methods.
Item pass/fail Criteria:
• Specify the criteria that will be used to determine whether each test item has
passed or failed testing.
Suspension Criteria and Resumption Requirements:
• Specify criteria to be used to suspend the testing activity.
• Specify testing activities which must be redone when is resumed.
Test Deliverables:
• List test deliverables, and links to them if available, including the following:
1. Test Plan
2. Test cases
3. Test Scripts
4. Defect /Enhancement logs
5. Test Reports
Test Environment:
• Specify the properties of test environment: Hardware, Software, network etc.
• List any testing or related tools.
Estimate:
• Provide a summary of test estimates and/or provide a link to the detailed
estimation.
Schedule:
• Provide a summary of test schedule, specifying key test milestones, and/or
provide a link to the detailed estimated.
Staffing and Training Needs:
• Specify staffing needs by role and required skills.
• Identify training that is necessary to provide those skills, if not already
acquired.
Responsibilities:
• List the responsibilities of each team/role/individual.
Risks:
• List the risk that have been identified.
• Specify the migration plan and the contingency plan for each risk.
Assumptions:
• List the assumptions that have been made during the preparation of this plan.
• List the dependencies.
Approvals:
• Specify the names and roles of all persons who must approve the plan.
• Provide space for signatures and dates.
29. Explain the quality characteristics of design.

A good design might be a design that allows efficient code to be produced. It might be A
minimal design where the implementation is as compact as possible or it might be the most
maintainable design. Following are some of the quality characteristics that equally applicable
to object-oriented and function-oriented design. These factors are:
1. Correctness
2. Understandability
3. Efficiency
4. Maintainability
• Correctness : The design of any software is evaluated for its correctness. The evaluators
check the software for every kind of input and action and observe the results that the
software will produce according to the proposed design.
• Understandability : The software design should be understandable so that the developers
do not find any difficulty to understand it. Good software design should be self-
explanatory.
• Efficiency : The software design must be efficient. The efficiency of the software can be
estimated from the design phase itself, because if the design is describing software that is
not efficient and useful, then the developed software would also stand on the same level of
efficiency.
• Maintainability : The software design must be in such a way that modifications can be
easily made in it. This is because every software needs time to time modifications and
maintenance. So, the design of the software must also be able to bear such changes.
30. Explain the characteristics of a good SRS.
Following are the characteristics of a good SRS document:
1. Correctness: SRS is said to be correct if it covers all the requirements that are actually
expected from the system.
2. Completeness: Completeness of SRS indicates every sense of completion including the
numbering of all the pages, resolving the to be determined parts to as much extent as
possible as well as covering all the functional and non-functional requirements properly.
3. Consistency: Requirements in SRS are said to be consistent if there are no conflicts
between any set of requirements.
4. Unambiguousness: An SRS is said to be unambiguous if all the requirements stated
have only 1 interpretation.
5. Ranking for importance and stability: There should a criterion to classify the
requirements as less or more important or more specifically as desirable or essential
6. Modifiability: SRS should be made as modifiable as possible and should be capable of
easily accepting changes to the system to some extent.
7. Verifiability: An SRS is verifiable if there exists a specific technique to quantifiably

measure the extent to which every requirement is met by the system.
8. Traceability: One should be able to trace a requirement to a design component and then
to a code segment in the program.
9. Design Independence: There should be an option to choose from multiple design
alternatives for the final system.
10. Testability: An SRS should be written in such a way that it is easy to generate test cases
and test plans from the document.
11. Understandable by the customer: An end user maybe an expert in his/her specific
domain but might not be an expert in computer science. Hence, the use of formal
notations and symbols should be avoided to as much extent as possible. The language
should be kept easy and clear.
12. Right level of abstraction: If the SRS is written for the requirements phase, the details
should be explained explicitly. Whereas, for a feasibility study, fewer details can be
used. Hence, the level of abstraction varies according to the purpose of the SRS.
31. Write a short note on quality control?
• Quality control means testing and it measures the quality of a product.the goal of
quality control is to ensure that the products services of processes provided must
specific requirements and are dependable and satisfactory.
The QC system is designed to:
• Provide routine and consistent checks to ensure data integrity,correctness and

completeness.
• Identify and address errors and omissions.
• Document and archive inventory material and record all QC activities.
Essentially, QC involves the examination of a product, service or process for certain

minimum levels of quality. the goal of a quality control team is to identify products or services
that do not meet a company’s specified standards of quality.
QC concerns not just products ,services and processes ,but also people. if a company has
employees that do not have adequate skills or training and knowledge then quality may be
severely diminished.
There are seven primary quality control tools which include:

• Checklists. At its most basic, quality control requires you to check off a list of items that are
imperative to manufacture and sell your product.
• Fishbone diagram. ...
• Control chart. ...
• Stratification. ...
• Pareto chart. ...
• Histogram. ...
• Scatter Diagram.
32. Write a short note on Software Quality Management?
Software Quality Management ensures that the required level of quality is achieved by
submitting improvements to the product development process. SQA aims to develop a
culture within the team and it is seen as everyone's responsibility.
Software Quality management should be independent of project management to ensure
independence of cost and schedule adherences. It directly affects the process quality and
indirectly affects the product quality.
Activities of Software Quality Management:

• Quality Assurance - QA aims at developing Organizational procedures and standards
for quality at Organizational level.
• Quality Planning - Select applicable procedures and standards for a particular project
and modify as required to develop a quality plan.
• Quality Control - Ensure that best practices and standards are followed by the
software development team to produce quality products.
33. Explain quality assurance in brief?
• Software Quality Assurance (SQA) is simply a way to assure quality in the software. It is
the set of activities which ensure processes, procedures as well as standards suitable for
the project and implemented correctly.
Software Quality Assurance have:
✓ A quality management approach
✓ Formal technical reviews
✓ Multi testing strategy
✓ Effective software engineering technology
✓ Measurement and reporting mechanism
Major Software Quality Assurance Activities:
✓ SQA Management Plan
✓ Set The Check Points
✓ Multi testing Strategy
✓ Measure Change Impact
✓ Manage Good Relations:
Benefits of Software Quality Assurance (SQA):
✓ SQA produce high quality software.
✓ High quality application saves time and cost.
✓ SQA is beneficial for better reliability.
✓ SQA is beneficial in the condition of no maintenance for long time.
✓ High quality commercial software increase market share of company.
✓ Improving the process of creating software.
✓ Improves the quality of the software.
34. Describe different requirements validation checks?

During the requirements validation process,checks should be carried out on the requirements
in the requirements document.these checks include:
REQUIREMENT DESCRIPTION
VALIDITY CHECKS
1.Validity checks These checks aims to ensure that the system meets all functional,
behavioral and performance requirements
2.Consistency checks Requirements collected must be consistent and should not lead
to conflict ie there should not be contradictory
Constraints or different descriptions of the same system
function
3.Realism checks Using knowledge of existing technology the requirement should
be checked to ensure that they can actually be implemented.
these checks also take account of the budget and schedule for the
system development
4.Verifiability At the completion of the system, it must be possible to
demonstrate that the delivered system meets all the
requirements
SOLUTION BANK
BCA 503T COMPUTER ARCHITECTURE

BCA503T: COMPUTER ARCHITECTURE
Total Teaching Hours: 60 No of Hours / Week: 04
Unit - I
DIGITAL LOGIC CIRCUITS: Logic gates Boolean algebra, map simplification,
combinational circuits, flip-flop, sequential circuits. INTEGRATED CIRCUITS AND
DIGITAL FUNCTIONS: Digital integrated circuits, IC flip –flops and registers, decoders
and multiplexers, binary counters, shift registers, random –access memories (RAM) read –
only memories (ROM). [12 Hours]
Unit - II
DATA REPRESENTATION: Data types, fixed-point representation, floating – point
representation, other binary codes, error detection codes. DATA TRANSFER
OPERATIONS: Register Transfer, Memory Transfer and I/O Transfer. [12 Hours]
Unit – III
BASIC COMPUTER ORGANISATION AND DESIGN: Instruction codes, computer
instruction, timing and control, execution and instruction, input-output and interrupt, design
of computer. [12 Hours]
Unit - IV
CENTRAL PROCESSOR ORGANIZATION: Processor bus organization, arithmetic logic
unit (ALU) instruction formats, addressing modes, data transfer and manipulation, program
control, microprocessor organization. [12 Hours]
Unit – V
INPUT-OUTPUT ORGANISATION: Peripheral devices. asynchronous data transfer, direct
memory access (DMA), priority interrupt, input –output processor (IOP). MEMORY
ORGANIZATION: Auxiliary memory, microcomputer memory hierarchy, associative
memory, virtual memory, cache memory. [12 Hours]
Text Books:
1. M. Morris Mano, Computer System, Architecture, 2nd Edition Prentice Hall of India.
Reference Books:
1. Heuring and Jordan, Computer systems design and Architecture, Pearson Edition
2. William Stallings, Computer Organization and Architecture, Pearson Education
3. Floyd, Digital Fundamentals,8th Edition, Pearson Education.
4. Andrew S. Tanenbaum, Structured Computer Organization, 3rd Edition; Prentice Hall of
India.
5. David Patterson & Hennessy, Computer Organization & Design, Elsevier.
BCA503T: COMPUTER ARCHITECTURE
BLUE PRINT
Question paper pattern for theory has foursections :
Section – A :Contains 12 questions, out of which a student has to answer 10 questions. Each
Section – B :Contains 8 questions, out of which a student has to answer 5 questions. Each
question carries 5 marks (5 x 5 = 25)
Section – C :Contains 5 full questions includes sub-question as (a) & (b). Student has to
answer 3 full questions. Each full question carries 15 marks(3 x 15 = 45 )
Section – D :Contains 2 questions, out of which a student has to answer 1 question. Each
SECTION A SECTION B SECTION C SECTION D

UNIT CHAPTER
2 MARKS 5 MARKS 15 MARKS 10 MARKS
Digital Logic Circuits 2 1 0.5 0.5

I
Integrated Circuits 0.5
2 1
and Digital Functions 1
II Data Representation 2 1 0.5 -
Basic Computer 1 0.5
III Organization and 2 2
Design
Central Processor 1 0.5
IV 2 1
Organization
Input-Output 0.5 -
1 1
Organization
V
Memory 0.5 -
1 1
Organization
Total Questions 12 8 5 2
Answer any Answer any Answer any Answer any
10 5 3 1
Total Marks (100) 20 25 45 10
UNIT-I
[ Nov / Dec 2015 ]
1. State and prove De-Morgan’s theorem
2. Draw the logic diagram of Boolean function using
NAND gates only.
3. What is decoder expansion?
4. What is unidirectional and bidirectional shift register
[ Nov / Dec 2016 ]

5. What is computer architecture?
7. Mention the different logic families of IC.
8. Distinguish between RAM and ROM.
[ Nov / Dec 2017 ]

9. Write the symbol, logical expression and truth table of NAND gate.
10. Give the classification of integrated circuits.
12. Define Multiplexer and Demultiplexer.
[ Nov / Dec 2018 ]

13. Explain full adder.
14. Define universal gates with logic circuit.
16. Define Flip-Flop.
17. Why we use shift register?

18. Define half adder.
19. What is full subtractor.
20. Define parity checker and generator.
21. What is k-map?
22. What are the different types of flipflops.
23. Mention the types of shift registers.
24. Mention the types of RAM and ROM.
25. Mention the different types of computer architecture.
UNIT-II
[ Nov / Dec 2015 ]
1. Convert (736.4)8 into decimal and binary
2. What is self-complementing code and weighted code?
[ Nov / Dec 2016 ]

3. What is parity bit?
4. Write the BCD code for decimal number 8745.42(10)
[ Nov / Dec 2017 ]

5. What are the types of Binary codes?
6. Subtract 24 from 13 using 2’s complement method.
[ Nov / Dec 2018 ]

7. Explain Hamming code.
8. Define Parity bit.

9. What self-complementary code?
10. What is true complement and radix-1 complement?
11. What is alphanumeric code?
12. Define floating point representation.
UNIT-III
[ Nov / Dec 2015 ]
1. What are the two types of control organization?
2. How many bits are needed to specify an address for a memory unit of 4096 words.
[ Nov / Dec 2016 ]

4. Define program counter.
[ Nov / Dec 2017 ]

5. Define opcode and operand.
6. What is BUN instruction?
[ Nov / Dec 2018 ]
7. Explain BSA instruction.
8. Define Indirect Addressing Mode.

9. What is the difference between BUN and BSA instruction.
10. What is stored program concept?
11. What do you mean by instruction execution?
12. What is timing control?
13. Define Hardwired Control.
UNIT-IV
[ Nov / Dec 2015 ]
1. What is PSW?
2. What is an external interrupt? Give an example?
[ Nov / Dec 2016 ]

3. Mention the major components of CPU.
4. What is PSW?
[ Nov / Dec 2017 ]

5. What are the two types of computer architecture based on registers?
6. What are the different types of interrupts?
[ Nov / Dec 2018 ]

No Questions

7. What is RTL?
8. What do you mean by microoperations.
9. What is the difference between single and stack organization.
10. What is word?
11. What is the expansion of RISC and CISC.
UNIT-V
[ Nov / Dec 2015 ]
1. What are peripherals?
2. What is memory management system?
[ Nov / Dec 2016 ]
3. What is polling?
[ Nov / Dec 2017 ]

5. Define access time and transfer rate.
6. Define Baud rate.
[ Nov / Dec 2018 ]

7. What is meant by Memory-Mapped I/O?
8. Define virtual memory
9. Define types of RAM.

10. Mention modes of transfer.
11. What is daisy chain priority?
12. What is cache memory?
13. Define Associate memory?
UNIT-I
[ Nov / Dec 2015 ]
1. Simplify the Boolean function F(A,B,C,D)=∑(0,1,2,5,8,9,10) in both SOP and POS .
2. Design 4-to-1 multiplexer.
[ Nov / Dec 2016 ]

3. Prove NAND and NOR gates as universal gates.
4. Explain PIPO shift register with a diagram.
[ Nov / Dec 2017 ]

5. Explain the steps involved in the design of the sequential circuits.
6. Explain synchronous binary counter with logical diagram.
[ Nov / Dec 2018 ]

7. Explain the steps involved in design of combinational circuit.
8. What is a K-map? Explain different types of K-maps.
UNIT-II
[ Nov / Dec 2015 ]
1. Define r and (r-1)’s complement. Represent -14 using integer representation stored in
an 8 bit register.
[ Nov / Dec 2016 ]

2. Discuss the Parity generator and Parity checker.
[ Nov / Dec 2017 ]

3. Discuss on error detection and correction codes briefly.
[ Nov / Dec 2018 ]

4. NO Questions
UNIT-III
[ Nov / Dec 2015 ]
1. List the micro operations of ADD and ISZ instruction.
2. Explain with neat block diagram the input-output configuration.
[ Nov / Dec 2016 ]

3. Explain the operation of interrupt cycle with a flow chart.
4. Explain input-output organization.
[ Nov / Dec 2017 ]

5. Explain any five register reference instructions.
6. With a block diagram, explain how BSA instruction execution.
[ Nov / Dec 2018 ]

7. Write a note on program counter and stack memory.
8. Explain any five register reference instructions
9. Explain timing signals.
UNIT-IV
[ Nov / Dec 2015 ]
1. Explain register stack with a neat block diagram.
[ Nov / Dec 2016 ]

2. Explain the three types of CPU organization.
[ Nov / Dec 2017 ]

3. Explain the addressing modes.
[ Nov / Dec 2018 ]

4. Compare CICS and RISC processors.
UNIT-V
[ Nov / Dec 2015 ]
1. What is polling? Explain.
2. Explain Associative memory with a neat diagram.
[ Nov / Dec 2016 ]

3. Explain the source initiated data transfer using handshaking with a block diagram and
timing diagram.
4. Write a note on memory hierarchy in a computer system.
[ Nov / Dec 2017 ]

5. Explain DMA Controller with a block diagram.
6. Write a note on virtual memory.
[ Nov / Dec 2018 ]

7. Write a note on cache memory.
8. What are the important characteristics of memory?

NOTE: ALL TMAQ questions for 5 marks and 10 marks will be given at the end please check
SECTION –C( 15 Marks )
UNIT-I
[ Nov / Dec 2015 ]
1. Design a octal to binary encoder
2. Explain with a neat diagram a 4-bit bidirectional shift register with parallel load.
[ Nov / Dec 2016 ]

3. Define K map? Simplify the following Boolean function using K-map:
4. Define counter. With a neat diagram explain 4-bit synchronous binary counter.
5. Explain octal to binary encoder with diagram.
[ Nov / Dec 2017 ]

6. Simplify F(ABCD)=∑m(1,3,7,11,15)+∑d(0,2,5) using K-map.
7. What is half adder? Design a half adder using only NAND gates.
8. Explain decoder expansion with the neat diagram.
[ Nov / Dec 2018 ]

9. Simplify F(ABCD)=∑m(1,2,4,6,8,10,12,14) and draw a circuit diagram.

UNIT-II
[ Nov / Dec 2015 ]
1. Design the circuit for a 3-bit parity generator using an odd-parity system.
[ Nov / Dec 2016 ]

2. Explain different binary codes.
[ Nov / Dec 2017 ]

3. Discuss the parity generator and parity checker.
[ Nov / Dec 2018 ]

4. What is parity bit? Explain in brief.
UNIT-III
[ Nov / Dec 2015 ]
1. Explain with a neat flowchart the computer operation.
[ Nov / Dec 2016 ]

2. Explain the design of basic computer with flow chart.
[ Nov / Dec 2017 ]

3. No questions
[ Nov / Dec 2018 ]

4. Explain the types of program interrupts.
5. Explain I/O commands.

UNIT-IV
[ Nov / Dec 2015 ]
1. What is addressing mode? Explain the different types of Addressing Modes with
example.
[ Nov / Dec 2016 ]

2. What is addressing mode? Explain the different types of addressing modes with
examples
[ Nov / Dec 2017 ]

3. Explain common bus organization of basic computer with neat diagram.
4. Distinguish between FGI and FGO.
5. What is a sub-routine? Explain CAL and RETURN instructions.
[ Nov / Dec 2018 ]

6. Explain common BUS organization of a Basic Computer
7. Explain different Addressing modes.
UNIT-V
[ Nov / Dec 2015 ]
1. Explain source-initiated data transfer using hand shaking.
2. What is virtual memory? Explain address space and memory space in detail.
[ Nov / Dec 2016 ]

3. Explain DMA controller with a block diagram/
4. Explain the working of Associative memory.
[ Nov / Dec 2017 ]

5. Explain I/O interface unit with a neat diagram.
6. Write a note on isolated vs memory mapped I/O.
[ Nov / Dec 2018 ]

7. Explain memory hierarchy.
SECTION –D( 10 Marks )

UNIT-I
[ Nov / Dec 2015 ]
1. What is binary counter? Explain a 4-bit synchronous counter with a neat block
diagram.
[ Nov / Dec 2016 ]

2. Explain the block diagram of computer with I/O processors.
[ Nov / Dec 2017 ]

3. Explain 4-bit shift register.
4. Explain the working of JK flipflop.
5. List the applications of EEPROM.
[ Nov / Dec 2018 ]

6. Explain the working of RS flip-flop.
7. Explain 8 to 3 encoder.
UNIT-II
[ Nov / Dec 2015 ]
No questions
[ Nov / Dec 2016 ]

No questions
[ Nov / Dec 2017 ]

No questions
[ Nov / Dec 2018 ]

1. Discuss error detection and correction codes.

UNIT-III
[ Nov / Dec 2015 ]
No questions
[ Nov / Dec 2016 ]

1. Explain the common bus system.
[ Nov / Dec 2017 ]

No questions
[ Nov / Dec 2018 ]

2. Explain direct address and indirect address modes.

UNIT-IV
[ Nov / Dec 2015 ]
1. What are the major characteristics of RISC architecture?
[ Nov / Dec 2016 ]

2. Write a note on RISC and CISC.
[ Nov / Dec 2017 ]
3. Explain interrupt cycle with suitable example.
[ Nov / Dec 2018 ]

No questions

UNIT-V
[ Nov / Dec 2015 ]
1. Explain the block diagram of computer with I/O processors.
[ Nov / Dec 2016 ]

2. Write a note on modes of data transfer
[ Nov / Dec 2017 ]

No questions
[ Nov / Dec 2018 ]

No questions

Unit – I
1. Explain any ten Boolean postulates.
2. Write the difference between Von Neuman and Harvard Architecture.
3. Explain JK-Master slave flipflop.
4. Explain the classification of IC Families.
5. Explain SISO in brief.
Unit – II
1. Explain floating point representation in brief.
2. Explain in brief Gray code.
3. What is Excess 3 code? Explain.
4. What is cyclic code? Explain.
5. Explain code conversion with an example.
Unit – III
1. What is stored program organization? Explain.
2. Explain computer registers.
3. Explain instruction execution.
4. Explain computer instruction with an example.
5. Explain the design of the computer with a flowchart.
Unit – IV
1. Explain Bus organization with a neat diagram.
2. Explain the formats of instructions.
3. What is program interrupt? Explain.
4. Distinguish between RISC and CISC.
5. Explain the arithmetic and logic unit.
Unit – V
1. Give the difference between Isolated I/O vs Memory mapped I/O.
2. Explain strobe control with an example.
3. Explain DMA with a neat diagram.
4. Explain in brief Cache memory and Virtual memory.
5. Explain classification of memory. Explain in brief.
*****
J
11111111111111111111111111111111111 SN - 664
V Semester B.C.A. Degree Examination, NovJDec. 2017
(CBCS) (F + R) (2016-17 and Onwards)
BCA 503 : COMPUTER ARCHITECTURE
Time: 3 Hours Max. Marks: 100
Instruction: Answerall Sections.
SECTION-A
I. Answer any ten questions. Each carries two marks. (10x2=20)

1) Write the symbol, logical expression and truth table of NAND gate.
2) Give the classification of integrated circuits.
3) Distinguish between RAM and ROM.
4) Define Multiplexer and Demultiplexer.
5) What are the types of binary codes?
6) Subtract 24(10)from 13(10)using 2's complement method.
7) Define opcode and operand.
8) What is BUN instruction?
9) What are the two types of computer architecture based on registers?
10) What are the different types of interrupts?
11) Define access time and transfer rate.
12), Define Baud rate.
SECTION-B
II. Answer any five questions. Each question carries five marks. (5x5=25)
13) Explain the steps involved in the design of the sequential circuits.
14) Explain synchronous binary counter with logic diagram.
15) Discuss on error detection and correction codes briefly.
16) Explain any five register reference instructions.
17) With a block diagram, explain how BSA instruction executes.
18) Explain the addressing modes.
19) Explain DMA controller with a block diagram.
20) Write a note on virtual memory.
p.T.a.
SN-664 11111111111111111111111111111111111
SECTION-C
III. Answerany threequestions. Each question carries fifteen marks. (3x15=45)
21) a) Simplify F(ABCD) = l: m (1,3,7, 11, 15) + l:d (0, 2, 5) using K-map. 7
b) What is a half adder? Design a half adder using only NAND gates. 8
22) a) Explain decoder expansion with neat diagram. 7
b) Discuss the parity generator and parity checker. 8
23) a) Explain common bus organization of basic computer with neat diagram. 8
b) Distinguish between FGI and FGO. 7
24) a) What is a sub-routine? Explain CALL and RETURN instructions. 8
b) Explain the arithmetic logic shift with a neat diagram. 7
25) a) Explain I/O interface unit with a neat diagram. 8
b) Write a note on isolated vs memory mapped I/O. 7
SECTION-D
IV.Answerany one question. Question carries ten marks. (1x10=10)

26) a) Explain 4-bit shift register. 5
b) Explain the working of J-K flip-flop. 5
27) a) Explain interrupt cycle with suitable example. 6
b) List the applications of EEPROM. 4
BCA503T – COMPUTER ARCHITECTURE
2 MARKS QUESTIONS AND ANSWERS
1. State and prove Demorgan’s Law.

1. The first theorem states that the compliment of the sum of Boolean expressions
is equal to the product of the compliments of the individual expression.
(x+y)’ = x’.y’
2. The second theorem states that the compliment of product of
Booleanexpressions is equal to sum of the compliment of the
individualexpressions.
(x.y)’ = x’+y’
2. What is Decoder expansion?

At times we may require decoder of a certain size while only small size decoders are
available. Then in order to obtain to require the size decoder, we have to combine
two or more available size decoders.
3. Convert (736.4)8 to decimal and binary.
(736.4)8 to decimal
= 7*82+3*81+6*80+4*8-1
=7*64+3*8+6*1+4*0.125
= 448+24+6+0.5 = 478.510
(736.4)8 = 478.510
(736.4)8 to Binary
= 7 3 6 . 4
111 011 110 . 100
(736.4)8 = 111011110.100(2)
4. What is unidirectional and bidirectional shift register?

Unidirectional: A register capable of shifting in one direction only is called
unidirectional shift register.
Bidirectional: A registers than can shift in both directions is called Bidirectional
shift register.
5. What is self-complementing code and weighted code ?

Weighted code :- Are those codes which obey the positional weighting principles.
Each position of number represents the specific weight.
Self-complementing code :- It is an unnatural BCD code. Sum of weights of
unnatural BCD codes is equal to 9. It is a self-complementing code. Self-
complementing codes provide the 9's complement of a decimal number, just by
interchanging 1's and 0's in its equivalent 2421 representation

1. Hardwired control
2. Microprogrammed control
7. Explain Full adder?

Full adder is an arithmetic circuit block that can be used to add three bits to
produce a SUM and CARRY output.
8. Define universal gates with logic circuits?
A universal gate is one of the logic gate which uses Boolean function
{0,1}. NAND and NOR gates are called universal gates.
The circuit diagram and truth table of NAND gate:
The circuit diagram and truth

table of NOR gate:
9. Define types of RAM?

Types of RAM are:
1. Static RAM (SRAM): SRAM is that it retains data bits in its memory as long as
power is being supplied.
2. Dynamic RAM (DRAM): DRAM is most common kind of RAM for personal
computers and workstations.
10. Define Flip-Flop?

A flip flop is an electronic circuit with two stable states that can be used to store
binary data. The stored data can be changed by applying varying inputs. Flip-
flops and latches are fundamental building blocks of digital electronics systems used
in computers, communications, and many other types of systems.
11. Why we use shift register?

Shift registers are used for the storage or transfer of data in the form of binary
numbers and “shifts” the data out once every clock cycle,hence the name shift
register.
12. Explain Hamming code?

Hamming code is a set of error-correction code s that can be used to detect and
correct bit errors that can occur when computer data is moved or stored.
13. What is computer architecture?

The architectural design of a computer system is concerned with the specifications
of the various functional modules, such as processors and memories and structuring
them together into a computer system.
14. What are the two types of computer architecture based on registers?
1.Von Neumann architecture
2. Harvard architecture
15. Mention the different families of IC.
a. Bipolar families
b. Metal Oxide Semiconductors(MOS) families
RAM(Random access memory) ROM(Read only memory)

In RAM the contents are lost when the ROM is a special type of memory which
computer is switched off. can be read and contents of which it are
not lost even when the computer is
switched off.
Read and Write operations are Only read operation are performed on
performed on RAM and they are ROM and they are classified as :-
classified as :- a. Masked programmed
a. Static RAM b. User programmed
b. Dynamic RAM
17. What is parity bit?

A parity bit is an extra bit included with a binary message to make the total
number of 1’s either even or odd.
18. Write the BCD code of decimal number 8745.42(10)?

Decimal Number = 8 7 4 5 . 4 2
BCD Code = 1000 0111 0100 0101 . 0100 0010
Therefore, 8745.42 = 1000011101000101.01000010(BCD).
19. Define program counter?

The program counter (PC)holds the address of the next instruction to be read from
the memory after the current instruction is executed.
20. Write the symbol, logical expression and truth table of NAND gate?
The Logical symbol and truth table
Logical Expression:
Z=(X.Y)’
21. Give a classification of integrated circuits?

1. Small Scale Integration (SSI ) 4. Very-Large Scale Integration(VLSI)
2. Medium Scale Integration(MSI) 5. Super-Large Scale Integration(SLSI)
3. Large Scale Integration (LSI) 6. Ultra-Large Scale Integration(ULSI)
22. Define multiplexer and demultiplexer?

A multiplexer (MUX) is a device used to select a single line of input from multiple input
lines using control signals. In this diagram, D0 to D3 are input data lines and Y is the
output. The S0 and S1 bits tell the mux which one out of the 4 input lines will be
selected as output. So, if S0 = 0 and S1=0, then Y= D0,
De-multiplexer(DMUX) is also a device with one input and multiple output lines. It is
used to send a signal to one of the many devices. The main difference between a
multiplexer and a de-multiplexer is that a multiplexer takes two or more signals and
encodes them on a wire, whereas a de-multiplexer does reverse to what the multiplexer
does.
23. what are the type of binary code?

1. Weighted Codes
2. Non-Weighted Codes
3. Alphanumeric Codes
24. Subtract 24 from 13 using 2’s complement method?
00001101 13
11101000 2’s complement of (-24)
---------------------------------------------------
10001011 Result (-11)
25. Explain BSA instruction?
BSA: (Branch and save return address)
This instruction is useful for branching to a position of the program called a
subroutine or producer. When executed, it stores the address of the next
instruction in sequence into a memory location specified by the effective address.
26. What is BUN instruction?

BUN (Branch unconditionally) his instruction transfers the program to the
instruction specifies by the effective address. The program counter PC holds the
address of the instruction to be read from memory in the text instruction cycle.
27. Define opcode and operand.
The operation code of an instruction is a group of bits that define operations such as
add, subtract, multiply, shift and complement.
Operand: An instruction code must not only specify the operation but also the
registers or the memory words.
28. Define indirect Address Mode.

When the bits in the second part of the instruction designate an address of a
memory word in which an address of the operand is found,it is called indirect
address mode.
29. How many bits are needed to specify an address for a memory until of 4096 words?
For a memory unit with 4096 words, weneed 12 bits to specify and address since
212 = 4096.
30. Mention the major components of CPU

a. Control Unit
b. Arithmetic Logical Unit
c. Immediate Access
31. What is PSW?
PSW in electronics means Program Status Word. A register, which is 32 bits in size
and holds all the information about the current state of an operation/program and
hence, it helps in proper program execution.
32. What is an external interrupt? Give an example?
It is initiated by an external event. It is asynchronous with program (acts
independent of program). It depends on external condition which is independent
of program being executed at that point of time.
Eg:- Input /output devices
33. What are peripherals?

Input or output devices attached to the computer are also called Peripherals.
Peripherals are Electromechanical and electromagnetic devices of some
complexity.

Memory management is the process of controlling and coordinating the computer
memory, assigning portions called blocks to various running programs to optimize
overall system performance.
35. What is meant by Memory-mapped I/O?

Memory mapped I/O is a way to exchange data and instructions between a CPU
and peripheral devices attached to it. Memory mapped IO is one where the
processor and the IO device share the same memory location(memory),i.e.,the
processor and IO devices are mapped using the memory address.
36. Define virtual memory?

A virtual memory system provides a mechanism for translating program
generated addresses into correct main memory locations.
37. What is Polling?

The software method used to identify the highest priority source is called as
Polling.in this there is one common branch address for all interrupts.
38. What are the different types of interrupts

1. External interrupts
2. Internal interrupts
3. Software interrupts
39. Define access time and transfer rate

Access time. The total time it takes the computer to read data from a storage device
such as computer memory, hard drive, CD-ROM or other mechanism. Computer
access time is commonly measured in nanoseconds or milliseconds and the lower the
access the time the better.Data rates are often measured in megabits (million bits)
or megabytes (million bytes) per second. These are usually abbreviated as Mbps
and MBps,respectively. Another term for data transfer rate is throughput.
40. Define Baud rate

Baud rate represents the number of times per second a signal (changing from zero
to one or one to zero) or symbol (the connection's voltage, frequency or phase) in a
communications channel changes state or varies. For example, a 2,400 Baud rate
means the channel is changing states up to 2,400 times per second.
LONG QUESTIONS WITH ANSWERS.
1. Prove NAND and NOR as universal gates.
NOR gate is a universal gate, meaning that any other gate can be represented as a
combination of NOR gates.
(a) Realizing NOT gate using NOR
(b) Realizing AND gate using NOR
(c) Realizing OR gate using NOR

(d) Realizing NAND gate using NOR
A NAND gate is a universal gate, meaning that any other gate can be represented as
a combination of NAND gates.
(A) Realizing NOT gate using NAND
(B) Realizing AND gate using NAND

(C) Realizing OR gate using NAND
(D) Realizing NOR gate using NAND

2. Explain the steps involved in design of combinational circuit.
A combinational circuit is a connection of logic gates with a set of inputs and
outputs. The design of a combinational circuit starts from the outline of the
problem and ends in a logic circuit diagram.
• The problem is stated.
• The input and output variables are assigned letter symbols.
• The truth table that defines the relationship between inputs and outputs
is derived.
• The simplified Boolean functions for each output are obtained.
• The logic diagram is drawn.
The design of combination circuits can be demonstrated with two simple
examples of arithmetic circuits the Half Adder and the Full Adder.
3. What is K-map? Explain with an example.

Karnaugh map is also called as K Map. The Karnaugh map is a method of
simplifying Boolean algebra expressions. There are three types of K map are
• 2-variables map (22=4 cells)
• 3-variables map (23=8 cells)
• 4 variables map (24=16 cells)
The K-map is used to simplify the complex expression into simplex using
different groping. Eg., Pair, Quad, Hexa, Overlapping, Rolling etc.,
Ex:
Boolean function F(A,B,C,D) = Σ (0,1,2,5,8,9,10) in sum-of-products.
4. Explain octal to binary encoder with a diagram.
An octal to binary encoder consists of eight input lines and three output lines. Each
input line corresponds to each octal digit and three outputs generate corresponding
binary code.
In encoders, it is to be assumed that only one input is active or has a value 1
at any given time otherwise the circuit has no meaning. The figure below shows the
logic symbol of octal to binary encoder along with its truth table.
From the above table, the output Y2 becomes 1 if any of the digits D4 or D5 or D6
or D7 is one. Thus, we can write its expression as
Y2 = D4 + D5 + D6 + D7
Similarly, Y1 = D2 + D3 + D6 + D7 and
Y0 = D1 + D3 + D5 + D7
Also it is to be observed that D0 does not exist in any of the expressions so it is
considered as don’t care. From the above expressions, we can implement the octal
to binary encoder using set of OR gates as shown in figure below
There is ambiguity in the octal to binary encoder that when all the inputs are zero,
an output with all 0’s is generated. Also, when Do is 1, the output generated is zero.
This is a major problem in this type of encoder. This can be resolved by specifying
the condition that none of the inputs are active with an additional output
5. What is half adder? Design a half adder using only NAND gates
Half Adder is the digital circuit which can generate the result of the addition of two
1-bit numbers. It consists of two input terminals through which 1-bit numbers can
be given for processing. After this, the half adder generates the sum of the numbers
and carry if present.
Half Adder using NAND Gates
The half adder can also be designed with the help of NAND gates. NAND gate is
considered as a universal gate. A universal gate can be used for designing of any
digital circuitry. It is always simple and efficient to use the minimum number of
gates in the designing process of our circuit. The minimum number of NAND gates
required to design half adder is 5.
The first NAND gate takes the inputs which are the two 1-bit numbers. The
resultant NAND operated inputs will be again given as input to 3- NAND gates
along with the original input. Out of these 3 NAND gates, 2-NAND gates will
generate the output which will be given as input to the NAND gate connected at the
end. The gate connected at the end will generate the sum bit. Out of the 3
considered NAND gates, the third NAND gate will generate the carry bit.
6. Design a 4-to-1 multiplexer

It is a logic circuit that switches digital data from several input lines onto a single
output line in a specified time sequence.
A multiplexer has several data input lines and a single output line. It also has data
select inputs which permit digital data on only one of the input to be switched to
the output lines.
4-to-1 Multiplexer
• A 4-to-1 multiplexer consists four data input lines as D0 to D3, two select lines as S0
and S1 and a single output line Y.
• The select lines S1 and S2 select one of the four input lines to connect the output
line.
• The particular input combination on select lines selects one of input (D0 through
D3) to the output.
• The figure below shows the block diagram of a 4-to-1 multiplexer in which the
multiplexer decodes the input through select line.
Truth table :
• If S1=0 and S0=0 then Y = D0

• If S1= 0 and S0=1, the Y = D1
• If S1=1 and S0=0, then Y = D2
• If S1=1 and S0=1 the Y = D3
Therefore, Y = D3 S1 S0
7. Explain the working of R-S flip-flop.

In clocked R-S flip flop the appropriate levels applied to their inputs are blocked till the
receipt of pulse from an other source called clock. The flip flop changes state only when
clock pulse is applied depending upon the inputs.
The basic circuit is shown below.
INPUTS OUTPUTS Mode of Effect on output

CLK S R X X Operation X
0 0 X X Hold or Idle No change

0 1 0 1 Reset Reset to 0
1 0 1 0 Set Set to 1
1 1 1 1 Forbidden or Should not be
Prohibited used
1. With inputs S=0 and R=0, the clock pulse has no effect on output X. The flip
flop is in the idle or hold mode.
2. With inputs S=0 and R=1, when the clock pulse is applied, the active high signal
on R resets or clears the flip flop to 0. Then flip flop is said to be in reset mode.
3. With inputs S=1 and R=0, when the clock pulse is applied, the active high signal
on S sets the flip flop to 1. Then flip flop is said to be in set mode.
4. With inputs S=1 and R=1, when the clock pulse is applied, the flip flop to 0.
The flip flop enters the prohibited or forbidden state. This sate cannot be used.
8. Explain 8 to 3 Encoder
The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs : Y7 to Y0 and 3
outputs : A2, A1 & A0. Each input line corresponds to each octal digit and three
outputs generate corresponding binary code.
The figure below shows the logic symbol of octal to binary encoder:
The truth table for 8 to 3 encoder is as follows :

Logical expression for A2, A1 and A0 :
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
The above two Boolean functions A2, A1 and A0 can be implemented using four
input OR gates :
9. Explain PIPO shift register with a diagram.

• The shift register, which allows parallel input (data is given separately to
each flip flop and in a simultaneous manner) and also produces a parallel
output is known as Parallel-In parallel-Out shift register.
• The circuit consists of four D flip-flops which are connected. The clear
(CLR) signal and clock signals are connected to all the 4 flip flops. In this
type of register, there are no interconnections between the individual flip-
flops since no serial shifting of the data is required. Data is given as input
separately for each flip flop and in the same way, output also collected
individually from each flip flop.
10. Explain the working of full adder.
Full Adder is the adder which adds three inputs and produces two outputs. The first
two inputs are A and B and the third input is an input carry as C-IN. The output carry
is designated as C-OUT and the normal output is designated as S which is SUM.
Truth Table :
The logic diagram for Full Adder can be developed from the 2 logical expressions
for S (sum) Cout Carry.
S = AB’Cin + A’BC’in + ABC’in + ABCin
Cout = A’BCin + AB’Cin + ABC’in + ABCin
11. Explain Parity checker and generator.
PARITY CHECKER
• When this device is used as even parity checker, the number of input bits
should always be even. When a parity error occurs, the ∑ even output goes
low and the ∑ odd goes high.
• When it is used as an odd parity checker, the number of input bits should
always be odd. When a parity error occurs, the ∑ odd output gets high.
Number of Inputs OUTPUTS

HIGH ∑Even ∑Odd
0,2,4,6,8 HIGH LOW
1,3,5,7,9 LOW HIGH
PARITY GENERATOR
• When this device is used as an even parity generator, the parity bit is taken
at the odd output because this output is a0 if there is an even number of
input bits, and it is a 1 if there is an odd number. When used an odd parity
generator, the parity bit is taken at the a 0 even output because it is a0 when
the number of inputs is odd.
12. Explain error detection and correction code.
• Error detection codes :- are used to detect the error(s) present in the
received data (bit stream). These codes contain some bit(s), which are
included (appended) to the original bit stream. These codes detect the error,
if it is occurred during transmission of the original data (bit
stream).Example − Parity code, Hamming code.
• Error correction codes :- are used to correct the error(s) present in the
received data (bit stream) so that, we will get the original data. Error
correction codes also use the similar strategy of error detection codes.
Example − Hamming code.
Therefore, to detect and correct the errors, additional bit(s) are appended to the data
bits at the time of transmission.
• Parity Code:-It is easy to include (append) one parity bit either to the left of
MSB or to the right of LSB of original bit stream. There are two types of parity
codes, namely even parity code and odd parity code based on the type of parity
being chosen.
• Even Parity Code:-The value of even parity bit should be zero, if even number
of ones present in the binary code. Otherwise, it should be one. So that, even
number of ones present in even parity code. Even parity code contains the data
bits and even parity bit.
The following table shows the even parity codes corresponding to each 3-bit binary
code. Here, the even parity bit is included to the right of LSB of binary code.
Binary Even Parity Even Parity
Code bit Code
000 0 0000
001 1 0011
010 1 0101
011 0 0110
100 1 1001
101 0 1010
110 0 1100
111 1 1111
• Odd Parity Code The value of odd parity bit should be zero, if odd number of ones
present in the binary code. Otherwise, it should be one. So that, odd number of
ones present in odd parity code. Odd parity code contains the data bits and odd
parity bit.
The following table shows the odd parity codes corresponding to each 3-bit binary code.
Here, the odd parity bit is included to the right of LSB of binary code.
13. What is a parity Bit? Explain in brief.
A parity bit is an extra bit included with a binary message to make the total
number of 1s either odd or even.
EVEN Parity ODD Parity
P BCD P BCD
0 0000 1 0000
1 0001 0 0001
1 0010 0 0010
0 0011 1 0011
1 0100 0 0100
0 0101 1 0101
0 0110 1 0110
1 0111 0 0111
1 1000 0 1000
0 1001 1 1001
1. The parity bit can be attached to the code at the beginning or the end,
depending on how the system is designed.
2. At the sending end, the message is applied to a parity generator, where the
required the required parity bit is generated.
3. The message, including the parity bit, is transmitted to its destination.
4. At the receiving end, all the incoming bits are applied to a parity checker that
checks the proper parity adopted (odd or even).
5. If the checked parity does not conform to the adopted parity, an error is
detected.
14. Explain the Common Bus system.
• The basic computer has eight registers, a memory unit, and a control unit . Paths
must be provided to transfer information from one register to another and between
memory and registers
• The number of wires will be excessive if connections are made between the outputs
of each register and the inputs of the other registers.
• A more efficient scheme for transferring information in a system with many
registers is to use a common bus.
• The connection of the registers and memory of the basic computer to a common bus
system is shown in Fig. below. The outputs of seven registers and memory are
connected to the common bus.
The specific output that is selected for the bus lines at any given time is determined
from the binary value of the selection variables S2, S1, and S0.
• The number along each output shows the decimal equivalent of the required binary
selection. For example, the number along the output of DR is 3.
• The 16-bit outputs of DR are placed on the bus lines when S2S1S0 = 011 since this is
the binary value of decimal 3.
• The lines from the common bus are connected to the inputs of each register and the
data inputs of the memory. The particular register whose LD (load) input is enabled
receives the data from the bus during the next clock pulse transition.
• The memory receives the contents of the bus when its write input is activated. The
memory places its 16-bit output onto the bus when the read input is activated and
S2S1S0 = 111.
• Four registers, DR, AC, IR, and TR, have 16 bits each. Two registers, AR
• and PC, have 12 bits each since they hold a memory address. When the contents of
AR or PC are applied to the 16-bit common bus, the four most significant bits are
set to 0's.
• When AR or PC receive information from the bus, only the 12 least significant bits
are transferred into the register. The input register INPR and the output register
OUTR have 8 bits each and communicate with the eight least significant bits in the
bus.
• INPR is connected to provide information to the bus but OUTR can only receive
information from the bus.
• This is because INPR receives a character from an input device which is then
transferred to AC. OUTR receives a character from AC and delivers it to an output
device. There is no transfer from OUTR to any of the other registers.
• The 16 lines of the common bus receive information from six registers and the
memory unit. The bus lines are connected to the inputs of six registers and the
memory. Five registers have three control inputs: LD (load), INR (increment), and
CLR (clear).
• This type of register is equivalent to a binary counter with parallel load and
synchronous clear. The increment operation is achieved by enabling the count input
of the counter. Two registers have only a LD input.
• The input data and output data of the memory are connected to the common bus,
but the memory address is connected to AR. Therefore, AR must always be used to
specify a memory address.
• By using a single register for the address, we eliminate the need for an address bus
that would have been needed otherwise. The content of any register can be specified
for the memory data input during a write operation. Similarly, any register can
receive the data from memory after a read operation except AC .
• The 16 inputs of AC come from an adder and logic circuit. This circuit has three
sets of inputs. One set of 16-bit inputs come from the outputs of AC . They are used
to implement register micro operations such as complement AC and shift AC .
• Another set of 16-bit inputs come from the data register DR. The inputs from DR
and AC are used for arithmetic and logic rnlcro operations, such as add DR to AC
or AND DR to AC.
• The result of an addition is transferred to AC and the end carry-out of the addition
is transferred to flip-flop E (extended AC bit). A third set of 8-bit inputs come from
the input register INPR.
• Note that the content of any register can be applied onto the bus and an operation
can be performed in the adder and logic circuit during the same clock cycle. The
clock transition at the end of the cycle transfers the content of the bus into the
designated destination register and the output of the adder and logic circuit into
AC.
15. Explain direct and indirect addressing mode with an example.
Direct address mode:
The effective address is equal to the address part of the instruction. The operand resides in
memory and its address is given directly by the address field of the instruction. In a branch
type instruction, the address field specifies the actual branch address.
It consists of a 3bit opcode, a 12 bit address and a mode bit 1 which is 0 for direct address.
A direct address instruction is placed is address 22 in memory.
Indirect Address mode:
The address field of the instruction gives the address where the effective address is stored
in memory. Control fetches the instruction from memory and uses its address part to
access memory again to read the effective address. One bit of the instruction code can be
used to distinguish between a direct and an indirect address.
The instruction is placed in address 35. The mode bit 1 and so is indirect address. The
address part is binary of 300. The control goes to address 300 to find the address of the
operand. The operand found in address 1350 is then added to the content of AC.
16. Explain any five Memory reference instruction.
Memory Reference – These instructions refer to memory address as an operand. The other
operand is always accumulator. Specifies 12-bit address, 3-bit opcode (other than 111) and
1-bit addressing mode for direct and indirect addressing.
The set of instructions incorporated in16 bit IR register are:

1. Arithmetic, logical and shift instructions (and, add, complement, circulate left,
right, etc)
2. To move information to and from memory (store the accumulator, load the
accumulator)
3. Program control instructions with status conditions (branch, skip)
4. Input output instructions (input character, output character)
Symbol Hexadecimal Code Description

AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store AC content in memory
BUN 4xxx Cxxx Branch Unconditionally
BSA 5xxx Dxxx Add memory word to AC
ISZ 6xxx Exxx Increment and skip if 0
17. What is addressing mode? Explain the different types of addressing modes.
The addressing mode gives or indicates a rule to identify the operands location.
Computers use addressing mode techniques for the purpose of accommodating the
following provisions.
• To give programming versatility to the user.
• To reduce the number of bits in the address field of the instruction.
• To provide flexibility for writing programs.
The various addressing modes available are:
• Implied mode:
In this mode the operands are specified implicitly in the definition of the
instruction. All register reference instructions that use an accumulator ar+
e implied mode instruction.
Ex: CMA
• Immediate mode:
The purpose of an address is to identify an operand value to be used in executing
the instruction. Sometimes the operand values is contained in the instruction
itself, this mode of operand specification is called immediate addressing mode.
Ex: MVI A, 45
• Register mode:
In this mode the operand are in registers which reside within the CPU. The
register is selected from the register field in the instruction.
Ex: MOV AX, BX
• Register indirect mode:
In this instruction, the address field specifies a processor register in the CPU
whose contents give the address of the operand in memory.
Ex: LXI H E000 ; memory address placed in processor register.
18. Explain three types of CPU organization.
There are three types of CPU organizations are:
• Single accumulator organization.
• General register organization.
• Stack organization.
a. Single accumulator organization: All operations are performed with an implied

accumulator register. The instruction format uses one address field.
ADD X
Where X is the address of the operand. This causes
AC <- AC +M[X].
The accumulator contents are added to the memory location content whose
address is X and the result is stored in the accumulator.
b. General register organization: General register type computers employ two or
three address fields in their instruction format. Each address field may specify a
processor register or a memory word.
ADD R1, X
This operation specifies R1 <- R1 + M[X]
It has two address fields, one for register R1 and the other for the memory
address X.
c. Stack organization: Computers with stack organization have PUSH and POP
instructions which require an address field.
PUSH X
The instruction will push the word at address X to the top of the stack.
19. Differentiate between CISC and RISC.
CISC RISC
1. Large number of instructions 1. Fewer instructions
2. Emphasis is on hardware 2.Emphasis is on software
3. It includes multi-clock complex 3.It includes single-clock, reduced
instructions instruction only
4. Memory-to-memory: “LOAD” 4.Register to register: “LOAD” and
and “STORE” incorporated in “STORE” are independent
instructions instructions
5. Code size is small but complex. 5.Code size is large but simple. Low
High cycles per second cycles per second
6. Variable length instruction 6.Fixed length instruction format
format
7. Large variety of addressing 7.Few addressing modes
modes
20. With a block diagram explain how BSA instruction executes .
Branch and Save Return Address
o This instruction is useful for branching to a portion of the program called a
subroutine or procedure.
o When executed, the BSA instruction stores the address of the next
instruction in sequence (which is available in PC) into a memory location
specified by the effective address.
o The effective address plus one is then transferred to PC to serve as the

address of the first instruction in the subroutine.
o This operation was specified with the following register transfer:

A numerical example that demonstrates how this instruction is used with
a subroutine is shown in Fig.
• The BSA instruction is assumed to be in memory at address 20.

• The I bit is 0 and the address part of the instruction has the binary equivalent of
135.
• After the fetch and decode phases, PC contains 21, which is the address of the
next instruction in the program (referred to as the return address). AR holds the
effective address 135.
• This is shown in part (a) of the figure.
• The BSA instruction performs the following numerical operation:
• The result of this operation is shown in part (b) of the figure.
• The return address21 is stored in memory location 135 and control continues
with the subroutine program starting from address 136.
• The return to the original program (at address 21) is accomplished by
means of an indirect BUN instruction placed at the end of the subroutine.
21. Explain sub-routine? Explain CALL and RETURN instructions?

• A set of Instructions which are used repeatedly in a program can be referred to as
Subroutine. Only one copy of this Instruction is stored in the memory. When a
Subroutine is required it can be called many times during the Execution of a
Particular program. A call Subroutine Instruction calls the Subroutine. Care
Should be taken while returning a Subroutine as Subroutine can be called from a
different place from the memory.
• Unconditional Return instruction: RET is the instruction used to mark the end of
sub-routine. It has no parameter. After execution of this instruction program
control is transferred back to main program from where it had stopped. Value of
PC (Program Counter) is retrieved from the memory stack and value of SP (Stack
Pointer) is incremented by 2.
• Conditional Return instruction –By these instructions program control is

transferred back to main program and value of PC is popped from stack only if
condition is satisfied. There is no parameter for return instruction.
Unconditional Call instruction –CALL address is the format for unconditional call
instruction. After execution of this instruction program control is transferred to a
sub-routine whose starting address is specified in the instruction. Value of PC
(Program Counter) is transferred to the memory stack and value of SP (Stack
Pointer) is decremented by 2.
• Conditional Call instruction –In these instructions program control is transferred

to subroutine and value of PC is pushed into stack only if condition is satisfied.
22. Explain the arithmetic logic shift with neat diagram

The arithmetic, logic, and shift circuits can be combined into one ALU with
common selection variables. One stage of an arithmetic logic shift unit is shown in
Fig. 4-13. The subscript i designates a typical stage. Inputs A1 and B1 are applied to
both the arithmetic and logic units.
• A particular microoperation is selected with inputs S1 and S0. A 4 x 1
multiplexer at the output chooses between an arithmetic output in E i and a
logic output in Hi. The data in the multiplexer are selected with inputs S3
and S2. The other two data inputs to the multiplexer receive inputs Ai - 1 for
the shift-right operation and Ai + 1 for the shift-left operation. Note that the
diagram shows just one typical stage. The circuit of Fig. 4-13 must be
repeated n times for an n-bit ALU. The output carry Ci + 1 of a given
arithmetic stage must be connected to the input carry Ci of the next stage in
sequence. The input carry to the first stage is the input carry C in, which
provides a selection variable for the arithmetic operations.
• The circuit whose one stage is specified in Fig. 4-13 provides eight arithmetic
operation, four logic operations, and two shift operations. Each operation is
selected with the five variables S3, S2, S1, S0, and Cin The input carry Cin is
used for selecting an arithmetic operation only.
• Table 4-B lists the 14 operations of the ALU. The first eight are arithmetic
operations and are selected with S3S2 = 00. The next four are logic
operations and are selected with S3S2 = 01. The input carry has no effect
during the logic operations and is marked with don't-care x's. The last two
operations are shift operations and are selected with S3S2 = 10 and 11. The
other three selection inputs have no effect on the shift.
23. With a block diagram explain how BSA instruction executes
Branch and Save Return Address
This instruction is useful for branching to a portion of the program called a
subroutine or procedure.
When executed, the BSA instruction stores the address of the next instruction in
sequence (which is available in PC) into a memory location specified by the
effective address.
The effective address plus one is then transferred to PC to serve as the address of
the first instruction in the subroutine.
This operation was specified with the following register transfer: A numerical
example that demonstrates how this instruction is used with a subroutine
The BSA instruction is assumed to be in memory at address 20.

The I bit is 0 and the address part of the instruction has the binary equivalent of
135.
After the fetch and decode phases, PC contains 21, which is the address of the
next instruction in the program (referred to as the return address). AR holds the
effective address 135.
This is shown in part (a) of the figure.
The BSA instruction performs the following numerical operation:
The result of this operation is shown in part (b) of the figure.
➢ The return address21 is stored in memory location 135 and control continues
with the subroutine program starting from address 136.
➢ The return to the original program (at address 21) is accomplished by means
of an indirect BUN instruction placed at the end of the subroutine.
24. Explain with a neat block diagram the input-output configuration ?

Each quantity of information consists of 8 bits of an alphanumeric code. The
serial information from the Keyboard is shifted into the input register INPR
through the transmitter interface from the input register, the information is
shifted in parallel into the Accumulator.
The terminal sends and receives serial information.
Each quantity of information has eight bits of an alphanumeric code.
The serial information from the keyboard is shifted into the input register INPR.
The serial information for the printer is stored in the output register OUTR.
These two registers communicate with a communication interface serially and
with the AC in parallel.
The input—output configuration is shown in Fig.
The input register INPR consists of eight bits and holds alphanumeric input
information.
The 1-bit input flag FGI is a control flip-flop.
The flag bit is set to 1 when new information is available in the input device and
is cleared to 0 when the information is accepted by the computer.
The output register OUTR works similarly but the direction of information flow
is reversed.
Initially, the output flag FGO is set to 1.
The computer checks the flag bit; if it is 1, the information from AC is
transferred in parallel to OUTR and FGO is cleared to 0.
The output device accepts the coded information, prints the corresponding
character, and when the operation is completed, it sets FGO to 1.
Input-Output Instructions:
Input and output instructions are needed for transferring information to and
from AC register, for checking the flag bits, and for controlling the interrupt
facility.
Input-output instructions have an operation code 1111 and are recognized by the
control when D7 = 1 and I = 1.
The remaining bits of the instruction specify the particular operation.
25. Explain the types of program interrupts.

Program interrupts: refers to the transfer of programs control from a currently
running program to another service program as a result of an external or internal
generated request.
Types of Interrupts:
There are three types of interrupts. They are:
(1) External interrupts
(2) Internal interrupts
(3) Software interrupts
(1) External interrupts are initiated from

✓ Input-output devices(I/O devices)
✓ Timing devices
✓ Circuit monitoring power supply
✓ Any external source
External interrupts are caused by
✓ I/O device requesting transfer of data
✓ I/O device finishing transfer of data
✓ Elapsed time of an event (timeout-program in endless loop) Power failure
(2) Internals interrupts are also called Traps. They arise from illegal or erroneous
use of an instruction or date.
Interrupts caused by internal error conditions are
✓ Register overflow
✓ Attempt to divide by zero
✓ Invalid operation code
✓ Stack overflow
✓ Protection violation
(3) Software interrupt is initiated by executing an instruction . It is a special call
instruction that behaves like an interrupt. It can be used to initiate an interrupt
procedure at any desired point in the program.
26. What are the major characteristics of RISC architecture?
Characteristics of RISC :
1. It has relatively fewer instructions.
2. There are relatively fewer and simple addressing modes.
3. Memory access is limited only to load and store instructions.
4. There are a large number of registers in the CPU.
5. All operations are carried out using the registers of the CPU.
6. Instructions format is of fixed length.
7. Instruction is easily decodable.
8. Instruction execution takes place in a single clock cycle.
9. Control is hardwired and not microprogrammed.
10. There are few data types in hardware
27. Explain the operation of interrupt cycle with a flow chart.

The interrupt cycle is a hardware implementation of a branch and save return
address operation.
1. The return address may be stored in a processor register, a memory stack or a
specific memory location. Here, the memory location at address 0 is chosen to store
the return address.
2. Then address 1 is inserted into Program Counter(PC), to branch to location 1.
3. The IEN and R are cleared so that no other interruptions can occur until the
interrupt request from the flag has been serviced.
Flowchart for Interrupt Cycle
There is an interrupt flip flop R.
• When R is 0, the computer goes through an instruction cycle.
• When R is 1, the computer goes through an interrupt cycle.
28. Write a note on RISC and CISC.
Complex Instruction Set Computer(CISC):

A computer with a large number of instructions is called Complex Instruction Set
Computer.
Features:
• The instructions provide direct manipulation of operands residing in
memory.
• A large number of instruction about 100 to 250 are provided.
• A large variety of addressing modes about 5 to 20 are provided.
Examples of CISC architecture are Digital Equipment Corporation VAX computer
and the IBM 370 computer.
Reduced Instruction Set Computer(RISC):
Computer that uses fewer instructions with simple constructs so that they can be
executed much faster within the CPU without having to use memory often is called
Reduced Instruction Set Computer.
Features:
• It has relatively fewer instructions.
• Memory access is limited only to load and store instructions.
• There are a large number of registers in the CPU
RISC families include Alpha, ARC, ARM, AVR, MIPS, SPARC, PIC, SuperH.
29. Explain input-output instructions.
Input/Output – These instructions are for communication between computer and

outside environment. The IR(14 – 12) is 111 (differentiates it from memory
reference) and IR(15) is 1 (differentiates it from register reference instructions).
The rest 12 bits specify I/O operation.
Example –
IR register contains = 1111100000000000, i.e. INP after fetch and decode cycle we
find out that it is an input/output instruction for inputing character. Hence, INPUT
character from peripheral device.
The set of instructions incorporated in16 bit IR register are:
Symbol Hexadecimal Code Description

INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
IEN F080 Interrupt On
30. Explain input and output interface unit with neat diagram?
Input Output Interface provides a method for transferring information between
internal storage and external I/O devices. Peripherals connected to a computer need
special communication links for interfacing them with the central processing unit.
The purpose of communication link is to resolve the differences that exist between
the central computer and each peripheral.
The Major Differences are:-
• Peripherals are electro technical and electromagnetic devices and CPU and
memory are electronic devices. Therefore, a conversion of signal values may be
needed.
• The data transfer rate of peripherals is usually slower than the transfer rate of
CPU and consequently, a synchronization mechanism may be needed.
• Data codes and formats in the peripherals differ from the word format in the
CPU and memory.
• The operating modes of peripherals are different from each other and must be
controlled so as not to disturb the operation of other peripherals connected to
the CPU
• To Resolve these differences, computer systems include special hardware
components between the CPU and Peripherals to supervises and synchronizes
all input and out transfers
These components are called Interface Units because they interface between the
processor bus and the peripheral devices.
I/O BUS and Interface Module: It defines the typical link between the processor
and several peripherals. The I/O Bus consists of data lines, address lines and control
lines. The I/O bus from the processor is attached to all peripherals interface. To
communicate with a particular device, the processor places a device address on
address lines. Each Interface decodes the address and control received from the I/O
bus, interprets them for peripherals and provides signals for the peripheral
controller. It is also synchronizing the data flow and supervises the transfer between
peripheral and processor. Each peripheral has its own controller.
For example, the printer controller controls the paper motion, the print timing. The
control lines are referred as I/O command. The commands are as following:
Control command- A control command is issued to activate the peripheral and to
inform it what to do.
Status command- A status command is used to test various status conditions in the
interface and the peripheral.
Data Output command- A data output command causes the interface to respond by
transferring data from the bus into one of its registers.
Data Input command- The data input command is the opposite of the data output.
In this case the interface receives on item of data from the peripheral and places it
in its buffer register. I/O Versus Memory Bus
31. Write a note on isolated vs memory mapped i/o?

Memory mapped I/O and Isolated I/O
As a CPU needs to communicate with the various memory and input-output devices
(I/O) as we know data between the processor and these devices flow with the help of
the system bus. There are three ways in which system bus can be allotted to them :
1. Separate set of address, control and data bus to I/O and memory.
2. Have common bus (data and address) for I/O and memory but separate
control lines.
3. Have common bus (data, address, and control) for I/O and memory.
In first case it is simple because both have different set of address space and
instruction but require more buses.
Isolated I/O
Then we have Isolated I/O in which we Have common bus(data and address) for I/O
and memory but separate read and write control lines for I/O. So when CPU decode
instruction then if data is for I/O then it places the address on the address line and
set I/O read or write control line on due to which data transfer occurs between CPU
and I/O. As the address space of memory and I/O is isolated and the name is so. The
address for I/O here is called ports. Here we have different read-write instruction
for both I/O and memory.
Memory Mapped I/O

In this case every bus in common due to which the same set of instructions
work for memory and I/O. Hence we manipulate I/O same as memory and
both have same address space, due to which addressing capability of
memory become less because some part is occupied by the I/O.
32. Differences between memory mapped I/O and isolated I/O –
Isolated I/O Memory Mapped I/O
Memory and I/O have separate address

Both have same address space
space
Due to addition of I/O addressable memory

All address can be used by the memory
become less for memory
Separate instruction control read and write Same instructions can control both I/O and
operation in I/O and Memory Memory
In this I/O address are called ports. Normal memory address are for both
More efficient due to separate buses Lesser efficient
Larger in size due to more buses Smaller in size
It is complex due to separate separate logic Simpler logic is used as I/O is also treated
is used to control both. as memory only.
33. Explain source initiated data transfer using handshaking

Source initiated Handshaking – When source initiates the data transfer process. It
consists of signals:
DATA VALID: if ON tells data on the data bus is valid otherwise invalid.
DATA ACCEPTED: if ON tells data is accepted otherwise not accepted.
(i) Source places data on the data bus and enable Data valid signal.
(ii) Destination accepts data from the data bus and enable Data accepted signal.
(iii) After this, disable Data valid signal means data on data bus is invalid now.
(iv) Disable Data accepted signal and the process ends.
Now there is surety that destination has read the data from the data bus through
data accepted signal. Signals can be seen as:
34. What is polling? Explain.
The software method used to identify the highest priority source is called Polling.
There is one common branch address for all interrupts.
1. The program begins at the branch address and polls the interrupt sources in
sequence.
2. The order in which they are tested decides the priority of the interrupts.
3. First the highest priority source is tested. If its interrupt signal is on, control
branches to a service routine for this source. Otherwise, the next lower priority
source is tested and so on.
4. The initial service routine for all interrupts consists of a program that tests the
interrupt sources in sequence and branches to one of many possible service
routines.
5. The particular service routine reached belongs to the highest priority device
among all devices that interrupted the computer.
35. Explain Associative memory with a neat block diagram.

The associative memory has cells that have storage capability as well as logic
circuits for matching its content with an external argument. These memories are
used in applications where the search time is very critical and must be very short. A
memory unit accessed by content is called an associative memory or content
addressable memory(CAM)
Block diagram of associative memory
• Each word in memory is compared in parallel with the content of the

argument register.
• The words that match the bits of the argument register set a corresponding
bit in the match register.
• Those bits in the match register that have been set indicate that their
corresponding words have been matched.
• A sequential access to memory for those words, whose corresponding bits in
the match register have been set, causes reading of words in memory.
• The key register provides a mask for choosing a particular field or key in the
argument word.
• Those bits in the argument that have 1’s in their corresponding position of
the key register are compared.
36. What are the important characteristics of memory?
Characteristics of memory:
1.Location 2.Capacity 3.Unit of transfer 4.Access Method 5.Performance
6.Physical type 7.Physical characteristics 8.Organization
1. Location:
It deals with location of the memory device in the computer system. There
are three possible locations:
• CPU : This is often in the form of CPU registers and small amount of cache.
• Internal or main: This is the main memory like RAM or ROM.The CPU can
directly access the main memory
• External or secondary: It comprises of secondary storage devices like hard
disks, magnetic tapes.
2. Capacity:
The capacity of any memory device is expressed in terms of:1) Word size
2)Number of words
• Word size: words are expressed in bytes(8 bits). A word can however mean
my number of bytes.
• Number of words: This specifies the number of words available in the
particular memory device.
3. Unit of transfer:
It is the maximum number of bits that can be read or written into the
memory.
4. Access Methods:
It is fundamental characteristics of memory devices. It is the sequence or order in
which memory can be accessed.
5. Performance
The performance of system is determined using three parameters:
• Access Time : In random access memories, it is the time taken by memory
to complete the read/write operation from the instant that an address is sent
to the memory.
• Memory cycle time: It is defined only for random access memories and is
the sum of the access time and the additional time required before the
second access can commence.
• Transfer rate: It is defined as the rate at which data can be transferred into
or out of a memory unit.
6. Physical rate:
Memory devices can be either semiconductor memory(like RAM) or magnetic
surface memory(Like hard disks).
7. Physical Characteristics:
✓ Volatile/Non Volatile: If a memory devices continues hold data even if power
is turned off. The memory device is non-volatile else it is volatile.
8. Organizations:
✓ Erasable/Non-erasable: The memories in which data once programmed
cannot be erased are called Non-erasable memories. Memory device in which
data in the memory can be erased is called erasable memory.
37. Explain the block diagram of a computer with I/O processors.
CPU is the master while the IOP is a slave processor. The CPU performs the task of
initiating all operations.
The operations include
✓ Starting an I/O transfer
✓ Testing I/O status conditions needed for making decisions on various
I/O activities.
I/O instructions are executed in the IOP. The IOP asks for the attention of the CPU
by means of an interrupt. It also responds to CPU requests by placing a status word
in a prescribed location in memory to be examined by CPU program.
For an I/O operation execution, the CPU informs the IOP where to find the I/O
program and then leaves the transfer details to the IOP.
The instructions that are read from memory by an IOP are sometimes called
Commands, to distinguish them from instructions that are read by the CPU.
38. Write a note on cache memory.
The active portions of the program and data are placed in a fast small memory.
This reduces the average memory access time and hence the total execution time of
the program. This memory is called Cache memory. It is placed between the CPU
and the main memory. Performance of cache memory is frequently measured in
terms of a quantity called Hit ratio. Loops and subroutines tend to localize the
references to memory for fetching instruction. Reference to memory at any given
interval of time tend to be confined within a few localized areas in memory. This
phenomenon is known as the property of locality of reference.
The basic operations of cache can be as follows:
1. When CPU wants to access memory, it first examines the cache.
a. If the word is found in the cache, it is read from this memory.
b. If the word is not found in the cache, the main memory is accessed.
2. A block of words containing the most recent accessed one is then transferred
from main memory to cache memory so that future references can find the
required words in cache.
39. Write a note on modes of data transfer

Modes of I/O Data Transfer
Data transfer between the central unit and I/O devices can be handled in generally
three types of modes which are given below:
1. Programmed I/O
2. Interrupt Initiated I/O
3. Direct Memory Access
Programmed I/O :
• Programmed I/O instructions are the result of I/O instructions written in
computer program. Each data item transfer is initiated by the instruction in
the program. Usually the program controls data transfer to and from CPU
and peripheral. Transferring data under programmed I/O requires constant
monitoring of the peripherals by the CPU.
Interrupt Initiated I/O

• In the programmed I/O method the CPU stays in the program loop until the
I/O unit indicates that it is ready for data transfer. This is time consuming
process because it keeps the processor busy needlessly.
This problem can be overcome by using interrupt initiated I/O. In this when the
interface determines that the peripheral is ready for data transfer, it generates an
interrupt. After receiving the interrupt signal, the CPU stops the task which it is
processing and service the I/O transfer and then returns back to its previous
processing task.
Direct Memory Access

• Removing the CPU from the path and letting the peripheral device manage
the memory buses directly would improve the speed of transfer. This
technique is known as DMA. In this, the interface transfer data to and from
the memory through memory bus. A DMA controller manages to transfer
data between peripherals and memory unit.
Many hardware systems use DMA such as disk drive controllers, graphic cards,
network cards and sound cards etc. It is also used for intra chip data transfer in
multicore processors. In DMA, CPU would initiate the transfer, do other operations
while the transfer is in progress and receive an interrupt from the DMA controller
when the transfer has been completed.
Above figure shows block diagram of DMA
40. Write a note on DMA
Direct Memory Access (DMA):

In the Direct Memory Access (DMA) the interface transfer the data into and out of
the memory unit through the memory bus. The transfer of data between a fast
storage device such as magnetic disk and memory is often limited by the speed of
the CPU. Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of transfer. This
transfer technique is called Direct Memory Access(DMA).
During the DMA transfer, the CPU is idle and has no control of the memory buses.
A DMA Controller takes over the buses to manage the transfer directly between the
I/O device and memory.
The CPU may be placed in an idle state in a variety of ways. One common method
extensively used in microprocessor is to disable the buses through special control
signals
such as:
◼ Bus Request (BR)
◼ Bus Grant (BG)
These two control signals in the CPU that facilitates the DMA transfer. The Bus
Request
(BR) input is used by the DMA controller to request the CPU. When this input is
active, theCPU terminates the execution of the current instruction and places the
address bus, data bus and read write lines into a high Impedance state. High
Impedance state means that the output is disconnected
The CPU activates the Bus Grant (BG) output to inform the external DMA that the
Bus Request (BR) can now take control of the buses to conduct memory transfer
without processor. When the DMA terminates the transfer, it disables the Bus
Request (BR) line. The CPU disables the Bus Grant (BG), takes control of the buses
and return to its normal operation.
The transfer can be made in several ways that are:
i. DMA Burst
ii. Cycle Stealing
i) DMA Burst :- In DMA Burst transfer, a block sequence consisting of a number of
memory words is transferred in continuous burst while the DMA controller is
master
of the memory buses.
ii) Cycle Stealing :- Cycle stealing allows the DMA controller to transfer one data
word at a time, after which it must returns control of the buses to the CPU.
41. Explain DMA controller with a block diagram.

• DMA controller provides an interface between the bus and the input-output
devices. Although it transfers data without intervention of processor, it is
controlled by the processor. The processor initiates the DMA controller by
sending the starting address, Number of words in the data block and
direction of transfer of data .i.e. from I/O devices to the memory or from
main memory to I/O devices. More than one external device can be
connected to the DMA controller.
• DMA controller contains an address unit, for generating addresses and
selecting I/O device for transfer. It also contains the control unit and data
count for keeping counts of the number of blocks transferred and indicating
the direction of transfer of data. When the transfer is completed, DMA
informs the processor by raising an interrupt. The typical block diagram of
the DMA controller is shown in the figure below.
• DMA controller has to share the bus with the processor to make the data
transfer. The device that holds the bus at a given time is called bus master.
When a transfer from I/O device to the memory or vice versa has to be
made, the processor stops the execution of the current program,
increments the program counter, moves data over stack then sends a DMA
select signal to DMA controller over the address bus. If the DMA controller
is free, it requests the control of bus from the processor by raising the bus
request signal. Processor grants the bus to the controller by raising the bus
grant signal, now DMA controller is the bus master. The processor initiates
the DMA controller by sending the memory addresses, number of blocks of
data to be transferred and direction of data transfer. After assigning the
data transfer task to the DMA controller, instead of waiting ideally till
completion of data transfer, the processor resumes the execution of the
program after retrieving instructions from the stack.
42. Explain the working of Associative memory,

The associative memory has cells that have storage capability as well as logic
circuits for matching its content with an external argument. These memories are
used in applications where the search time is very critical and must be very short. A
memory unit accessed by content is called an associative memory or content
addressable memory(CAM)
• Each word in memory is compared in parallel with the content of the
argument register.
• The words that match the bits of the argument register set a corresponding
bit in the match register.
• Those bits in the match register that have been set indicate that their
corresponding words have been matched.
• A sequential access to memory for those words, whose corresponding bits in
the match register have been set, causes reading of words in memory.
• The key register provides a mask for choosing a particular field or key in the
argument word.
• Those bits in the argument that have 1’s in their corresponding position of
the key register are compared.
•
43. Explain memory hierarchy.
Memory Hierarchy is the combination of storage components that make up the
overall physical memory system of a computer. The various components are
typically arranged from fastest to the slowest in terms of their access time. So the
term ‘hierarchy’ is used. The goal of using hierarchy is to obtain the highest
possible access speed whole minimizing total cost of entire memory system. The
memory hierarchy system consists of all storage devices used in a computer system
from smaller and faster cache memory to the slower high capacity auxiliary
memory.
Memory Hierarchy in a computer

The total memory capacity of a computer can be visualized by hierarchy of
components. The memory hierarchy system consists of all storage devices contained
in a computer system from the slow Auxiliary Memory to fast Main Memory and to
smaller Cache memory.
Auxillary memory access time is generally 1000 times that of the main memory,
hence it is at the bottom of the hierarchy.
The main memory occupies the central position because it is equipped to
communicate directly with the CPU and with auxiliary memory devices through
Input/output processor (I/O).
When the program not residing in main memory is needed by the CPU, they are
brought in from auxiliary memory. Programs not currently needed in main
memory are transferred into auxiliary memory to provide space in main memory
for other programs that are currently in use.
The cache memory is used to store program data which is currently being executed
in the CPU. Approximate access time ratio between cache memory and main
memory is about 1 to 7~10.
44. Write a note on virtual memory?

virtual memory is a memory management capability of an operating system (OS)
that uses hardware and software to allow a computer to compensate for physical
memory shortages by temporarily transferring data from random access memory
(RAM) to disk storage. Virtual address space is increased using active memory in
RAM and inactive memory in hard disk drives (HDDs) to form contiguous
addresses that hold both the application and its data.
Virtual memory was developed at a time when physical memory -- the installed
RAM -- was expensive. Computers have a finite amount of RAM, so memory can
run out, especially when multiple programs run at the same time. A system using
virtual memory uses a section of the hard drive to emulate RAM. With virtual
memory, a system can load larger programs or multiple programs running at the
same time, allowing each one to operate as if it has infinite memory and without
having to purchase more RAM.
While copying virtual memory into physical memory, the OS divides memory into
pagefiles or swap files with a fixed number of addresses. Each page is stored on a
disk and when the page is needed, the OS copies it from the disk to main memory
and translates the virtual addresses into real addresses.
*****
SOLUTION BANK
BCA 504T JAVA PROGRAMMING

BCA504T: OBJECT ORIENTED PROGRAMMING USING JAVA
Total Teaching Hours: 60 No of Hours / Week: 04
Unit - I
Introduction to JAVA: JAVA Evolution: Java History, Java Features, How Java Differs from C and
C++, Java and Internet, Java and World Wide Web, Web Browsers, Hardware and Software
Requirements, Java Support Systems, Java Environment. Overview of JAVA Language: Introduction,
Simple Java program, More of Java Statements, Implementing a Java Program, Java Virtual Machine,
Command Line Arguments, Programming Style. Constants, Variables, and Data Types: Introduction,
Constants, Variables, Data Types, Declaration of Variables, Giving Values to Variables, Scope of
Variables, Symbolic Constants, Type Casting, Getting Values of Variables, Standard Default Values,
Operators and Expressions: Introduction, Arithmetic Operators, Relational Operators Logical
Operators, Assignment Operators, Increment and Decrement Operators, Conditional Operators,
Bitwise Operators, Special Operators, Arithmetic Expressions, Evaluation of Expressions, Precedence
of Arithmetic Operators, Type Conversion and Associativity, Mathematical Functions. Decision
Making and Branching: Introduction, Decision Making with if Statement, Simple if Statement, The
if…..else Statement, Nesting of if………Else Statements, The else if Ladder, The Switch Statement,
The ?: Operator. Decision Making and Looping: Introduction. The while Statement, The do Statement,
Thefor Statement, Jumps in Loops Labeled Loops. [12 hours]
Unit -II
Classes, Arrays, Strings and Vectors: Classes, Objects and Methods: Introduction, Defining a Class,
Adding Variables, Adding Methods, Creating Objects, Accessing Class Members, Constructors,
Methods Overloading, Static Members, Nesting of Methods, Inheritance: Extending a Class
Overriding Methods, Final Variables and Methods, Finalizer methods, Abstract Methods and Classes,
Visibility Control. Arrays, Strings and Vectors: Arrays, One-dimensional Arrays, Creating an Array,
Two -Dimensional Arrays, Creating an Array, Two – dimensional Arrays, Strings, Vectors, Wrapper
Classes. [ 12 Hours ]
Unit - III
Interfaces, Packages, and Multithreaded Programming: Interfaces: Multiple Inheritance: Introduction,
Defining Interfaces, Extending Interfaces, Implementing Interfaces, Accessing Interface Variables.
Packages: Putting Classes together: Introduction, Java API Packages, Using System Packages,
Naming Conventions, Creating Packages, Accessing a Package, Using a Package, Adding a Class to a
Package, Hiding Classes. Multithreaded Programming: Introduction, Creating Threads, Extending the
Thread Class, Stopping and Blocking a thread, Life Cycle of a thread, Using Thread Methods, Thread
Exceptions, Thread Priority, Synchronization, Implementing the ‘Runnable’ Interface. [12 Hours]
Unit - IV
Managing Exceptions, Applet Programming: Managing Errors and Exception: Introduction, Types of
Exception Handling Code, Multiple Catch Statements, Using Finally Statement, Throwing Our Own
Exceptions, Using Exceptions for Debugging. Applet Programming: Introduction, How Applets
Differ from Applications, Preparing to Write Applets, Building Applet Code, Applet Life Cycle,
Creating an Executable applet, Designing a Web Page, Applet Tag, Adding Applet to HTML File,
running the Applet, More About HTML Tags, Displaying Numerical Values, Getting Input from the
User. [12 Hours
Unit - V
Graphics Programming, Input/Output: Graphics programming: Introduction, The Graphics Class,
Lines and rectangles, circles, and Ellipses, Drawing Arcs, Drawing Polygons, Lines Graphs, Using
Control Loops in Applets, Drawing Bar Charts. Managing Input/Output Files in JAVA: Introduction,
Concept of Streams, Stream Classes, Byte Stream Classes, Character Stream Classes, Using Streams,
Other Useful I/O Classes, Using the File Class, Input / Output Exceptions, Creation of Files, Reading /
Writing Characters, Reading / Writing Bytes, Handling Primitive Data Types, Concatenating and
Buffering Files, Interactive Input and output, Other Stream Classes. [ 12 Hours ]
Text Books:
1. A.Balaguruswamy, “Programming with JAVA”, A Primer, TMH, 1999.
Reference Books:
1. Thomas Boutel, “CGI programming in C and Perl”, Addison – Wesley, 1996.
2. Jefry Dwight et al, Using CGI, Second Edition, Prentice Hall, India, 1997.
3. Patrick Naughton & Herbert Schildt, JAVA 2: The Complete Reference, THM, 1999.
4. Schildt, “JAVA The Complete Reference”, 7th Edition.
BCA504T: OBJECT ORIENTED PROGRAMMING USING JAVA
BLUE PRINT
Question paper pattern for theory has two sections :
Section – A :Contains 12 questions, out of which a student has to answer 10 questions.
Each question carries 2 marks ( 10 x 2 = 20 )
Section – B :Contains 5 full questions includes sub-question as (a) & (b). Each full
question carries 10 marks (5 x 10 = 50)
SECTION A SECTION B
UNIT CHAPTER
2 MARKS 10 MARKS
Introduction to JAVA 1 -
Overview of JAVA Language - 1
I Constants, Variables, and Data Types 1 1
Operators and Expressions 1 1
Decision Making and Branching - -
Classes, Objects and Methods 1 1
Inheritance - 1
II
Arrays, Strings and Vectors 1 1
Wrapper Class - -
Interfaces 1 1
III Packages 1 1
Multithreaded Programming: 1 2
Managing Exceptions 1 1
IV
Applet Programming 1 2
Graphics Programming 1 2
V
Managing Input/Output Files in JAVA 1 1
TOTAL 12 16
ANSWER ANY 10 ANSWER ANY 5
TOTAL MARKS 20 50
UNIT-I
[Nov / Dec 2015]
1. What do you mean by command line argument?
2. What are the two ways of giving values to the variable?
3. Write down the default values of byte and char data types?
[Nov / Dec 2016]

1. Why java is simple? Mention any two reasons?
2. What are string literals?
3. Give the general form of ‘switch’ statement?
[Nov / Dec 2017]

1.What is byte code? Justify how java is platform independent?
2.What is ‘labelled break’ and ‘labelled continue’?
3.Mention the data types in java?
[Nov / Dec 2018]

1. What are important elements of internet architecture?
2. What are the default values of float and char primitive data types in java?
3. Give the general form of switch statement?
1. What is difference between JDK, JRE and JVM?
2. What are the different types of comments in Java?
3. What is the difference between Java and C++?
4. What is difference between Java and C?
5. What are the reserved literals in Java?
6. What is System.in and System.out?
UNIT-II
[Nov / Dec 2015]
1. Define a class and write down its syntax?
2. What is the use of ‘this’ and ‘super’ keyword?
3. How multiple inheritances are achieved in Java?
[Nov / Dec 2016]

1. What is instance variable? Give an example.
2. Write a few points about ‘default constructor’.
3. What does ‘static’ keyword do in a class?
[Nov / Dec 2017]

1. What is default constructor and parameterized constructor?
2. What is the use of ‘super ‘and ‘this ‘keyword?
3. Difference b/w ‘string’ class and ‘string buffer’ class.
[Nov / Dec 2018]

1. What is the difference between constructor and methods?
2. Difference between class and abstract class?

1. What is an object? How to create an object?
2. How to get primitive values from wrapper objects?
3. What is explicit casting?
4. What is the difference between overloading and overriding.
5. What is a vector?
6. Why strings are called as immutable?
7. How is an array created in Java?
8. What is constructor? How constructor are overloaded?
9. What is inheritance? List types of Inheritance.
UNIT-III
[Nov / Dec 2015]
1. What is concurrency?
[Nov / Dec 2016]

1. What is java API?
[Nov / Dec 2017]

1. Define package. Mention its use.
2. Mention the ways of implementing multithreading in java.
[Nov / Dec 2018]

1. Mention any four thread methods?
2. What are the different access modifiers in java?

1. What is Thread and Synchronization?
2. List all the access control modifiers in Java. Explain default access modifier.
3. What is an interface and abstract class?
4. What are the different ways of creating thread?
UNIT-IV
[Nov / Dec 2015]
1. What is exception?
2. How user defined exception is done?
3. Write down the applet code for “hello-class”file?
4. Why repaint () method is used?
[Nov / Dec 2016]

1. What is exception handling?
2. What is the need for ‘applet viewer’?
3. What is error? Compare with exception.
4. What is the purpose of ‘init ()’ method in applet?
[Nov / Dec 2017]
1. Define an exception. How is exception handling done in java.
[Nov / Dec 2018]
1. What is the difference between error and exception?
2. How applets differ from applications?

1. How exceptions are classified in Java?
2. What is use of throw keyword?
3. Mention the attributes of PARAM tag?
4. Explain <APPLET> tag with an example.
5. Explain update() and repaint() methods.
6. How to create user defined exceptions?
UNIT-V
[ Nov / Dec 2015 ]
1. Which method is used to draw a circle?
[ Nov / Dec 2016 ]

1.What is the use of canvas in AWT?
[ Nov / Dec 2017 ]

1. Mention any four classes in AWT package?
2. Define a stream in java. Briefly mention the broad classification of java stream classes?
[Nov / Dec 2017]

1. What is the use of java I/O classes?
1. What is the difference between character oriented and byte oriented streams?
2. What is stream? How stream are classified?
3. What is the use of Graphic class?
UNIT-I
[Nov / Dec 2015]
1. Explain the features of java?
2. Write a note on scope of variables?
4. Write a program to display all prime numbers between two limits using command line
argument.
[Nov / Dec 2016]

1. Explain the line “public static void main(String args[] )”.
2. Explain the history and evolution of java.
3. Explain bitwise and logical operators with example.
[Nov / Dec 2017]

1. What are static variables and static methods?
[Nov / Dec 2018]

1. Explain the difference between JDK and JRE.
2. Explain bitwise operators.
1. What is the role of JVM and explain its components.
2. How to define a constants in Java?
3. Explain operators in Java.
4. Explain Java tokens.
5. Explain the iterative statements in Java?
6. What is System.out.println()? Explain what is System.out.
SECTION – B( 5Marks)
UNIT-II
[Nov / Dec 2015]
1. Differentiate between string and string buffer.
2. What is vector? Mention its advantages over an array.
3. How string class different from string buffer class? Give two methods of string class.
4. What is method overriding? Write a program to demonstrate method overriding.
5. Explain any seven string methods with example.
6. Write a note on inheritance.
[Nov / Dec 2016]
1. How to create object? What happens when you create objects?
2. Demonstrate ‘this’ keyword with simple java program.
3. Differentiate component and container class.
4. Give the general form of inheritance with one example.
5. Illustrate array declaration and accessing data elements using an example.
6. Differentiate constructors and methods.
7. Write a program to sort a list of elements in ascending order.
[Nov / Dec 2017]

1. Explain with example:
i. Method overloading.
ii. Method overriding
iii. Abstract method.
iv. Abstract class.
2. Define inheritance. Explain the types of inheritance supported by java.
3. Explain the tree string methods with example.
4. Differentiate between arrays and vectors.
5. Explain visibility control in java.
[Nov / Dec 2018]

1. What is the difference between overloading and overriding?
2. Explain any four string methods with example.
1. Explain the various uses of wrapper classes.
2. Explain array of object references.
3. Why multiple inheritance is not supported in Java?
4. What are the rules of method overriding?
5. What is the use of abstract classes?
6. What is the use of finalize() method?
7. How to create wrapper object?
UNIT-III
[Nov / Dec 2015]
1. What is package? Write down the steps for creating user defined package.
2. What is thread ?explain thread cycle with neat diagram.
3. What is interface? Write a program to demonstrate interface.
[Nov / Dec 2016]

1. Give the general form of interface with one example.
2. Give the steps to create and use a java package with an example.
3. Explain the life cycle of thread.
[Nov / Dec 2017]

1. What is interface? Explain with an example how a class implements an interface.
2. Explain with an example the implementation of multithreading by extending ‘thread class’.
[Nov / Dec 2018]

1. Explain the process of creating user defined package with an example.
2. Write the steps involved in creating thread by implementing runnable interface.
1. What is use of interface? What are the rules for defining an interface?
2. How multiple interface is achieved using interface?
3. What are access control modifiers?.
4. How to hide classes?
5. What are the different types of creating thread?
6. Explain thread priorities with an example.
7. Explain different method of thread class?
UNIT-IV
[Nov / Dec 2015]

1. What do u mean by unchecked exception? Write a program to illustrate try, catch and finally
statement.
2. What is applet? Explain applet life cycle with a neat diagram.
3. Write a program to implement mouse events.
[Nov / Dec 2016]

1. Explain the steps to of executing an applet using a simple code.
2. Explain try, catch with example.
[Nov / Dec 2017]

1. Explain user defined exception in java.
2. Explain how parameters passed to an applet.
[Nov / Dec 2018]

1. Explain the life cycle of an applet with a neat diagram.
1. How Java handles the exception? What are the types of exception in Java?
2. Name few of the exception classes in Java?
3. How to display numeric values in an applet?
4. Explain update() and repaint() methods.
5. What are the different ways of executing an applet?
UNIT-V
[Nov / Dec 2015]

1. Write down the steps for drawing polygons.
2. Give the classification of input stream classes
3. Write a note on graphics class and its methods.
[Nov / Dec 2016]

1. Write a short note on graphics class
2. Give classification on “java.io.IOException”. Explain IOException .
[Nov / Dec 2017]

1. Explain any seven methods of graphics class with an example for each.
2. Explain the use of file input stream class and file output stream class.
[Nov / Dec 2018]

1. Write a short note on data output stream and data output stream.
1. Explain the graphics cocordinatesystem.?
2. How to draw bar chart in an applet?
3. What is BufferedInputStream and BufferedOutputStream?
BCA-504 JAVA PROGRAMMING (2 marks)
1. What are the two ways of giving values to the variable?
Ans. The two ways of giving values to the variable are:
➢ By using an assignment statement
➢ By using a read statement
2. Write down the default values of byte and char data types?
➢ The default value of byte=0
➢ The default value of char=NULL CHARACTER
3. What do you mean by command line argument?

Ans. Command line arguments are the parameters that are supplied to the application
program at the time of invoking it for execution.
4. Define a class and write down its syntax?

Ans. A class is a template that defines the form of an object. A class definition consists of
two members- Data member and Methods.
Syntax:
[access modifier] [class modifier] class class_name [extends super_class_name]
[implementinterfacelist]
{
[variable declaration]
[method declaration]
}
5. What is the use of ‘this’ and ‘super’ keyword?
Ans. Use of ‘this’ keyword:

➢ This refers to the current object.
➢ The first use of this is to call constructor from another constructor, specially one in
the current class. The second function is to avoid namespace conflicts between a
methods or constructors parameter list and its variable.
Use of ‘super’ keyword:

➢ The super is used to call super class constructor explicitly.
➢ If the same variables are defined in both super class and subclass, then super is used
to access super class variable inside subclass method.
➢ If the same methods are present in both super class and subclass, then super is used
to call super class method from subclass method.
6. How multiple inheritances are achieved in Java?
Ans. Multiple inheritance in Java programming is achieved or implemented using

interfaces. Java does not support multiple inheritances using classes.A class can extend
only one class but it can implement multiple interfaces.
7. What is concurrency?
Ans. Concurrency is the ability to run several programs or several parts of a program in
parallel. The backbone of java concurrency is threads. A thread is a lightweight process
which has its own call stack, but can access shared data of other threads in the same
process.
8. What is exception?
Ans. An exception is an error that occurs at run time.
9. How user defined exception is done?

Ans. To create the exception object, the program uses the throw keyword followed by the
instantiation of the exception object. At runtime, the throw clause will terminate
execution of the method and pass the exception to the calling method.
10. Write down the applet code for “hello-class”file?
Ans.
import java.applet.Applet;
import java.awt.Graphics;
public class HelloCLASSApplet extends Applet
{
public void paint(Graphics g){
g.drawString("Hello CLASS", 50, 50);
}
}
11. Why repaint () method is used?

Ans. This method can't be overridden. It controls the update() -> paint() cycle. You
should call this method to get a component to repaint itself. If you have done anything to
change the look of the component, but not its size ( like changing color, animating, etc. )
then call this method.
12. Which method is used to draw a circle?

Ans. drawOval() is the method used to draw a circle.
13. Mention the ways of implementing multithreading in Java?

Ans. The ways of implementing multithreading in Java are:
➢ Extends Thread class. Create a thread by a new class that extends Thread class and
create an instance of that class.
➢ Implementing the runnable interface. The easiest way to create a thread is to create a
class that implements the runnable interface.
Ans. Thread methods are:

➢ start()
➢ run()
➢ yield()
➢ wait()
15. Mention any four classes in AWT package?

Ans.
➢ GUI Component classes
➢ GUI Container classes
➢ Layout managers
➢ Custom graphics classes
16. Why java is simple? Mention any two reasons.
Ans. Java is one of the simple programming language because java removes some
complex concept like pointer and execution time will be less.
Reasons:-
➢ Much easier to write bug free code.
➢ Java has considerably more functionality than c.
17. What are string literals?

Ans. String literals are a sequence of characters from the source character set enclosed in
double quotation marks (“ ”).
18. Give the general form of ‘switch’ statement.
Ans.
switch(expression)
{
Case value1:
break;
Case value2:
break;
……….
default:
}
19. What is instance variable? Give an example.
Ans.
➢ Instance variables are declared in a class , but outside a method. They are also
called member or field variables.
➢ Instance variables are created when an object is created and destroyed when the
object is destroyed.
20. Write a few points about ‘default constructor’.
Ans. Constructor with no arguments is called as default constructor

The default constructor is useful to initialize all objects with same data.
Ex:
A()
{
}
21. What does ‘static’ keyword do in a class?

Ans. The keyword static indicates that the particular member belongs to a type itself,
rather than to an instance of that type. This means that only one instance of
that static member is created which is shared across all instances of the class.
22. What is java API?

Ans. Java API(application programming interface) is the set of huge number of classes
and methods grouped into packages and it is included with the java development
environment. The most commonly used packages are:
➢ java.lang
➢ java.io
23. What is exception handling?
Ans. The java mechanism that deals with handling the errors I an organized fashion is
called as the exception handling.
24. What is the need for ‘applet viewer’?

Ans. An applet viewer is tool provided with the standard java JDK to execute an applet.
25. What is error? Compare with exception.
Ans. Errors are related to errors that occur in the java virtual machine itself, and not in
a program. These types of exceptions are beyond our control, and a program will not
handle them.An exception is an error which can be handled .An error is an error which
cannot be handled.
26. What is the purpose of ‘init ()’ method in applet?
Ans. init()- is called to initialize the applet before it gets loaded.
27. What is the use of canvas in AWT?

Ans. A canvas is for drawing on, basically. It also serves like a Panel for creating a
custom AWT-based component, but unlike Panel it can't contain other components.
28. What is byte code? Justify how java is platform independent.

Ans. Byte code are the machine level language of the JVM. when a JVM loads a class
file, it gets one stream of bytecodes for each method in the class. Java is a platform
independent because java compiler converts the source code to byte code. It can be
executed on any platform using JVM.
29. What is default constructor and parameterized constructor?

Ans. Default constructor: Constructor with no arguments is called as default
constructor
Ex:
A()
{
}
Parameterized constructor: Constructor with arguments is called as parameterized
constructor.
Ex:
A(int a)
{
}
30. What are the default values of float and char primitive data types in java?
Ans.
• Default value of float =0.0f
• Default value of char = NULL CHARACTER
31. What is ‘labelled break’ and ‘labelled continue’?
Ans. Labeled break: the break statement breaks out the closest loop or switch
statement.
Ex: for(int i=0;i<10;i++){
while(true){
break;
}
}
Labelled continue: the continue statement transfers the control to the closest enclosing
loop.
Ex: for(int i=0;i<10;i++){
while(j<10){
if(j==5)
continue;
}
}
32. Define package. Mention its use.
Ans. Package in Java is a mechanism to encapsulate a group of classes, sub packages and
interfaces. Packages are used for preventing naming conflicts.
33. What are important elements of internet architecture?

Ans.
• Modem
• ISP
• Router
• Internet
• Backbone
• TCP/IP
• Network access points or NAPs
• Domain name service(DNS) and DNS Servers
34. Give the general form of switch statement.

Ans.
switch (expression)
{
Case value1:
Break;
Case value2:
Break;
………………..
default:
}
35. What is the difference between constructor and methods?

Constructor Methods
Constructor is used to initialise the A Method is used for any general
instance variables of a class purpose tasks like calculations
A constructor name should be always The method and class name can be same
same as class name or different
36. Difference between class and abstract class?
Class Abstract class
The class does not contain abstract It contains abstract methods
methods
The class can be instantiated Abstract classes cannot be instantiated
37. What is instance variable? Give an example?

Ans. Instance variable are the variable declared in a class but outside a method
Ex: class rectangle
{
double length;
double breadth;
}
Ans.
➢ CurrentThread()
➢ getName()
➢ run()
➢ sleep()
39. What are the different access modifiers in java?
Ans.
➢ Private
➢ Default
➢ Protected
➢ Public
40. What is the use of java I/O classes?

Ans. Java I/O (Input and Output) is used to process the input and produce the
output. Java uses the concept of a stream to make I/O operation fast.
41. What is the difference between error and exception?

ERROR EXCEPTION
All errors in java are unchecked type Exception s include both checked as well
as unchecked type
Errors are mostly caused by the exception are mainly caused by
environment In which applications is application itself
running
42. Define a stream in java. Briefly mention the broad classification of java stream classes?
Ans. A stream can be defined as a sequence of data. The input stream is used to read data
from a source and the Output Stream is used for writing data to a destination.
43. How applets differ from applications?
Ans. The main difference between Applet and Application is that the applet is a small
java program that can be executed by a Java-compatible web browser while
the application is a standalone program that can directly run on the machine.
44. What is the use of ‘super ‘and ‘this ‘keyword?
Ans. super : it is used to call the constructors of super class.

this : it is used to call the constructors of same class.
45. Mention the data types in java?

Ans.
Primitive data types
Non-Primitive data types
46. Difference b/w ‘string’ class and ‘string buffer’ class.

STRING CLASS STRING BUFFER
It is immutable It is mutable
It is slow and consumes more memory It is fast and consumes less memory
5 MARKS QUESTIONS
Ans: Features of java are:

• Simple: Easy to learn. Because java inherits the c/c++ syntax and many of the
object oriented features of c++.
• Secure: Java provides a firewall between a networked application and user
computer.
• Portable: Translating a java program into bytecode makes it much easier to run
a program in a wide variety of environments.
• Object oriented: Java enhances and refines the object oriented paradigm used by
C++. The object model in java is simple and easy to extend.
• Robust: Java eliminates memory management problems by managing memory
allocation and deallocation.
• Multithreaded: Java supports multithreaded programming which allows you to
write programs that do many things simultaneously.
• Dynamic: Java programs have run time information that is used to verify and
resolve accesses to objects at run time.
• Distributed: Java is designed for the distributed environment of the internet,
because it handles TCP/IP protocols.
• Interpreted and Performance: Java bytecode can be interpreted on any system
that provides a high JVM. Java is well designed to perform well on very low
power CPUs.
• Architecture Neutral: Java programs can be executed on any processors like
Pentium, Celeron, dual core, AMD and so on,hence it is called architecture
neutral.
2. What are static variables and static methods?

Ans: Static variables:
• The instance variables are non-static and it is part of an object. But static
variables are special type of variables that are not associated with an object, they
are associated with class.
• The static variables are also called as class variables.
• The static variables can be accessed without an object.
• A static variable can be accessed directly by the class name and does not need
any object.
Syntax: <class_name>.<variable_name>
Example:
class staticdemo{
int x,y;
static int z;
System.out.println(staticdemo.z);
}
Static Methods:
• The methods can also be declared as static. A static method is associated with a
class rather than the instances.
• The static methods are also called as class members.
• The most common example of a static member is main(). The main() is declared
as static because it must be called by the operating systemwhen our program
begins.
• A static methods can be accessed directly by the class name and does not need
any object.
Syntax:
<class_name>.<method_name>(arguments)
Example:
staticdemo.method1();
Declaration:
class staticdemo{
int x,y;
static int z;
}
3. Explain any three string methods with example?
• concat(): This method creates a new string by appending the contents of string
object passed as arguments to the contents of string on which the method is
invoked.
Example:
publicString concat(String str)
String str=”Skyward”;
System.out.println(str.concat(“Publishers”)); //”Skyward Publishers” is printed.
• replace(): This method creates a new string using the same contents as that of the
string object on which the method is invoked.
Example:
public String replace(char old,char new)
String original=”Java ProgrAmming”;
System.out.println(original.replace(‘a’,’o’)); //”Javo Programming” is printed.
• substring(): The substring method creates a new string using partial contents of
the string on which it is invoked. This method has two overloaded version.
Example:
public String substring(int begin)
public String substring(int begin,int end)
String original=”watermelon”;
System.out.println(original.substring(5)); // prints “rings”
4. Differentiate between arrays and vectors?
Ans:
5. Explain visibility control in Java?

Ans:Visibility controls in Java are:
Private: The private modifiers specifies the most restrictive access level, it can apply it
to methods and member variables. The private methods and variables are accessible
only within the declaring class.
• A top level class cannot be declared as private, as it would mean that the class
cannot be instantiated and it would obviously unreasonable to declare a class that
can never be accessible.
Example:
class A{
private int data=40;
private void msg(){System.out.println(“Hello java”);}
}
public class Simple{
public static void main(String args[]){
A obj=new A();
System.out.println(obj.data);//Compile Time Error
Obj.msg();//Compile Time Error
}
Default: When a class,method or variable declaration does not have any access
modifier, it will have a default or package level. A class or its members with default
access are available to all the classes within the same package in which the class is
declared.
EXAMPLE:
package pack;
class A{
void msg(){System.out.println(“Hello”);}
}
//save by B.java
package mypack;
import pack.*;
class B{
A obj = new A();//Compile Time Error
Obj.msg();//Compile Time Error
}
}
Protected: The protected modifiers is applicable only to methods and member variables.
A top level class cannot be declared as protected.The member variables and methods of
a class,declared as protected are accessible to all classes in same package and all the
subclasses of the declaring class in other package.
EXAMPLE:
package pack;
public class A{
protected void msg(){System.out.println(“Hello”);}
}
package mypack;
import pack.*;
class B extends A{
B obj = new B();
Obj.msg();
}
}
Public: The public modifiers is the least restrictive of all access modifiers. It can apply it
to a class, its methods and its member variables. A public class can be instantiated
without any restrictions.
EXAMPLE:
package pack;
public class A{
public void msg(){System.out.println(“Hello”);}
}
//save by B.java
package mypack;
import pack.*;
class B{
A obj = new A();
Obj.msg();
}
}
6. What is Interface? Explain with an example how a class implements an interface.
Ans: An interface is a description of a set of abstract methods that is supported to be
implemented by the classes. In an interface no method can include a body. It specifies
what can be done, but no implementation. Once an interface is defined any number of
classes can be implemented. The interface can be defined using the interface keyword.
Syntax:
interface interface_name {
public static varibles
public abstract methods
}
Example:
interface XYZ
{
public void functionx();
public void functiony();
}
class ABC implements XYZ
{
public void functionx() { }
public void functiony() { }
}
7.Explain user defined exception in Java?
Ans: Java provides us facility to create our own exceptions which are basically derived
classes of exception. Things to remember before writing an exception
• All exceptions must be a child of Throwable
• To write a runtime exception, extend the RuntimeException class.
Steps to define our own exception.

• Extend the exception class
• Setup the constructor. The constructor takes the variable that is used to tell the
user that the number is incorrect.
• Create the function that returns the error to the user and override toString( )
method.
• When the error occurs, the code throws an exception.
Example:
class MyException extends Exception{
String str1;
MyException(String str2){
str1=str2;
}
public String toString(){
return(“MyException Occurred:”+str1);
}
}
class Example1{
public static void main(String args[]) {
try{
System.out.println(“Starting of try block”);
throw new MyException(“This is my error message”);
}
catch(MyException exp) {
System.out.println(“Catch block”);
System.out.println(exp);
}
}
}
8.Explain with an example the implementation of multithreading by extending Thread
class.
Ans: The implementation of multithreading by extending three Thread classes
ThreadA, ThreadB, ThreadC. Then create three thread objects on ThreadA, ThreadB,
ThreadC. Attach these three object to t1, t2, t3. The following example is printing the
numbers 1 to 20. ThreadA prints the value from 1 to 5, threadB prints the value from 6
to 10, thread prints the value from 11 to 15 and the main class prints the value from 16
to 20.
Example:
class ThreadA extends Thread {
public void run() {
for(int i=1;i<=5;i++)
System.out.println(Thread.currentThread().getName()+”=”+i);
System.out.println(“End of Thread One”);
}
}
class ThreadB extends Thread {
public void run() {
for(int i=6;i<=10;i++)
System.out.println(“End of Thread Two”);
}
}
class ThreadC extends Thread {
public void run() {
for(int i=11;i<=15;i++)
System.out.println(“End of Thread Three”);
}
}
class MultipleThreads {
public static void main(String args[]) {
ThreadA ta = new ThreadA();
ThreadB tb = new ThreadB();
ThreadC tc = new ThreadC();
Thread t1=new Thread(ta,”Thread One”);
Thread t2=new Thread(tb,”Thread Two”);
Thread t3=new Thread(tc,”Thread Three”);
t1.start();
t2.start();
t3.start();
for(int i=16;i<=20;i++)
System.out.println(“End of Main”);
}
}
9.Explain the cycle of thread with a neat diagram?
Ans: Start(): When the start() method is called, the thread enters in a ready- to- run
state. This thread is now in the pool of threads ready for the execution. Sometimes
later the thread is picked up by the scheduler for execution and moved to the
running state.
• The thread scheduler may move the thread out of the running state even if it has not
finished the execution.
Ready-to-run state(Runnable): A thread is in ready-to-run state when it is eligible to

run, but the scheduler has not yet picked it to actually run. A thread can also return to
ready-to-run state either after running or after the not-ready-to-run state.
• Call the start() method only once on a thread object. Re invoking a start method on
thread object that is already started is illegal.
Running: When the thread enters in this state, the JVM starts to execute the thread
run() method. The thread remains in this state and keep running until it is either
swapped out by thread scheduler or it voluntarily give up its turn for some reasons.
Not-ready-to-run (Blocked state): A thread moves out of the running state when it is
waiting for something to happen.
Sleeping: We may want a thread to do-nothing for some time. We can call
Thread.sleep() method in the thread run() method. This method tells the currently
running thread to sleep for some period of time.
Waiting: Sometimes a thread might wait(), just because we have asked it to wait in its
run method. In that case,the thread changes its state from running to waiting .
Blocked: Sometimes a thread needs to wait for a resource while running. For instance ,if
it is reading from a network resources in its run method, it has to wait until that
resource becomes available.
Dead state: A java thread enters this state when it has finished the execution of its run
method. We cannot start the thread once it is dead. The thread can be started only once
in its life time. If we re-invoke start() on a thread which is dead,it does not start again.
Using isAlive() method we can test whether the thread is alive or dead.
ready-to-run running dead
Start the thread
not-ready-to-run
[waiting/blocked/sleep
ing]
10.Explain how parameters are passed to an applet?
Ans: Applet can get different input from the HTML file that contains the
<APPLET>tag through the use of applet parameter. To set up and handle parameters
in the applet , we need two things:
1. A special parameter tag in the HTML file.
2. Code in our applet to read those parameters.
Example:
import java.awt.Font;
public class MyFontApplet extends Applet {
String fontName;
int fontSize;
public void init() {
fontName = getParameter(“font”);
fontSize = Integer.parseInt(getParameter(“size”));
}
Public void paint (Graphics g) {
Font f = new Font(fontName and fontSize);
g.setFont(f);
g.drawString(“Skyward Publishers”,50,50);
}
}
11.Explain any seven methods of graphics class with an example for each?
Ans:
METHODS DESCRIPTION
draw3Drect() Draws a 3-D rectangle
drawArc() Draws an arc
drawLine() Draws a line
drawOval() Draws an oval
fillArc() Draws a filled arc
fillOval() Draws a filled oval
fillRect Draws a filled rectangle
• Example for drawLine( )
public class DrawLineDemo extends java.applet.Applet {
public void paint(Graphics g) {
g.drawLine(25,25,75,75);
}
• Example for draw3Drect( )
g.draw3DRect(20,20,60,60,true);
g.draw3DRect(120,20,60,60,false);
}
• Example for drawArc( ) and fillArc( )
g.drawArc (50,50,80,60,45,120);
g.fillArc(150,50,80,60,45,120);
}
12.Explain the use of FileInputStream class and FileOutputStream class?

Ans: Use of FileInputStream:
• A file is opened for input by creating a FileInputStream object.
FileInputStream(String fileName) throws FileNotFoundException
Here, filename specifies the name of the file you want to open. If the file does
not exist, then FileNotFoundException is thrown.
Example:
FileInputStream fis;
try {
fis = new FileInputStream(“myFile.dat”);
}catch(IOException) {
}
Use ofFileOutputStream:
• To open a file for output, create a FileOutputStream object.
FileOutputStream(File file) throws FileNotFoundException
Here, creates a file output stream to write to the file represented by the
specified file object. If the file cannot be created, then FileNotFoundException is
thrown.
Example:
File f = new File(“myFile.dat”);
FileOutputStream fos;
try {
fos = new FileOutputStream(f);
}catch(IOException) {
}
13. Explain with example:
Method overloading: Method Overloading means to have two or more methods with
same name in the same class with different arguments.
Example:
class Myclass {
public void getAmount (int rate) {….}
public void getAmount (int rate, long principal) {….}
}
Method overriding: Method overriding occurs when sub class declares a method that
has the same type arguments as a method declared by one of its super class.
Example:
class Baseclass {
}
class Myclass extends Baseclass{
}
Abstract method: A method without body is known as abstract method. A method must
always be declared in an abstract class.
Example:
abstract void method1(); // Abstract method
Abstract class: Abstract classes are classes that contain one or more abstract methods.
Example:
abstract class Test { // Abstract class
int a,b,c;
void method3() {
}
}
14. Write a short notes on data output stream and data input stream?
Input stream
• Input stream is an abstract class that provides the framework from which all
the other input streams are derived
• We cannot create an instance of inputstream class as it is abstract class .
• Whenever we want to read the data in bytes format, then we use the input
stream classes
• The inputsream class contains lot of methods for reading bytes , closing stream
,skipping part of data in the streams. finding the number of bytes present in the
input data ,etc.
Output stream
• Output stream is an abstract class that provides the framework from which all
other output streams are derived
• We cannot create an instance of outputstream class as it is abstract class
• Whenever we want to write data in byte format, then we use the output stream
classes.
• The outputstream class contains lot of methods for writing bytes, closing streams
,etc.
15. Write a program to implement mouse events.

import java.awt.*;
import java.awt.event.*;
•
public class AppletMouseListener extends Applet implements MouseListener
{
String str="";
public void init()

{
public void mousePressed(MouseEvent e)
{
str = "You pressed mouse";
repaint();
}
public void mouseReleased(MouseEvent e)
{
str = "You released mouse";
repaint();
}
public void mouseClicked(MouseEvent e)
{
str = "You clicked mouse";
repaint();
}
public void mouseEntered(MouseEvent e)
{
str = "Mouse entered frame";
repaint();
}
public void mouseExited(MouseEvent e)
{
str = "Mouse existed frame";
repaint();
}
public void paint(Graphics g)
{
g.drawString(str, 75, 150);
}
}
16. Explain the life cycle of an applet with a neat diagram?

• An applet is born with init() method and starts executing with start() method.
To stop the applet, stop() method is called and to terminate the applet
destroy() method is called. Once the applet is terminated we should reload the
HTML page to get the applet start once again from init() method this way of
executing the methods are called as life cycle of an applet.
Applet life cycle diagram
• init( ): The first method called by an applet once it has been loaded by the
browser. It is called before the applet begins execution, and can be overridden to
perform any initialization tasks. When the method execution is completed,
browser looks for the next method start( ).
Syntax:
public void init( )
{
-----------
}
• start( ): start( ) is automatically called to begin the execution of the applet. This
method is called each time the applet is revisited by the user.
Syntax:
public void start( )
{
-------------
}
• stop( ): This method is called by the browser when an applet is to stopped.
Syntax:
public void stop( )
{
--------------------
}
• destroy( ): this method is called when an applet is being terminated from the
memory. The stop( ) method will always be called before destroy( ). The code
related to releasing memory allocated to the applet should be done in this
method.
Syntax:
public void destroy( )
{
--------------------
}
17. Difference between JDK and JRE?
JDK JRE
It is called java development tool It is called java runtime

kit environment
JDK is needed for developingJava JRE is a plug in neededfor running java

application programs
JDK can be downloaded,supported JRE can be downloaded,supported freely

Freely from java.sun.com fromJava.com
JDK needs more disk space as it JRE is smaller than JDK so it needs less disk
contains JRE along with various
Development tools space
It is bundle of software that you can It is an implementation of java virtual machine

be used to develop java Based whichactually executes java Program
application
18. Explain bitwise operator?

Ans Bitwise operator works on bits and performs bit by bit operations. The
operations on the bits are performed on 1s and 0s only. This means that any number
is decimal or hexadecimal format involved in a bit operation must be converted to
binary first
OPERATOR DISCRIPTION
&binary AND operator copies a bit to the result if it
Exists in both operands
| binary OR operator copies a bit if it exists in either
Operands
^ binary XOR operator copies the bit if it is set in one
Operand but not both
~ binary 1s complement operator is unary and has the
Effect of negating bits
<<binary left shift operator . this left operands value is
Moved left by the number of bits specified by the right
Operand
>>binary right shift operator . this left operands value is
Moved right by the number of bits specified by the
Right Operand .
19. What is the difference b/w overloading and overriding?
Overloading
1. Signature has to be different just a difference in return type is not enough.
2. Any access modifier can be used.
3. The methods exception list may vary freely
4. The method to be called will be decided at the time of compilation.
5. Methods can be static or non-static.
Over Ridding
1. Signature can be same.
2. Over ridding method cannot be more restrictive than the over ridden method.
3. Over ridding method may not throw more checked exceptions than the
overridden method.
4. The method to be called will be decided at the time of run time based on type of
the object.
5. Static method don’t participate in over ridding since they are resolved at compile
time based on the type of reference variable.
20. What is inheritance explain two types of inheritance?

• Inheritance can be defined as the process of acquiring properties of one object
from other object.
• Inheritance is one of the important principles of object oriented programming
because it allows creating a new class based on the class that has already been
defined using inheritance.
• We can create a general class that can defines common functionality this class
can be inherited by another classes each class can add new functionality that are
unique to it.
• Types of inheritance
a. Multilevel Inheritance: A class extending another class as in hierarchical
structure is termed as multilevel inheritance.
Eg: class A {
int x,y;
method1( )
}
class B extends A{
int i, j;
method2( )
}
class C extends B {
int a,b;
method3( )
}
b. Single Inheritance : A class extends from another class.

Eg: class A {
int x,y;
method1( )
}
class B extends A{
int i, j;
method2( )
}
c. Hierarchical Inheritance: Many class extending from single super class. One
super class and many sub classes.
Eg: class A {
int x,y;
method1( )
}
class B extends A{
int i, j;
method2( )
}
class C extends A {
int a,b;
method3( )
}
21. Explain the line “public static void main(string args[])”

• main() method: main() method is the starting point for JVM to start execution of
a java program.
• public: public keyword is an access specifier in this case, main() must be
declared as public, since it must be called outside of its class when the program is
started.
• static: static method can be called and executed without creating an object of
class, since we want to call main() method without creating any object, we should
declare main() as static.
• void: The keyword void simply tells the compiler that main() does not return a
value.
• String args[]: String is java’s predefined class and args[] is the name of an array.
22. Explain the history and evolution of java.
Ans. Java was originally designed for interactive television, but it was too advanced
technology for the digital cable television industry at the time. The history of java starts
with Green Team. Java team members (also known as Green Team), initiated this
project to develop a language for digital devices such as set-top boxes, televisions, etc.
However, it was suited for internet programming. Later, Java technology was
incorporated by Netscape.
23) How to create objects? What happens when you create objects?
An object is created by instantiating a class. The process of creating an object of a class
is called as instantiation and created object is called as an instance.
• To create a new object, java uses the new keyword
• The object are created using the new operator with the name of the class we
want to create an instance of, then parentheses after that. The general form of
creating an object is
<classname><reference-
variable>=new<classname>([arguments])
• When an object is created an instance of a class is created. Reference variable
does not define an object but it is simply a variable that can refer to an
object. The new operator dynamically allocates memory for an object and
returns a reference to it.
• Eg: Account acc = new Account();
Where Account is a class name, acc is reference variable and new is the
operator to create an object. The Account object is created in the heap
memory. The address of that object is assigned to the reference variable acc.
The reference variable is declared in the stack.
24) Demonstrate ‘this’ keyword with simple java program.

• This keyword is used to refer the current object
• It is used to call the constructors of same class
class Test
{
int a;
int b;
Test(int a, int b)
{
this.a = a;
this.b = b;
}
void display()
{
System.out.println("a = " + a + "b = " + b +);
}
public static void main(String[] args)

{
Test object = new Test(10, 20);
object.display();
}
}
25. Differentiate component and container class.
Component class:
• The component class is found under java. AWT package.

• The container class is the subclass of component class.
• All non-menu related elements that comprise a graphical user interface are
derived from the abstract class component.
• The component class defines a number of methods for handling events, changing
window bounds, controlling fonts and colours, and drawing components, and
their content.
Container class
• A container is a components that that can accommodate other components and

also other containers.
• Containers provides the support for building complex hierarchical graphical
user interface
• Container provides the overloaded methods add() to include components in the
container
26) Explain logical operators with example.
Logical operators return a true or false value based on the state of the variables.
The logical operators are
operator Description Example(A=true and B=false)

& (AND operator) If both the operands are non zero then ( A&B ) is false
the condition becomes true.
&& (Short circuit If both the operands are non zero then ( A&&B ) is false
AND operator) the condition becomes true.
| (OR operator) If any of the two operands are non zero ( A|B ) is true
then the condition becomes true
|| (Short circuit OR If any of the two operands are non zero ( A||B ) is true
operator) then the condition becomes true.
^ (XOR operator) This return true only if its operand. If ( A^B ) is true
its operand are different otherwise
false.
! (NOT operator) Use to reverses the logical state of its !( A&&B ) is true
operand. If a condition is true then
logical NOT operator make false.
27. Illustrate array declaration and accessing data elements using an example.
Array is collection of elements of same type. The array stores a fixed-size sequential
collection of elements of the same type.
Declaring an array
An array is declared by specifying the datatype of elements it is going to hold.
The array declaration is usually the data type followed by a pair of square brackets
followed by the name of the array
General form of declaring an array

Datatype[ ] arrayName;
Example :
int[ ] numbers;
accessing data elements using array
ex: create an integer array and display the elements of an array
public class simpleArray
{
Public static void main(String args[])
{
Int[ ] numbers = {10,20,30,40,50};
for (int a : numbers)
{
System.out.println(a);
}
}
}
28. Differentiate constructor and methods
Constructor
• The constructor is used to initialize the instance variables of a class
• A constructor name should be always same as class name.
• A constructor is called at the time of creating an object.
• A constructor is called only once per object.
• A constructor is called and executed automatically
Method
• A method is used for any general purpose tasks like calculations.
• The method name and class name can be same or different.
• A method can be called after creating the object.
• A method can be called any number of times on the object
• A method is executed only when we want it.
29) Explain try and catch with an example.
Ans. The core of exception handling is try and catch . these keywords works together.
we cannot have a try without a try.
General form of the try/catch exception handling blocks
try
{
// do risky things
}
catch(Exception ex)
{
//try to recover
}
Try
A try block is simply the keyword try. followed by braces enclosing the risky code that
can throw the exception.
try
{
}
Catch
A catch block consists of the keyword catch followed by a single parameter between
parentheses that identify the type of exception that the block is to deal with. this is
followed by the code to handle the exception enclosed between braces
try{
}
catch(Exception ex){
}
Example: To demonstrate arithmetic exception using try-catch block.

public class ArithmeticExceptionDemo
{
public static void main(String args[ ])
{
int i=100, j=0;
int k;
try
{
K=i/j;
}
catch (ArithmeticException e)
{
System.out.println(“exception occurred: divition by zero”);
K=i/(j+2);
}
System.out.println(“the value of k is :” + k);
}
}
30) Write a short note on Graphics class

• The graphics class provides the framework for all graphics operations
within the AWT. It plays two different, but related roles.
• Graphics context:the graphics context is information that will affect
drawing operations.
• The graphic context holds the following.
a. The component object on which to draw
b. Background and foreground colours
c. Font
d. A translation origin for rendering coordinates
e. The region of a component in which graphics can be drawn.
• Graphics class methods: The graphics class provides methods for drawing simple
geometric shapes, text and images to the graphics destination. In order to draw, a
program requires a valid graphics context. Because the graphics class is an abstract base
class, it cannot be instantiated directly. An instance is typically created by components,
and handed to the program as an argument to a components update() and paint()
methods.
• The graphics context encapsulated by the graphics class is obtained in two ways:
a. It is passed to an applet when pain or update method is called.
b. Abstract classes cannot be instantiated. Therefore, programmers must request a
graphics object from a component, which is accomplished by using a method of
the form.
Component.getGraphics();
c. This method is defined in component and returns a graphics object. Therefore,

any class that is a subclass of component can be drawn upon. The functionality
of the graphics class can be accessed even though it is abstract class.
31) Write program to sort a list of elements in ascending order.
class sorting
{
public static void main(String args[])
{
int a[ ] = new int[5];
System.out.println(“ enter five elements \n”);
for( int i=0;i<5;i++)
a[i]=Integer.parseInt(args[i]);
System.out.println(“\n before sorting \n”);
System.out.print(“ “ +a[i]);
bubbleSort(a,5);
System.out.println(“\n\n after sorting \n”);
System.out.println(“ Ascending order \n”);
System.out.print(“ “ +a[i]);
}
}
private static void bubbleSort(int[ ] arr, int length)

{
int temp,i,j;
for(i=0;i<length-1;i++)
{
If(arr[j] > arr[j+1]
{
temp = arr[j];
arr[j] = arr[j+1];
arr[j+1] = temp;
}
}
}
32) Give the steps to create and use a java package with an example.
Ans.
• To create a package, put a package command at the top of a java source file. the
classes declare within that file will then belong to the specified package. Since a
package defines a namespace, the names of the classes that we put into the file
become part of that package’s namespace.
• This is the general form of the package statement:
Package pkg;
• Here, pkg is the name of the package. for example, the following statement
creates a package called project1.
package pack1;
• Java uses the file system to manage packages, with each package stored in its
own directory. for example, the class files for any classes we declare to be part of
pack1 must be stored in directory called pack1.
• Step1: create a program which is part of package called pack1
package pack1;
public class packageExample

{
Public void packMethod()
{
System.out.println(“ I am packMethod() in pack1.packageExample”);
}
}
• Step2: the command is javac –d.packageExample.java. We can see that pack1

directory is automatically created by the compiler.
• Step3: create another file called packageDemo.java in pack2 package
Package pack2;
Import pack1.*;;
Public class packageDemo

{
Public static void main(String args[ ])
{
packageExample obj=new packageExample();
obj.packageMethod();
}
}
• In this file, we are trying to import the pack1 classes and creating an object of
packageExample
33) Explain steps of executing an applet using simple code.

Ans.
Step1: Writing applet code
Create the applet program called MyFirstApplet as shown
public class MyFirstApplet extends Applet

{
public void paint(graphics g)
{
g.drawString(“hello applet”, 20, 20);
}
}
Step2: Compile applet code and generate byte code.

Save the applet code and generate the byte code using java compiler javac
Step3: Create an HTML page.

<HTML>
<HEAD>
<TITLE> this is my first applet </TITLE>
<BODY>
<applet code=MyFirstApplet.class width= 400 height=500>
</Applet>
</BODY>
<HEAD>
</HTML>
Step4: Executing an applet using appletviewer

• There are two ways in which we can run an applet: inside a browser or with a
special development tool that displays applets. The tool provided with the
standard java JDK is called appletviewer.
• The appletviewer is much easier to use during development.
• Executing an applet using appletviewer
• Appletviewer appletExample.html
SOLUTION BANK
BCA 505T MICROPROCESSOR & ASSEMBLY LANGUAGE

BCA505T : MICROPROCESSOR AND ASSEMBLY LAGUAGE

Unit - I
Architecture and Operation: Introduction to 8085, Microprocessor organization/ architecture
& its operation Microprocessor based system, memory interfacing , basic interfacing
concepts ,interfacing I/O devices
[ 12 Hours ]
Unit - II
Programming the 8085: Programming model, instruction classification , Instruction format,
addressing modes, writing assembly level programs-overview of instruction set, timing
diagrams data transfer, Arithmetic, Logic branch operations.
[ 12 Hours ]
Unit - III
Programming techniques- Looping Counting and Indexing , 16 bit arithmetic operations ,
logic operations Compare and rotate operations . Counters and Time delays , Generation of
pulse waveforms. Stacks and subroutines- conditional CALL and RETURN instructions.
Advanced subroutine concepts. BCD to Binary and Binary to BCD conversions, BCD to 7
segment conversion , Binary to ASCII and ASCII to Binary code conversion, BCD addition
and subtraction , multiplication and division.
[ 12 Hours ]
Unit – IV
Memory Interface: Memory and I/O mapping and interfacing concepts. Interrupts : 8085
vectored interrupts , Restart as Software instructions, additional I/O concepts and processes.
[ 12 Hours ]
Unit – V
Interfacing of peripherals (I/Os) and applications: Interfacing Keyboard (linear and matrix)
and 7 segment display including multiplexes, 8279 programmable keyboard
/display interface, 8255 PPI , 8259 PIC , DMA and 8257 DMA controller , Serial
communication using 8251, D to A converters and interfacing, RS323
serial communication standard.
Suggested Question Pattern
V BCA
(Y2K14 – CBCS)
Bangalore University
BCA 505T –MP
Unit Chapter Part A Part B Total
Marks
2Marks 5 Marks Question
Question
(Part of 10 Marks
Question of Part B)
Unit - I Architecture and Operation 3 2 26
Unit - II Programming the 8085 3 1 16
Unit - III 2 3 34
Programming techniques
Unit - IV Memory Interface 2 2 24
Unit - V Interfacing of peripherals 2 1 14

(I/Os) and applications
Total 12 11 104
UNIT-I
[ Nov / Dec 2016 ]
01. Draw the flag register mentioning the flag status?
[ Nov / Dec 2017]
01. What is Microprocessor? Give the word length of 8085 Microprocessor.
02.Explain Program Counter and Stack Pointer.
03. Explain SID and SOD pins of 8085.
[ Nov / Dec 2018]
01. What is a microprocessor?
02. Explain briefly about the different types of buses in 8085.
03. Name the flags of 8085.
04. Define the terms machine cycle and instruction cycle.
05. What is memory interfacing?
[ TMAQ - important tutor mark assignment questions ]
01.Define T- state, Machine Cycle and Instruction Cycle.
02. What is address bus and data bus.
03. What is the use of ALE.
UNIT-II
[ Nov / Dec 2016]
01. What is the function of instruction register and decoder?
02. What is Immediate addressing? Mention an example.
03. Write any two instructions to clear the contents of accumulator register.
04. Find the contents of accumulator after executing the following block of program segment.
Content of B register is 3EH. Initially.
MOV A,B
RLC
RLC
HLT
05. Explain DAA instruction
06. Two consecutive memory locations store 3EH and 2FH data respectively. Find the content of
accumulator after executing following segment of program.
LXI H 2050H
MOV A,M
INX H
SUB M
INX H
MOV M, A
[ Nov / Dec 2017]
01. Write any two examples for 3 byte Instructions.
02. Explain Instruction DAD D.
03. Find the number of bytes required to store the following instructions:
I. CPI FFH.
II. LXI D, 8500.
[ Nov / Dec 2018]
01. Mention any two instructions which clear the contents of accumulator.
02.. Explain any two data transfer instructions of 8085.
03. Compare SUB reg and CMP reg instructions.
04. Write an assembly language program to find the 2’s complement of an 8-bit number.
UNIT-II
[ Nov / Dec 2016]
01. Draw the flowchart to generate delay loop using register.
[ Nov / Dec 2017]
01.What is Subroutine?
02. Define counting and looping.
03.Compare POP and PUSH Instruction.
[ Nov / Dec 2018]
01. Define counters and time delays.
02. Write an ALP to add two-N byte numbers.
UNIT-IV
[ Nov / Dec 2016]
01. Differentiate between absolute and partial decoding.
[ Nov / Dec 2017]
02. Define maskable and Non-maskable interrupts of 8085.
[ Nov / Dec 2018]
03. Define interrupt.
UNIT-V
[ Nov / Dec 2016]

01. What is I/O Interfacing?
02. Draw the bit pattern of control word for 8255.
03. Explain the priority modes of 8259.
[ Nov / Dec 2017]
01. What are handshake signals?
SECTION – B ( 5 Marks)
UNIT-I
[ Nov / Dec 2016]
01. a) Draw the pin configuration of 8085 microprocessor.

b) With diagram explain how control signals are generated?
02. Explain Memory read machine cycle with timing diagram.
[ Nov / Dec 2017]
01. Draw the architecture of 8085 microprocessor and briefly explain.
02. What are flags? Draw the format of flag register and explain their function.
UNIT-II
[Nov / Dec 2016]
01.a) Write an ALP to add two-N byte numbers.
b) Classify the instructions based on sizes and explain each with example.
02. a) Explain i) STAX D ii) ADC R iii)XCHG instructions.
03. Write an ALP for block transfer of data bytes.
[ Nov / Dec 2017]
01. Write a program to load 07F in the register B and find its 2’s compliment.
02. Explain the following instructions of 8085:
STAXD
CMPM
XCHG
3. Write short notes on :
a) Addressing modes of 8085.
b) Data transfer instructions in 8085.
[ Nov / Dec 2018]

01. a) What is addressing mode? explain briefly the various addressing modes of
8085Microprocessor
b) Explain the classification of 8085 microprocessor instruction based on word size. Give
example.
02. a) write assembly language program to subtract two 16- bit numbers.
b) Explain the instructions DAA and DAD Rp.
03. With an example, explain the logical instructions of 8085 microprocessors.
01 Explain Call, Reset, Conditional(any instructions)
02 Data transfer instructions
03 Logical Instructions
04 Stack operations
05 Machine control instructions
UNIT III
[ Nov / Dec 2016]

01. Explain unconditional Jump Instructions.
02. Explain nesting of subroutine with an example.
[ Nov / Dec 2017]

01. What is stack? Explain PUSH and POP operation.
02. Explain CALL and RETURN operations in 8085.

01 What is time delay and counter?
02 Explain programmed I/O data transfer
03 Explain Push and Pop operations
04 Explain Subroutine and call.
UNIT-IV
[ Nov / Dec 2016]

01. Compare memory mapped I/O and I/O mapped I/O.
02. a) What is an Interrupt? Explain the classification of interrupts.
b) Explain RIM instruction with bit pattern.
[ Nov / Dec 2018]
01. Briefly explain the 8085 vectored interrupts.
1. 01 Algorithm and steps for Binary to ASCII

02 Algorithm and steps for ASCII to Binary
03 Algorithm and steps for ASCII to BCD conversion
04 Types of Interrupts
05 Explain Daisy Chain Method
06 What is hardware and software interrupt?
07 What is maskable and nonmaskable interrupts?
UNIT-V
[ Nov / Dec 2016]
01. Explain the functional block diagram of 8255 PPI.
02. write a note on interfacing devices.
[ Nov / Dec 2017]

01. Explain SIM and RIM Instructions.
[ Nov / Dec 2018]

01. Write short notes on:
DMA (Direct memory Access)
01. 8257 DMA Controller
02 .8255 Control word format
03 .8255 Block diagram and Pin diagram
04 .8259 Block diagram and Pin configuration
UNIT-I
[ Nov / Dec 2016 ]
01. Draw the flag register mentioning the flag status?
[ Nov / Dec 2017]
01. What is Microprocessor? Give the word length of 8085 Microprocessor.
A microprocessor is a multipurpose programmable clock driven register based
semiconductor device manufactured by using VLSI techniques to perform all
computations in digital computer.
02.Explain Program Counter and Stack Pointer.

 Program Counter: This register is used to sequence the execution of the instructions. The
function of the program counter is to point to the memory address from which the next byte
is to be fetched. When a byte (machine code) is being fetched, the program counter is
incremented by one to point to the next memory location.
 Stack Pointer: It is used as a memory pointer. It points to a memory location in read/write
memory, called the stack. It is always incremented/decremented by 2 during push and pop
operation.
03. Explain SID and SOD pins of 8085.

 SID (Serial Input port): It is a data line for serial input. The 7 th bit of the
accumulator is loaded with the data on SID line, when RIM (Read Interrupt
Mask) instruction is executed.
 SOD (Serial Output port): It is a data line for serial output. The 7th bit of
the accumulator is outputted on SOD line, when SIM(Set Interrupt Mask)
instruction is executed.
[ Nov / Dec 2018]

1. What is a microprocessor?
A microprocessor is a multipurpose programmable clock driven register based
semiconductor device manufactured by using VLSI techniques to perform all
computations in digital computer.
2. Explain briefly about the different types of buses in 8085.

Address bus: It is a group of 16 lines identified as A0to A15 used to identify the
peripheral devices or memory locations in a digital computer system & is
unidirectional i.e., data bits flow in one direction.
Data bus: The data bus is a group of 8 lines identified as D0 to D7 and is a
bidirectional bus used to carry 8-bits data between μP and other external units in
both directions.
Control bus: It contains various single lines which have specific functions for
coordinating and controlling μP operations.
3. Name the flags of 8085.
 Sign Flags[S]
 Zero Flags[Z]
 Auxiliary Carry Flags[AC]
 Parity Flags[P]
 Carry Flags[CY]
04. Define the terms machine cycle and instruction cycle.

 Machine cycle: It is the time required to access the memory devices or I/O
devices. In machine cycle various operations like opcode fetch, memory
read, memory write, I/O read, I/O write are performed.
 Instruction cycle: The time taken to complete the execution of one
instruction. The 8085 microprocessor consists of one to six machine cycle
or operations.
05. What is memory interfacing?

 While executing a program, the microprocessor needs to access memory
frequently to read instruction codes and data stored in memory and the
interfacing circuit enables that access.
UNIT-II
[ Nov / Dec 2016]

01. What is the function of instruction register and decoder?
 When an instruction is fetched from memory then it is stored in the Instruction register.
 Instruction decoder decodes the information present in the Instruction register. 8085
microprocessor is one of the most interesting topic.
02. What is Immediate addressing? Mention an example.

In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand.
For example: MVI K, 20F: means 20F is copied into register K.
03. Write any two instructions to clear the contents of accumulator register.
1.MVI A 00H
2.XRA A
3.SUB A
4.ANI 00H....
04. Find the contents of accumulator after executing the following block of
program segment. Content of B register is 3EH. Initially.
MOV A,B
RLC
RLC
HLT
3 E
0011 1110 1st RLC (to shift left by 1 bit)
0011 1110 2nd RLC (again shift by 1 bit)
F 8
1111 1000 Accumulator=F8
05. Explain DAA instruction

The DAA (Decimal Adjust after Addition) instruction allows addition of numbers represented in
8-bit packed BCD code.
It is used immediately after normal addition instruction operating on BCD codes.
06. Two consecutive memory locations store 3EH and 2FH data respectively.
Find the content of accumulator after executing following segment of
program.
LXI H 2050H
MOV A,M
INXH
SUBM
INXH
MOV M, A
(1111) Borrow
3E-> 00111110
2F-> 00101111
00001111
[ Nov / Dec 2017]

01. Write any two examples for 3 byte Instructions.
LDA 8509 Hex code = 3A, 09, 85 (Three bytes)
STA 2600 Hex code = 32, 00, 26 (Three bytes)
02. Explain Instruction DAD D.
DAD is a mnemonic, which stands for Double ADD and also rp stands for any one of the
following register pairs as mentioned below.
rp = BC, DE, or HL
As rp can have any of the three values, there are three opcodes for this type of instruction. It
occupies only 1-Byte in memory.
03. Find the number of bytes required to store the following instructions:
I. CPI FFH.
II. LXI D, 8500.
I. 16bits (2 bytes).
II. 8bits (3 byte).
[ Nov / Dec 2018]

01. Mention any two instructions which clear the contents of accumulator.
 MVI A 00H
 XRA A
 SUB A
 ANI 00H....
02.. Explain any two data transfer instructions of 8085.
MOV Rd, RS [Move the content of one register to another]: This instruction
copies the contents of the source register [, RS] into the destination register [Rd].
LDA 16-bit address: It transfers the content stored in the addressed memory
location to accumulator.
STA 16-bit address: It transfers the content stored in the accumulator to
addressed memory location. i.e.,[M address] [A].
03. Compare SUB reg and CMP reg instructions.

SUB(subtracts register from accumulator):The contents of the register are subtracted from the
contents of the accumulator and the result is placed in the ‘A’.
CMP(compare register with accumulator): The contents of register R is subtracted from the
contents of accumulator but the result is not stored.
04. Write an assembly language program to find the 2’s complement of an 8-
bit number. Algorithm –
MEMORY MNEMONICS OPERANDS COMMENT
2000 LDA [3000] [A] <- [3000]
2003 CMA [A] <- [A^]
2004 STA [3001] 1’s complement
2007 ADI 01 [A] <- [A] + 01
2009 STA [3002] 2’s complement
200C HLT Stop
UNIT-III
[ Nov / Dec 2016]

01. Draw the flowchart to generate delay loop using register.
[ Nov / Dec 2017]
01.What is Subroutine?
A subroutine is a sequence of program instructions that perform a specific task, packaged as a unit. This
unit can then be used in programs wherever that particular task have to be performed. A subroutine is
often coded so that it can be started (called) several times and from several places during one execution of
the program, including from other subroutines, and then branch back (return) to the next instruction after
the call, once the subroutine’s task is done. It is implemented by using Call and Return instructions.
02. Define counting and looping.

Counting: This technique allows programmer to count how many times the instruction/set of
instructions are executed.
Looping: In this technique, the program is instructed to execute certain set of instructions
repeatedly to execute a particular task number of times.
03.Compare POP and PUSH Instruction.

POP instruction: It is a one byte instruction, which can be used to retrieve the contents of
registers from the stack. It is generally represented by POP Rp.
PUSH instruction: It is a one byte instruction, which can be used to copy the contents of
register pairs [Rp] to the me0mory location
MEMORY pointed by Stack pointer(SP). It is generally
MNEMONICS COMMENTS
ADDRESS represented by the instruction.
2000 LDA 2050 A ← 2050

[ Nov / Dec 2018]
2003 MOV B, A B←A 01. Define counters and time delays.
A counter is designed simply by loading
2004 LDA 2052 A ← 2052 appropriate number into one of the registers and
using INR or DCR instructions.
2007 ADD B A ← A+B Time delay is a procedure used to design a
specific delay. It is designed by loading a
2008 STA 3050 A → 3050 register with a delay count and set up a loop to
decrement the count until zero.
200B LDA 2051 A ← 2051
200E MOV B, A B←A 02. Write an ALP to add two-N byte

numbers.
200F LDA 2053 A ← 2053
2012 ADC B A ← A+B+CY
2013 STA 3051 A → 3051
2016 HLT Stops execution
UNIT-IV
[ Nov / Dec 2016]
01. Differentiate between absolute and partial decoding.

Absolute Decoding Partial Decoding
The decoding in which all available address line The decoding in which all available address line(16
(16 lines in memory mapped and 8 lines in lines in memory mapping and 8 lines in. peripheral
peripheral mapping) are used for decoding to mapping) are not used for decoding resulting in
generate a unique address. multiple address for same port.
[ Nov / Dec 2017]
01. Define maskable and Non-maskable interrupts of 8085.
 Maskable interrupt:Maskable Interrupts are those which can be disabled or ignored by
the microprocessor. These interrupts are either edge-triggered or level-triggered, so they
can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085
microprocessor.
 Non-Maskable interrupt:Non-Maskable Interrupts are those which cannot be disabled
or ignored by microprocessor. TRAP is a non-maskable interrupt. It consists of both level
as well as edge triggering and is used in critical power failure conditions.
[ Nov / Dec 2018]
01. Define interrupt.

Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
UNIT-V
[ Nov / Dec 2016]

01. What is I/O Interfacing?
There are various communication devices like the keyboard, mouse, printer, etc. To interface the
keyboard and other devices with the microprocessor by using latches and buffers. This type of
interfacing is known as I/O interfacing.
02. Draw the bit pattern of control word for 8255.
03. Explain the priority modes of 8259.
1. Fully Nested Mode(FNM):
The fully nested mode is the general purpose mode is the purpose mode in which all
interrupt requests are arranged from the highest to lowest priority level.’
2.Automatic Rotation mode:
A device after being serviced receives the lowest priority.
3.Specific Rotation Mode:
This mode is similar to the automatic rotation mode, except that the user can select an IR
for the lowest priority, thus fixing all other priorities.
[ Nov / Dec 2017]

01. What are handshake signals?
Handshaking is a I/O control method to synchronize I/O devices with the microprocessor. As
many I/O devices accepts or release information at a much slower rate than the microprocessor,
this method is used to control the microprocessor to work with a I/O device at the I/O devices
data transfer rate.
SECTION – B ( 5 Marks)
UNIT-I
[ Nov / Dec 2016]
01. a) Draw the pin configuration of 8085 microprocessor.
1. Address Bus and Data Bus:

The address bus is a group of sixteen lines i.e., A0-A15. The address bus is
unidirectional, i.e., bits flow in one direction from the microprocessor unit to the
peripheral devices and uses the high order address bus.
2. Control and Status Signals:
 ALE– It is an Address Latch Enable signal. It goes high during first T state of a
machine cycle and enables the lower 8-bits of the address, if its value is 1
otherwise data bus is activated.
 IO/M’ – It is a status signal which determines whether the address is for input-
output or memory. When it is high(1) the address on the address bus is for input-
output devices. When it is low(0) the address on the address bus is for the
memory.
 SO, S1– These are status signals. They distinguish the various types of operations
such as halt, reading, instruction fetching or writing.
 RD’– It is a signal to control READ operation. When it is low the selected
memory or input-output device is read.
 WR’ – It is a signal to control WRITE operation. When it goes low the data on the
data bus is written into the selected memory or I/O location.
 READY – It senses whether a peripheral is ready to transfer data or not. If
READY is high(1) the peripheral is ready. If it is low(0) the microprocessor waits
till it goes high. It is useful for interfacing low speed devices.
3. Power Supply and Clock Frequency:
 Vcc– +5v power supply
 Vnn– Ground ReferenceXI, X2 – A crystal is connected at these two pins. The
frequency is internally divided by two, therefore, to operate a system at 3MHZ the
crystal should have frequency of 6MHZ.
 CLK (OUT) – This signal can be used as the system clock for other devices.
 Interrupts and Peripheral Initiated Signals:
 The 8085 has five interrupt signals that can be used to interrupt a program
execution.
b) With diagram explain how control signals are generated?
Control signals:
The control signals are provided to support the 8085 memory instructions. They control
functions such as when the bus is to carry a valid address in which direction data are to be
transferred over the bus, when to put read data on the system bus.
Three control signals are RD, WR & ALE.
 RD – This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
 WR – This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
 ALE – It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.
02. Explain Memory read machine cycle with timing diagram.

Operation:
 It is used to fetch one byte from the memory.
 It requires 3 T-States.
 It can be used to fetch operand or data from the memory.
 During T1, A8-A15 contains higher byte of address. At the same time ALE is high.
Therefore Lower byte of address A0-A7 is selected from AD0-AD7.
 Since it is memory ready operation, IO/M(bar) goes low.
 During T2 ALE goes low, RD(bar) goes low. Address is removed from AD0-AD7
and data D0-D7 appears on AD0-AD7.
 During T3, Data remains on AD0-AD7 till RD(bar) is at low signal.
[ Nov / Dec 2017]

01. Draw the architecture of 8085 microprocessor and briefly explain
The following are the functional blocks in the 8085 Microprocessor.
1. Accumulator
2. Temporary register
3. Arithmetic and Logic Unit (ALU)
4. Flag register
5. Instruction Register
6. Instruction Decoder and Machine cycle encoder
7. General purpose registers
8. Stack Pointer
9. Program Counter
10. Increment / Decrement
11. Timing and Control unit
12. Interrupt control
13. Serial I/O control
14. Address buffer and Address / Data buffer
1. Accumulator (A-register)
It is an 8-bit register. It is associated with ALU. The accumulator is also called A-register.
During the arithmetic / logic operations, one of the operand is available in Accumulator. The
result of the arithmetic / logic operations is also stored in the Accumulator.
2. Temporary (TEMP) register

It is an 8-bit register. It is also associated with ALU. This register is used to hold one of the data
(from memory or general purpose registers) during an arithmetic / logic operation.
3. Arithmetic and Logic Unit (ALU)

The Arithmetic and Logic Unit includes Accumulator, Temporary register, arithmetic and logic
circuits and flag register. The ALU can perform arithmetic (such as addition and subtraction) and
logic operations (such as AND, OR and EX-OR) on 8-bit data. It receives the data from
accumulator and or TEMP register. The result is stored in the accumulator. The conditions of the
result (such as carry, zero) are indicated in the flags.
4. Flag register
It is an 8-bit register. But only five bits are used. The flag positions in the flag register are shown
below.
Flag register of 8085: The flags are affected by the arithmetic and logic operations in the ALU.
The flag register is also known as Status register or Condition code register. There are five flags
namely Sign (S) flag, Zero (Z) flag, Auxiliary Carry (AC) flag, Parity (P) flag and Carry (CY)
flag.
• Sign (S) flag: Sign flag is set (1) if the bit D7 of the result in the accumulator is 1, otherwise it
is reset (0). This flag is set when the result is negative. This flag is used only for signed numbers.
• Zero (Z) flag: Zero flag is set (1) if the result in the accumulator is zero, otherwise it is reset
(0).
• Auxiliary Carry (AC): Auxiliary Carry flag is set (1) if there is a carry from bit position D3of
result in the accumulator, otherwise it is reset (0). This flag is used for BCD operations.
• Parity (P) flag: Parity flag is set (1) if the result in the accumulator has even number of 1s,
otherwise it is reset (0).
• Carry (CY) flag: Carry flag is set (1) if the result of an arithmetic operation results in a carry
from bit position D7, otherwise it is reset (0). This flag is also used to indicate a borrow
condition during subtraction operations.
5. Instruction register
When an instruction is fetched from memory, it is stored in the Instruction register. It is an 8-bit
register. This resister cannot be used in the programs.
6. Instruction Decoder and Machine cycle encoding

This unit decodes the instruction stored in the Instruction register. It determines the nature of the
instruction and establishes the sequence of events to be followed by the Timing and control unit.
7. General purpose registers

There are six 8-bit general purpose registers namely B, C, D, E, H and L registers. B and C
registers are combined together as BC register pair for 16-bit operations. Similarly, D and E
registers can be used as DE resister pair and H and L as HL register pair. The HL register pair is
also used as memory pointer (M-register) for storing 16-bit address in some instructions. There
are two more 8-bit temporary registers W and Z. These registers are used to hold data during the
execution of some instructions. W and Z registers cannot be used in programs.
8. Stack Pointer (SP)

Stack is a portion of memory (RAM) used as FILO (First In Last Out) buffer. This is mainly
used during subroutine operations. Stack Pointer is a 16-bit register used as a memory pointer
(16-bit address) for denoting the stack position in memory. The Stack pointer is decremented
each time when data is loaded into the stack and incremented when data is retrieved from the
stack. Stack pointer always points to the top of the stack memory.
9. Program Counter (PC)

The Program Counter (PC) is a 16-bit register. It is used to point the address of the next
instruction to be fetched from the memory. When one instruction is fetched from memory, PC is
automatically incremented to point out the next instruction.
10. Increment / Decrement

This unit is used to increment or decrement the contents of the 16-bit registers.
11. Timing and Control unit

The internal clock generator is available in this unit. This unit has the micro programs for all the
instructions to carry out the micro steps required in completing the instructions. This unit
receives signals from the Instruction decoder and Machine cycle encoding unit and generates
control signals according to the micro-program for the instruction.
12. Interrupt control

There are five hardware interrupts available in 8085 Microprocessor namely TRAP, RST 7.5,
RST 6.5, RST 5.5 and INTR for interfacing the peripherals with the microprocessor. These
interrupts are handled by the Interrupt control unit. INT A signal is generated by the Interrupt
control unit as an acknowledgement for an interrupting device. If two or more interrupts occur at
the same time, service is given according to the priority basis.
13. Serial I/O control

Serial data is transmitted to the peripherals through SOD pin and received through the SID pin.
The SOD and SID pins are handled by the Serial I/O control unit using the SIM and RIM
instructions.
14. Address buffer and Address / Data buffer

The Address buffer is an 8-bit unidirectional buffer from which the higher order address bits A8
– A15 leaves the microprocessor to the memory and peripherals. The Address / Data buffer is an
8-bit bidirectional buffer used for sending the lower order address bits A0 – A7 and sending and
receiving the data bits D0 – D7 to the memory and peripherals.
02. What are flags? Draw the format of flag register and explain their
function.
The Flag register is a Special Purpose Register. Depending upon the value of result after any
arithmetic and logical operation the flag bits become set (1) or reset (0). In 8085
microprocessor, flag register consists of 8 bits and only 5 of them are useful.
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
These are the set of 5 flip-flops −
 Sign Flag: It occupies the seventh bit of the flag register, which is also known as the most
significant bit. It helps the programmer to know whether the number stored in the
accumulator is positive or negative. If the sign flag is set, it means that number stored in
the accumulator is negative, and if reset, then the number is positive.
 Zero Flag:It occupies the sixth bit of the flag register. It is set, when the operation
performed in the ALU results in zero (all 8 bits are zero), otherwise it is reset. It helps in
determining if two numbers are equal or not.
 Auxiliary Carry Flag: It occupies the fourth bit of the flag register. In an arithmetic
operation, when a carry flag is generated by the third bit and passed on to the fourth bit,
then Auxiliary Carry flag is set. If not flag is reset. This flag is used internally for BCD
(Binary-Coded Decimal Number) operations.
 Parity Flag: It occupies the second bit of the flag register. This flag tests for number of
1’s in the accumulator. If the accumulator holds even number of 1’s, then this flag is set
and it is said to even parity. On the other hand, if the number of 1’s is odd, then it is reset
and it is said to be odd parity.
 Carry Flag: It occupies the zeroth bit of the flag register. If the arithmetic operation
results in a carry (if result is more than 8 bit), then Carry Flag is set; otherwise it is reset.
UNIT-II
[ Nov / Dec 2016]
01. Write an ALP to add two-N byte numbers.
MEMORY
MNEMONICS COMMENTS
ADDRESS
2000 LDA 2050 A ← 2050
2003 MOV B, A B←A

b) Classify the instructions based on
sizes and explain each with example.
2004 LDA 2052 A ← 2052
8085 instruction set is classified into 3
2007 ADD B A ← A+B categories by considering the length of the
instructions. In 8085, the length is measured
2008 STA 3050 A → 3050 in terms of “byte” rather then “word” because
8085 microprocessor has 8-bit data bus. Three
200B LDA 2051 A ← 2051 types of instruction are: 1-byte instruction, 2-
byte instruction, and 3-byte instruction.
200E MOV B, A B←A 1. One-byte instructions –
In 1-byte instruction, the opcode and the
200F LDA 2053 A ← 2053
operand of an instruction are represented in
2012 ADC B A ← A+B+CY one byte.
Example-1:
2013 STA 3051 A → 3051 Copy the contents of accumulator in register
B.
2016 HLT Stops execution
Mnemonic- MOV B, A
Opcode- MOV
Operand- B, A
Hex Code- 47H
Binary code- 0100 0111
02. Two-byte instructions –

Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next 8 bits indicates the operand.
Example-1:
Task- Load the hexadecimal data 32H in the accumulator.
Mnemonic- MVI A, 32H
Opcode- MVI
Operand- A, 32H
Hex Code- 3E
32
0011 0010
03.Three-byte instructions –
Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next two bytes specify the 16-bit address. The low-order address is represented in second
byte and the high-order address is represented in the third byte.
Example-1:
Task- Load contents of memory 2050H in the accumulator.
Mnemonic- LDA 2050H
Opcode- LDA
Operand- 2050H
Hex Code- 3A
50
20
0101 0000
0010 0000
02. a) Explain i) STAX D ii) ADC R iii)XCHG instructions.

i) STAX(Store accumulator indirect): - The contents of the accumulator are copied into the
memory location specified by the contents of the operand (register pair). The contents of the
accumulator are not altered.
Eg: - STAX B (the content of accumulator is stored into the memory location specified by the
DE register pair.)
ii) ADC R:-Adds the destination operand (first operand), the source operand (second operand),
and the carry (CF) flag and stores the result in the destination operand. The destination operand
can be a register or a memory location; the source operand can be an immediate, a register, or a
memory location.
iii) XCHG: - Exchange H and L with D and E. The contents of register H are exchanged with the
contents of register D, and the contents of register L are exchanged with the contents of register
E.
Eg: - XCHG
03. Write an ALP for block transfer of data bytes.
[ Nov / Dec 2017]

01. Write a program to load 07F in the register B and find its 2’s compliment.
MVI B 07H  Move 07 in register B
CMA Complement 07
INR A 2’s Complement of 07
STA Store the 2’s complement
01. Explain the following instructions of 8085:
STAXD
CMPM
XCHG
STAX (Store accumulator indirect):- The contents of the accumulator are copied into the
memory location specified by the contents of the operand (register pair). The contents of the
accumulator are not altered.
Eg:- STAX B (the content of accumulator is stored into the memory location specified by the
BC register pair.)
Compare (register or memory) with accumulator (CMP R/M):
This is a 1-byte instruction. It compares the data byte in the register or memory with the contents
of accumulator.
1. If A less than (R/M), the CY flag is set and Zero flag is reset.
2. If A equals to (R/M), the Zero flag is set and CY flag is reset.
3. If A greater than (R/M), the CY and Zero flag are reset.
When memory is an operand, its address is specified by HL Pair. No contents are modified;
however all remaining flags (S, P, AC) are affected according to the result of subtraction.
XCHG:-Exchange H and L with D and E. The contents of register H are exchanged with the
contents of register D, and the contents of register L are exchanged with the contents of
register E.
1. Write short notes on :

c) Addressing modes of 8085.
Addressing modes are the instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the memory without any
alteration in the content. In 8085 microprocessor there are 5 types of addressing modes:
1. Immediate Addressing Mode –
In immediate addressing mode the source operand is always data. If the data is 8-bit, then
the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3
bytes.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)
2. Register Addressing Mode –
In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore the operation is performed within various registers of
the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
3. Direct Addressing Mode –
In direct addressing mode, the data to be operated is available inside a memory location
and that memory location is directly specified as an operand. The operand is directly
available in the instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 01)
4. Register Indirect Addressing Mode –
IN register indirect addressing mode, the data to be operated is available inside a memory
location and that memory location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contains of B-C register to the accumulator)
LXIH 9570 (load immediate the H-L pair with the address of the location 9570)
5. Implied/Implicit Addressing Mode –
In implied/implicit addressing mode the operand is hidden and the data to be operated is
available in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contains of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
d) Data transfer instructions in 8085.

 MOV Rd, Rs [Move the content of one register to another]: This instruction copies
the contents of the source register (Rs) into the destination register (Rd). The contents of
the source register are not altered. The Rd, Rscan be any general purpose registers or
Accumulator (B, C, D, E H, L or A).
Ex: Assume register C contains 42H. To transfer the contents of register C to register B,
the required instruction is MOV B, C.
 It has one-byte size.
 Register addressing mode.
 4 T-state.
 1 machine cycle.
 No flags are affected.
 MVI R, 8-bit data [Move immediate 8-bit data to register]: This instruction transfer
the given 8-bit data to the register[R]. Where, R is any general purpose register or
Accumulator (A, B, C, D, E, H or L).
Ex: The instruction required to copy the 8-bit data (88H) into Accumulator is MVI A,
88H.
 It has 2-byte size.
 Immediate addressing mode.
 7 T-state.
 No flags affected.
 LXI Rp, 16-bit data [Load register pair immediate]: Specified 16-bit data is loaded
into the register pair[Rp]. Where, Rpis BC, DE or HL register pair or SP (Stack Pointer).
Ex: The instruction required to load 16-bit data 2050H into the DE register pair is LXID
D, 2050H
 It is 3-byte size.
 Immediate addressing mode.
 10 T-state.
 LDA 16-bit address: It transfers the content stored in the addressed memory location to
accumulator.
Ex: Assume 2050 memory location contains the 8-bit data is 25H into the accumulator.
Instruction: LDA 2050H.
 3-byte size.
 Direct addressing mode.
 13 T-state.
 STA 16-bit address (Store Accumulator direct): It transfers the content stored in the
accumulator to addressed memory location.
Ex: Assume Accumulator contains 25H as 8-bit data. The instruction required to transfer
the contents of accumulator(25H) into the memory location of 2050H.
Instruction: STA 2050H.
 3-byte size.
 13 T-state.
 LDAX Rp (Load accumulator indirect): The contents of memory location whose
address is in BC or DE register pair is loaded into the accumulator. Here Rp can be BC or
DE register pair.
[A] [[Rp]]
Ex: Assume the contents of B and C are 20H and 50H respectively and memory location
2050H has the 8-bit data is 30H. The instruction required to load this content into the
accumulator.
Instruction: LDAX B
 1-byte size.
 7 T-state.
 STAX Rp (Store accumulator indirect): The content of accumulator is stored in
memory location whose address is in either BC or DE register pair. Here also Rpcan be
BC or DE register pair.
[[Rp]][A]
Ex: Assume accumulator content is 70H and registers D and E respectively. The
instruction required to store the content of accumulator into 2050H memory location.
Instruction: STAX D
 1-byte size.
 Register direct addressing mode.
 7 T-state.
 LHLD 16-bit address [Load H and L direct]: The instruction copies the contents of the
memory location pointed out by the 16-bit address in register L and copies the contents of
the next memory location in register H.
[L][16-bit address]
[H][16-bit address + 1]
Ex: Assume the contents of memory location 2050H and 2051 are 42H and 32H. The
instruction required to store the data 42H are 32H into H and L register.
Instruction: LHLD 2050H
 3-byte size.
 16 T-state.
 SHLD 16-bit address (Store H and L direct): This instruction copies the contents of L
and H registers into two consecutive memory locations. The contents of L register are
stored in the memory location specified by the 16-bit address in the operand and the
contents of H register are stored in the next memory locations by incrementing the
operand.
[16-bit address] [L]
[16-bit address + 1] [H]
Ex: Assume the contents of H and L are 50H and 62H respectively. To store this data in two
consecutive memory location 2050H and 2051H.
Instruction: SHLD 2050H.
 3-byte size.
 16 T-state.
No flags are affected.
 XCHG (Exchange H and L with D and E): The contents of H and L registers are
exchanged with the contents of D and E registers.
Ex: Assume H and L registers contents are 10H and 15H and the contents of D and E
registers are 20H and 25H respectively. The instruction required to exchange the HL and
DE register pair content.
Instruction: XCHG.
 3-byte size.
 4 T-state.
[ Nov / Dec 2018]

01. a) What is addressing mode? explain briefly the various addressing modes
of 8085Microprocessor
The various techniques used to specify the data (operand) for instruction to perform specific task
is called addressing mode
There are five types of addressing modes:
1. Direct addressing mode

2. Immediate addressing mode
3. Register addressing mode
4. Register indirect addressing mode
5. Implicit addressing mode
1. Direct addressing mode
In this mode the address of the data is given in the instruction itself.
For example:
STA 9000H: Store the content of accumulator in memory location 9000H
9000HA
LDA 2050H: Load accumulator with the data of specified location 2050H
A2050H
2.Immediate addressing mode:
In this mode the operand is available in the instruction itself.
For example:
MVI A, 50H: Move immediately the given data 50H to the accumulator.
ADI,65H: Add immediately the given data 65H with the content of accumulator.
3. Register addressing mode:
In this mode the data is available in a general purpose register.
For example:
MOV A, C: Move the content of register to accumulator.
ADD B: Add the content of register B with the content of accumulator.
4. Register indirect addressing mode:
In this addressing mode the address of the data is stored in a register pair and that register pair is
specified in the instruction
For example:
STAX D: The content of accumulator is stored to memory location of DE register pair.
MOV A, M: Move the content of memory location pointed by HL register pair to accumulator.
5. Implicit addressing mode:

In this addressing mode the instructions operate only on one operandThese instructions assume
that the data is to be in accumulator. All these instructions are one-byte instruction.
For example:
CMA: Compliment the content of accumulator.
RAL: Rotate accumulator content left.
b) Explain the classification of 8085 microprocessor instruction based on word

size. Give example.
The 8085 microprocessoris an 8-bitmicroprocessor and it can handle 8-bit data at a time. Thus
the memory location of 8085 microprocessors is designed to accommodate 8-bit data. If 16-bit
are to stored, they are stored in two consecutive memory location.
Three types of instruction are:
1. 1-byte instruction
2. 2-byte instruction
3. 3-byte instruction.
1. One-byte instructions –
In 1-byte instruction, the opcode and the operand of an instruction are represented in one byte.
operand are internal register and are coded into the instruction. These instruction requires only
one memory location to store single byte in memory.
 Example-1:
Task- Copy the contents of accumulator in register B.
 Mnemonic- MOV B, A
 Opcode- MOV
 Operand- B, A
 Hex Code- 47H
 Binary code- 0100 0111
2. Two-byte instructions –
Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next 8 bits indicates the operand.
 Example-1:
Task- Load the hexadecimal data 32H in the accumulator.
 Mnemonic- MVI A, 32H
 Opcode- MVI
 Operand- A, 32H
 Hex Code- 3E
 32
0011 0010
3. Three-byte instructions –
Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next two bytes specify the 16-bit address. The low-order address is represented in second
byte and the high-order address is represented in the third byte.
 Example-1:
Task- Load contents of memory 2050H in the accumulator.
 Mnemonic- LDA 2050H
 Opcode- LDA
 Operand- 2050H
 Hex Code- 3A
 50
 20
 0101 0000
02. a) write assembly language program to subtract two 16- bit numbers.
Memory Label Mnemonics operand Machine comments
code
Address
F000 START LXI H F102 21 02 F1 Point to 2nd number
F003 LXI D F100 11 00 F1 Point to 1st number
F006 LXI B FFF7 01 F7 FF Point to result
F009 LDAX D IA Get lower byte of 1st
number into
accumulator
F00A SUB M 96 Subtract lower byte
of 2nd number
F00B STAX B 02 Store lower byte
result in FFF7
FOOC INX H 23 Point to higher byte
of 2nd number
F00D INX D 13 Point to higher of 1st
byte number
F00El INX B 03 Point to higher byte
of result
F00F LDAX D IA Get higher byte of
1st number
F010 SUB M 9E Subtract higher byte
of 2nd number
F011 STAX B 02 Store higher byte
result in FFF8
F012 CALL UPDAD CDBC 06 -
F015 JMP DISP C3 12 F0 -
b) Explain the instructions DAA and DAD Rp.

DAA-Decimal Adjust Accumulator: The 8-bit result in accumulator is normally in binary form
represented by 2 Hexadecimal digits [00H to FFH]. The contents of the accumulator are changed
from a binary value to two 4-binary coded decimal [BCD] digits by using DAA instruction. This
instruction is used always immediately after any ADD instruction to convert the auxiliary carry
flag[AC] and carry flag[CY] to perform binary to BCD conversion.
DAD Rp – Add register pair to HL register pair: The 16 bit contents of the specified register pair
are added to the contents of the HL register pair and the sum is saved in the HL register pair. The
content of the source register pair is not altered.
03. With an example, explain the logical instructions of 8085 microprocessors.
 AND Operations
ANA R [AND register ‘R’ with accumulator]: In this instruction each bit of the given
register contents are ANDed with each bit f the accumulator contents [bit by bit]. The result
is saved in the accumulator. It does not affect the contents of the given register
[A][A]AND[R]
Where, R can bean accumulator or any general purpose register [A,B,C,D,E,H or L].
Ex: Assume ‘A’ contain 54H and register B contains 82H and CY=1
Instruction: ANA B
 1-byte size
 4 T-state.
 Z, S and P flags are affected.
 OR Operations
ORA R[OR register with accumulator]: In this instruction each bit of the given register
contents are ORed with each bit of the accumulator contents[bit by bit]. The result is saved in the
accumulator. It does not affect the contents of the given register.
[A][A] OR [R]
Where, R can be an accumulator or any general purpose register[A,B,C,D,E,H or L].
Ex: Assume[A]=73H and [C]=C3H before execution of the instruction ORA C. After execution
of the instruction ORA C is:
Instruction ORA C
 1-byte size
 Register addressing mode
 4 T-state
 1 Machine cycle
 Z, S and P flags are affected
 EX-OR operation
XRA R:[Exclusive OR register with Accumulator]: In this instruction each bit of the
given register contents are XORed with each bit of the accumulator contents. The result is saved
in the accumulator. It does not affect the contents of the given register.
[A][A]XOR[R]
Where, R can be an accumulator or any general purpose register[A,B,C,D,E,H or L].
Ex: Assume [A]= 77H and register[D]=56H
Instruction: XRA D; [21H][77H]XOR[56H]
 1-byte size
 4 T-state
 1 Machine cycle
 Z, S and P flags are affected
 Compare instructions
The microprocessor compares the contents of the accumulator with the data byte memory
contents by subtracting the data byte or register contentsfrom the accumulator.
CMP R:The contents of register R is subtracted from the contents of Accumulator but the result
is not stored. Result not stored [A]- [R].
Ex: Assume [A] =25H and Register [C] =09H. The instruction required to compare the contents
of register C from the Accumulator.
Instruction: CMP C
 1-byte size
 4 T-state
 1 Machine cycle
 All flags are affected.
 CPI 8-bit data [Compare immediate 8-bit data with Accumulator]: The given 8-bit is
subtracted from the contents of accumulator but the result in not stored.
[A]- 8-bit data.

Ex: Assume [A]=23H. Compare the 8-bit data byte 2A from the accumulator.
Instruction: CPI 2AH
 2-byte size
 Immediate addressing mode
 7 T-state
 2 Machine cycle
 All flags are affected
 RLC (Rotate Accumulator Left): Each binary bit of the accumulator is rotated left by one bit
position. The high order bit (D7) is shifted to low-order bit(D0) as well as to the carry
flag(CY). Cy is modified according to bit D7.
Ex: Assume [A]=C6H and CY=0, before executing the RLC instructions.
 1-byte size
 Implicit addressing mode
 4 T-state
 1 Machine cycle +
 CY flag is affected.
 CMC (Complement the carry status): This instruction complements the carry flag.
CYCY
Ex: If CY=1 before the execution of CMC instruction, the carry flag will be reset (CY=0)
after the execution of this instruction. Similarly, if CY=0 before the execution of CMC
instruction, the carry flag will be set(CY=10 after the execution of this instruction.
 1-byte size
 4 T-state
 1 Machine cycle
 CY flag is affected
 STC (Set carry flag): The carry flag is set to 1.
CY1
 1-byte size
 4 T-state
 1 Machine cycle
 CY flag is affected
UNIT III
[ Nov / Dec 2016]
01. Explain unconditional Jump Instructions.
The unconditional Jump instructions enable the programmer to set up continuous loops.
INSTRUCTION
Opcode Operand Description
JMP 16-bit Jump
 This is a 3-byte instruction.

 The second and third bytes specify the 16-bit memory address. The second byte specifies the
low-order and the third byte specifies the high-order memory address.
 Eg: To instruct the microprocessor to got to the memory location 2000H, and the mnemonics
and the machine code entered will be as:
 Machine Code Mnemonics
C3 JMP 2000H
00
20
02. Explain nesting of subroutine with an example.
The programming technique of a subroutine calling another subroutine is called nesting. This
process is limited only by the number of available stack locations. When a subroutine calls
another subroutine, all return addresses are stored on the stack.
The main program calls the subroutine from location 2050H. The address of the next instruction,
2050H, is placed on the stack, and the program is transferred to the subroutine at 2090H.
Subroutine 1 calls Subroutine 2 from location 209AH. The address 209DH is placed on the
stack, and the program is transferred to Subroutine 2. The sequence of execution returns to the
main program.
[ Nov / Dec 2017]

01. What is stack? Explain PUSH and POP operation.
Stack is a group of memory locations in the R/W memory (RAM) defined by the
programmer for temporary storage of data bytes of the register pairs or program status
word(PSW) during the execution of program.
PUSH operation: PUSH is used to store register pair data onto stack.
Syntax
PUSH Reg. pair
The contents of the register pair designated in the operand are copied onto the stack in the
following sequence. The stack pointer register is decremented and the contents of the high
order register (B, D, H, A) are copied into that location. The stack pointer register is
decremented again and the contents of the low-order register (C, E, L, flags) are copied to
that location.
Example: PUSH B
Suppose B contains 34 and C contains 56 and Top of Stack (i.e. SP) =2000
34 56
The PUSH B instruction makes the following changes in memory as shown and top of stack
is decremented by 2.
i.e. Top Of Stack = SP – 2 = 2000 – 2 = 1998
Memory location Data
2000 34
1999 56
1998 POP operation:
POP is used to
extract data off stack and to store in register pair
Syntax
POP Reg. pair
The contents of the memory location pointed out by the stack pointer register are copied to
the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented
by 1 and the contents of that memory location are copied to the high-order register (B, D, H,
A) of the operand. The stack pointer register is again incremented by 1.
03. Explain CALL and RETURN operations in 8085.

CALL:
The call instructions allow the programmer to call the subroutine program. The address of the
subroutine program is specified with the CALL instruction. During the execution of CALL
instruction, the current contents of program counter are saved on the stack and the address of
subroutine is copied in the program counter. Like the jump instructions, the CALL instructions
are also of two types:
Unconditional Call Instructions: - The unconditional all instructions transfer the program
execution flow to the address of the subroutine program unconditionally.
Example:
CALL 16-bit address [Calls the addressed subroutine program]: When this instruction is
executed the current contents of program counter are saved on this stack and the address
specified with call instruction is copied into the program counter to transfer the program
sequence to the specified memory location of the subroutine program unconditionally.
[SP-1][PCH]
[SP-2][PCL]
and [PC]16-bit address
Conditional Call Instructions: - The conditional call instructions transfer the program
execution flow to the address of the subroutine program when certain condition is satisfied.
 CC 16-bit address [CALL Subroutine if Carry Flag is set]: The addressed subroutine will
be called by the microprocessor, if the Carry Flag is Set (CY=1) as per the result of the
preceding instruction.
[SP-1][PCH]
[SP-2][PCL]
and [PC]16-bit address, to transfer the program sequence to specified memory location of the
subroutine program.
Return Instructions:The return instructions are used to end of the subroutine to transfers the
program sequence from subroutine program to the calling program unconditionally or
conditionally.
It is of two types:
 Unconditional return instruction:
1. RET (Return from Subroutine unconditionally): The RET instruction is used at the
end of the subroutine to transfers the program sequence from subroutine program to
the instructions of the main program next to the CALL instruction which called the
subroutine.
[PCL][SP]
[PCH][SP + 1]
[SP] [SP] + 2
 1-byte size.
 Register Indirect addressing mode.
 10 T-state.
 Conditional return instruction: If the condition is true the execution of the conditional
return instruction takes 3 machine cycles and 12 T-states. If the condition is not true only
one Machine cycles and 6 T-states are required to execute the instructions.
[PCL][SP]
[PCH][SP + 1]
 1-byte size.
 Register Indirect addressing mode.
 12 T-state.
UNIT-IV
[ Nov / Dec 2016]
01. Compare memory mapped I/O and I/O mapped I/O.
02. a) What is an Interrupt? Explain the classification of interrupts.

Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter –
 Vector interrupt – In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt – In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
 Maskable interrupt – In this type of interrupt, we can disable the interrupt by writing
some instructions into the program. For example: RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt – In this type of interrupt, we cannot disable the interrupt by

writing some instructions into the program. For example: TRAP.
 Software interrupt – In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e.
RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt – There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
b) Explain RIM instruction with bit pattern.

Read Interrupt Mask.
 It is a 1-Byte multi-purpose instruction. It is used for the following purposes.
 To check whether RST7.5, RST6.5, and RST5.5 are masked or not;
 To check whether interrupts are enabled or not;
 To check whether RST7.5, RST6.5, or RST5.5 interrupts are pending or not;
 To perform serial input of data.
Read Interrupt Mask instruction provides status information about interrupt system and this
instruction can be used for serial input of data. Through this RIM instruction, 8085 can know
which interrupt is masked or unmasked, etc. The contents of the Accumulator after the execution
of the RIM instruction provide this information.
[ Nov / Dec 2018]

01. Briefly explain the 8085 vectored interrupts.
• The instructions EI sets the interrupt enable flip-flop to enable the interrupt.
• The use of EI instructions enable all the interrupts.
• The instructions DI(Disable Interrupt is used to disable interrupt.
• In some case it can be situation to present the occurrence of interrupt when some task is
being performed in MPU. This is done by using DI instructions.
• The DI instructions resets the interrupt enable flip-flop and disable all the interrupt except
nonmaskable interrupt TRAP.
• When an interrupt line goes HIGH the processor completes its current instructions and same
PC on the stack.
It resets interrupt enable flip-flop before taking up ISS.
• All the interrupt except TRAP are disable by resetting the interrupt enable flip-flop.
UNIT-IV
[ Nov / Dec 2016]
01. Explain the functional block diagram of 8255 PPI.
Programmable peripheral interface 8255

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
 It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We
can assign different ports as input or output functions.
 The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O under certain conditions as required. It can be used with almost
any microprocessor.
 It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as
per the requirement.
Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and upper
PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed
in three different modes, i.e. the first mode is named as mode 0, the second mode is named as
Mode 1 and the third mode is named as Mode 2.
Operating Modes
8255A has three different operating modes –
 Mode 0 – In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit
ports. Each port can be programmed in either input mode or output mode where outputs
are latched and inputs are not latched. Ports do not have interrupt capability.
 Mode 1 – In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as
either input or output ports. Each port uses three lines from port C as handshake signals.
Inputs and outputs are latched.
 Mode 2 – In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals
for data transfer. The remaining three signals from Port C can be used either as simple
I/O or as handshake for port B.
Features of 8255A
The prominent features of 8255A are as follows –
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux’d.
 It is TTL compatible.
 It has improved DC driving capability.
02. write a note on interfacing devices.

 Interfacing can be defined as transferring data between microcontrollers and interfacing
peripherals such as sensors, keypads, microprocessors, analog to digital converters or ADC, LCD
displays, motors, external memories, even with other microcontrollers, some other interfacing
peripheral devices and so on or input devices and output devices. These devices that are
interfacing with 8051 microcontroller are used for performing special tasks or functions are called
as interfacing devices.
 The transfer of data between keyboard and microprocessor, and microprocessor and display
device is called Input Output Interfacing 8085 Microprocessor or I/O data transfer. This data
transfer is done with the help of I/O ports.
 Input Port :
 It is used to read data from the input device such as keyboard. The simplest form of input port is a
buffer. The input device is connected to the microprocessor through buffer as shown in the Fig.
4.28. This buffer is a tri-state buffer and its output is available only when enable signal is active.
 Output Port :
 It is used to send data to the output device such as display from the microprocessor. The simplest
form of output port is a latch.
[ Nov / Dec 2017]

01. Explain SIM and RIM Instructions.
SIM Instruction:
The individual masks for RST 5.5, RST 6.5, and RST 7.5 are manipulated using SIM instruction.
This instruction takes the bit pattern in the Accumulator and applies it to the interrupt to enable
or disable the specific interrupts. The accumulator is loaded by MVI A, data (data bits are as per
the requirements) instruction. The SIM instruction is then executed.
1. The bit D0is the mask for RST 5.5,bit D1is the mask for RST 6.5 and bit D2 is the mask
for RST 7.5.
 If the mask bit is 0, the interrupt is available.
 If the mask bit is 1, the interrupt is masked.
2. Bit D3(Mask Set Enable-MSE) is an control bit for bits D0, D1 and D2
 If it is set to 0 the mask is ignored and the old settings remain.
 If it is set to 1, the bits D0, D1and D2are effective and the new setting is applied.
3. The RST 7.5 is only the interrupt that has memory. Bit D4is additional control for RST
7.5. If D4=1, RST 7.5 is reset. This is used to override or ignore RST 7.5 without
servicing it.
4. Bits D7 and D6 of the accumulator are used for serial I/O and it do not affect the
interrupts.
 If D6 = 1, the bit D7 is used to transmit serial data.
 If D6 = 0, the bit D7 do not transmit serial data.
RIM (Read Interrupt Mask) instruction: This instruction will give the present status of the
interrupt. This instruction loads the accumulator with 8 bit data pattern and it shows the status of
each interrupt pin and mask. The RIM is a one byte instruction that can be used for the following
instructions:
 To read interrupt mask: This instruction loads the accumulator with 8-bit data pattern,
which indicates the current status of the interrupt mask. The bits D2-D6 show the current
setting of the mask for each of RST 7.5, RST 6.5, RST 5.5. Bit D3 shows whether the
maskable interrupt process is enabled or not. If D3=1, maskable interrupt process is
enabled.
To identify the pending interrupts: The bits D6 D5 D4 identify the pending interrupts. If bits are
1, the interrupt is pending.
[ Nov / Dec 2018]
01. Write short notes on:

DMA (Direct memory Access):
In a microprocessor, data transfers between I/O devices and memory will take place
through the microprocessor. The involvement of the processor slows down the data transfers
speed between I/O devices and memory because each instructions needs to defected and
executed. The transfer of data directly from I/O devices and memory without involvement of
microprocessor is called DMA, thus it is commonly used for high speed data transfer. In DMA,
the MPU releases the control of buses to a device called DMA controller. It uses two signals
named as HOLD and HLDA signals.
 HOLD signal: This is an active high input signal to the 8085 and active high output signal
to the DMA controller. This signal is operated by DMS controller to transfers the data
between two peripherals through DMA controller or without being routed through
microprocessor. This signal goes high when the DMA controller requesting to use the
address and data buses for data transfer between I/O devices to memory and vice-versa
without involvement of microprocessor.
 HLDA (Hold Acknowledge): This is an active high output signal to the microprocessor.
This signal goes high when the microprocessor surrenders the address and the data buses
to transfer data between the peripherals through DMA controller.
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SOLUTION BANK

BACHELOUR OF COMPUTER APPLICATIONS (B.C.A)

BCA501-T DATA COMMUNICATION AND NETWORKS

BCA503-T COMPUTER ARCHITECTURE

BCA504-T JAVA PROGRAMMING

BCA 501T DATA COMMUNICATION & NETWORKS

Total Teaching Hours : 60 No of Hours / Week : 04

BCA501T: DATA COMMUNICATIONS AND NETWORKS

ANSWER ANSWER ANSWER ANSWER

[Nov / Dec 2017]

[Nov / Dec 2018]

[TMAQ – Important Tutor Mark Assignment Questions]

[TMAQ – Important Tutor Mark Assignment Questions]

[TMAQ – Important Tutor Mark Assignment Questions]

[Nov / Dec 2018]

SECTION – B (10 Marks)

[TMAQ – Important Tutor Mark Assignment Questions]

[Nov / Dec 2017]

[TMAQ – Important Tutor Mark Assignment Questions]

[Nov / Dec 2017]

[Nov / Dec 2018]

SECTION – C (15 Marks)

[Nov / Dec 2016]

[Nov / Dec 2017]

[Nov / Dec 2018]

[Nov / Dec 2016]

SECTION – C (15 Marks)

[Nov / Dec 2016]

[Nov / Dec 2017]

[Nov / Dec 2018]

3.Explain ALOHA and slotted ALOHA

[Nov / Dec 2017]

[Nov / Dec 2018]

SECTION – D (10 Marks)

[Nov / Dec 2018]

3.Explain OSI reference model in detail.

SECTION – D (10 Marks)

4. Write any two difference between analog and digital signals?

9. What is Network Topology? List out any two network topologies.

10. Define attenuation?

12. What is telnet? How it differs from FTP ?

14. Define encoding and decoding.

15.Define datagram and packet.

16. Define bit rate and baud rate.

17. Define multiplexing?

18. What is cellular telephone network?

19. What do you mean by Nyquist signaling rate ? explain.

22. What is the use of repeaters?

23. Expand FDDI and CSMA

Offers 100 Mbps speed. Provide 1 Gbps speed.

Generate more delay. Less comparatively.

Simple Complicated and create more errors.

Can cover distance up to 10 km. Has the limit of 70 km.

Successor of 10-Base-T Ethernet. A successor of fast Ethernet.

3. Differentiate datagrams with virtual circuits

5. Explain Shannon capacity.

11. Differentiate connectionless and connection oriented services

NO CONNECTION-ORIENTED SERVICE CONNECTION-LESS SERVICE