Instructions and Instruction Sequencing
Instructions and Instruction Sequencing
Instructions and Instruction Sequencing
The tasks carried out by a computer program consist of a sequence of small steps, such as adding
two numbers, testing for a particular condition, reading a character from the keyboard, or sending
a character to be displayed on a display screen.
A computer must have instructions capable of performing four types of operations:
REGISTER TRANSFER NOTATION
We need to describe the transfer of information from one location in the computer to another.
Possible locations that may be involved in such transfers are memory locations, processor
registers, or registers in the I/O subsystem.
Most of the time, we identify a location by a symbolic name standing for its hardware binary address.
For example, names for the addresses of memory locations may be LOC, PLACE, A, VAR2;
processor register names may be RO, R5; and I/O register names may be DATAIN, OUTSTATUS,
and so on.
The contents of a location are denoted by placing square brackets around the name of the location.
Thus, the expression:
R1← [LOC]
means that the contents of memory location LOC are transferred into processor register R1.
As another example, consider the operation that adds the contents of registers R1 and R2, and then
places their sum into register R3.
This action is indicated as:
R3← [R1] + [R2]
The second example of adding two numbers contained in processor registers R1 and R2 and
placing their sum in R3 can be specified by the assembly language statement:
Add R1, R2, R3
BASIC INSTRUCTION TYPES
Let us first assume that this action is to be accomplished by a single machine Instruction.
Furthermore, assume that this instruction contains the memory addresses of the three operands- A,
B, and C.
This three-address instruction can be represented symbolically as:
Add A,B,C
Operands A and B are called the source operands, C is called the destination operand, and Add is
the operation to be performed on the operands.
A general instruction of this type has the format:
Operation Source1,Source2,Destination
If k bits are needed to specify the memory address of each operand, the encoded form of the above
instruction must contain 3k bits for addressing purposes in addition to the bits seeded to denote the
Add operation.
For a modern processor with a 32-bit address space, a 3-address instruction is too large to fit in one
word for a reasonable word length.
Thus, a format that allows multiple words to be used for a single instruction would be needed to
represent an instruction of this type.
An alternative approach is to use a sequence of simpler instructions to perform the same task, with
each instruction having only one or two operands.
Suppose that Two-address instructions of the form:
Operation Source, Destination
are available.
A single two-address instruction cannot be used to solve our original problem, which is to add the
contents of locations A and B, without destroying either of them, and to place the sum in location C.
The problem can be solved by using another two-address instruction that copies the contents of
one memory location into another.
Such an instruction is which performs the operation C←[B], leaving the contents of location B
unchanged.
Move BC
The word "Move" is a misnomer here; it should be "Copy"
However, this instruction name is deeply entrenched in computer nomenclature.
The operation C←[A]+[B], can now be performed by the two-instruction sequence:
Move BC
Add A,C
In all the instructions given above, the source operands are specified first, followed by the
destination.
This order is used in the assembly language expressions for machine instructions in many
computers.
But there are also many computers in which the order of the source and destination operands is
reversed.
But, even two-address instructions will not normally fit into one word for usual word lengths and
address sizes.
Another possibility is to have machine instructions that specify only one memory operand. When a
second operand is needed, as in the case of an Add instruction, it is understood implicitly to be in a
unique location.
A processor register, usually called the accumulator, may be used for this purpose.
Thus, the one-address instruction:
Add A
means the following:
Add the contents of memory location A to the contents of the accumulator register and place
the sum back into the accumulator.
Let us also introduce the one-address instructions:
Load A
and
Store A
The Load instruction copies the contents of memory location A into the accumulator, and the Store
instruction copies the contents of the accumulator into memory location A.
Using only one-address instructions, the operation C←[A] + [B] can be performed by executing the
sequence of instructions:
Load A
Add B
Store C
Note that the operand specified in the instruction may be a source or a destination, depending on
the instruction.
In the Load instruction, address A specifies the source operand, and the destination location, the
accumulator, is implied.
On the other hand, C denotes the destination location in the Store instruction, whereas the source,
the accumulator, is implied.
When a processor has several general-purpose registers, many instructions involve only operands
that are in the registers.
In fact, in many modem processors, computations can be performed directly only on data held to
processor registers.
Instructions such as
Add Ri,Rj
or
Add Ri,Rj,Rk
are of this type.
In both of these instructions, the source operands are the contents of registers Ri and Rj.
In the first instruction, Rj also serves as the destination register, whereas in the second instruction,
a third register, Rk, is used as the destination.
Such instructions, when only register names are contained in the instruction, will normally it into
one word.
In processors where one operand may be in the memory but the other must be in a register, an
instruction sequence for the required task would be:
Move A,Ri
Add B,Ri
Move Ri,C
The speed with which a given task is carried out depends on the time it takes to transfer
instructions from memory into the processor and to access the operands referenced by these
instructions.
Transfers that involve the memory are much slower than transfers within the processor. Hence, a
substantial increase in speed is achieved when several operations are performed in succession on
data in processor registers without the need to copy data to or from the memory.
When machine language programs are generated by compilers from high-level languages, it is
important to minimize the frequency with which data is moved back and forth between the memory
and processor registers.
It is also possible to use instructions in which the locations of all operands are defined implicitly.
Such instructions are found in machines that store operands in a structure called a pushdown stack.
In this case, the instructions are called zero-address instructions.
INSTRUCTION EXECUTION AND STRAIGHT-LINE SEQUENCING
Figure (1) shows a possible program segment for this task as it appears in the memory of a
computer.
Executing a given instruction is a two-phase procedure.
In the first phase, called instruction fetch, the instruction is fetched from the memory location
whose address is in the PC.
This instruction is placed in the instruction register (IR) in the processor.
At the start of the second phase, called instruction execute, the instruction in IR is examined to
determine which operation is to be performed.
The specified operation is then performed by the processor.
This often involves fetching operands from the memory or from processor registers, performing
an arithmetic or logic operation, and storing the result in the destination location. At some point
during this two-phase procedure, the contents of the PC are advanced to point to the next
instruction.
When the execute phase of an instruction is completed, the PC contains the address of the t
instruction, and a new instruction fetch phase can begin.
In most processors, the execute phase itself is divided into a small number of distinct phases
corresponding to fetching operands, performing the operation, and storing the result.