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TPS53014
SLVSBF1A – MAY 2012 – REVISED FEBRUARY 2019

TPS53014 4.5-V to 28-V Input, D-CAP2™ synchronous buck controller

1 Features 3 Description
1• D-CAP2™ mode control The TPS53014 is a single, adaptive on-time D-
CAP2™ mode synchronous buck controller. The
– Fast transient response TPS53014 enables system designers to complete the
– No external parts required for loop suite of various end equipment's power bus
compensation regulators with cost effective low external component
– Compatible with ceramic output capacitors count and low standby current solution. The main
control loop for the TPS53014 uses the D-CAP2
• High initial reference accuracy (±1%) mode control which provides a very fast transient
• Wide input voltage range: 4.5 V to 28 V response with no external compensation
• Output voltage range: 0.77 V to 7.0 V components. The Adaptive on-time control supports
seamless transition between PWM mode at higher
• Low-side RDS(on) loss-less current sensing
load condition and Eco-mode™ operation at light
• Adjustable soft start load. Eco-mode allows the TPS53014 to maintain
• Non-sinking pre-biased soft start high efficiency during lighter load conditions. The
• 500-kHz Switching frequency TPS53014 is also able to adapt to both low
equivalent series resistance (ESR) output capacitors
• Cycle-by-cycle overcurrent limiting control such as POSCAP or SP-CAP and ultra-low ESR
• Auto-Skip Eco-ModeTM for High Efficiency at Light ceramic capacitors. The device provides convenient
load and efficient operation with input voltages from 4.5 V
• OCL/OVP/UVP/UVLO/TSD Protections to 28 V and output voltage from 0.77 V to 7 V.
• Adaptive Gate Drivers with Integrated Boost The TPS53014 is available in the 3-mm × 3-mm 10-
PMOS Switch pin VSSOP (DGS) package and is specified for an
• Thermally Compensated OCP, 4000 ppm/°C ambient temperature range of –40°C to +85°C.
• 10 pin VSSOP Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications TPS53014 DGS (10) 3.00 mm × 3.00 mm
• Point-of-load regulation in low power systems for (1) For all available packages, see the orderable addendum at
wide range of applications the end of the data sheet.
– Digital TV power supply
– Networking home terminal
– Digital set-top box (STB)
– DVD player / recorder
– Gaming consoles and other
Typical Application

VIN

TPS53014
1 VFB VBST 10

2 SS DRVH 9

VOUT
3 VREG5 SW 8

EN 4 EN DRVL 7

VIN 5 VIN PGND 6

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.1 Overview ................................................................. 12
2 Applications ........................................................... 1 7.2 Functional Block Diagram ....................................... 12
3 Description ............................................................. 1 7.3 Feature Description................................................. 12
4 Revision History..................................................... 2 8 Application and Implementation ........................ 15
8.1 Typical Application ................................................. 15
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Layout ................................................................... 17
9.1 Layout Guidelines ................................................... 17
6.1 Absolute Maximum Ratings ..................................... 4
6.2 Recommended Operating Conditions....................... 4 10 Device and Documentation Support ................. 18
6.3 Thermal Information .................................................. 4 10.1 Receiving Notification of Documentation Updates 18
6.4 Electrical Characteristics........................................... 5 10.2 Community Resources.......................................... 18
6.5 Typical Characteristics ............................................. 7 10.3 Trademarks ........................................................... 18
10.4 Electrostatic Discharge Caution ............................ 18
7 Detailed Description ............................................ 12
10.5 Glossary ................................................................ 18

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (May 2012) to Revision A Page

• Editorial changes only; no technical changes; update to current TI data sheet standards for current content ..................... 1

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5 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View

TPS53014
1 VFB VBST 10

2 SS DRVH 9

3 VREG5 SW 8

4 EN DRVL 7

5 VIN PGND 6

Pin Functions
PIN
I/O DESCRIPTION
NAME VSSOP-10
VFB 1 I D-CAP2 feedback input. Connect to output voltage with resistor divider.
SS 2 O Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time.
VREG5 3 O Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum 4.7-μF high
quality ceramic capacitor. VREG5 is active when EN is asserted high.
EN 4 I Enable. Pull High to enable converter.
VIN 5 I Supply Input for 5-V linear regulator. Bypass to GND with a minimum 0.1-μF high quality ceramic capacitor.
PGND 6 I System ground.
DRVL 7 O Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF)
and VREG5(ON).
SW 8 I/O Switch node connections for both the high-side driver and over current comparator.
High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and
DRVH 9 O
VBST(ON).
High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from VBST to SW. An internal
VBST 10 I
diode is connected between VREG5 and VBST

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
Operating under free-air temperature range (unless otherwise noted)
VALUE UNIT
VIN, EN –0.3 to 30
VBST –0.3 to 36
VBST - SW –0.3 to 6
Input voltage range V
VFB –0.3 to 6
SW –0.3 to 30
SW (10 nsec transient) –3.0 to 30
DRVH –2 to 36
DRVH - SW –0.3 to 6
Output voltage range V
DRVL, VREG5, SS –0.3 to 6
PGND –0.3 to 0.3
TA Operating ambient temperature range –40 to 85 °C
TSTG Storage temperature range –55 to 150 °C
TJ Junction temperature range –40 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Recommended Operating Conditions

MIN MAX UNIT
Supply input voltage range VIN 4.5 28 V
VBST –0.1 33.5
VBST - SW –0.1 5.5
Input voltage range VFB –0.1 5.5 V
EN –0.1 28
SW –1.0 28
DRVH –1.0 33.5
DRVH - SW –0.1 5.5
Output Voltage range V
DRVL, VREG5, SS –0.1 5.5
PGND –0.1 0.1
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 125 °C

6.3 Thermal Information

TPS53014
THERMAL METRIC (1) UNITS
DGS (10 PINS)
θJA Junction-to-ambient thermal resistance 172.2 °C/W
θJCtop Junction-to-case (top) thermal resistance 44.0 °C/W
θJB Junction-to-board thermal resistance 93.0 °C/W
ψJT Junction-to-top characterization parameter 1.6 °C/W
ψJB Junction-to-board characterization parameter 91.4 °C/W
θJCbot Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).

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6.4 Electrical Characteristics

over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA = 25°C, EN = 5V, VVFB = 0.8V, 660
IIN VIN Supply current μA
VSW = 0 V
IVINSDN VIN Shutdown current VIN current, TA = 25°C, No Load , VEN = 0V, 6.0 μA
VREG5 = OFF
VFB VOLTAGE and DISCHARGE RESISTANCE
VVFBTHL VFB Threshold voltage TA = 25°C , VOUT = 1.05 V 765.3 773.0 780.7 mV
(1)
TCVFB VFB Temperature coefficient Relative to TA = 25°C -140 140 ppm/°C
IVFB VFB Input current VFB = 0.8V, TA = 25°C -150 -10 100 nA
VREG5 OUTPUT
VVREG5 VREG5 Output voltage TA=25°C, 6 V < VIN < 28 V, IVREG5 = 5 mA 5.1 V
IVREG5 Output current VIN = 5.5V, VVREG5 = 4.0V, TA = 25°C 120 mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
Source, IDRVH = –50mA, TA = 25°C 3.2 4.7
RDRVH DRVH resistance Ω
Sink, IDRVH = 50mA, TA = 25°C 1.4 2.4
Source, IDRVL = –50mA, TA = 25°C 6.9 8.2
RDRVL DRVL resistance Ω
Sink, IDRVL = 50mA, TA = 25°C 0.8 1.7
DRVH-low to DRVL-on (1) 15
TD Dead time ns
DRVL-low to DRVH-on (1) 20
INTERNAL BOOST DIODE
VFBST Forward voltage VVREG5-VBST, IF = 10mA, TA = 25°C 0.1 0.2 V
SOFT START
Issc SS Charge current VSS = 0V , TA = 25°C -7.36 -6.4 -5.44 μA
Issd SS Discharge current VSS = 0.5V , TA = 25°C 4.5 5.0 mA
TCISSC ISSC Temperature coefficient Relative to TA = 25°C -4.5 4.5 nA/°C
UVLO
VREG5 Rising 4.0 V
VUVVREG5 VREG5 UVLO threshold
Hysteresis 0.3
LOGIC THRESHOLD
VENH EN H-level threshold voltage 1.6 V
VENL EN L-level threshold voltage 0.5 V
REN EN pin resistance to GND VEN = 12 V 225 450 900 kΩ
CURRENT SENSE
ITRIP TRIP Source current VDRVL = 0.1V, TA = 25°C 14.3 15 15.8 μA
TCVTRIP VTRIP Temperature coefficient Relative to TA = 25°C 4000 ppm/°C
RTRIP = 75kΩ, TA = 25°C 234 336 424
VOCL Current limit threshold RTRIP = 27kΩ, TA = 25°C 121 174 220 mV
RTRIP = 6.8kΩ, TA = 25°C 35 50 63
ON-TIME TIMER CONTROL
TON On time VOUT = 1.05 V (1) 250 ns
TOFF(MIN) Minimum off time VIN = 4.5 V, VVFB = 0.7 V, TA = 25°C 230 ns

(1) Ensured by design. Not production tested.

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Electrical Characteristics (continued)

over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Output OVP trip threshold OVP detect voltage 115% 120% 125%
TOVPDEL Output OVP propagation delay 10 μs
VUVP Output UVP trip threshold UVP detect voltage 63% 68% 73%
TUVPDEL Output UVP delay 1 ms
TUVPEN Output UVP enable delay UVP enable delay / soft start time X1.4 X1.7 X2.0
THERMAL SHUTDOWN
Shutdown temperature (1) 150 °C
TSDN Thermal shutdown threshold
Hysteresis (1) 25

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6.5 Typical Characteristics

VIN = 12 V, TA= 25°C (unless otherwise noted)

1200 12

1000 10

Supply Current−Shutdown Current (µA)

800 8
Supply Current (µA)

600 6

400 4

200 2

VIN = 12 V VIN = 12 V
0 0
−50 0 50 100 150 −50 0 50 100 150
Junction Temperature (°C) Junction Temperature (°C)
G001 G002

Figure 1. VIN Supply Current vs Junction Temperature Figure 2. VIN Shutdown Current vs Junction Temperature
80 600

70
500

60
Switching Frequency (kHz)

400
EN Input Current (µA)

50

40 300

30
200

20

100
10 VOUT = 1.05 V
VOUT = 1.8 V
VIN = 12 V IOUT = 3 A VOUT = 3.3 V
0 0
0 5 10 15 20 25 30 −50 0 50 100 150
EN Input Voltage (V) Junction Temperature (°C)
G003 G004

Figure 3. En Input Current Vs En Input Voltage Figure 4. Switching Frequency vs Junction Temperature

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Typical Characteristics (continued)

VIN = 12 V, TA= 25°C (unless otherwise noted)
600 0.800

0.795
500
0.790
Switching Frequency (kHz)

0.785
400

VFB Voltage (V)

0.780

300 0.775

0.770
200
0.765

0.760
100
VOUT = 1.05 V
VOUT = 1.8 V 0.755 IOUT = 50 mA
IOUT = 3 A VOUT = 3.3 V IOUT = 2 A
0 0.750
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Input Voltage (V) Input Voltage (V)
G005 G006

Figure 5. Switching Frequency vs Input Voltage Figure 6. Vfb Voltage vs Input Voltage

0.800 1.10

0.795 1.09

0.790 1.08

0.785 1.07
Output Voltage (V)
VFB Voltage (V)

0.780 1.06

0.775 1.05

0.770 1.04

0.765 1.03

0.760 1.02
VIN = 5 V
0.755 IOUT = 50 mA 1.01 VIN = 12 V
IOUT = 2 A VIN = 28 V
0.750 1.00
−50 0 50 100 150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Ambient Temperature (°C) Output Current (A)
G007 G008

Figure 7. Vfb Voltage vs Ambient Temperature Figure 8. Load Regulation

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Typical Characteristics (continued)

VIN = 12 V, TA= 25°C (unless otherwise noted)
1.10

1.09
VO (50 mV/div ac coupled)
1.08

1.07
Output Voltage (V)

1.06

1.05

1.04 IOUT (5 A/div)

1.03

1.02

Slew Rate (0.3 A/µsec)

1.01 IOUT = 50 mA
IOUT = 2 A Time Scale (100 µsec/div)
1.00
0 5 10 15 20 25 30
Input Voltage (V)
G009

Figure 10. Transient Response

Figure 9. Line Regulation
100
EN (10 V/div)
90

80

VREG5 (5 V/div) 70
VO (500 mV/div)
60
Efficiency (%)

50
SS (2 V/div)
40

30

20
VOUT = 1.05 V
10 VOUT = 1.8 V
Time (1 msec/div) VIN = 12 V VOUT = 3.3 V
0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Output Current (A)
G012

Figure 11. Start Up Waveforms

Figure 12. Efficiency

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Typical Characteristics (continued)

VIN = 12 V, TA= 25°C (unless otherwise noted)
100

90 VO = 1.05 V VO (20 mV/div ac coupled)

80

70

60
Efficiency (%)

50
SW (5 V/div)
40

30

20
VOUT = 1.05 V
10 VOUT = 1.8 V
VIN = 12 V VOUT = 3.3 V Time (1 µsec/div)
0
0.001 0.01 0.1 1 10
Output Current (A)
G013

Figure 14. Output Voltage Ripple, IOUT = 8 A

Figure 13. Light Load Efficiency

VO = 1.05 V
VO = 1.05 V VO (20 mV/div ac coupled) VIN (50 mV/div ac coupled)

SW (5 V/div) SW (5 V/div)

Time (10 µsec/div) Time (1 µsec/div)

Figure 15. Output Voltage Ripple, IOUT = 50 mA Figure 16. Input Voltage Ripple, IOUT = 8 A

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Typical Characteristics (continued)

VIN = 12 V, TA= 25°C (unless otherwise noted)

VO = 1.05 V
VIN (10 mV/div ac coupled)

SW (5 V/div)

Time (10 µsec/div)

Figure 17. Input Voltage Ripple, IOUT = 50 mA

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7 Detailed Description

7.1 Overview
The TPS53014 is single synchronous step-down (buck) controller. It operates using D-CAP2™ mode control.
The fast transient response of D-CAP2™ control reduces the required amount of output capacitance to meet a
specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including
ceramic and special polymer types.

7.2 Functional Block Diagram

TPS53014 VREG5 VIN

VBST
-32% + 10
UV
- DRVH
CONTROL
9
+ LOGIC
OV XCON
SW VOUT
+20% - 8

REF + VREG5
VFB + DRVL
SS
- 1 7
1 SHOT
PGND
6

10µA

PGND
SGND 6.4µA
- ADC
SS OCL
2 + SW
VIN
SGND 5 VIN
EN
EN
EN 4 SS LOGIC VREG5
LOGIC
VREG5 3

UV REF REF UVLO

PGND
OV PROTECTION
UVLO LOGIC
TSD

7.3 Feature Description

7.3.1 PWM Operation
The main control loop of the TPS53014 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the
beginning of each cycle, the high-side MOSFET is turned on. this MOSFET is turned off when the internal timer
expires. This timer is set by the converter input voltage VIN, and the output voltage VO, to maintain a pseudo-
fixed frequency over the input voltage range, hence it is called adaptive on-time control. The timer is reset and
the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An
internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced
output ripple from D-CAP2™ mode control.
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Feature Description (continued)

7.3.2 Auto-Skip Eco-Mode™ Control
The TPS53014 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point where
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost half
as is was in the continuous conduction mode because it takes longer time to discharge the output capacitor with
smaller load current to the level of the reference voltage. The transition point to the light load operation IOX(LL)
current can be calculated in Equation 1 with 500kHz used as fsw.

IOUT(LL) =
1 (V -V )×VOUT
× IN OUT
2×L×fSW VIN (1)

7.3.3 Drivers
TPS53014 contains two high-current resistive MOSFET gate drivers. The low-side driver is a PGND referenced,
VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET whose
source is connected to PGND. The high-side driver is a floating SW referenced, VBST powered driver designed
to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the VBST voltage during the
high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to
Gate Charge (Qg @ Vgs = 5V) times Switching frequency (fsw). To prevent cross-conduction, there is a narrow
dead-time when both high-side and low-side drivers are OFF between each driver transition. During this time the
inductor current is carried by one of the MOSFETs body diodes.

7.3.4 5-Volt Regulator

The TPS53014 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all both
drivers and the ICs internal logic. A high-quality 4.7µF or greater ceramic capacitor from VREG5 to GND is
required to stabilize the internal regulator.

7.3.5 Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6.4-µA current begins charging the
capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during
start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.773 V and SS pin source
current is 6.4-µA.
CSS (nF) x VFB(V) CSS (nF) x 0.773 V
t (ms) = =
SS I (mA) 6.4mA
SS (2)
The TPS53014 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VO) starts
and ramps up smoothly into regulation from pre-biased startup to normal mode operation.

7.3.6 Overcurrent Protection

TPS53014 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53014 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, a resister should
be connected between DRVL and PGND. The recommended values are given inTable 1.

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Table 1. OCL Resistor Values

RESISTER VALUE ( kΩ) Vtrip (V)
6.8 0.050
11 0.087
18 0.125
27 0.174
39 0.224
56 0.274
75 0.336

IOCL is determined by Equation 3.

æ (V -V ) V ö V
IOCL = ç IN OUT × OUT ÷ + TRIP
ç 2×L×f VIN ÷ø RDS(ON)
è SW (3)
The trip voltage is set between 0.05 V to 0.336 V over all operational temperature, including the 4000ppm/°C
temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the
overcurrent limit, the voltage will begin to drop. If the over-current conditions continues the output voltage will fall
below the under voltage protection threshold and the TPS53014 will shut down.

7.3.7 Over/Undervoltage Protection

TPS53014 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 120% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 68% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 1ms, TPS53014 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 × Tss after power-on. The OVP and UVP latch off is
reset when EN goes low.

7.3.8 UVLO Protection

TPS53014 has under voltage lock out protection (UVLO) that monitors the voltage of VREG5 pin. When the
VREG5 voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF. The
UVLO is non-latch protection.

7.3.9 Thermal Shutdown

TPS53014 monitors its temperature. If the temperature exceeds the threshold value (typically 150°C), the device
shuts off. When the temperature falls below the threshold, the IC starts again. When VIN starts up and VREG5
output voltage is below its nominal value, the thermal shutdown threshold is kept lower than 150°C. As long as
VIN rises, TJ must be kept less than 110°C.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Typical Application

A typical application schematic is shown in Figure 18.

VIN
C5
R1 10µF
3.96k TPS53014
1 VFB VBST 10
R2 Q1
10.0k CSD17307Q5A
C1
2 SS DRVH 9
C4 L1 1.5µH
0.01µF 0.1µF VOUT
3 VREG5 SW 8
C2 Q2
4.7µF CSD17510Q5A C6 C7 C8
SGND EN 4 EN DRVL 7
R3 22µF 22µF 22µF

VIN 5 VIN PGND 6

C3
10µF
PGND

PGND

Figure 18. Application Schematic

8.1.1 Detailed Design Procedure

8.1.1.1 Component Selection

8.1.1.1.1 Inductor
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 4 can be used to calculate te value for LOUT.
VIN(MAX) -VOUT V
L OUT = × OUT
IL(RIPPLE) ×fSW VIN(MAX)
(4)
The inductors current ratings needs to support both the RMS (thermal) current and the peak (saturation) current.
The RMS and peak inductor current can be estimated as follows:
VIN(MAX) -VOUT V
IL(RIPPLE) = × OUT
LOUT ×fSW VIN(MAX)
(5)
V
IL(PEAK) = TRIP +IL(RIPPLE)
RDS(ON)
(6)
2 2
IL(RMS) = IOUT + 1 ×IL(RIPPLE)
12 (7)
Note:
The calculation above shall serve as a general reference. To further improve transient response, the output
inductance could be reduced further. This needs to be considered along with the selection of the output
capacitor.

Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS53014
TPS53014
SLVSBF1A – MAY 2012 – REVISED FEBRUARY 2019 www.ti.com

Typical Application (continued)

8.1.1.1.2 Output Capacitor
The capacitor value and ESR determines the amount of output voltage ripple and load transient response.
Ceramic output capacitors with X5R dielectric or better are recommended .
IL(RIPPLE) 1
COUT = ×
8×VOUT(RIPPLE) fSW
(8)
2
ΔILOAD
COUT = ×L OUT
2×VOUT ×ΔVOS (9)
2
ΔILOAD
COUT = ×L OUT
2×K×ΔVUS (10)
Where:
TON
K= (VIN -VOUT )×
TON -TOFF(MIN)
• ΔVOS = The allowable amount of overshoot voltage in load transition
• ΔVUS = The allowable amount of undershoot voltage in load transition
• TOFF(MIN) = Minimum off time (11)
Select the capacitance value greater than the largest value calculated from Equation 8, Equation 9 and
Equation 10. The minimum recommended output capacitance is 44 μF.

8.1.1.1.3 Input Capacitor

The TPS53014 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.

8.1.1.1.4 Bootstrap Capacitor

The TPS53014 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side
drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The capacitor voltage rating should
be greater than 10 V.

8.1.1.1.5 VREG5 Capacitor

The TPS53014 requires that the VREG5 regulator is bypassed. A minimum 4.7-μF high-quality ceramic capacitor
must be connected between the VREG5 and PGND for proper operation. The capacitor voltage rating should be
greater than 10 V.

8.1.1.1.6 Choose Output Voltage Resistors

The output voltage is set with a resistor divider from output voltage node to the VFB pin. TI recommends using
1% tolerance or better resistors. Select R2 between 10 kΩ and 100 kΩ and use Equation 12 to calculate R1.
æV ö
R1 = ç OUT -1÷ ×R2
V
è VFB ø (12)
spacer

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 TPS53014
www.ti.com SLVSBF1A – MAY 2012 – REVISED FEBRUARY 2019

9 Layout

9.1 Layout Guidelines

• Keep the input switching current loop as small as possible.
• Place the input capacitor close to the top switching FET. Keep the output current loop as small as possible.
• Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (VFB) of the device.
• Keep analog and non-switching components away from switching components.
• Make a single point connection from the signal ground to power ground.
• Do not allow switching current to flow under the device.

Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPS53014
TPS53014
SLVSBF1A – MAY 2012 – REVISED FEBRUARY 2019 www.ti.com

10 Device and Documentation Support

10.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

10.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

10.3 Trademarks
D-CAP2, Eco-mode, Eco-Mode, E2E are trademarks of Texas Instruments.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

18 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated

Product Folder Links: TPS53014

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS53014DGS ACTIVE VSSOP DGS 10 80 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 53014

TPS53014DGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 53014

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53014DGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53014DGSR VSSOP DGS 10 2500 366.0 364.0 50.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS53014DGS DGS VSSOP 10 80 330 6.55 500 2.88

Pack Materials-Page 3
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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