Bipolar Junction Transistors

3
CHAPTER OBJECTIVES
●
● Become familiar with the basic construction and operation of the Bipolar
Junction Transistor.
● Be able to apply the proper biasing to insure operation in the active region.
● Recognize and be able to explain the characteristics of an npn or pnp transistor.
● Become familiar with the important parameters that define the
response of a transistor.
● Be able to test a transistor and identify the three terminals.

3.1 INTRODUCTION
●
During the period 1904 to1947, the vacuum tube was the electronic device of interest and
development. In 1904, the vacuum-tube diode was introduced by J. A. Fleming. Shortly Dr. William Shockley (seated);
thereafter, in 1906, Lee De Forest added a third element, called the control grid, to the Dr. John Bardeen (left); Dr. Walter
vacuum diode, resulting in the first amplifier, the triode. In the following years, radio H. Brattain. (Courtesy of AT&T
and television provided great stimulation to the tube industry. Production rose from Archives and History Center.)
Dr. Shockley Born: London,
about 1 million tubes in 1922 to about 100 million in 1937. In the early 1930s the four-
England, 1910
element tetrode and the five-element pentode gained prominence in the electron-tube PhD Harvard,
industry. In the years to follow, the industry became one of primary importance, and rapid 1936
advances were made in design, manufacturing techniques, high-power and high-frequency Dr. Bardeen Born: Madison,
applications, and miniaturization. Wisconsin, 1908
On December 23, 1947, however, the electronics industry was to experience the advent PhD Princeton,
of a completely new direction of interest and development. It was on the afternoon of this 1936
day that Dr. S. William Shockley, Walter H. Brattain, and John Bardeen demonstrated the Dr. Brattain Born: Amoy,
amplifying action of the first transistor at the Bell Telephone Laboratories as shown in China, 1902
Fig. 3.1. The original transistor (a point-contact transistor) is shown in Fig. 3.2. The ad- PhD University
vantages of this three-terminal solid-state device over the tube were immediately obvious: of Minnesota,
1928
It was smaller and lightweight; it had no heater requirement or heater loss; it had a rugged
construction; it was more efficient since less power was absorbed by the device itself; it All shared the Nobel Prize in 1956
was instantly available for use, requiring no warm-up period; and lower operating voltages for this contribution.
were possible. Note that this chapter is our first discussion of devices with three or more
terminals. You will find that all amplifiers (devices that increase the voltage, current, or FIG. 3.1
power level) have at least three terminals, with one controlling the flow or potential between Coinventors of the first transistor
at Bell Laboratories.
the other two.

129
130 BIPOLAR JUNCTION 3.2 TRANSISTOR CONSTRUCTION
TRANSISTORS ●
The transistor is a three-layer semiconductor device consisting of either two n- and one
p-type layers of material or two p- and one n-type layers of material. The former is called
an npn transistor, and the latter is called a pnp transistor. Both are shown in Fig. 3.3 with
the proper dc biasing. We will find in Chapter 4 that the dc biasing is necessary to establish
the proper region of operation for ac amplification. The emitter layer is heavily doped,
with the base and collector only lightly doped. The outer layers have widths much greater
than the sandwiched p- or n-type material. For the transistors shown in Fig. 3.2 the ratio of
the total width to that of the center layer is 0.150兾0.001  150:1. The doping of the sand-
wiched layer is also considerably less than that of the outer layers (typically, 1:10 or less).
FIG. 3.2 This lower doping level decreases the conductivity (increases the resistance) of this mate-
The first transistor. (Courtesy of rial by limiting the number of “free” carriers.
AT&T Archives and History Center.) For the biasing shown in Fig. 3.3 the terminals have been indicated by the capital letters
E for emitter, C for collector, and B for base. An appreciation for this choice of notation will
0.150 in. develop when we discuss the basic operation of the transistor. The abbreviation BJT, from
bipolar junction transistor, is often applied to this three-terminal device. The term bipolar
0.001 in.
reflects the fact that holes and electrons participate in the injection process into the oppo-
sitely polarized material. If only one carrier is employed (electron or hole), it is considered
E p n p C a unipolar device. The Schottky diode of Chapter 16 is such a device.
B
3.3 TRANSISTOR OPERATION
●
+ – + – The basic operation of the transistor will now be described using the pnp transistor of Fig. 3.3a.
The operation of the npn transistor is exactly the same if the roles played by the electron and
VEE VCC hole are interchanged. In Fig. 3.4a the pnp transistor has been redrawn without the base-to-
(a) collector bias. Note the similarities between this situation and that of the forward-biased diode
in Chapter 1. The depletion region has been reduced in width due to the applied bias, resulting
in a heavy flow of majority carriers from the p- to the n-type material.
0.150 in.
Let us now remove the base-to-emitter bias of the pnp transistor of Fig. 3.3a as shown
0.001 in. in Fig. 3.4b. Consider the similarities between this situation and that of the reverse-biased
diode of Section 1.6. Recall that the flow of majority carriers is zero, resulting in only a
E n p n C minority-carrier flow, as indicated in Fig. 3.4b. In summary, therefore:
One p–n junction of a transistor is reverse-biased, whereas the other is forward-biased.
B

– + – + + Majority carriers + Minority carriers

VEE VCC ++–– ++ – + –+– +– –+

–+ p –+ –n– – + ++– C
n–
E
++ p– +
(b) – +
+– +– + + –
– +–+ – – –+
–
FIG. 3.3 + – B B + –
Types of transistors: (a) pnp; Depletion region
Depletion region
(b) npn.
+ – + –
VEE VCC
(a) (b)

FIG. 3.4
Biasing a transistor: (a) forward-bias; (b) reverse-bias.

In Fig. 3.5 both biasing potentials have been applied to a pnp transistor, with the resulting
majority- and minority-carrier flows indicated. Note in Fig. 3.5 the widths of the depletion
regions, indicating clearly which junction is forward-biased and which is reverse-biased.
As indicated in Fig. 3.5, a large number of majority carriers will diffuse across the forward-
biased p–n junction into the n-type material. The question then is whether these carriers will
contribute directly to the base current IB or pass directly into the p-type material. Since the
sandwiched n-type material is very thin and has a low conductivity, a very small number of
 + Majority carriers + Minority carriers COMMON-BASE 131
p n p CONFIGURATION
IE IC
E C

B
Depletion regions
IB
+ – + –
VEE VCC

FIG. 3.5
Majority and minority carrier flow of a pnp
transistor.

these carriers will take this path of high resistance to the base terminal. The magnitude of the
base current is typically on the order of microamperes, as compared to milliamperes for the
emitter and collector currents. The larger number of these majority carriers will diffuse across IE IC
the reverse-biased junction into the p-type material connected to the collector terminal as indi- p n p
E C
cated in Fig. 3.5. The reason for the relative ease with which the majority carriers can cross the
reverse-biased junction is easily understood if we consider that for the reverse-biased diode B
IB
the injected majority carriers will appear as minority carriers in the n-type material. In other
words, there has been an injection of minority carriers into the n-type base region material. + – + –
Combining this with the fact that all the minority carriers in the depletion region will cross the
reverse-biased junction of a diode accounts for the flow indicated in Fig. 3.5. VEE VCC
Applying Kirchhoff’s current law to the transistor of Fig. 3.5 as if it were a single node,
IE IC
we obtain
E C
IE = IC + IB (3.1)
IB
and find that the emitter current is the sum of the collector and base currents. The collector
current, however, comprises two components—the majority and the minority carriers as
B
indicated in Fig. 3.5. The minority-current component is called the leakage current and is
given the symbol ICO (IC current with emitter terminal Open). The collector current, there- (a)
fore, is determined in total by

IC = ICmajority + ICOminority (3.2)

IE IC
For general-purpose transistors, IC is measured in milliamperes and ICO is measured in n p n
microamperes or nanoamperes. ICO, like Is for a reverse-biased diode, is temperature sen- E C
sitive and must be examined carefully when applications of wide temperature ranges are B
considered. It can severely affect the stability of a system at high temperature if not con- IB
sidered properly. Improvements in construction techniques have resulted in significantly – + – +
lower levels of ICO, to the point where its effect can often be ignored.
VEE VCC

3.4 COMMON-BASE CONFIGURATION

● E
IE IC
C
The notation and symbols used in conjunction with the transistor in the majority of texts
and manuals published today are indicated in Fig. 3.6 for the common-base configuration
with pnp and npn transistors. The common-base terminology is derived from the fact that
IB
the base is common to both the input and output sides of the configuration. In addition, the
base is usually the terminal closest to, or at, ground potential. Throughout this text all cur-
B
rent directions will refer to conventional (hole) flow rather than electron flow. The result is
that the arrows in all electronic symbols have a direction defined by this convention. Recall (b)
that the arrow in the diode symbol defined the direction of conduction for conventional
FIG. 3.6
current. For the transistor:
Notation and symbols used with the
The arrow in the graphic symbol defines the direction of emitter current (conventional common-base configuration: (a) pnp
flow) through the device. transistor; (b) npn transistor.
132 BIPOLAR JUNCTION All the current directions appearing in Fig. 3.6 are the actual directions as defined by the
TRANSISTORS choice of conventional flow. Note in each case that IE = IC + IB. Note also that the applied
biasing (voltage sources) are such as to establish current in the direction indicated for each
branch. That is, compare the direction of IE to the polarity of VEE for each configuration
and the direction of IC to the polarity of VCC.
To fully describe the behavior of a three-terminal device such as the common-base am-
plifiers of Fig. 3.6 requires two sets of characteristics—one for the driving point or input
parameters and the other for the output side. The input set for the common-base amplifier
as shown in Fig. 3.7 relates an input current (IE) to an input voltage (VBE) for various levels
of output voltage (VCB).

FIG. 3.7
Input or driving point characteristics for a
common-base silicon transistor amplifier.

The output set relates an output current (IC) to an output voltage (VCB) for various levels
of input current (IE) as shown in Fig. 3.8. The output or collector set of characteristics has
three basic regions of interest, as indicated in Fig. 3.8: the active, cutoff, and saturation

IC (mA)

Active region (unshaded area)

7 mA
7

6 mA
6

5 mA
5
Saturation region

4 mA
4

3 mA
3

2 mA
2

I E = 1 mA
1
ICO = ICBO
I E = 0 mA
0
−1 0 10 20 30 40 V CB (V)
Cutoff region BV CBO

FIG. 3.8
Output or collector characteristics for a common-base transistor amplifier.
regions. The active region is the region normally employed for linear (undistorted) ampli- COMMON-BASE 133
fiers. In particular: CONFIGURATION

In the active region the base–emitter junction is forward-biased, whereas the collector–
base junction is reverse-biased.
The active region is defined by the biasing arrangements of Fig. 3.6. At the lower end of
the active region the emitter current (IE) is zero, and the collector current is simply that due to
the reverse saturation current ICO, as indicated in Fig. 3.9. The current ICO is so small (micro-
amperes) in magnitude compared to the vertical scale of IC (milliamperes) that it appears on
virtually the same horizontal line as IC  0. The circuit conditions that exist when IE  0 for
the common-base configuration are shown in Fig. 3.9. The notation most frequently used FIG. 3.9
for ICO on data and specification sheets is, as indicated in Fig. 3.9, ICBO (the collector-to- Reverse saturation current.
base current with the emitter leg open). Because of improved construction techniques, the
level of ICBO for general-purpose transistors in the low- and mid-power ranges is usually
so low that its effect can be ignored. However, for higher power units ICBO will still appear
in the microampere range. In addition, keep in mind that ICBO, like Is, for the diode (both
reverse leakage currents) is temperature sensitive. At higher temperatures the effect of ICBO
may become an important factor since it increases so rapidly with temperature.
Note in Fig. 3.8 that as the emitter current increases above zero, the collector current
increases to a magnitude essentially equal to that of the emitter current as determined by
the basic transistor-current relations. Note also the almost negligible effect of VCB on the
collector current for the active region. The curves clearly indicate that a first approximation
to the relationship between IE and IC in the active region is given by

IC ⬵ IE (3.3)

As inferred by its name, the cutoff region is defined as that region where the collector
current is 0 A, as revealed on Fig. 3.8. In addition:
In the cutoff region the base–emitter and collector–base junctions of a transistor are
both reverse-biased.
The saturation region is defined as that region of the characteristics to the left of
VCB  0 V. The horizontal scale in this region was expanded to clearly show the dramatic
change in characteristics in this region. Note the exponential increase in collector current
as the voltage VCB increases toward 0 V.
In the saturation region the base–emitter and collector–base junctions are forward-biased.
The input characteristics of Fig. 3.7 reveal that for fixed values of collector voltage (VCB),
as the base-to-emitter voltage increases, the emitter current increases in a manner that closely
resembles the diode characteristics. In fact, increasing levels of VCB have such a small effect
on the characteristics that as a first approximation the change due to changes in VCB can be
ignored and the characteristics drawn as shown in Fig. 3.10a. If we then apply the piecewise-
linear approach, the characteristics of Fig. 3.10b result. Taking it a step further and ignoring
the slope of the curve and therefore the resistance associated with the forward-biased junction
results in the characteristics of Fig. 3.10c. For the analysis to follow in this book the equivalent
model of Fig. 3.10c will be employed for all dc analysis of transistor networks. That is, once a
transistor is in the “on” state, the base-to-emitter voltage will be assumed to be the following:

VBE ⬵ 0.7 V (3.4)

In other words, the effect of variations due to VCB and the slope of the input characteristics
will be ignored as we strive to analyze transistor networks in a manner that will provide a
good approximation to the actual response without getting too involved with parameter
variations of less importance.
It is important to fully appreciate the statement made by the characteristics of Fig. 3.10c.
They specify that with the transistor in the “on” or active state the voltage from base to
emitter will be 0.7 V at any level of emitter current as controlled by the external network.
In fact, at the first encounter of any transistor configuration in the dc mode, one can now
immediately specify that the voltage from base to emitter is 0.7 V if the device is in the
active region—a very important conclusion for the dc analysis to follow.
 I E (mA) I E (mA) I E (mA)

8 8 8

7 7 7
Any V CB
6 6 6

5 5 5

4 4 4

3 3 3

2 2 2

1 1 0.7 V 1 0.7 V

0 0.2 0.4 0.6 0.8 1 VBE (V) 0 0.2 0.4 0.6 0.8 1 VBE (V) 0 0.2 0.4 0.6 0.8 1 VBE (V)

(a) (b) (c)

FIG. 3.10
Developing the equivalent model to be employed for the base-to-emitter region of an amplifier in the dc mode.

EXAMPLE 3.1
a. Using the characteristics of Fig. 3.8, determine the resulting collector current if IE  3 mA
and VCB  10 V.
b. Using the characteristics of Fig. 3.8, determine the resulting collector current if IE
remains at 3 mA but VCB is reduced to 2 V.
c. Using the characteristics of Figs. 3.7 and 3.8, determine VBE if IC  4 mA and VCB  20 V.
d. Repeat part (c) using the characteristics of Figs. 3.8 and 3.10c.

Solution:
a. The characteristics clearly indicate that IC ⬵ IE = 3 mA.
b. The effect of changing VCB is negligible and IC continues to be 3 mA.
c. From Fig. 3.8, IE ⬵ IC = 4 mA. On Fig. 3.7 the resulting level of VBE is about 0.74 V.
d. Again from Fig. 3.8, IE ⬵ IC = 4 mA. However, on Fig. 3.10c, VBE is 0.7 V for any
level of emitter current.

Alpha (A)
DC Mode In the dc mode the levels of IC and IE due to the majority carriers are related by
a quantity called alpha and defined by the following equation:

IC
adc = (3.5)
IE

where IC and IE are the levels of current at the point of operation. Even though the charac-
teristics of Fig. 3.8 would suggest that a  1, for practical devices alpha typically extends
from 0.90 to 0.998, with most values approaching the high end of the range. Since alpha is
defined solely for the majority carriers, Eq. (3.2) becomes

IC = aIE + ICBO (3.6)

For the characteristics of Fig. 3.8 when IE  0 mA, IC is therefore equal to ICBO, but as
mentioned earlier, the level of ICBO is usually so small that it is virtually undetectable on
the graph of Fig. 3.8. In other words, when IE  0 mA on Fig. 3.8, IC also appears to be 0 mA
for the range of VCB values.
134
AC Mode For ac situations where the point of operation moves on the characteristic COMMON-BASE 135
curve, an ac alpha is defined by CONFIGURATION

IC
aac = ` (3.7)
IE VCB = constant

The ac alpha is formally called the common-base, short-circuit, amplification factor, for
reasons that will be more obvious when we examine transistor equivalent circuits in
Chapter 5. For the moment, recognize that Eq. (3.7) specifies that a relatively small change
in collector current is divided by the corresponding change in IE with the collector-to-base
voltage held constant. For most situations the magnitudes of aac and adc are quite close,
permitting the use of the magnitude of one for the other. The use of an equation such as
(3.7) will be demonstrated in Section 3.6.

Biasing
The proper biasing of the common-base configuration in the active region can be deter-
mined quickly using the approximation IC ⬵ IE and assuming for the moment that
IB ⬵ 0 mA. The result is the configuration of Fig. 3.11 for the pnp transistor. The arrow of
the symbol defines the direction of conventional flow for IE ⬵ IC. The dc supplies are
then inserted with a polarity that will support the resulting current direction. For the npn
transistor the polarities will be reversed.

+ – + –
VEE VCC

FIG. 3.11
Establishing the proper biasing
management for a common-base pnp
transistor in the active region.

Some students feel that they can remember whether the arrow of the device symbol is
pointing in or out by matching the letters of the transistor type with the appropriate letters
of the phrases “pointing in” or “not pointing in.” For instance, there is a match between
the letters npn and the italic letters of not pointing in and the letters pnp with pointing in.

Breakdown Region
As the applied voltage VCB increases there is a point where the curves take a dramatic
upswing in Fig. 3.8. This is due primarily to an avalanche effect similar to that described
for the diode in Chapter 1 when the reverse-bias voltage reached the breakdown region.
As stated earlier the base-to-collector junction is reversed biased in the active region, but
there is a point where too large a reverse-bias voltage will lead to the avalanche effect.
The result is a large increase in current for small increases in the base-to-collector
voltage. The largest permissible base-to-collector voltage is labeled BVCBO as shown
in Fig. 3.8. It is also referred to as V(BR)CBO as shown on the characteristics of Fig. 3.23 to
be discussed later. Note in each of the above notations the use of the uppercase letter O to
represent that the emitter leg is in the open state (not connected). It is important to remem-
ber when taking note of this data point that this limitation is only for the common-base
configuration. You will find in the common-emitter configuration that this limiting volt-
age is quite a bit less.
136 BIPOLAR JUNCTION 3.5 COMMON-EMITTER CONFIGURATION
TRANSISTORS ●
The most frequently encountered transistor configuration appears in Fig. 3.12 for the pnp
and npn transistors. It is called the common-emitter configuration because the emitter is
common to both the input and output terminals (in this case common to both the base and
collector terminals). Two sets of characteristics are again necessary to describe fully the
behavior of the common-emitter configuration: one for the input or base–emitter circuit
and one for the output or collector–emitter circuit. Both are shown in Fig. 3.13.

(a) (b)

FIG. 3.12
Notation and symbols used with the common-emitter configuration: (a) npn transistor;
(b) pnp transistor.

IC (mA)
8

90 μA
7 80 μA
70 μA I B (μA)
6 VCE = 1 V
60 μA VCE = 10 V
100
(Saturation region) 5 50 μA VCE = 20 V
90
40 μA 80
4 70
30 μA
60
3
(Active region) 50
20 μA
2 40
30
10 μA
1 20

I B = 0 μA 10

0 5 10 15 20 VCE (V) 0 0.2 0.4 0.6 0.8 1.0 VBE (V)

VCEsat
(Cutoff region)
~ β I CBO
I CEO =

(a) (b)

FIG. 3.13
Characteristics of a silicon transistor in the common-emitter configuration: (a) collector characteristics; (b) base characteristics.
 The emitter, collector, and base currents are shown in their actual conventional current COMMON-EMITTER 137
direction. Even though the transistor configuration has changed, the current relations devel- CONFIGURATION
oped earlier for the common-base configuration are still applicable. That is, IE = IC + IB
and IC = aIE.
For the common-emitter configuration the output characteristics are a plot of the output
current (IC) versus output voltage (VCE) for a range of values of input current (IB). The input
characteristics are a plot of the input current (IB) versus the input voltage (VBE) for a range
of values of output voltage (VCE).
Note that on the characteristics of Fig. 3.14 the magnitude of IB is in microamperes,
compared to milliamperes of IC. Consider also that the curves of IB are not as horizontal as
those obtained for IE in the common-base configuration, indicating that the collector-to-
emitter voltage will influence the magnitude of the collector current.
The active region for the common-emitter configuration is that portion of the upper-right
quadrant that has the greatest linearity, that is, that region in which the curves for IB are
nearly straight and equally spaced. In Fig. 3.14a this region exists to the right of the verti-
cal dashed line at VCEsat and above the curve for IB equal to zero. The region to the left of
VCEsat is called the saturation region.
In the active region of a common-emitter amplifier, the base–emitter junction is
forward-biased, whereas the collector–base junction is reverse-biased.
You will recall that these were the same conditions that existed in the active region of
the common-base configuration. The active region of the common-emitter configuration
can be employed for voltage, current, or power amplification.
The cutoff region for the common-emitter configuration is not as well defined as for the
common-base configuration. Note on the collector characteristics of Fig. 3.14 that IC is not
equal to zero when IB is zero. For the common-base configuration, when the input current
IE was equal to zero, the collector current was equal only to the reverse saturation current
ICO, so that the curve IE  0 and the voltage axis were, for all practical purposes, one.
The reason for this difference in collector characteristics can be derived through the
proper manipulation of Eqs. (3.3) and (3.6). That is,
Eq. (3.6): IC = aIE + ICBO
Substitution gives Eq. (3.3): IC = a(IC + IB) + ICBO
aIB ICBO
Rearranging yields IC = + (3.8)
1 - a 1 - a
If we consider the case discussed above, where IB  0 A, and substitute a typical value
of a such as 0.996, the resulting collector current is the following:
a(0 A) ICBO
IC = +
1 - a 1 - 0.996
ICBO
= = 250ICBO
0.004
If ICBO were 1 mA, the resulting collector current with IB  0 A would be 250(1 mA) 
0.25 mA, as reflected in the characteristics of Fig. 3.14.
For future reference, the collector current defined by the condition IB  0 mA will be
assigned the notation indicated by the following equation:

ICBO
ICEO = ` (3.9)
1 - a IB = 0 mA

In Fig. 3.13 the conditions surrounding this newly defined current are demonstrated with
its assigned reference direction.
For linear (least distortion) amplification purposes, cutoff for the common-emitter
configuration will be defined by IC  ICEO.
In other words, the region below IB  0 mA is to be avoided if an undistorted output
signal is required.
When employed as a switch in the logic circuitry of a computer, a transistor will have
two points of operation of interest: one in the cutoff and one in the saturation region. The
138 BIPOLAR JUNCTION I B (μA)
TRANSISTORS

100
90
80
70
60
50
40
30
20
10

0 0.2 0.4 0.6 0.8 1 V BE (V)

0.7 V

FIG. 3.14 FIG. 3.15

Circuit conditions related to ICEO. Piecewise-linear equivalent for the
diode characteristics of Fig. 3.13b.

cutoff condition should ideally be IC  0 mA for the chosen VCE voltage. Since ICEO is typi-
cally low in magnitude for silicon materials, cutoff will exist for switching purposes when
IB  0 mA or IC = ICEO for silicon transistors only. For germanium transistors, however,
cutoff for switching purposes will be defined as those conditions that exist when IC = ICBO.
This condition can normally be obtained for germanium transistors by reverse-biasing the
base-to-emitter junction a few tenths of a volt.
Recall for the common-base configuration that the input set of characteristics was ap-
proximated by a straight-line equivalent that resulted in VBE  0.7 V for any level of IE
greater than 0 mA. For the common-emitter configuration the same approach can be taken,
resulting in the approximate equivalent of Fig. 3.15. The result supports our earlier conclu-
sion that for a transistor in the “on” or active region the base-to-emitter voltage is 0.7 V. In
this case the voltage is fixed for any level of base current.

EXAMPLE 3.2
a. Using the characteristics of Fig. 3.13, determine IC at IB  30 mA and VCE  10 V.
b. Using the characteristics of Fig. 3.13, determine IC at VBE  0.7 V and VCE  15 V.

Solution:
a. At the intersection of IB  30 mA and VCE  10 V, IC  3.4 mA.
b. Using Fig. 3.13b, we obtain IB  20 mA at the intersection of VBE  0.7 V and VCE 
15 V (between VCE  10 V and 20 V). From Fig. 3.13a we find that IC  2.5 mA at the
intersection of IB  20 mA and VCE  15 V.

Beta (B)
DC Mode In the dc mode the levels of IC and IB are related by a quantity called beta and
defined by the following equation:

IC
bdc = (3.10)
IB

where IC and IB are determined at a particular operating point on the characteristics. For
practical devices the level of b typically ranges from about 50 to over 400, with most in the
midrange. As for a, the parameter b reveals the relative magnitude of one current with
respect to the other. For a device with a b of 200, the collector current is 200 times the
magnitude of the base current.
 On specification sheets bdc is usually included as hFE with the italic letter h derived from COMMON-EMITTER 139
an ac hybrid equivalent circuit to be introduced in Chapter 5. The subscript FE is derived CONFIGURATION
from forward-current amplification and common-emitter configuration, respectively.

AC Mode For ac situations an ac beta is defined as follows:

IC
bac = ` (3.11)
IB VCE = constant

The formal name for bac is common-emitter, forward-current, amplification factor. Since the
collector current is usually the output current for a common-emitter configuration and the base
current is the input current, the term amplification is included in the nomenclature above.
Equation (3.11) is similar in format to the equation for aac in Section 3.4. The procedure
for obtaining aac from the characteristic curves was not described because of the difficulty
of actually measuring changes of IC and IE on the characteristics. Equation (3.11), however,
can be described with some clarity, and, in fact, the result can be used to find aac using an
equation to be derived shortly.
On specification sheets bac is normally referred to as hfe. Note that the only difference
between the notation used for the dc beta, specifically, bdc = hFE, is the type of lettering
for each subscript quantity.
The use of Eq. (3.11) is best described by a numerical example using an actual set of
characteristics such as appearing in Fig. 3.13a and repeated in Fig. 3.17. Let us determine
bac for a region of the characteristics defined by an operating point of IB  25 mA and VCE
 7.5 V as indicated on Fig. 3.16. The restriction of VCE  constant requires that a vertical
line be drawn through the operating point at VCE  7.5 V. At any location on this vertical
line the voltage VCE is 7.5 V, a constant. The change in IB(IB) as appearing in Eq. (3.11)
is then defined by choosing two points on either side of the Q-point along the vertical axis
of about equal distances to either side of the Q-point. For this situation the IB  20 mA and
30 mA curves meet the requirement without extending too far from the Q-point. They also

I C (mA)
9

8 90 μA

80 μA
7
70 μA

6 60 μA

50 μA
5
40 μA
4
IC2 IB 2 30 μA

3 25 μA
Δ IC
Q - pt. 20 μA
IC1 2 IB1
10 μA
1

IB = 0 μA

0 5 10 15 20 25 VCE (V)
VCE = 7.5 V

FIG. 3.16
Determining bac and bdc from the collector characteristics.
140 BIPOLAR JUNCTION define levels of IB that are easily defined rather than require interpolation of the level of IB
TRANSISTORS between the curves. It should be mentioned that the best determination is usually made by
keeping the chosen IB as small as possible. At the two intersections of IB and the vertical axis,
the two levels of IC can be determined by drawing a horizontal line over to the vertical axis and
reading the resulting values of IC. The resulting bac for the region can then be determined by
IC IC2 - IC1
bac = ` =
IB VCE = constant IB2 - IB1
3.2 mA - 2.2 mA 1 mA
= =
30 mA - 20 mA 10 mA
= 100
The solution above reveals that for an ac input at the base, the collector current will be
about 100 times the magnitude of the base current.
If we determine the dc beta at the Q-point, we obtain
IC 2.7 mA
bdc = = = 108
IB 25 mA
Although not exactly equal, the levels of bac and bdc are usually reasonably close and
are often used interchangeably. That is, if bac is known, it is assumed to be about the same
magnitude as bdc, and vice versa. Keep in mind that in the same lot (large number of transis-
tors manufactured at the same time), the value of bac will vary somewhat from one transistor
to the next even though each transistor has the same number code. The variation may not
be significant, but for the majority of applications, it is certainly sufficient to validate the
approximate approach above. Generally, the smaller the level of ICEO, the closer are the
magnitudes of the two betas. Since the trend is toward lower and lower levels of ICEO,
the validity of the foregoing approximation is further substantiated.
If the characteristics of a transistor are approximated by those appearing in Fig. 3.17,
the level of bac would be the same in every region of the characteristics. Note that the step
in IB is fixed at 10 mA and the vertical spacing between curves is the same at every point in
the characteristics—namely, 2 mA. Calculating the bac at the Q-point indicated results in
IC 9 mA - 7 mA 2 mA
bac = ` = = = 200
IB VCE = constant 45 mA - 35 mA 10 mA

FIG. 3.17
Characteristics in which bac is the same everywhere and bac = bdc.

Determining the dc beta at the same Q-point results in

IC 8 mA
bdc = = = 200
IB 40 mA
revealing that if the characteristics have the appearance of Fig. 3.17, the magnitudes of bac and
bdc will be the same at every point on the characteristics. In particular, note that ICEO  0 mA.
 Although a true set of transistor characteristics will never have the exact appearance of COMMON-EMITTER 141
Fig. 3.17, it does provide a set of characteristics for comparison with those obtained from CONFIGURATION
a curve tracer (to be described shortly).
For the analysis to follow, the subscript dc or ac will not be included with b to avoid
cluttering the expressions with unnecessary labels. For dc situations it will simply be rec-
ognized as bdc and for any ac analysis as bac. If a value of b is specified for a particular
transistor configuration, it will normally be used for both the dc and ac calculations.
A relationship can be developed between b and a using the basic relationships in-
troduced thus far. Using b = IC >IB, we have IB = IC >b, and from a = IC >IE we have
IE = IC >a. Substituting into
IE = IC + IB
IC IC
we have = IC +
a b
and dividing both sides of the equation by IC results in
1 1
= 1 +
a b
or b = ab + a = (b + 1)a

b
so that a = (3.12)
b + 1

a
or b = (3.13)
1 - a

In addition, recall that

ICBO
ICEO =
1 - a
but using an equivalence of
1
= b + 1
1 - a
derived from the above, we find that
ICEO = (b + 1)ICBO

or ICEO ⬵ bICBO (3.14)

as indicated on Fig. 3.13a. Beta is a particularly important parameter because it provides a

direct link between current levels of the input and output circuits for a common-emitter
configuration. That is,

IC = bIB (3.15)

and since IE = IC + IB
= bIB + IB

we have IE = (b + 1)IB (3.16)

Both of the equations above play a major role in the analysis in Chapter 4.

Biasing
The proper biasing of a common-emitter amplifier can be determined in a manner similar
to that introduced for the common-base configuration. Let us assume that we are presented
with an npn transistor such as shown in Fig. 3.18a and asked to apply the proper biasing to
place the device in the active region.
 (a) (b) (c)

FIG. 3.18
Determining the proper biasing arrangement for a common-emitter npn transistor configuration.

The first step is to indicate the direction of IE as established by the arrow in the tran-
sistor symbol as shown in Fig. 3.18b. Next, the other currents are introduced as shown,
keeping in mind Kirchhoff’s current law relationship: IC + IB = IE. That is, IE is the sum
of IC and IB and both IC and IB must enter the transistor structure. Finally, the supplies are
introduced with polarities that will support the resulting directions of IB and IC as shown
in Fig. 3.18c to complete the picture. The same approach can be applied to pnp transistors.
If the transistor of Fig. 3.18 was a pnp transistor, all the currents and polarities of Fig.
3.18c would be reversed.

Breakdown Region
As with the common-base configuration, there is a maximum collector-emitter voltage that
can be applied and still remain in the active stable region of operation. In Fig. 3.19 the
characteristics of Fig. 3.8 have been extended to demonstrate the impact on the character-
istics at high levels of VCE. At high levels of base current the currents almost climb verti-
cally, whereas at lower levels a region develops that seems to back up on itself. This region
is particularly noteworthy because an increase in current is resulting in a drop in voltage—
totally different from that of any resistive element where an increase in current results in
an increase in potential drop across the resistor. Regions of this nature are said to have a

IC (mA)
8
90 μA

7 80 μA

70 μA
6
60 μA

5 50 μA

40 μA
4
30 μA
Negative
3 resistance
20 μA region –R
2
10 μA
1
I B = 0 μA

0 5 10 15 20 25 VCE
BVCEO

FIG. 3.19
Examining the breakdown region of a transistor in the common-emitter
configuration.
142
negative-resistance characteristic. Although the concept of a negative resistance may COMMON-COLLECTOR 143
seem strange at this point, this text will introduce devices and systems that rely on this type CONFIGURATION
of characteristic to perform their desired task.
The recommended maximum value for a transistor under normal operating conditions is
labeled BVCEO as shown in Fig. 3.19 or V(BR)CEO as shown in Fig. 3.23. It is less than BVCBO
and in fact, is often half the value of BVCBO. For this breakdown region there are two reasons
for the dramatic change in the curves. One is the avalanche breakdown mentioned for the
common-base configuration, whereas the other, called punch-through, is due to the Early
Effect, to be introduced in Chapter 5. In total the avalanche effect is dominant because any
increase in base current due to the breakdown phenomena will be increase the resulting
collector current by a factor beta. This increase in collector current will then contribute to
the ionization (generation of free carriers) process during breakdown, which will cause a
further increase in base current and even higher levels of collector current.

3.6 COMMON-COLLECTOR CONFIGURATION

●
The third and final transistor configuration is the common-collector configuration, shown
in Fig. 3.20 with the proper current directions and voltage notation. The common-collector
configuration is used primarily for impedance-matching purposes since it has a high input
impedance and low output impedance, opposite to that of the common-base and common-
emitter configurations.

IE
IE
E E
p n
IB + IB –
n V EE p V EE
B B
– + +
– p n
V BB V BB
+ C IC – C
IC

IE IE
E E

IB IB
B B

IC
IC

C C

(a) (b)

FIG. 3.20
Notation and symbols used with the common-collector configuration: (a) pnp transistor;
(b) npn transistor.
C
A common-collector circuit configuration is provided in Fig. 3.21 with the load resistor
connected from emitter to ground. Note that the collector is tied to ground even though the B
transistor is connected in a manner similar to the common-emitter configuration. From a
design viewpoint, there is no need for a set of common-collector characteristics to choose E
the parameters of the circuit of Fig. 3.21. It can be designed using the common-emitter
characteristics of Section 3.5. For all practical purposes, the output characteristics of the R
common-collector configuration are the same as for the common-emitter configuration. For
the common-collector configuration the output characteristics are a plot of IE versus VCE
for a range of values of IB. The input current, therefore, is the same for both the common- FIG. 3.21
emitter and common-collector characteristics. The horizontal voltage axis for the common- Common-collector configuration
collector configuration is obtained by simply changing the sign of the collector-to-emitter used for impedance-matching
voltage of the common-emitter characteristics. Finally, there is an almost unnoticeable purposes.
144 BIPOLAR JUNCTION change in the vertical scale of IC of the common-emitter characteristics if IC is replaced
TRANSISTORS by IE for the common-collector characteristics (since a ⬵ 1). For the input circuit of the
common-collector configuration the common-emitter base characteristics are sufficient for
obtaining the required information.

3.7 LIMITS OF OPERATION

●
For each transistor there is a region of operation on the characteristics that will ensure that
the maximum ratings are not being exceeded and the output signal exhibits minimum dis-
tortion. Such a region has been defined for the transistor characteristics of Fig. 3.22. All of
the limits of operation are defined on a typical transistor specification sheet described in
Section 3.8.
Some of the limits of operation are self-explanatory, such as maximum collector
current (normally referred to on the specification sheet as continuous collector current)
and maximum collector-to-emitter voltage (often abbreviated as BVCEO or V(BR)CEO on
the specification sheet). For the transistor of Fig. 3.22, ICmax was specified as 50 mA and
BVCEO as 20 V. The vertical line on the characteristics defined as VCEsat specifies the
minimum VCE that can be applied without falling into the nonlinear region labeled the
saturation region. The level of VCEsat is typically in the neighborhood of the 0.3 V speci-
fied for this transistor.
The maximum dissipation level is defined by the following equation:

PCmax = VCEIC (3.17)

BVCEO

FIG. 3.22
Defining the linear (undistorted) region of operation for a transistor.

For the device of Fig. 3.22, the collector power dissipation was specified as 300 mW.
The question then arises of how to plot the collector power dissipation curve specified by
the fact that
PCmax = VCE IC = 300 mW
or VCE IC = 300 mW
At ICmax At any point on the characteristics the product of VCE and IC must be equal to TRANSISTOR 145
300 mW. If we choose IC to be the maximum value of 50 mA and substitute into the rela- SPECIFICATION SHEET
tionship above, we obtain
VCE IC = 300 mW
VCE (50 mA) = 300 mW
300 mW
VCE = = 6V
50 mA

At VCEmax As a result we find that if IC  50 mA, then VCE  6 V on the power dissipa-
tion curve as indicated in Fig. 3.22. If we now choose VCE to be its maximum value of
20 V, the level of IC is the following:
(20 V)IC = 300 mW
300 mW
IC = = 15 mA
20 V
defining a second point on the power curve.

At IC ⴝ 12ICmax If we now choose a level of IC in the midrange such as 25 mA and solve

for the resulting level of VCE, we obtain
VCE (25 mA) = 300 mW
300 mW
and VCE = = 12 V
25 mA
as also indicated in Fig. 3.22.
A rough estimate of the actual curve can usually be drawn using the three points defined
above. Of course, the more points one has, the more accurate is the curve, but a rough es-
timate is normally all that is required.
The cutoff region is defined as that region below IC = ICEO. This region must also be
avoided if the output signal is to have minimum distortion. On some specification sheets
only ICBO is provided. One must then use the equation ICEO = bICBO to establish some
idea of the cutoff level if the characteristic curves are unavailable. Operation in the result-
ing region of Fig. 3.22 will ensure minimum distortion of the output signal and current and
voltage levels that will not damage the device.
If the characteristic curves are unavailable or do not appear on the specification sheet
(as is often the case), one must simply be sure that IC, VCE, and their product VCE IC fall
into the following range:

ICEO F IC F ICmax
VCEsat F VCE F VCEmax (3.18)
VCEIC F PCmax

For the common-base characteristics the maximum power curve is defined by the following
product of output quantities:

PCmax = VCBIC (3.19)

3.8 TRANSISTOR SPECIFICATION SHEET

●
Since the specification sheet is the communication link between the manufacturer and
user, it is particularly important that the information provided be recognized and correctly
understood. Although all the parameters have not been introduced, a broad number will
now be familiar. The remaining parameters will be introduced in the chapters that follow.
Reference will then be made to this specification sheet to review the manner in which the
parameter is presented.
The information provided as Fig. 3.23 is provided by the Fairchild Semiconductor
Corporation. The 2N4123 is a general-purpose npn transistor with the casing and terminal
146 BIPOLAR JUNCTION identification appearing in the top-right corner of Fig. 3.23a. Most specification sheets are
TRANSISTORS broken down into maximum ratings, thermal characteristics, and electrical characteristics.
The electrical characteristics are further broken down into “on,” “off,” and small-signal
characteristics. The “on” and “off” characteristics refer to dc limits, whereas the small-
signal characteristics include the parameters of importance to ac operation.
Note in the maximum rating list that VCEmax = VCEO = 30 V with ICmax = 200 mA.
The maximum collector dissipation PCmax = PD = 625 mW. The derating factor under
the maximum rating specifies that the maximum rating must be decreased 5 mW for every
1° rise in temperature above 25°C. In the “off” characteristics ICBO is specified as 50 nA

MAXIMUM RATINGS
Rating Symbol 2N4123 Unit
Collector-Emitter Voltage VCEO 30 Vdc FAIRCHILD
Collector-Base Voltage VCBO 40 Vdc SEMICONDUCTOR TM

Emitter-Base Voltage VEBO 5.0 Vdc

Collector Current – Continuous IC 200 mAdc 2N4123
Total Device Dissipation @ TA = 25˚C PD 625 mW
Derate above 25˚C 5.0 mW˚C
Operating and Storage Junction Tj,Tstg –55 to +150 ˚C
Temperature Range
C TO-92
THERMAL CHARACTERISTICS BE
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 83.3 ˚C W
General Purpose
Thermal Resistance, Junction to Ambient RθJA 200 ˚C W
Transistor
NPN Silicon
ELECTRICAL CHARACTERISTICS (TA = 25˚C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector-Emitter Breakdown Voltage (1) V(BR)CEO 30 Vdc
(IC = 1.0 mAdc, IE = 0)
Collector-Base Breakdown Voltage V(BR)CBO 40 Vdc
(IC = 10 μAdc, IE = 0)
Emitter-Base Breakdown Voltage V(BR)EBO 5.0 – Vdc
(IE = 10 μAdc, IC = 0)
Collector Cutoff Current ICBO – 50 nAdc
(VCB = 20 Vdc, IE = 0)
Emitter Cutoff Current IEBO – 50 nAdc
(VBE = 3.0 Vdc, IC = 0)
ON CHARACTERISTICS
DC Current Gain(1)
(IC = 2.0 mAdc, VCE = 1.0 Vdc) hFE 50 150 –
(IC = 50 mAdc, VCE = 1.0 Vdc) 25 –
Collector-Emitter Saturation Voltage(1) VCE(sat) – 0.3 Vdc
(IC = 50 mAdc, IB = 5.0 mAdc)
Base-Emitter Saturation Voltage(1) VBE(sat) – 0.95 Vdc
(IC = 50 mAdc, IB = 5.0 mAdc)
SMALL-SIGNAL CHARACTERISTICS
Current-Gain – Bandwidth Product fT 250 MHz
(IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz)
Output Capacitance Cobo – 4.0 pF
(VCB = 5.0 Vdc, IE = 0, f = 100 MHz)
Input Capacitance Cibo – 8.0 pF
(VBE = 0.5 Vdc, IC = 0, f = 100 kHz)
Collector-Base Capacitance Ccb – 4.0 pF
(IE = 0, VCB = 5.0 V, f = 100 kHz)
Small-Signal Current Gain hfe 50 200 –
(IC = 2.0 mAdc, VCE = 10 Vdc, f = 1.0 kHz)
Current Gain – High Frequency
(IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz) hfe 2.5 – –
(IC = 2.0 mAdc, VCE = 10 V, f = 1.0 kHz) 50 200
Noise Figure NF – 6.0 dB
(IC = 100 μAdc, VCE = 5.0 Vdc, RS = 1.0 k ohm, f = 1.0 kHz)
(1) Pulse Test: Pulse Width = 300 μs. Duty Cycle = 2.0%

(a)

FIG. 3.23
Transistor specification sheet.
 h PARAMETERS
VCE = 10 V, f = 1 kHz, TA = 25°C
Figure 1 – Current Gain Figure 3 – Capacitance
10
300
7.0
200
5.0

Capacitance (pF)
C ibo
h fe Current gain

100 3.0

70 Cobo
2.0
50

30 1.0
0.1 0.2 0.5 1.0 2.0 5.0 10 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 40
I C , Collector current (mA) Reverse bias voltage (V)
(b) (d)

STATIC CHARACTERISTICS
Figure 2 – DC Current Gain
2.0
TJ = +125° C VCE = 1 V
h FE DC Current gain (normalized)

1.0 +25° C

0.7
0.5 –55° C

0.3

0.2

0.1
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200
I C , Collector current (mA)
(c)

AUDIO SMALL SIGNAL CHARACTERISTICS

NOISE FIGURE
(VCE = 5 Vdc, TA = 25°C)
Bandwidth = 1.0 Hz

Figure 5 – Frequency Variations

12
Figure 4 – Switching Times
200
10 Source resistance = 200 Ω
ts IC = 1 mA
100 Source resistance = 200 Ω
NF, Noise figure (dB)

8
70 IC = 0.5 mA
50 Source resistance = 1 k Ω
Time (ns)

6
td IC = 50 μ A
30
tr
20 tf 4
VCC = 3 V
10.0 IC / IB = 10 2
7.0 VEB (off) = 0.5 V Source resistance = 500 Ω
IC = 100 μA
5.0 0
1.0 2.0 3.0 5.0 10 20 30 50 100 200 0.1 0.2 0.4 1 2 4 10 20 40 100
I C , Collector current (mA) f, Frequency (kHz)

(e) (f)

FIG. 3.23
Continued.
 Figure 6 – Source Resistance
14
f = 1 kHz
Figure 7 – Input Impedance
12
20
IC = 1 mA
10
NF, Noise figure (dB)

10

h ie Input impedance (kΩ)

IC = 0.5 mA
8 5.0

IC = 50 μA
6 2.0

4 1.0
IC = 100 μA

2 0.5

0 0.2
0.1 0.2 0.4 1.0 2.0 4.0 10 20 40 100 0.1 0.2 0.5 1.0 2.0 5.0 10
RS , Source resistance (k Ω) I C , Collector current (mA)

(g) (h)

Figure 8 – Voltage Feedback Ratio Figure 9 – Output Admittance

10 100
hre Voltage feedback ratio (× 10−4 )

h oe Output admittance (μ mhos)

7.0 50

5.0
20
3.0
10
2.0
5.0
1.0
0.7 2.0
0.5 1.0
0.1 0.2 0.5 1.0 2.0 5.0 10 0.1 0.2 0.5 1.0 2.0 5.0 10
I C , Collector current (mA) I C , Collector current (mA)
(i) (j)

FIG. 3.23
Continued.

and in the “on” characteristics VCEsat = 0.3 V. The level of hFE has a range of 50 to 150 at
IC  2 mA and VCE  1 V and a minimum value of 25 at a higher current of 50 mA at the
same voltage.
The limits of operation have now been defined for the device and are repeated below
in the format of Eq. (3.18) using hFE = 150 (the upper limit) and ICEO ⬵ bICBO = (150)
(50 nA) = 7.5 mA. Certainly, for many applications the 7.5 mA  0.0075 mA can be con-
sidered to be 0 mA on an approximate basis.

Limits of Operation
7.5 mA F IC F 200 mA
0.3 V F VCE F 30 V
VCE IC F 650 mW

B Variation
In the small-signal characteristics the level of hfe (bac) is provided along with a plot of how
it varies with collector current in Fig. 3.23b. In Fig. 3.23c the effect of temperature and
collector current on the level of hFE (bdc) is demonstrated. At room temperature (25°C),
note that hFE (bdc) is a maximum value of 1 in the neighborhood of about 8 mA. As IC
increases beyond this level, hFE drops off to one-half the value with IC equal to 50 mA. It
also drops to this level if IC decreases to the low level of 0.15 mA. Since this is a normalized
148
curve, if we have a transistor with bdc = hFE = 120 at room temperature (25°C), the TRANSISTOR TESTING 149
maximum value at 8 mA is 120. At IC  50 mA it has dropped to about 0.52 and hfe 
(0.52)120  62.4. In other words, normalizing reveals that the actual level of hFE at any
level of IC has been divided by the maximum value of hFE at that temperature and
IC  8 mA. Note also that the horizontal scale of Fig. 3.23(c) is a log scale. Log scales are
examined in depth in Chapter 9. You may want to look back at the plots of this section
when you find time to review the first few sections of Chapter 9.

Capacitance Variation The capacitance Cibo and Cobo of Fig. 3.23(d) are the input and
output capacitance levels, respectively, for the transistor in the common-base configura-
tion. Their level is such that their impact can be ignored except for relatively high frequen-
cies. Otherwise, they can be approximated by open circuits in any dc or ac analysis.

Switching Times Figure 3.23(e) includes the important parameters that define the
response of a transistor to an input that switches from the “off” to “on” state or vice versa.
Each parameter will be discussed in detail in Section 4.15.

Noise Figures Versus Frequency and Source Resistance The noise figure is a measure of
the additional disturbance that is added to the desired signal response of an amplifier. In
Fig. 3.23(f) the dB level of the noise figure is displayed for a wide frequency response at
particular levels of source resistance. The lowest levels occur at the highest frequencies for
the variety of collector currents and source resistance. As the frequency drops the noise
figure increases with a strong sensitivity to the collector current.
In Fig. 3.23(g) the noise figure is plotted for various levels of source resistance and
collector current. For each current level the higher the source resistance, the higher the
noise figure.

Hybrid Parameters Figures 3.23(b), (h), (i), and (j) provide the components of a hybrid
equivalent model for the transistor that will be discussed in detail in Chapter 5. In each case,
note that the variation is plotted against the collector current—a defining level for the equiv-
alent network. For most applications the most important parameters are hfe and hie. The
higher the collector current, the higher the magnitude of hfe and the lower the level of hie. As
indicated above, all the parameters will be discussed in detail in Sections 5.19–5.21.
Before leaving this description of the characteristics, note that the actual collector char-
acteristics are not provided. In fact, most specification sheets provided by manufacturers
fail to provide the full characteristics. It is expected that the data provided are sufficient to
use the device effectively in the design process.

3.9 TRANSISTOR TESTING

●
As with diodes, there are three routes one can take to check a transistor: use of a curve
tracer, a digital meter, and an ohmmeter.

Curve Tracer
The curve tracer of Fig. 1.43 will provide the display of Fig. 3.24 once all the controls have
been properly set. The smaller displays to the right reveal the scaling to be applied to the
characteristics. The vertical sensitivity is 2 mA/div, resulting in the scale shown to the left
of the monitor’s display. The horizontal sensitivity is 1 V/div, resulting in the scale shown
below the characteristics. The step function reveals that the curves are separated by a dif-
ference of 10 mA, starting at 0 mA for the bottom curve. The last scale factor provided can
be used to quickly determine the bac for any region of the characteristics. Simply multiply
the displayed factor by the number of divisions between IB curves in the region of interest.
For instance, let us determine bac at a Q-point of IC  7 mA and VCE  5 V. In this region
9
of the display, the distance between IB curves is 10 of a division, as indicated on Fig. 3.25.
Using the factor specified, we find that
9 200
bac = div a b = 180
10 div
150 BIPOLAR JUNCTION 20 mA
TRANSISTORS
18 mA Vertical
80 μA per div
2 mA
16 mA
70 μA
14 mA
60 μA Horizontal
per div
12 mA 1V
50 μA
10 mA
40 μA
8 mA Per Step
30 μA 10 μ A
6 mA
20 μA
4 mA B or gm
10 μA per div
2 mA 200
0 μA
0 mA
0V 1V 2V 3V 4V 5V 6V 7V 8V 9V 10 V

FIG. 3.24
Curve tracer response to 2N3904 npn transistor.

IC = 8 mA IB 2 = 40 μA
IC 2 = 8.2 mA

Δ IC ≅ 10
9 div Q-point
( IC = 7 m A, VCE = 5 V)
IB 1 = 30 μA
IC 1 = 6.4 mA

Transistor IC = 6 mA VCE = 5 V
test
FIG. 3.25
Determining bac for the transistor characteristics of Fig. 3.24 at IC  7 mA
and VCE  5 V.

(a)
Using Eq. (3.11) gives
IC IC1 - IC1 8.2 mA - 6.4 mA
bac = ` = =
IB VCE = constant IB2 - IB1 40 mA - 30 mA
Transistor 1.8 mA
= = 180
JFET 10 mA
SCR verifying the determination above.

Transistor Testers
There is a variety of transistor testers available. Some are simply part of a digital meter as
shown in Fig. 3.26a that can measure a variety of levels in a network. Others, such as that
in Fig. 3.26, are dedicated to testing a limited number of elements. The meter of Fig. 3.26b
can be used to test transistors, JFETs (Chapter 6), and SCRs (Chapter 17) in and out of the
circuit. In all cases the power must first be turned off to the circuit in which the element
appears to ensure that the internal battery of the tester is not damaged and to provide a cor-
(b)
rect reading. Once a transistor is connected, the switch can be moved through all the pos-
FIG. 3.26 sible combinations until the test light comes on and identifies the terminals of the transistor.
Transistor testers: (a) digital meter; The tester will also indicate an OK if the npn or pnp transistor is operating properly.
(b) dedicated tester. (Courtesy of Any meter with a diode-checking capability can also be used to check the status of a
B+K Precision Corporation.) transistor. With the collector open the base-to-emitter junction should result in a low voltage
of about 0.7 V with the red (positive) lead connected to the base and the black (negative) TRANSISTOR CASING 151
lead connected to the emitter. A reversal of the leads should result in an OL indication to AND TERMINAL
IDENTIFICATION
represent the reverse-biased junction. Similarly, with the emitter open, the forward- and
reverse-bias states of the base-to-collector junction can be checked.
Low R
Open
Ohmmeter
Ω
B
An ohmmeter or the resistance scales of a digital multimeter (DMM) can be used to check + –
the state of a transistor. Recall that for a transistor in the active region the base-to-emitter
junction is forward-biased and the base-to-collector junction is reverse-biased. Essentially, E
therefore, the forward-biased junction should register a relatively low resistance, whereas
the reverse-biased junction shows a much higher resistance. For an npn transistor, the FIG. 3.27
Checking the forward-biased base-to-
forward-biased junction (biased by the internal supply in the resistance mode) from base to
emitter junction of an npn transistor.
emitter should be checked as shown in Fig. 3.27 and result in a reading that will typically
fall in the range of 100  to a few kilohms. The reverse-biased base-to-collector junction
High R
(again reverse-biased by the internal supply) should be checked as shown in Fig. 3.28 with
a reading typically exceeding 100 k. For a pnp transistor the leads are reversed for each
Ω
junction. Obviously, a large or small resistance in both directions (reversing the leads) for + – C
either junction of an npn or pnp transistor indicates a faulty device.
If both junctions of a transistor result in the expected readings, the type of transistor can
also be determined by simply noting the polarity of the leads as applied to the base-emitter B
junction. If the positive (+) lead is connected to the base and the negative lead (−) to the
emitter, a low resistance reading would indicate an npn transistor. A high resistance reading E
would indicate a pnp transistor. Although an ohmmeter can also be used to determine the FIG. 3.28
leads (base, collector, and emitter) of a transistor, it is assumed that this determination can Checking the reverse-biased
be made by simply looking at the orientation of the leads on the casing. base-to-collector junction of an npn
transistor.

3.10 TRANSISTOR CASING AND

TERMINAL IDENTIFICATION
●
After the transistor has been manufactured using one of the techniques described in Appen-
dix A, leads of, typically, gold, aluminum, or nickel are then attached and the entire struc-
ture is encapsulated in a container such as that shown in Fig. 3.29. Those with the
heavy-duty construction are high-power devices, whereas those with the small can (top
hat) or plastic body are low- to medium-power devices.

(a) (b) (c)

FIG. 3.29
Various types of general-purpose or switching transistors: (a) low power; (b) medium power;
(c) medium to high power.

Whenever possible, the transistor casing will have some marking to indicate which leads
are connected to the emitter, collector, or base of a transistor. A few of the methods com-
monly used are indicated in Fig. 3.30.
The internal construction of a TO-92 package in the Fairchild line appears in Fig. 3.31.
Note the very small size of the actual semiconductor device. There are gold bond wires, a
copper frame, and an epoxy encapsulation.
152 BIPOLAR JUNCTION E B C
White
TRANSISTORS dot

C C (case) C
E C
B E B
B
E B E C EB C E

FIG. 3.30
Transistor terminal identification.

Axial molding
compound injection
Passivated die
Epoxy package
Copper frame
Locking tabs

(a) (b) (c)

FIG. 3.31
Internal construction of a Fairchild transistor in a TO-92 package.

Four (quad) individual pnp silicon transistors can be housed in the 14-pin plastic dual-in-
line package appearing in Fig. 3.32a. The internal pin connections appear in Fig. 3.32b. As
with the diode IC package, the indentation in the top surface reveals the number 1 and 14 pins.

(Top View)
C B C NC E B C
14 13 12 11 10 9 8

1 2 3 4 5 6 7
C B E NC E B C
NC – No internal connection
(a) (b)
FIG. 3.32
Type Q2T2905 Texas Instruments quad pnp silicon transistor:
(a) appearance; (b) pin connections.

3.11 TRANSISTOR DEVELOPMENT

●
As mentioned in Section 1.1, Moore’s law predicts that the transistor count of an inte-
grated circuit will double every 2 years. First presented in a paper by Gordon E. Moore in
1965, the prediction has had an amazing accuracy level. A plot of the transistor count ver-
sus years appearing in Fig. 3.33 is almost linear through the years. The amazing number of
two billion transistors in a single integrated circuit using 45 nm lines is really beyond com-
prehension. A 1 in. line contains more than 564,000 of the 45 nm lines of construction used
in ICs today. Try to draw 100 lines in a 1 in. width using a pencil—almost impossible. The
relative dimensions of drawing 45 nm lines in a 1 in. width would be like drawing a line
 Transistor count TRANSISTOR 153
DEVELOPMENT
10,000,000,000
Xeon Nehalem-Ex Intel
2 billion level Tukwila Intel
Dual-Core Itanium 2 Power 7
1,000,000,000 IBM Power 6 Opteron 2400 AMD
Core i7 Intel
Itanium 2 Core 2 Duo Intel
100 million level
100,000,000
Pentium IV

10,000,000 Pentium III

Pentium II
Intel 804861 Pentium
1 million level
1,000,000
Intel 80386
Intel 80286
100,000
Moore’s prediction
Log scale 10,000 level
10,000
RCA 1802
Intel 8085
Intel 8004
Motorola 6800
Intel 4004
1000

100 level
100

10
Moore’s paper presented

1
1960 1965 1970 1980 1990 2000 2010 Year
Linear scale

FIG. 3.33
Transistor IC count versus time for the period 1960 to the present.

with a width of 1 in. across a highway that is almost 9 miles long.* Although there is con-
tinuing talk that Moore’s law will eventually suffer from density, performance, reliability,
and budget corners, the general consensus of the industrial community is that Moore’s law
will continue to be applicable for the next decade or two. Although silicon continues to be
the leading fabrication material, there is a family of semiconductors referred to as III V
compound semiconductors (the three and five referring to the number of valence elec-
trons in each element) that are making important inroads into future development. One in
particular is indium gallium arsenide, or InGaAs, which has improved transport character-
istics. Others include GaAlAs, AlGaN, and AllnN, which are all being developed for
increased speed, reliability, stability, reduced size, and improved fabrication techniques.
Currently the Intel® CoreTM i7 Quad Core processor has over 730 million transistors
with a clock speed of 3.33 GHz in a package slightly larger than a 1.6 square. Recent
developments by Intel include their Tukwila processor that will house over two billion
transistors. Interestingly enough, Intel continues to employ silicon in its research develop-
ment of transistors that will be 30% smaller and 25% faster than today’s fastest transistors
using 20 nm technology. IBM, in concert with the Georgia Institute of Technology, has
developed a silicon-germanium transistor that can operate at frequencies exceeding 500
GHz—an enormous increase over current standards.
Innovation continues to be the backbone of this ever-developing field, with one Swedish
team introducing a junctionless transistor primarily to simplify the manufacturing process.
Another has introduced carbon nanotubes (a carbon molecule in the form of a hollow
cylinder that has a diameter about 1兾50,000 the width of a human hair) as a path toward
faster, smaller, and cheaper transistors. Hewlett Packard is developing a Crossbar Latch
transistor that employs a grid of parallel conducting and signal wires to create junctions
that act as switches.
The question was often asked many years ago: Where can the field go from here? Obvi-
ously, based on what we see today, there seems to be no limit to the innovative spirit of
individuals in the field as they search for new directions of investigation.

*In metric units, it would be like drawing more than 220,000 lines in a 1-cm length or a 1-cm width line across
a highway over 2.2 km long.
154 BIPOLAR JUNCTION 3.12 SUMMARY
TRANSISTORS ●
Important Conclusions and Concepts
1. Semiconductor devices have the following advantages over vacuum tubes: They are
(1) of smaller size, (2) more lightweight, (3) more rugged, and (4) more efficient. In
addition, they have (1) no warm-up period, (2) no heater requirement, and (3) lower
operating voltages.
2. Transistors are three-terminal devices of three semiconductor layers having a base or
center layer a great deal thinner than the other two layers. The outer two layers are
both of either n- or p-type materials, with the sandwiched layer the opposite type.
3. One p–n junction of a transistor is forward-biased, whereas the other is reverse-
biased.
4. The dc emitter current is always the largest current of a transistor, whereas the base
current is always the smallest. The emitter current is always the sum of the other two.
5. The collector current is made up of two components: the majority component and
the minority current (also called the leakage current).
6. The arrow in the transistor symbol defines the direction of conventional current flow
for the emitter current and thereby defines the direction for the other currents of the
device.
7. A three-terminal device needs two sets of characteristics to completely define its
characteristics.
8. In the active region of a transistor, the base–emitter junction is forward-biased,
whereas the collector–base junction is reverse-biased.
9. In the cutoff region the base–emitter and collector–base junctions of a transistor are
both reverse-biased.
10. In the saturation region the base–emitter and collector–base junctions are forward-
biased.
11. On an average basis, as a first approximation, the base-to-emitter voltage of an operat-
ing transistor can be assumed to be 0.7 V.
12. The quantity alpha (a) relates the collector and emitter currents and is always close to
one.
13. The impedance between terminals of a forward-biased junction is always relatively
small, whereas the impedance between terminals of a reverse-biased junction is usu-
ally quite large.
14. The arrow in the symbol of an npn transistor points out of the device (not pointing
in), whereas the arrow points in to the center of the symbol for a pnp transistor
(pointing in).
15. For linear amplification purposes, cutoff for the common-emitter configuration will
be defined by IC = ICEO.
16. The quantity beta (b) provides an important relationship between the base and collec-
tor currents, and is usually between 50 and 400.
17. The dc beta is defined by a simple ratio of dc currents at an operating point,
whereas the ac beta is sensitive to the characteristics in the region of interest. For
most applications, however, the two are considered equivalent as a first approximation.
18. To ensure that a transistor is operating within its maximum power level rating, simply
find the product of the collector-to-emitter voltage and the collector current, and
compare it to the rated value.

Equations
IE = IC + IB, IC = ICmajority + ICOminority, VBE ⬵ 0.7 V
IC IC ICBO
adc = , aac = ` , ICEO = `
IE IE VCB = constant 1 - a IB = 0 mA
IC IC b
bdc = , bac = ` , a =
IB IB VCE = constant b + 1
IC = bIB, IE = (b + 1)IB, PCmax = VCEIC
3.13 COMPUTER ANALYSIS COMPUTER ANALYSIS 155
●
Cadence OrCAD
Since the transistor characteristics were introduced in this chapter, it seems appropriate
that a procedure for obtaining those characteristics using PSpice Windows should be exam-
ined. The transistors are listed in the EVAL library and start with the letter Q. The library
includes two npn transistors, two pnp transistors, and two Darlington configurations. The
fact that there is a series of curves defined by the levels of IB will require that a sweep of IB
values (a nested sweep) occur within a sweep of collector-to-emitter voltages. This is
unnecessary for the diode, however, since only one curve would result.
First, the network in Fig. 3.34 is established using the same procedure as defined in
Chapter 2. The voltage VCC will establish our main sweep, whereas the voltage VBB will
determine the nested sweep. For future reference, note the panel at the top right of the menu
bar with the scroll control when building networks. This option allows you to retrieve ele-
ments that have been used in the past. For instance, if you placed a resistor a few elements
ago, simply return to the scroll bar and scroll until the resistor R appears. Click the location
once, and the resistor will appear on the screen.

FIG. 3.34
Network employed to obtain the collector
characteristics of the Q2N2222 transistor.

Once the network is established as appearing in Fig. 3.34, select the New Simulation
Profile key and insert OrCAD 3-1 as the Name. Then select Create to obtain the Simula-
tion Settings dialog box. The Analysis type will be DC Sweep, with the Sweep variable
being a Voltage Source. Insert VCC as the name for the swept voltage source and select
Linear for the sweep. The Start value is 0 V, the End value 10 V, and the Increment 0.01 V.
It is important not to select x in the top right corner of the box to leave the settings
control. We must first enter the nested sweep variable by selecting Secondary Sweep and
inserting VBB as the voltage source to be swept. Again, it will be a Linear sweep, but now
the starting value will be 2.7 V to correspond with an initial current of 20 mA as determined by
VBB - VBE 2.7 V - 0.7 V
IB = = = 20 mA
RB 100 k
The End value is 10.7 V to correspond with a current of 100 mA. The Increment is set
at 2 V, corresponding to a change in base current of 20 mA. Both sweeps are now set, but
before leaving the dialog box be sure both sweeps are enabled by a check in the box
next to each sweep. Often after entering the second sweep, the user fails to establish the
second sweep before leaving the dialog box. Once both are selected, leave the dialog box
and select Run PSpice. The result will be a graph with a voltage VCC varying from 0 V
156 BIPOLAR JUNCTION
TRANSISTORS

IC IB = 100 ␮A

IB = 80 ␮A

IB = 60 ␮A

IB = 40 ␮A

IB = 20 ␮A

VCE

FIG. 3.35
Collector characteristics for the transistor of Fig. 3.34.

to 10 V. To establish the various I curves, apply the sequence Trace-Add Trace to obtain
the Add Trace dialog box. Select IC(Q1), the collector current of the transistor for the
vertical axis. An OK, and the characteristics will appear. Unfortunately, however, they
extend from −10 mA to +20 mA on the vertical axis. This can be corrected by the sequence
Plot-Axis Settings, which again will result in the Axis Settings dialog box. Select Y-Axis
and under Data Range choose User Defined and set the range as 0–20 mA. An OK, and
the plot of Fig. 3.35 will appear. Labels on the plot can be added using the production ver-
sion of OrCAD.
The first curve at the bottom of Fig. 3.35 represents IB  20 mA. The curve above is IB 
40 mA, the next 60 mA, and so on. If we choose a point in the middle of the characteristics
defined by VCE  4 V and IB  60 mA as shown in Fig. 3.35 b can be determined from
IC 11 mA
b = = = 183.3
IB 60 mA
Like the diode, the other parameters of the device will have a noticeable effect on the oper-
ating conditions. If we return to the transistor specifications using Edit-PSpice Model to
obtain the PSpice Model Editor Demo dialog box, we can delete all the parameters except
the Bf value. Be sure to leave the parentheses surrounding the value of Bf during the dele-
tion process. When you exit the box the Model Editor/16.3 dialog box will appear asking
you to save changes. It was saved as OrCAD 3-1 and the circuit was simulated again to
obtain the characteristics of Fig. 3.36 following another adjustment of the range of the
vertical axis.
Note first that the curves are all horizontal, meaning the element is void of any resistive
characteristics. In addition, the equal spacing of the curves throughout reveals that beta is the
same everywhere. At the intersection of VCE  4 V and IB  60 mA, the new value of b is
IC 14.6 mA
b = = = 243.3
IB 60 mA
The real value of the above analysis is to recognize that even though beta may be provided,
the actual performance of the device will be very dependent on its other parameters.
Assume an ideal device is always a good starting point, but an actual network provides a
different set of results.
 PROBLEMS 157

IB = 80 ␮A
IC

IB = 60 ␮A

IB = 40 ␮A

IB = 20 ␮A

VCE

FIG. 3.36
Ideal collector characteristics for the transistor of Fig. 3.34.

PROBLEMS
●
*Note: Asterisks indicate more difficult problems.
3.2 Transistor Construction
1. What names are applied to the two types of BJT transistors? Sketch the basic construction of
each and label the various minority and majority carriers in each. Draw the graphic symbol next
to each. Is any of this information altered by changing from a silicon to a germanium base?
2. What is the major difference between a bipolar and a unipolar device?

3.3 Transistor Operation

3. How must the two transistor junctions be biased for proper transistor amplifier operation?
4. What is the source of the leakage current in a transistor?
5. Sketch a figure similar to Fig. 3.4a for the forward-biased junction of an npn transistor.
Describe the resulting carrier motion.
6. Sketch a figure similar to Fig. 3.4b for the reverse-biased junction of an npn transistor. Describe
the resulting carrier motion.
7. Sketch a figure similar to Fig. 3.5 for the majority- and minority-carrier flow of an npn transis-
tor. Describe the resulting carrier motion.
8. Which of the transistor currents is always the largest? Which is always the smallest? Which
two currents are relatively close in magnitude?
9. If the emitter current of a transistor is 8 mA and IB is 1兾100 of IC, determine the levels of IC and IB.
3.4 Common-Base Configuration
10. From memory, sketch the transistor symbol for a pnp and an npn transistor, and then insert the
conventional flow direction for each current.
11. Using the characteristics of Fig. 3.7, determine VBE at IE  5 mA for VCB  1, 10, and 20 V. Is
it reasonable to assume on an approximate basis that VCB has only a slight effect on the rela-
tionship between VBE and IE?
158 BIPOLAR JUNCTION 12. a. Determine the average ac resistance for the characteristics of Fig. 3.10b.
TRANSISTORS b. For networks in which the magnitude of the resistive elements is typically in kilohms, is the
approximation of Fig. 3.10c a valid one [based on the results of part (a)]?
13. a. Using the characteristics of Fig. 3.8, determine the resulting collector current if IE  3.5 mA
and VCB  10 V.
b. Repeat part (a) for IE  3.5 mA and VCB  20 V.
c. How have the changes in VCB affected the resulting level of IC?
d. On an approximate basis, how are IE and IC related based on the results above?
14. a. Using the characteristics of Figs. 3.7 and 3.8, determine IC if VCB = 5 V and VBE  0.7 V.
b. Determine VBE if IC  5 mA and VCB  15 V.
c. Repeat part (b) using the characteristics of Fig. 3.10b.
d. Repeat part (b) using the characteristics of Fig. 3.10c.
e. Compare the solutions for VBE for parts (b) through (d). Can the difference be ignored if
voltage levels greater than a few volts are typically encountered?
15. a. Given an adc of 0.998, determine IC if IE  4 mA.
b. Determine adc if IE  2.8 mA, IC  2.75 mA and ICBO  0.1 mA.
16. From memory only, sketch the common-base BJT transistor configuration (for npn and pnp)
and indicate the polarity of the applied bias and resulting current directions.

3.5 Common-Emitter Configuration

17. Define ICBO and ICEO. How are they different? How are they related? Are they typically close
in magnitude?
18. Using the characteristics of Fig. 3.13:
a. Find the value of IC corresponding to VBE  750 mV and VCE  4 V.
b. Find the value of VCE and VBE corresponding to IC  3.5 mA and IB  30 mA.
*19. a. For the common-emitter characteristics of Fig. 3.13, find the dc beta at an operating point
of VCE  6 V and IC  2 mA.
b. Find the value of a corresponding to this operating point.
c. At VCE  6 V, find the corresponding value of ICEO.
d. Calculate the approximate value of ICBO using the dc beta value obtained in part (a).
*20. a. Using the characteristics of Fig. 3.13a, determine ICEO at VCE  10 V.
b. Determine bdc at IB  10 mA and VCE  10 V.
c. Using the bdc determined in part (b), calculate ICBO.
21. a. Using the characteristics of Fig. 3.13a, determine bdc at IB  60 mA and VCE  4 V.
b. Repeat part (a) at IB  30 mA and VCE  7 V.
c. Repeat part (a) at IB  10 mA and VCE  10 V.
d. Reviewing the results of parts (a) through (c), does the value of bdc change from point to point
on the characteristics? Where were the higher values found? Can you develop any general con-
clusions about the value of bdc on a set of characteristics such as those provided in Fig. 3.13a?
*22. a. Using the characteristics of Fig. 3.13a, determine bac at IB  60 mA and VCE  4 V.
b. Repeat part (a) at IB  30 mA and VCE  7 V.
c. Repeat part (a) at IB  10 mA and VCE  10 V.
d. Reviewing the results of parts (a) through (c), does the value of bac change from point to
point on the characteristics? Where are the high values located? Can you develop any gen-
eral conclusions about the value of bac on a set of collector characteristics?
e. The chosen points in this exercise are the same as those employed in Problem 21. If Prob-
lem 21 was performed, compare the levels of bdc and bac for each point and comment on
the trend in magnitude for each quantity.
23. Using the characteristics of Fig. 3.13a, determine bdc at IB  25 mA and VCE  10 V. Then
calculate adc and the resulting level of IE. (Use the level of IC determined by IC = bdcIB.)
24. a. Given that adc = 0.980, determine the corresponding value of bdc.
b. Given bdc = 120, determine the corresponding value of a.
c. Given that bdc = 120 and IC  2.0 mA, find IE and IB.
25. From memory only, sketch the common-emitter configuration (for npn and pnp) and insert the
proper biasing arrangement with the resulting current directions for IB, IC, and IE.

3.6 Common-Collector Configuration

26. An input voltage of 2 V rms (measured from base to ground) is applied to the circuit of Fig. 3.21.
Assuming that the emitter voltage follows the base voltage exactly and that Vbe (rms)  0.1 V,
calculate the circuit voltage amplification (Av = Vo >Vi) and emitter current for RE  1 k.
 27. For a transistor having the characteristics of Fig. 3.13, sketch the input and output characteris- PROBLEMS 159
tics of the common-collector configuration.

3.7 Limits of Operation

28. Determine the region of operation for a transistor having the characteristics of Fig. 3.13 if
ICmax = 6 mA, BVCEO  15 V, and PCmax = 35 mW.
29. Determine the region of operation for a transistor having the characteristics of Fig. 3.8 if
ICmax = 7 mA, BVCBO  20 V, and PCmax = 42 mW.

3.8 Transistor Specification Sheet

30. Referring to Fig. 3.23, determine the temperature range for the device in degrees Fahrenheit.
31. Using the information provided in Fig. 3.23 regarding PDmax, VCEmax, ICmax and VCEsat, sketch the
boundaries of operation for the device.
32. Based on the data of Fig. 3.23, what is the expected value of ICEO using the average value of bdc?
33. How does the range of hFE (Fig. 3.23c, normalized from hFE = 100) compare with the range
of hfe (Fig. 3.23b) for the range of IC from 0.1 to 10 mA?
34. Using the characteristics of Fig. 3.23d, determine whether the input capacitance in the common-
base configuration increases or decreases with increasing levels of reverse-bias potential. Can
you explain why?
*35. Using the characteristics of Fig. 3.23b, determine how much the level of hfe has changed from
its value at 1 mA to its value at 10 mA. Note that the vertical scale is a log scale that may require
reference to Section 11.2. Is the change one that should be considered in a design situation?
*36. Using the characteristics of Fig. 3.23c, determine the level of bdc at IC  10 mA at the three
levels of temperature appearing in the figure. Is the change significant for the specified tem-
perature range? Is it an element to be concerned about in the design process?

3.9 Transistor Testing

37. a. Using the characteristics of Fig. 3.24, determine bac at IC  14 mA and VCE  3 V.
b. Determine bdc at IC  1 mA and VCE  8 V.
c. Determine bac at IC  14 mA and VCE  3 V.
d. Determine bdc at IC  1 mA and VCE  8 V.
e. How does the level of bac and bdc compare in each region?
f. Is the approximation bdc ⬵ bac a valid one for this set of characteristics?
 BJT AC Analysis
5
CHAPTER OBJECTIVES
●
● Become familiar with the re, hybrid, and hybrid p models for the BJT transistor.
● Learn to use the equivalent model to find the important ac parameters for an amplifier.
● Understand the effects of a source resistance and load resistor on the overall gain and
characteristics of an amplifier.
● Become aware of the general ac characteristics of a variety of important BJT
configurations.
● Begin to understand the advantages associated with the two-port systems approach to
single- and multistage amplifiers.
● Develop some skill in troubleshooting ac amplifier networks.

5.1 INTRODUCTION
●
The basic construction, appearance, and characteristics of the transistor were introduced in
Chapter 3. The dc biasing of the device was then examined in detail in Chapter 4. We now
begin to examine the ac response of the BJT amplifier by reviewing the models most fre-
quently used to represent the transistor in the sinusoidal ac domain.
One of our first concerns in the sinusoidal ac analysis of transistor networks is the mag-
nitude of the input signal. It will determine whether small-signal or large-signal techniques
should be applied. There is no set dividing line between the two, but the application—and
the magnitude of the variables of interest relative to the scales of the device characteristics—
will usually make it quite clear which method is appropriate. The small-signal technique is
introduced in this chapter, and large-signal applications are examined in Chapter 12.
There are three models commonly used in the small-signal ac analysis of transistor
networks: the re model, the hybrid p model, and the hybrid equivalent model. This chapter
introduces all three but emphasizes the re model.

5.2 AMPLIFICATION IN THE AC DOMAIN

●
It was demonstrated in Chapter 3 that the transistor can be employed as an amplifying device.
That is, the output sinusoidal signal is greater than the input sinusoidal signal, or, stated
another way, the output ac power is greater than the input ac power. The question then arises
as to how the ac power output can be greater than the input ac power. Conservation of energy
dictates that over time the total power output, Po, of a system cannot be greater than its power

253
254 BJT AC ANALYSIS input, Pi, and that the efficiency defined by h = Po >Pi cannot be greater than 1. The factor
missing from the discussion above that permits an ac power output greater than the input ac
power is the applied dc power. It is the principal contributor to the total output power even
though part of it is dissipated by the device and resistive elements. In other words, there is an
“exchange” of dc power to the ac domain that permits establishing a higher output ac power.
In fact, a conversion efficiency is defined by h = Po(ac) >Pi(dc), where Po(ac) is the ac power
to the load and Pi(dc) is the dc power supplied.
Perhaps the role of the dc supply can best be described by first considering the simple
dc network of Fig. 5.1. The resulting direction of flow is indicated in the figure with a plot
Idc R
Idc of the current i versus time. Let us now insert a control mechanism such as that shown in
+ Fig. 5.2. The control mechanism is such that the application of a relatively small signal to
E the control mechanism can result in a substantial oscillation in the output circuit.
–
Idc
Idc
Control iT R iT iT = Idc + iac
mechanism
i +
Idc ic
E
–
iT
iT 0 t

0 t

FIG. 5.1 FIG. 5.2

Steady current established by a Effect of a control element on the steady-state flow of the electrical
dc supply. system of Fig. 5.1.

That is, for this example,

iac(p@p) W ic(p@p)
and amplification in the ac domain has been established. The peak-to-peak value of the
output current far exceeds that of the control current.
For the system of Fig. 5.2, the peak value of the oscillation in the output circuit is con-
trolled by the established dc level. Any attempt to exceed the limit set by the dc level will
result in a “clipping” (flattening) of the peak region at the high and low end of the output
signal. In general, therefore, proper amplification design requires that the dc and ac com-
ponents be sensitive to each other’s requirements and limitations.
However, it is extremely helpful to realize that:
The superposition theorem is applicable for the analysis and design of the dc and ac
components of a BJT network, permitting the separation of the analysis of the dc and
ac responses of the system.
In other words, one can make a complete dc analysis of a system before considering the
ac response. Once the dc analysis is complete, the ac response can be determined using a
completely ac analysis. It happens, however, that one of the components appearing in the
ac analysis of BJT networks will be determined by the dc conditions, so there is still an
important link between the two types of analysis.

5.3 BJT TRANSISTOR MODELING

●
The key to transistor small-signal analysis is the use of the equivalent circuits (models) to
be introduced in this chapter.
A model is a combination of circuit elements, properly chosen, that best approximates
the actual behavior of a semiconductor device under specific operating conditions.
Once the ac equivalent circuit is determined, the schematic symbol for the device can
be replaced by this equivalent circuit and the basic methods of circuit analysis applied to
determine the desired quantities of the network.
In the formative years of transistor network analysis the hybrid equivalent network was
employed the most frequently. Specification sheets included the parameters in their listing,
and analysis was simply a matter of inserting the equivalent circuit with the listed values.
The drawback to using this equivalent circuit, however, is that it is defined for a set of oper- BJT TRANSISTOR 255
ating conditions that might not match the actual operating conditions. In most cases, this is MODELING
not a serious flaw because the actual operating conditions are relatively close to the chosen
operating conditions on the data sheets. In addition, there is always a variation in actual
resistor values and given transistor beta values, so as an approximate approach it was quite
reliable. Manufacturers continue to specify the hybrid parameter values for a particular
operating point on their specification sheets. They really have no choice. They want to give
the user some idea of the value of each important parameter so comparisons can be made
between transistors, but they really do not know the user’s actual operating conditions.
In time the use of the re model became the more desirable approach because an impor-
tant parameter of the equivalent circuit was determined by the actual operating conditions
rather than using a data sheet value that in some cases could be quite different. Unfortu-
nately, however, one must still turn to the data sheets for some of the other parameters of
the equivalent circuit. The re model also failed to include a feedback term, which in some
cases can be important if not simply troublesome.
The re model is really a reduced version of the hybrid p model used almost exclusively
for high-frequency analysis. This model also includes a connection between output and
input to include the feedback effect of the output voltage and the input quantities. The full
hybrid model is introduced in Chapter 9.
Throughout the text the re model is the model of choice unless the discussion centers
on the description of each model or a region of examination that predetermines the model
that should be used. Whenever possible, however, a comparison between models will be
discussed to show how closely related they really are. It is also important that once you gain
a proficiency with one model it will carry over to an investigation using a different model,
so moving from one to another will not be a dramatic undertaking.
In an effort to demonstrate the effect that the ac equivalent circuit will have on the
analysis to follow, consider the circuit of Fig. 5.3. Let us assume for the moment that the
small-signal ac equivalent circuit for the transistor has already been determined. Because
we are interested only in the ac response of the circuit, all the dc supplies can be replaced
by a zero-potential equivalent (short circuit) because they determine only the dc (quiescent
level) of the output voltage and not the magnitude of the swing of the ac output. This is
clearly demonstrated by Fig. 5.4. The dc levels were simply important for determining the
proper Q-point of operation. Once determined, the dc levels can be ignored in the ac analy-
sis of the network. In addition, the coupling capacitors C1 and C2 and bypass capacitor C3
were chosen to have a very small reactance at the frequency of application. Therefore, they,
too, may for all practical purposes be replaced by a low-resistance path or a short circuit.
Note that this will result in the “shorting out” of the dc biasing resistor RE. Recall that ca-
pacitors assume an “open-circuit” equivalent under dc steady-state conditions, permitting
an isolation between stages for the dc levels and quiescent conditions.

FIG. 5.3
Transistor circuit under examination in this introductory discussion.
256 BJT AC ANALYSIS
Io

+
Ii

Zo
+ Vo
Zi

Vi

–
–

FIG. 5.4
The network of Fig. 5.3 following removal of the dc
supply and insertion of the short-circuit equivalent
for the capacitors.

It is important as you progress through the modifications of the network to define the ac
equivalent that the parameters of interest such as Zi, Zo, Ii, and Io as defined by Fig. 5.5 be
carried through properly. Even though the network appearance may change, you want to be
sure the quantities you find in the reduced network are the same as defined by the original
network. In both networks the input impedance is defined from base to ground, the input
current as the base current of the transistor, the output voltage as the voltage from collector
to ground, and the output current as the current through the load resistor RC.

Ii Io

+ + Ii Io
Vi System Vo
Zi Zo + + + +
– – Vi Ri Ro Vo
– – – –

FIG. 5.5 FIG. 5.6

Defining the important parameters Demonstrating the reason for the defined
of any system. directions and polarities.

The parameters of Fig. 5.5 can be applied to any system whether it has one or a thou-
sand components. For all the analysis to follow in this text, the directions of the currents,
the polarities of the voltages, and the direction of interest for the impedance levels are as
appearing in Fig. 5.5. In other words, the input current Ii and output current Io are, by defini-
tion, defined to enter the system. If, in a particular example, the output current is leaving the
system rather than entering the system as shown in Fig. 5.5, a minus sign must be applied.
The defined polarities for the input and output voltages are also as appearing in Fig. 5.5. If
Vo has the opposite polarity, the minus sign must be applied. Note that Zi is the impedance
“looking into” the system, whereas Zo is the impedance “looking back into” the system
from the output side. By choosing the defined directions for the currents and voltages as
appearing in Fig. 5.5, both the input impedance and output impedance are defined as having
positive values. For example, in Fig. 5.6 the input and output impedances for a particular
system are both resistive. For the direction of Ii and Io the resulting voltage across the resis-
tive elements will have the same polarity as Vi and Vo, respectively. If Io had been defined
as the opposite direction in Fig. 5.5 a minus sign would have to be applied. For each case
Zi = Vi >Ii and Zo = Vo >Io with positive results if they all have the defined directions and
polarity of Fig. 5.5. If the output current of an actual system has a direction opposite to that
of Fig. 5.5 a minus sign must be applied to the result because Vo must be defined as appear- THE r e TRANSISTOR 257
ing in Fig. 5.5. Keep Fig. 5.5 in mind as you analyze the BJT networks in this chapter. It is MODEL
an important introduction to “System Analysis,” which is becoming so important with the
expanded use of packaged IC systems.
If we establish a common ground and rearrange the elements of Fig. 5.4, R1 and R2 will
be in parallel, and RC will appear from collector to emitter as shown in Fig. 5.7. Because
the components of the transistor equivalent circuit appearing in Fig. 5.7 employ familiar
components such as resistors and independent controlled sources, analysis techniques
such as superposition, Thévenin’s theorem, and so on, can be applied to determine the
desired quantities.

Ii

B
Zi

FIG. 5.7
Circuit of Fig. 5.4 redrawn for small-signal ac analysis.

Let us further examine Fig. 5.7 and identify the important quantities to be determined
for the system. Because we know that the transistor is an amplifying device, we would
expect some indication of how the output voltage Vo is related to the input voltage Vi—
the voltage gain. Note in Fig. 5.7 for this configuration that the current gain is defined
by Ai = Io >Ii.
In summary, therefore, the ac equivalent of a transistor network is obtained by:
1. Setting all dc sources to zero and replacing them by a short-circuit equivalent
2. Replacing all capacitors by a short-circuit equivalent
3. Removing all elements bypassed by the short-circuit equivalents introduced by steps
1 and 2
4. Redrawing the network in a more convenient and logical form
In the sections to follow, a transistor equivalent model will be introduced to complete
the ac analysis of the network of Fig. 5.7.

5.4 THE re TRANSISTOR MODEL

●
The re model for the CE, CB, and CC BJT transistor configurations will now be introduced
with a short description of why each is a good approximation to the actual behavior of a
BJT transistor.

C
Ib
Common-Emitter Configuration B

The equivalent circuit for the common-emitter configuration will be constructed using the + +
device characteristics and a number of approximations. Starting with the input side, we find Vi Vbe E
the applied voltage Vi is equal to the voltage Vbe with the input current being the base cur- Ie
– –
rent Ib as shown in Fig. 5.8.
Recall from Chapter 3 that because the current through the forward-biased junction of
the transistor is IE, the characteristics for the input side appear as shown in Fig. 5.9a for FIG. 5.8
various levels of VBE. Taking the average value for the curves of Fig. 5.9a will result in the Finding the input equivalent circuit
single curve of Fig. 5.9b, which is simply that of a forward-biased diode. for a BJT transistor.
258 BJT AC ANALYSIS IE IE

Various Average
values value
of VCB of VCB

0 0.7 V VBE 0 0.7 V VBE

(a) (b)

FIG. 5.9
Defining the average curve for the characteristics of Fig. 5.9a.

Ic
Ib For the equivalent circuit, therefore, the input side is simply a single diode with a current
Ie, as shown in Fig. 5.10. However, we must now add a component to the network that will
+
establish the current Ie of Fig. 5.10 using the output characteristics.
Ie
Vbe If we redraw the collector characteristics to have a constant b as shown in Fig. 5.11
(another approximation), the entire characteristics at the output section can be replaced by
–
a controlled source whose magnitude is beta times the base current as shown in Fig. 5.11.
Because all the input and output parameters of the original configuration are now present, the
FIG. 5.10 equivalent network for the common-emitter configuration has been established in Fig. 5.12.
Equivalent circuit for the input side
of a BJT transistor. IC
IB6

IB5
Ic
IB4
+
IB3
β Ib
Constant β
Ib
IB2
Vce
+ Ie
IB1
Vbe

0 VCE – –

FIG. 5.11 FIG. 5.12

Constant b characteristics. BJT equivalent circuit.

The equivalent model of Fig. 5.12 can be awkward to work with due to the direct con-
nection between input and output networks. It can be improved by first replacing the diode
by its equivalent resistance as determined by the level of IE, as shown in Fig. 5.13. Recall
from Section 1.8 that the diode resistance is determined by rD = 26 mV>ID. Using the sub-
script e because the determining current is the emitter current will result in re = 26 mV>IE.
Vi Vbe
β Ib Now, for the input side: Zi = =
Ib Ib Ib
Solving for Vbe: Vbe = Iere = (Ic + Ib)re = (bIb + Ib)re
+ + Ie
= (b + 1)Ibre
Vi Vbe Zi re
Vbe (b + 1)Ibre
and Zi = =
– – Ib Ib

FIG. 5.13
Zi = (b + 1)re ⬵ bre (5.1)
Defining the level of Zi.
The result is that the impedance seen “looking into” the base of the network is a resistor THE r e TRANSISTOR 259
equal to beta times the value of re, as shown in Fig. 5.14. The collector output current is MODEL
still linked to the input current by beta as shown in the same figure.

Ib Ic
b c

β re β Ib

e e

FIG. 5.14
Improved BJT equivalent circuit.

The equivalent circuit has therefore been defined for the ideal characteristics of Fig. 5.11,
but now the input and output circuits are isolated and only linked by the controlled source—a
form much easier to work with when analyzing networks.

Early Voltage
We now have a good representation for the input circuit, but aside from the collector out-
put current being defined by the level of beta and IB, we do not have a good representation
for the output impedance of the device. In reality the characteristics do not have the ideal
appearance of Fig. 5.11. Rather, they have a slope as shown In Fig. 5.15 that defines the
output impedance of the device. The steeper the slope, the less the output impedance and
the less ideal the transistor. In general, it is desirable to have large output impedances to
avoid loading down the next stage of a design. If the slope of the curves is extended until
they reach the horizontal axis, it is interesting to note in Fig. 5.15 that they will all intersect
at a voltage called the Early voltage. This intersection was first discovered by James M.
Early in 1952. As the base current increases the slope of the line increases, resulting in an
increase in output impedance with increase in base and collector current. For a particular
collector and base current as shown in Fig. 5.15, the output impedance can be found using
the following equation:

V VA + VCEQ
ro = = (5.2)
I ICQ

IC (mA)
1
Slope = ro
1
ΔIC
ΔVCE

1 ICQ
Slope = ro
2
ΔIC
ΔVCE

VA 0 VCEQ VCE (V)

VA + VCEQ

FIG. 5.15
Defining the Early voltage and the output impedance of a transistor.
260 BJT AC ANALYSIS Typically, however, the Early voltage is sufficiently large compared with the applied
collector-to-emitter voltage to permit the following approximation.

VA
ro ⬵ (5.3)
ICQ

Clearly, since VA is a fixed voltage, the larger the collector current, the less the output
impedance.
For situations where the Early voltage is not available the output impedance can be found
from the characteristics at any base or collector current using the following equation:
⌬y ⌬IC 1
Slope = = =
⌬x ⌬VCE r o

⌬VCE
and ro = (5.4)
⌬IC

For the same change in voltage in Fig. 5.15 the resulting change in current ¢IC is signifi-
cantly less for ro2 than ro1, resulting in ro2 being much larger than ro1.
In situations where the specification sheets of a transistor do not include the Early volt-
age or the output characteristics, the output impedance can be determined from the hybrid
parameter hoe that is normally plotted on every specification sheet. It is a quantity that will
be described in detail in Section 5.19.
In any event, an output impedance can now be defined that will appear as a resistor in
parallel with the output as shown in the equivalent circuit of Fig. 5.16.

FIG. 5.16
re model for the common-emitter transistor configuration
including effects of ro.

The equivalent circuit of Fig. 5.16 will be used throughout the analysis to follow for the
common-emitter configuration. Typical values of beta run from 50 to 200, with values of
bre typically running from a few hundred ohms to a maximum of 6 k⍀ to 7 k⍀. The output
resistance r is typically in the range of 40 k⍀ to 50 k⍀.

Common-Base Configuration
The common-base equivalent circuit will be developed in much the same manner as
applied to the common-emitter configuration. The general characteristics of the input and
output circuit will generate an equivalent circuit that will approximate the actual behavior
of the device. Recall for the common-emitter configuration the use of a diode to represent
the connection from base to emitter. For the common-base configuration of Fig. 5.17a the
pnp transistor employed will present the same possibility at the input circuit. The result is
the use of a diode in the equivalent circuit as shown in Fig. 5.17b. For the output circuit, if
we return to Chapter 3 and review Fig. 3.8, we find that the collector current is related to
the emitter current by alpha a. In this case, however, the controlled source defining the
collector current as inserted in Fig. 5.17b is opposite in direction to that of the controlled
source of the common-emitter configuration. The direction of the collector current in the
output circuit is now opposite that of the defined output current.
 Ii Ie Ic Io Ii Ie Ic Io

+ +

Vi Vo
Zi Zo Zi Zo

− −

(a) (b)

FIG. 5.17
(a) Common-base BJT transistor; (b) equivalent circuit for configuration of (a).

For the ac response, the diode can be replaced by its equivalent ac resistance determined
by re = 26 mV>IE as shown in Fig. 5.18. Take note of the fact that the emitter current
continues to determine the equivalent resistance. An additional output resistance can be
determined from the characteristics of Fig. 5.19 in much the same manner as applied to the
common-emitter configuration. The almost horizontal lines clearly reveal that the output
resistance ro as appearing in Fig. 5.18 will be quite high and certainly much higher than that
for the typical common-emitter configuration.
The network of Fig. 5.18 is therefore an excellent equivalent circuit for the analysis of
most common-base configurations. It is similar in many ways to that of the common-emitter
configuration. In general, common-base configurations have very low input impedance
because it is essentially simply re. Typical values extend from a few ohms to perhaps 50 .
The output impedance ro will typically extend into the megohm range. Because the output
current is opposite to the defined Io direction, you will find in the analysis to follow that
there is no phase shift between the input and output voltages. For the common-emitter
configuration there is a 180° phase shift.

Ii Ie Ic Io

+ +

ro
Vi Zi Zo Vo

– –

FIG. 5.18
Common base re equivalent circuit.

IC (mA) 1
Slope = ro
IE = 4 mA
4

IE = 3 mA
3

IE = 2 mA
2

IE = 1 mA
1

IE = 0 mA
0 VCB

FIG. 5.19
Defining Zo.
261
262 BJT AC ANALYSIS Common-Collector Configuration
For the common-collector configuration, the model defined for the common-emitter configu-
ration of Fig. 5.16 is normally applied rather than defining a model for the common-collector
configuration. In subsequent chapters, a number of common-collector configurations will be
investigated, and the effect of using the same model will become quite apparent.

npn versus pnp

The dc analysis of npn and pnp configurations is quite different in the sense that the currents
will have opposite directions and the voltages opposite polarities. However, for an ac analy-
sis where the signal will progress between positive and negative values, the ac equivalent
circuit will be the same.

5.5 COMMON-EMITTER FIXED-BIAS

CONFIGURATION
●
The transistor models just introduced will now be used to perform a small-signal ac analy-
sis of a number of standard transistor network configurations. The networks analyzed rep-
resent the majority of those appearing in practice. Modifications of the standard
configurations will be relatively easy to examine once the content of this chapter is reviewed
and understood. For each configuration, the effect of an output impedance is examined for
completeness.
The computer analysis section includes a brief description of the transistor model em-
ployed in the PSpice and Multisim software packages. It demonstrates the range and depth
of the available computer analysis systems and how relatively easy it is to enter a complex
network and print out the desired results. The first configuration to be analyzed in detail is
the common-emitter fixed-bias network of Fig. 5.20. Note that the input signal Vi is applied
to the base of the transistor, whereas the output Vo is off the collector. In addition, recognize
that the input current Ii is not the base current, but the source current, and the output current
Io is the collector current. The small-signal ac analysis begins by removing the dc effects
of VCC and replacing the dc blocking capacitors C1 and C2 by short-circuit equivalents,
resulting in the network of Fig. 5.21.

VCC

RC
RB Io C Vo
C Vo
Ii Ii Io
C2 B
B Vi
Vi
RC
C1 Zo
Zo
RB E
E Zi
Zi

FIG. 5.20 FIG. 5.21

Common-emitter fixed-bias configuration. Network of Fig. 5.20 following the removal
of the effects of VCC, C1, and C2.

Note in Fig. 5.21 that the common ground of the dc supply and the transistor emitter
terminal permits the relocation of RB and RC in parallel with the input and output sections
of the transistor, respectively. In addition, note the placement of the important network
parameters Zi, Zo, Ii, and Io on the redrawn network. Substituting the re model for the
common-emitter configuration of Fig. 5.21 results in the network of Fig. 5.22.
The next step is to determine b, re, and ro. The magnitude of b is typically obtained
from a specification sheet or by direct measurement using a curve tracer or transistor
 COMMON-EMITTER 263
Ii Ib Ic FIXED-BIAS
CONFIGURATION
+Z b c +
i Io

Vi Vo
RB β re β Ib ro RC
– –
Zo

FIG. 5.22
Substituting the re model into the network of Fig. 5.21.

testing instrument. The value of re must be determined from a dc analysis of the system,
and the magnitude of ro is typically obtained from the specification sheet or characteristics.
Assuming that b, re, and ro have been determined will result in the following equations for
the important two-port characteristics of the system.

Zi Figure 5.22 clearly shows that

Zi = RB 7 bre ohms (5.5)

For the majority of situations RB is greater than bre by more than a factor of 10 (recall
from the analysis of parallel elements that the total resistance of two parallel resistors is
always less than the smallest and very close to the smallest if one is much larger than the
other), permitting the following approximation:

Zi ⬵ bre ohms (5.6)

RB Ú 10bre

Zo Recall that the output impedance of any system is defined as the impedance Zo
determined when Vi  0. For Fig. 5.22, when Vi  0, Ii = Ib = 0, resulting in an open-
Zo
circuit equivalence for the current source. The result is the configuration of Fig. 5.23.
ro RC
We have

Zo = RC 7 ro ohms (5.7)

If ro Ú 10RC, the approximation RC 7 ro ⬵ RC is frequently applied, and FIG. 5.23

Determining Zo for the network
Zo ⬵ RC (5.8) of Fig. 5.22.
ro Ú 10RC

Av The resistors ro and RC are in parallel, and

Vo = -bIb(RC 7 ro)
Vi
but Ib =
bre
Vi
so that Vo = -ba b (RC 7 ro)
bre

Vo (RC 7 ro)
and Av = = - (5.9)
Vi re

If ro Ú 10RC, so that the effect of ro can be ignored,

RC
Av = - (5.10)
re
ro Ú 10RC

Note the explicit absence of b in Eqs. (5.9) and (5.10), although we recognize that b must
be utilized to determine re.
264 BJT AC ANALYSIS Phase Relationship The negative sign in the resulting equation for Av reveals that a 180°
phase shift occurs between the input and output signals, as shown in Fig. 5.24. The is a
result of the fact that bIb establishes a current through RC that will result in a voltage across
RC, the opposite of that defined by Vo.

VCC

Vo
RC
RB
Vi Vo 0 t

0 t Vi

FIG. 5.24
Demonstrating the 180° phase shift between input and output waveforms.

EXAMPLE 5.1 For the network of Fig. 5.25:

a. Determine re.
b. Find Zi (with ro =  ).
c. Calculate Zo (with ro =  ).
d. Determine Av (with ro =  ).
e. Repeat parts (c) and (d) including ro = 50 k in all calculations and compare results.

12 V

3 kΩ
470 kΩ Io
Ii Vo
10 μ F
Vi
10 μ F β = 100 Zo
ro = 50 kΩ
Zi

FIG. 5.25
Example 5.1.

Solution:
a. DC analysis:
VCC - VBE 12 V - 0.7 V
IB = = = 24.04 mA
RB 470 k
IE = (b + 1)IB = (101)(24.04 mA) = 2.428 mA
26 mV 26 mV
re = = = 10.71 ⍀
IE 2.428 mA
b. bre = (100)(10.71 ) = 1.071 k
Zi = RB 7 bre = 470 k 7 1.071 k = 1.07 k⍀
c. Zo = RC = 3 k⍀
RC 3 k
d. Av = - = - = ⴚ280.11
re 10.71 
e. Zo = ro 7 RC = 50 k 7 3 k = 2.83 k⍀ vs. 3 k VOLTAGE-DIVIDER BIAS 265
ro 7 RC 2.83 k
Av = - = = ⴚ264.24 vs. -280.11
re 10.71 

5.6 VOLTAGE-DIVIDER BIAS

●
The next configuration to be analyzed is the voltage-divider bias network of Fig. 5.26.
Recall that the name of the configuration is a result of the voltage-divider bias at the input
side to determine the dc level of VB.
Substituting the re equivalent circuit results in the network of Fig. 5.27. Note the absence
of RE due to the low-impedance shorting effect of the bypass capacitor, CE. That is, at the
frequency (or frequencies) of operation, the reactance of the capacitor is so small compared
to RE that it is treated as a short circuit across RE. When VCC is set to zero, it places one
end of R1 and RC at ground potential as shown in Fig. 5.27. In addition, note that R1 and
R2 remain part of the input circuit, whereas RC is part of the output circuit. The parallel
combination of R1 and R2 is defined by

R1R2
R = R1 7 R2 = (5.11)
R1 + R2

Zi From Fig. 5.27

Zi = R 7 bre (5.12)

VCC

Io

RC
R1
C Vo
Ii C2
B
Vi
C1 Zo

E
Zi R2
RE CE

FIG. 5.26
Voltage-divider bias configuration.

Ii
b Ib c

+ Io +
Zi
Vi R1 R2 β re β Ib ro RC Vo

– e e Zo –

R'

FIG. 5.27
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.26.
266 BJT AC ANALYSIS Zo From Fig. 5.27 with Vi set to 0 V, resulting in Ib = 0 mA and bIb = 0 mA,

Zo = RC 7 ro (5.13)

If ro Ú 10RC,

Zo ⬵ RC (5.14)
ro Ú 10RC

Av Because RC and ro are in parallel,

Vo = -(bIb)(RC 7 ro)
Vi
and Ib =
bre
Vi
so that Vo = -ba b (RC 7 ro)
bre

Vo -RC 7 ro
and Av = = (5.15)
Vi re

which you will note is an exact duplicate of the equation obtained for the fixed-bias con-
figuration.
For ro Ú 10RC,

Vo RC
Av = ⬵ - (5.16)
Vi re
ro Ú 10RC

Phase Relationship The negative sign of Eq. (5.15) reveals a 180° phase shift between
Vo and Vi.

EXAMPLE 5.2 For the network of Fig. 5.28, determine:

a. re.
b. Zi.
c. Zo (ro =  ).
d. Av (ro =  ).
e. The parameters of parts (b) through (d) if ro = 50 k and compare results.

22 V

Io

6.8 kΩ
56 kΩ 10 μF
Vo
10 μ F
Vi β = 90 Zo

Ii

8.2 kΩ
Zi 20 μ F
1.5 kΩ

FIG. 5.28
Example 5.2.
Solution: CE EMITTER-BIAS 267
CONFIGURATION
a. DC: Testing bRE 7 10R2,
(90)(1.5 k) 7 10(8.2 k)
135 k 7 82 k (satisfied)
Using the approximate approach, we obtain
R2 (8.2 k)(22 V)
VB = V = = 2.81 V
R1 + R2 CC 56 k + 8.2 k
VE = VB - VBE = 2.81 V - 0.7 V = 2.11 V
VE 2.11 V
IE = = = 1.41 mA
RE 1.5 k
26 mV 26 mV
re = = = 18.44 ⍀
IE 1.41 mA
b. R = R1 7 R2 = (56 k) 7 (8.2 k) = 7.15 k
Zi = R 7 bre = 7.15 k 7 (90)(18.44 ) = 7.15 k 7 1.66 k
= 1.35 k⍀
c. Zo = RC = 6.8 k⍀
RC 6.8 k
d. Av = - = - = ⴚ368.76
re 18.44 
e. Zi = 1.35 k⍀
Zo = RC 7 ro = 6.8 k 7 50 k = 5.98 k⍀ vs. 6.8 k
RC 7 ro 5.98 k
Av = - = - = ⴚ324.3 vs. -368.76
re 18.44 
There was a measurable difference in the results for Zo and Av, because the condition
ro Ú 10RC was not satisfied.

5.7 CE EMITTER-BIAS CONFIGURATION

●
The networks examined in this section include an emitter resistor that may or may not be
bypassed in the ac domain. We first consider the unbypassed situation and then modify the
resulting equations for the bypassed configuration.

Unbypassed
The most fundamental of unbypassed configurations appears in Fig. 5.29. The re equiva-
lent model is substituted in Fig. 5.30, but note the absence of the resistance ro. The effect
of ro is to make the analysis a great deal more complicated, and considering the fact that in

VCC Ii
b c
Ib
+ +
RC β re β Ib
Zi Io
RB Io
Vo Zb Zo
Ii C2 Vi RB RC Vo
Vi e
C1 Ie = ( β + 1)Ib
Zo RE
RE
– –
Zi

FIG. 5.29 FIG. 5.30

CE emitter-bias configuration. Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.29.
268 BJT AC ANALYSIS most situations its effect can be ignored, it will not be included in the present analysis.
However, the effect of ro will be discussed later in this section.
Applying Kirchhoff’s voltage law to the input side of Fig. 5.30 results in
Vi = Ibbre + IeRE
or Vi = Ibbre + (b + I)IbRE
and the input impedance looking into the network to the right of RB is
Vi
Zb = = bre + (b + 1)RE
Ib
The result as displayed in Fig. 5.31 reveals that the input impedance of a transistor with
an unbypassed resistor RE is determined by

re β Zb = bre + (b + 1)RE (5.17)

Because b is normally much greater than 1, the approximate equation is

Zb
RE Zb ⬵ bre + bRE

and Zb ⬵ b(re + RE) (5.18)

FIG. 5.31
Defining the input impedance of a Because RE is usually greater than re, Eq. (5.18) can be further reduced to
transistor with an unbypassed
emitter resistor. Zb ⬵ bRE (5.19)

Zi Returning to Fig. 5.30, we have

Zi = RB 7 Zb (5.20)

Zo With Vi set to zero, Ib = 0, and bIb can be replaced by an open-circuit equivalent.

The result is

Zo = RC (5.21)

Av
Vi
Ib =
Zb
and Vo = -Io RC = -bIbRC
Vi
= -ba b RC
Zb

Vo bRC
with Av = = - (5.22)
Vi Zb

Substituting Zb ⬵ b(re + RE) gives

Vo RC
Av = ⬵ - (5.23)
Vi re + RE

and for the approximation Zb ⬵ bRE,

Vo RC
Av = ⬵ - (5.24)
Vi RE

Note the absence of b from the equation for Av demonstrating an independence in variation
of b.

Phase Relationship The negative sign in Eq. (5.22) again reveals a 180° phase shift
between Vo and Vi.
Effect of ro The equations appearing below will clearly reveal the additional complexity CE EMITTER-BIAS 269
resulting from including ro in the analysis. Note in each case, however, that when certain CONFIGURATION
conditions are met, the equations return to the form just derived. The derivation of each
equation is beyond the needs of this text and is left as an exercise for the reader. Each
equation can be derived through careful application of the basic laws of circuit analysis
such as Kirchhoff’s voltage and current laws, source conversions, Thévenin’s theorem,
and so on. The equations were included to remove the nagging question of the effect of ro
on the important parameters of a transistor configuration.

Zi

(b + 1) + RC>ro
Zb = bre + c dR (5.25)
1 + (RC + RE)>ro E

Because the ratio RC>ro is always much less than (b + 1),

(b + 1)RE
Zb ⬵ bre +
1 + (RC + RE)>ro
For ro Ú 10(RC + RE),
Zb ⬵ bre + (b + 1)RE
which compares directly with Eq. (5.17).
In other words, if ro Ú 10(RC + RE), all the equations derived earlier result. Because
b + 1 ⬵ b, the following equation is an excellent one for most applications:

Zb ⬵ b(re + RE) (5.26)

ro Ú 10(RC + RE)

Zo

b(ro + re)
Zo = RC 储 £ ro + (5.27)
bre §
1 +
RE

However, ro W re, and

b
Zo ⬵ RC 储 ro £ 1 +
bre §
1 +
RE

which can be written as

1
Zo ⬵ RC 储 ro £ 1 +
1 re §
+
b RE

Typically 1>b and re>RE are less than one with a sum usually less than one. The result
is a multiplying factor for ro greater than one. For b = 100, re = 10 , and RE = 1 k,
1 1 1
= = = 50
1 re 1 10  0.02
+ +
b RE 100 1000 
and Zo = RC 7 51ro
which is certainly simply RC. Therefore,

Zo ⬵ RC (5.28)
Any level of ro

which was obtained earlier.

270 BJT AC ANALYSIS Av

bRC re RC
- c1 + d +
Vo Zb ro ro
Av = = (5.29)
Vi RC
1 +
ro
re
The ratio V 1, and
ro
bRC RC
- +
Vo Zb ro
Av = ⬵
Vi RC
1 +
ro
For ro Ú 10RC,

Vo bRC
Av = ⬵ - (5.30)
Vi Zb ro Ú 10RC

as obtained earlier.

Bypassed
If RE of Fig. 5.29 is bypassed by an emitter capacitor CE, the complete re equivalent model
can be substituted, resulting in the same equivalent network as Fig. 5.22. Equations (5.5)
to (5.10) are therefore applicable.

EXAMPLE 5.3 For the network of Fig. 5.32, without CE (unbypassed), determine:
a. re.
b. Zi. 20 V
c. Zo.
d. Av.
Io

2.2 kΩ
10 μ F
470 kΩ
Vo
C2
10 μ F Zo
Vi β = 120, ro = 40 kΩ
Ii C1

Zi 0.56 kΩ CE
10 μ F

FIG. 5.32
Example 5.3.

Solution:
a. DC:
VCC - VBE 20 V - 0.7 V
IB = = = 35.89 mA
RB + (b + 1)RE 470 k + (121)0.56 k
IE = (b + 1)IB = (121)(35.89 mA) = 4.34 mA
26 mV 26 mV
and re = = = 5.99 ⍀
IE 4.34 mA
b. Testing the condition ro Ú 10(RC + RE), we obtain CE EMITTER-BIAS 271
CONFIGURATION
40 k Ú 10(2.2 k + 0.56 k)
40 k Ú 10(2.76 k) = 27.6 k (satisfied)
Therefore,
Zb ⬵ b(re + RE) = 120(5.99  + 560 )
= 67.92 k
and Zi = RB Zb = 470 k 7 67.92 k
7
= 59.34 k⍀
c. Zo = RC = 2.2 k⍀
d. ro Ú 10RC is satisfied. Therefore,
Vo bRC (120)(2.2 k)
Av = ⬵ - = -
Vi Zb 67.92 k
= ⴚ3.89
compared to -3.93 using Eq. (5.20): Av ⬵ -RC>RE.

EXAMPLE 5.4 Repeat the analysis of Example 5.3 with CE in place.

Solution:
a. The dc analysis is the same, and re = 5.99 .
b. RE is “shorted out” by CE for the ac analysis. Therefore,
Zi = RB 7 Zb = RB 7 bre = 470 k 7 (120)(5.99 )
= 470 k 7 718.8  ⬵ 717.70 ⍀
c. Zo = RC = 2.2 k⍀
RC
d. Av = -
re
2.2 k
= - = ⴚ367.28 (a significant increase)
5.99 

EXAMPLE 5.5 For the network of Fig. 5.33 (with CE unconnected), determine (using
appropriate approximations):
a. re.
b. Zi.
c. Zo.
d. Av.

16 V

Io

2.2 kΩ
90 kΩ

+
C2
Vi β = 210, ro = 50 kΩ
Ii C1
Zo
Vo
Zi 10 kΩ
0.68 kΩ CE

FIG. 5.33
Example 5.5.
272 BJT AC ANALYSIS Solution:
a. Testing bRE 7 10R2,
(210)(0.68 k) 7 10(10 k)
142.8 k 7 100 k (satisfied)
we have
R2 10 k
VB = V = (16 V) = 1.6 V
R1 + R2 CC 90 k + 10 k
VE = VB - VBE = 1.6 V - 0.7 V = 0.9 V
VE 0.9 V
IE = = = 1.324 mA
RE 0.68 k
26 mV 26 mV
re = = = 19.64 ⍀
IE 1.324 mA
b. The ac equivalent circuit is provided in Fig. 5.34. The resulting configuration is differ-
ent from Fig. 5.30 only by the fact that now
RB = R = R1 7 R2 = 9 k

Ii +
+ Io
Zo
Zi 2.2 kΩ Vo
Vi 10 kΩ 90 kΩ
0.68 kΩ
– –

R'

FIG. 5.34
The ac equivalent circuit of Fig. 5.33.

The testing conditions of ro Ú 10(RC + RE) and ro Ú 10RC are both satisfied. Using
the appropriate approximations yields
Zb ⬵ bRE = 142.8 k
Zi = RB 7 Zb = 9 k 7 142.8 k
= 8.47 k⍀
c. Zo = RC = 2.2 k⍀
RC 2.2 k
d. Av = - = - = ⴚ3.24
RE 0.68 k

EXAMPLE 5.6 Repeat Example 5.5 with CE in place.

Solution:
a. The dc analysis is the same, and re = 19.64 ⍀.
b. Zb = bre = (210)(19.64 ) ⬵ 4.12 k
Zi = RB 7 Zb = 9 k 7 4.12 k
= 2.83 k⍀
c. Zo = RC = 2.2 k⍀
RC 2.2 k
d. Av = - = - = ⴚ112.02 (a significant increase)
re 19.64 

Another variation of an emitter-bias configuration is shown in Fig. 5.35. For the dc

analysis, the emitter resistance is RE1 + RE2, whereas for the ac analysis, the resistor RE in
the equations above is simply RE1 with RE2 bypassed by CE.
 VCC EMITTER-FOLLOWER 273
CONFIGURATION
Io
RC
RB C2
Vo
C1
Vi

Ii

RE Zo
1
Zi

RE CE
2

FIG. 5.35
An emitter-bias configuration with a
portion of the emitter-bias resistance
bypassed in the ac domain.

5.8 EMITTER-FOLLOWER CONFIGURATION

●
When the output is taken from the emitter terminal of the transistor as shown in Fig. 5.36,
the network is referred to as an emitter-follower. The output voltage is always slightly less
than the input signal due to the drop from base to emitter, but the approximation Av ⬵ 1
is usually a good one. Unlike the collector voltage, the emitter voltage is in phase with the
signal Vi. That is, both Vo and Vi attain their positive and negative peak values at the same
time. The fact that Vo “follows” the magnitude of Vi with an in-phase relationship accounts
for the terminology emitter-follower.

VCC

RB C
Ii
B
Vi
C1 C2
E Vo
Io
Zi RE

Zo

FIG. 5.36
Emitter-follower configuration.

The most common emitter-follower configuration appears in Fig. 5.36. In fact, because
the collector is grounded for ac analysis, it is actually a common-collector configuration.
Other variations of Fig. 5.36 that draw the output off the emitter with Vo ⬵ Vi will appear
later in this section.
The emitter-follower configuration is frequently used for impedance-matching pur-
poses. It presents a high impedance at the input and a low impedance at the output, which
is the direct opposite of the standard fixed-bias configuration. The resulting effect is much
the same as that obtained with a transformer, where a load is matched to the source imped-
ance for maximum power transfer through the system.
Substituting the re equivalent circuit into the network of Fig. 5.36 results in the network
of Fig. 5.37. The effect of ro will be examined later in the section.
274 BJT AC ANALYSIS Ii
b c
Ib
+
β re β Ib

Zi
Vi RB

e
+
Io

Zb Zo Vo
RE
– Ie = ( β + 1) Ib –

FIG. 5.37
Substituting the re equivalent circuit into the ac
equivalent network of Fig. 5.36.

Zi The input impedance is determined in the same manner as described in the preceding
section:

Zi = RB 7 Zb (5.31)

with Zb = bre + (b + 1)RE (5.32)

or Zb ⬵ b(re + RE) (5.33)

and Zb ⬵ bRE RE W re
(5.34)

Zo The output impedance is best described by first writing the equation for the current Ib,
Vi
Ib =
Zb
and then multiplying by (b + 1) to establish Ie. That is,
Vi
Ie = (b + 1)Ib = (b + 1)
Zb
Substituting for Zb gives
(b + 1)Vi
Ie =
bre + (b + 1)RE
Vi
or Ie =
[bre >(b + 1)] + RE
but (b + 1) ⬵ b
bre bre
and ⬵ = re
b + 1 b
re
Vo
Vi
+ Ie so that Ie ⬵ (5.35)
re + RE
Vi RE
Zo
– If we now construct the network defined by Eq. (5.35), the configuration of Fig. 5.38
results.
To determine Zo, Vi is set to zero and
FIG. 5.38
Defining the output impedance for
Zo = RE 7 re (5.36)
the emitter-follower configuration.
Because RE is typically much greater than re, the following approximation is often applied: EMITTER-FOLLOWER 275
CONFIGURATION
Zo ⬵ r e (5.37)

Av Figure 5.38 can be used to determine the voltage gain through an application of the
voltage-divider rule:
REVi
Vo =
RE + re

Vo RE
and Av = = (5.38)
Vi RE + re

Because RE is usually much greater than re, RE + re ⬵ RE and

Vo
Av = ⬵1 (5.39)
Vi

Phase Relationship As revealed by Eq. (5.38) and earlier discussions of this section, Vo
and Vi are in phase for the emitter-follower configuration.

Effect of ro
Zi

(b + 1)RE
Zb = bre + (5.40)
RE
1 +
ro

If the condition ro Ú 10RE is satisfied,

Zb = bre + (b + 1)RE
which matches earlier conclusions with

Zb ⬵ b(re + RE) ro Ú 10RE

(5.41)

Zo

bre
Zo = ro 储 RE 储 (5.42)
(b + 1)

Using b + 1 ⬵ b, we obtain
Zo = ro 7 RE 7 re
and because ro W re,

Zo ⬵ RE 7 re Any ro
(5.43)

Av

(b + 1)RE>Zb
Av = (5.44)
RE
1 +
ro

If the condition ro Ú 10RE is satisfied and we use the approximation b + 1 ⬵ b, we find

bRE
Av ⬵
Zb
276 BJT AC ANALYSIS But Zb ⬵ b(re + RE)
bRE
so that Av ⬵
b(re + RE)

RE
and Av ⬵ (5.45)
re + RE ro Ú 10RE

EXAMPLE 5.7 For the emitter-follower network of Fig. 5.39, determine:

a. re.
b. Zi.
c. Zo.
d. Av.
e. Repeat parts (b) through (d) with ro = 25 k and compare results.
12 V

RB 220 kΩ
10 μ F
Vi β = 100, ro = ∞ Ω

Ii 10 μ F
Vo

Io

Zi RE 3.3 kΩ

Zo

FIG. 5.39
Example 5.7.
Solution:
VCC - VBE
a. IB =
RB + (b + 1)RE
12 V - 0.7 V
= = 20.42 mA
220 k + (101)3.3 k
IE = (b + 1)IB
= (101)(20.42 mA) = 2.062 mA
26 mV 26 mV
re = = = 12.61 ⍀
IE 2.062 mA
b. Zb = bre + (b + 1)RE
= (100)(12.61 ) + (101)(3.3 k)
= 1.261 k + 333.3 k
= 334.56 k ⬵ bRE
Zi = RB 7 Zb = 220 k 7 334.56 k
= 132.72 k⍀
c. Zo = RE 7 re = 3.3 k 7 12.61 
= 12.56 ⍀ ⬵ re
Vo RE 3.3 k
d. Av = = =
Vi RE + re 3.3 k + 12.61 
= 0.996 @ 1
e. Checking the condition ro Ú 10RE, we have COMMON-BASE 277
CONFIGURATION
25 k Ú 10(3.3 k) = 33 k
which is not satisfied. Therefore,
(b + 1)RE (100 + 1)3.3 k
Zb = bre + = (100)(12.61 ) +
RE 3.3 k
1 + 1 +
ro 25 k
=
1.261 k + 294.43 k
=
295.7 k
with RB 7 Zb = 220 k 7 295.7 k
Zi =
=
126.15 k⍀ vs. 132.72 k obtained earlier
RE 7 re = 12.56 ⍀ as obtained earlier
Zo =
(b + 1)RE >Zb (100 + 1)(3.3 k)>295.7 k
Av = =
RE 3.3 k
c1 + d c1 + d
ro 25 k
= 0.996 @ 1
matching the earlier result.

In general, therefore, even though the condition ro Ú 10RE is not satisfied, the results
for Zo and Av are the same, with Zi only slightly less. The results suggest that for most ap-
plications a good approximation for the actual results can be obtained by simply ignoring
the effects of ro for this configuration.
The network of Fig. 5.40 is a variation of the network of Fig. 5.36, which employs
a voltage-divider input section to set the bias conditions. Equations (5.31) to (5.34) are
changed only by replacing RB by R = R1 7 R2.
The network of Fig. 5.41 also provides the input/output characteristics of an emitter-
follower, but includes a collector resistor RC. In this case RB is again replaced by the parallel
combination of R1 and R2. The input impedance Zi and output impedance Zo are unaffected
by RC because it is not reflected into the base or emitter equivalent networks. In fact, the
only effect of RC is to determine the Q-point of operation.

VCC VCC

RC
R1 R1

Ii C1
Vi Vi
C1 C2 C2
Vo Vo
R2 R2 Io
Zi Io Zi
RE RE
Zo Zo

FIG. 5.40 FIG. 5.41

Emitter-follower configuration with a Emitter-follower configuration with
voltage-divider biasing arrangement. a collector resistor RC.

5.9 COMMON-BASE CONFIGURATION

●
The common-base configuration is characterized as having a relatively low input and a high
output impedance and a current gain less than 1. The voltage gain, however, can be quite
large. The standard configuration appears in Fig. 5.42, with the common-base re equivalent
model substituted in Fig. 5.43. The transistor output impedance ro is not included for the
 Ic
Ii Ie Ic e Ie c

+ E C + + Ii Io
+
Io
RE RC Vi RE re α Ie RC Vo Zo
Vi Zi Vo Zo Zi
+ B – – –
V EE VCC
– – + –

FIG. 5.42 FIG. 5.43

Common-base configuration. Substituting the re equivalent circuit into the ac equivalent network
of Fig. 5.44.

common-base configuration because it is typically in the megohm range and can be ignored
in parallel with the resistor RC.
Zi
Zi = RE 7 re (5.46)
Zo
Zo = RC (5.47)

Av
Vo = -Io RC = -(-Ic)RC = aIe RC
Vi
with Ie =
re
Vi
so that Vo = a a bR
re C

Vo aRC RC
and Av = = ⬵ (5.48)
Vi re re

Ai Assuming that RE W re yields

Ie = Ii
and Io = -aIe = -aIi

Io
with Ai = = -a ⬵ -1 (5.49)
Ii

Phase Relationship The fact that Av is a positive number shows that Vo and Vi are in
phase for the common-base configuration.

Effect of ro For the common-base configuration, ro = 1>hob is typically in the megohm

range and sufficiently larger than the parallel resistance RC to permit the approximation
ro 7 RC ⬵ RC.

EXAMPLE 5.8 For the network of Fig. 5.44, determine:

a. re.
10 μ F Ie ⬵ Ii 10 μF
b. Zi.
c. Zo. + Io +
d. Av. Ii
RE 1 kΩ α = 0.98 RC 5 kΩ
e. Ai. Vi ro = 1 MΩ Vo
Zi + – Zo
2V 8V
– – + –

FIG. 5.44
Example 5.8.
278
Solution: COLLECTOR FEEDBACK 279
CONFIGURATION
VEE - VBE 2 V - 0.7 V 1.3 V
a. IE = = = = 1.3 mA
RE 1 k 1 k
26 mV 26 mV
re = = = 20 ⍀
IE 1.3 mA
b. Zi = RE 7 re = 1 k 7 20 
= 19.61 ⍀ ⬵ re
c. Zo = RC = 5 k⍀
RC 5 k
d. Av ⬵ = = 250
re 20 
e. Ai = ⴚ0.98 ⬵ -1

5.10 COLLECTOR FEEDBACK CONFIGURATION

●
The collector feedback network of Fig. 5.45 employs a feedback path from collector to
base to increase the stability of the system as discussed in Section 4.6. However, the sim-
ple maneuver of connecting a resistor from base to collector rather than base to dc supply
has a significant effect on the level of difficulty encountered when analyzing the network.
Some of the steps to be performed below are the result of experience working with
such configurations. It is not expected that a new student of the subject would choose
the sequence of steps described below without taking a wrong step or two. Substituting the
equivalent circuit and redrawing the network results in the configuration of Fig. 5.46. The
effects of a transistor output resistance ro will be discussed later in the section.

VCC

RC
RF Io
Vo
C2
C
B – RF + C Io
Ii
B + Ii Ib Ic +
Vi I'
Zo
C1 Vi β re β Ib RC Zo V
o
Zi
E
Zi – –

FIG. 5.45 FIG. 5.46

Collector feedback configuration. Substituting the re equivalent circuit into the ac
equivalent network of Fig. 5.45.

Zi
Io = I + bIb
Vo - Vi
and I =
RF
but Vo = -Io RC = -(I + bIb)RC
with Vi = Ibbre
(I + bIb)RC - Ibbre IRC bIb RC Ibbre
so that I = - = - - -
RF RF RF RF
which when rearranged in the following:
RC (RC + re)
Ia 1 + b = -bIb
RF RF
280 BJT AC ANALYSIS (RC + re)
and finally, I = -bIb
RC + RF
Vi
Now Zi = :
Ii
(RC + re)
and Ii = Ib - I = Ib + bIb
RC + RF
(RC + re)
or Ii = Ib a 1 + b b
RC + RF
Substituting for Vi in the above equation for Zi leaves
Vi Ibbre bre
Zi = = =
Ii (RC + r e) (RC + re)
Ib a 1 + b b 1 + b
RC + RF RC + RF

Since RC W re
bre
Zi =
bRC
1 +
RC + RF

re
or Zi = (5.50)
1 RC
+
b RC + RF

Zo If we set Vi to zero as required to define Zo, the network will appear as shown in Fig. 5.47.
The effect of bre is removed, and RF appears in parallel with RC and

Zo ⬵ RC 7 RF (5.51)

RF

Ib = 0 A

Vi = 0 β re β Ib = 0 A RC Zo

FIG. 5.47
Defining Zo for the collector feedback configuration.

Av
Vo = -Io RC = -(I + bIb)RC
(RC + re)
= - a -bIb + bIb b RC
RC + RF
(RC + re
or Vo = -bIb a 1 - bR
RC + RF C
Then
(RC + re)
-bIb a 1 - b RC
Vo RC + RF
Av = =
Vi bre Ib
(RC + re) RC
= - a1 - b
RC + RF re
For RC W re
RC RC
Av = - a 1 - b
RC + RF re
 (RC + RF - RC) RC COLLECTOR FEEDBACK 281
or Av = - CONFIGURATION
RC + RF re

RF RC
and Av = - a b (5.52)
RC + RF re

For RF W RC

RC
Av ⬵ - (5.53)
re

Phase Relationship The negative sign of Eq. (5.52) indicates a 180° phase shift between
Vo and Vi.

Effect of ro
Zi A complete analysis without applying approximations results in

RC 7 ro
1 +
RF
Zi = (5.54)
1 1 RC 储 ro RC 储 ro
+ + +
bre RF bre RF RFre

Applying the condition ro Ú 10RC, we obtain

RC RC
1 + re c 1 + d
RF RF
Zi = =
1 1 RC RC 1 1 RC
+ + + + cr + + RC d
bre RF bre RF RFre b RF e b
RC
Applying RC W re and ,
b
RC RF + RC
re c 1 + d re c d
RF RF re
Zi ⬵ = =
1 RC RF + bRC 1 RF RC
+ a b +
b RF bRF b RF + RC RC + RF
RF
but, since RF typically W RC, RF + RC ⬵ RF and = 1
RF + RC
re
Zi ⬵ (5.55)
1 RC
+
b RC + RF ro W RC, RF 7 RC

as obtained earlier.

Zo Including ro in parallel with RC in Fig. 5.47 results in

Zo = ro 7 RC 7 RF (5.56)

For ro Ú 10RC,

Zo ⬵ RC 7 RF ro Ú 10RC
(5.57)

as obtained earlier. For the common condition of RF W RC,

Zo ⬵ RC ro Ú 10RC,RF W RC
(5.58)
282 BJT AC ANALYSIS Av

RF RC 储 ro
Av = - a b (5.59)
RC 储 ro + RF re

For ro Ú 10RC,

RF RC
Av ⬵ - a b (5.60)
RC + RF re
ro Ú 10RC

and for RF W RC

RC
Av ⬵ - (5.61)
re
ro Ú 10RC, RF Ú RC

as obtained earlier.

EXAMPLE 5.9 For the network of Fig. 5.48. determine:

a. re.
b. Zi.
c. Zo.
d. Av.
e. Repeat parts (b) through (d) with ro = 20 k and compare results.

9V

2.7 kΩ

180 kΩ Io
Vo
Ii 10 μF
Vi β = 200, ro = ∞ Ω
10 μF
Zo
Zi

FIG. 5.48
Example 5.9.

Solution:
VCC - VBE 9 V - 0.7 V
a. IB = =
RF + bRC 180 k + (200)2.7 k
= 11.53 mA
IE = (b + 1)IB = (201)(11.53 mA) = 2.32 mA
26 mV 26 mV
re = = = 11.21 ⍀
IE 2.32 mA
re 11.21  11.21 
b. Zi = = =
1 RC 1 2.7 k 0.005 + 0.0148
+ +
b RC + RF 200 182.7 k
11.21 
= = 566.16 ⍀
0.0198
c. Zo = RC 7 RF = 2.7 k 7 180 k = 2.66 k⍀
RC 2.7 k
d. Av = - = - = ⴚ240.86
re 11.21 
e. Zi: The condition ro Ú 10RC is not satisfied. Therefore, COLLECTOR FEEDBACK 283
CONFIGURATION
RC 7 ro 2.7 k 7 20 k
1 + 1 +
RF 180 k
Zi = =
1 1 RC 兩兩ro RC 兩兩 ro 1 1 2.7 k 兩兩 20 k 2.7 k 兩兩 20 k
+ + + + + +
bre RF breRF RFre (200)(11.21) 180 k (200)(11.21 )(180 k) (180 k)(11.21 )
2.38 k
1 +
180 k 1 + 0.013
= =
-3 -3
0.45 * 10 + 0.006 * 10 + 5.91 * 10 + 1.18 * 10 -6 -3
1.64 * 10-3
= 617.7 ⍀ vs. 566.16  above
Zo:
Zo = ro 7 RC 7 RF = 20 k 7 2.7 k 7 180 k
= 2.35 k⍀ vs. 2.66 k above
Av:
RF RC 储 ro 180 k 2.38 k
= -a b = -c d
RC 储 ro + RF re 2.38 k + 180 k 11.21
= - 3 0.987 4 212.3
= ⴚ209.54

For the configuration of Fig. 5.49, Eqs. (5.61) through (5.63) determine the variables of
interest. The derivations are left as an exercise at the end of the chapter.

VCC

RC
RF Io
Vo
Ii C2
Vi
C1
Zo
Zi
RE

FIG. 5.49
Collector feedback configuration with an emitter resistor RE.

Zi

RE
Zi ⬵ (5.62)
1 (RE + RC)
c + d
b RF

Zo

Zo = RC 7 RF (5.63)
Av

RC
Av ⬵ - (5.64)
RE
284 BJT AC ANALYSIS 5.11 COLLECTOR DC FEEDBACK CONFIGURATION
●
The network of Fig. 5.50 has a dc feedback resistor for increased stability, yet the capacitor
C3 will shift portions of the feedback resistance to the input and output sections of the net-
work in the ac domain. The portion of RF shifted to the input or output side will be deter-
mined by the desired ac input and output resistance levels.

VCC

RC
RF RF Io
1 2
Vo
C2
C3
C1
Vi
Zo
Ii

Zi

FIG. 5.50
Collector dc feedback configuration.

At the frequency or frequencies of operation, the capacitor will assume a short-circuit

equivalent to ground due to its low impedance level compared to the other elements of the
network. The small-signal ac equivalent circuit will then appear as shown in Fig. 5.51.

Ii
Ib
+ Io +
Zi RF β re β Ib ro RF RC
Vi 1 2 Vo

Zo
– –

R'

FIG. 5.51
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.50.

Zi

Zi = RF1 7 bre (5.65)

Zo

Zo = RC 7 RF2 7 ro (5.66)

For ro Ú 10RC,

Zo ⬵ RC 7 RF2 (5.67)
ro Ú 10RC

Av
R = ro 7 RF2 7 RC
and Vo = -bIbR
Vi
but Ib =
bre
 Vi COLLECTOR 285
and Vo = -b R DC FEEDBACK
bre
CONFIGURATION
so that

Vo ro 7 RF2 7 RC
Av = = - (5.68)
Vi re

For ro Ú 10RC,

Vo RF2 7 RC
Av = ⬵ - (5.69)
Vi re
ro Ú 10RC

Phase Relationship The negative sign in Eq. (5.68) clearly reveals a 180° phase shift
between input and output voltages.

EXAMPLE 5.10 For the network of Fig. 5.52, determine:

a. re.
b. Zi.
c. Zo.
d. Av.
e. Vo if Vi  2 mV

12 V

3 kΩ

120 kΩ 68 kΩ Io
Vo
10 μF
0.01 μF
Ii Zo
Vi β = 140, ro = 30 k Ω
10 μF

Zi

FIG. 5.52
Example 5.10.

Solution:
VCC - VBE
a. DC: IB =
RF + bRC
12 V - 0.7 V
=
(120 k + 68 k) + (140)3 k
11.3 V
= = 18.6 mA
608 k
IE = (b + 1)IB = (141)(18.6 mA)
= 2.62 mA
26 mV 26 mV
re = = = 9.92 ⍀
IE 2.62 mA
b. bre = (140)(9.92 ) = 1.39 k
The ac equivalent network appears in Fig. 5.53.
Zi = RF1 7 bre = 120 k 7 1.39 k
⬵ 1.37 k⍀
286 BJT AC ANALYSIS Ib
+ Ii Io +
β re β Ib ro
120 kΩ 68 kΩ 3 kΩ
Vi 1.395 kΩ 140 Ib 30 kΩ Vo

Zi
Zo
– –

FIG. 5.53
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.52.

c. Testing the condition ro Ú 10RC, we find

30 k Ú 10(3 k) = 30 k
which is satisfied through the equals sign in the condition. Therefore,
Zo ⬵ RC 7 RF2 = 3 k 7 68 k
= 2.87 k⍀
d. ro Ú 10RC; therefore,
RF2 7 RC 68 k 7 3 k
Av ⬵ - = -
re 9.92 
2.87 k
⬵ -
9.92 
⬵ ⴚ289.3
Vo
e. 兩 Av 兩 = 289.3 =
Vi
Vo = 289.3Vi = 289.3(2 mV) = 0.579 V

5.12 EFFECT OF RL AND RS

●
All the parameters determined in the last few sections have been for an unloaded amplifier
with the input voltage connected directly to a terminal of the transistor. In this section the
effect of applying a load to the output terminal and the effect of using a source with an
internal resistance will be investigated. The network of Fig. 5.54a is typical of those inves-
tigated in the previous section. Because a resistive load was not attached to the output ter-
minal, the gain is commonly referred to as the no-load gain and given the following
notation:

Vo
AvNL = (5.70)
Vi

In Fig. 5.54b a load has been added in the form of a resistor RL, which will change the
overall gain of the system. This loaded gain is typically given the following notation:

Vo
AvL = (5.71)
Vi
with RL

In Fig. 5.54c both a load and a source resistance have been introduced, which will have
an additional effect on the gain of the system. The resulting gain is typically given the fol-
lowing notation:

Vo
Avs = (5.72)
Vs
with RL and Rs

The analysis to follow will show that:

The loaded voltage gain of an amplifier is always less than the no-load gain.
 VCC VCC VCC

RC RC RC
RB RB RB

+ + +

+ + Rs
Vo
RL
Vo + RL
Vo
Vi Vi Vs
–
– – – – –

Vo Vo Vo
Av = Av = Av =
NL Vi L Vi s Vs

(a) (b) (c)

FIG. 5.54
Amplifier configurations: (a) unloaded; (b) loaded; (c) loaded with a source resistance.

In other words, the addition of a load resistor RL to the configuration of Fig. 5.54a will
always have the effect of reducing the gain below the no-load level.
Furthermore:
The gain obtained with a source resistance in place will always be less than that
obtained under loaded or unloaded conditions due to the drop in applied voltage across
the source resistance.
In total, therefore, the highest gain is obtained under no-load conditions and the lowest
gain with a source impedance and load in place. That is:
For the same configuration AvNL + AvL + Avs.
It will also be interesting to verify that:
For a particular design, the larger the level of RL, the greater is the level of ac gain.
In other words, the larger the load resistance, the closer it is to an open-circuit approxi-
mation that would result in the higher no-load gain.
In addition:
For a particular amplifier, the smaller the internal resistance of the signal source, the
greater is the overall gain.
In other words, the closer the source resistance is to a short-circuit approximation, the
greater is the gain because the effect of Rs will essentially be eliminated.
For any network, such as those shown in Fig. 5.54 that have coupling capacitors, the
source and load resistance do not affect the dc biasing levels.
The conclusions listed above are all quite important in the amplifier design process.
When one purchases a packaged amplifier, the listed gain and all the other parameters are
for the unloaded situation. The gain that results due to the application of a load or source
resistance can have a dramatic effect on all the amplifier parameters, as will be demon-
strated in the examples to follow.
In general, there are two directions one can take to analyze networks with an applied
load and/or source resistance. One approach is to simply insert the equivalent circuit, as
was demonstrated in Section 5.11, and use methods of analysis to determine the quantities
of interest. The second is to define a two-port equivalent model and use the parameters
determined for the no-load situation. The analysis to follow in this section will use the first
approach, leaving the second method for Section 5.14.
For the fixed-bias transistor amplifier of Fig. 5.54c, substituting the re equivalent circuit
for the transistor and removing the dc parameters results in the configuration of Fig. 5.55.
287
288 BJT AC ANALYSIS Ib
+ Rs + +
Zo
Vs Vi RB β re β Ib ro RC RL Vo
Zi
–
– –
–
RL = ro RC RL ≅ RC RL

FIG. 5.55
The ac equivalent network for the network of Fig. 5.54c.

It is particularly interesting that Fig. 5.55 is exactly the same in appearance as Fig. 5.22
except that now there is a load resistance in parallel with RC and a source resistance has
been introduced in series with a source Vs.
The parallel combination of
RL = ro 7 RC 7 RL ⬵ RC 7 RL
and Vo = -bIbRL = -bIb(RC 7 RL)
Vi
with Ib =
bre
Vi
gives Vo = -ba b (RC 7 RL)
bre

Vo RC 7 RL
so that AvL = = - (5.73)
Vi re

The only difference in the gain equation using Vi as the input voltage is the fact that RC
of Eq. (5.10) has been replaced by the parallel combination of RC and RL. This makes good
sense because the output voltage of Fig. 5.55 is now across the parallel combination of the
two resistors.
The input impedance is

Zi = RB 7 bre (5.74)

as before, and the output impedance is

Zo = RC 7 ro (5.75)

as before.
If the overall gain from signal source Vs to output voltage Vo is desired, it is only neces-
sary to apply the voltage-divider rule as follows:
ZiVs
Vi =
Zi + Rs
Vi Zi
and =
Vs Zi + Rs

or AvS =
Vo
= # = AvL Zi
Vo Vi
Vs Vi Vs Zi + Rs

Zi
so that AvS = A (5.76)
Zi + Rs vL

Because the factor Zi >(Zi + Rs) must always be less than one, Eq. (5.76) clearly supports
the fact that the signal gain AvS is always less than the loaded gain AvL.
 EFFECT OF R L AND R S 289
EXAMPLE 5.11 Using the parameter values for the fixed-bias configuration of Example 5.1
with an applied load of 4.7 k and a source resistance of 0.3 k, determine the following
and compare to the no-load values:
a. AvL.
b. Avs.
c. Zi.
d. Zo.

Solution:
RC 7 RL 3 k 7 4.7 k 1.831 k
a. Eq. (5.73): AvL = - = - = - = ⴚ170.98
re 10.71  10.71 
which is significantly less than the no-load gain of -280.11.
Zi
b. Eq. (5.76): Avs = A
Zi + Rs vL
With Zi = 1.07 k from Example 5.1, we have
1.07 k
Avs = (-170.98) = ⴚ133.54
1.07 k + 0.3 k
which again is significantly less than AvNL or AvL.
c. Zi = 1.07 k⍀ as obtained for the no-load situation.
d. Zo = RC = 3 k⍀ as obtained for the no-load situation.
The example clearly demonstrates that AvNL 7 AvL 7 Avs.

For the voltage-divider configuration of Fig. 5.56 with an applied load and series source
resistor the ac equivalent network is as shown in Fig. 5.57.

VCC

RC
C2
R1

Ib
+
Rs

C1
+
+ RL Vo
R2 Zo
Vs Vi
– Zi RE CE
– –

FIG. 5.56
Voltage-divider bias configuration with Rs and RL.

Ii
Rs Io
b Ib c
+ + +
Zi
Vs Vi R1 R2 β re β Ib ro RC RL Vo

– – e e Zo –

R'

FIG. 5.57
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.56.
290 BJT AC ANALYSIS First note the strong similarities with Fig. 5.55, with the only difference being the par-
allel connection of R1 and R2 instead of just RB. Everything else is exactly the same. The
following equations result for the important parameters of the configuration:

Vo RC 7 RL
AvL = = - (5.77)
Vi re

Zi = R1 7 R2 7 bre (5.78)

Zo = RC 7 ro (5.79)

For the emitter-follower configuration of Fig. 5.58 the small-signal ac equivalent net-
work is as shown in Fig. 5.59. The only difference between Fig. 5.59 and the unloaded
configuration of Fig. 5.37 is the parallel combination of RE and RL and the addition of the
source resistor Rs. The equations for the quantities of interest can therefore be determined
by simply replacing RE by RE 7 RL wherever RE appears. If RE does not appear in an equation,
the load resistor RL does not affect that parameter. That is,

Vo RE 7 RL
AvL = = (5.80)
Vi RE 7 RL + re

VCC

RB C

Ii
B

Rs C1
+ C2 Io
+ Vo
Vs Vi
Zi
– RE RL
Zo
–

FIG. 5.58
Emitter-follower configuration with Rs and RL.

Ii
b c
Ib
Rs +
β re βIb
Zi

+
Vs Vi RB
Io
– e +
Zo
RE RL Vo
–
–

FIG. 5.59
Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.58.
 DETERMINING THE 291
Zi = RB 7 Zb (5.81) CURRENT GAIN

Zb ⬵ b(RE 7 RL) (5.82)

Zo ⬵ r e (5.83)

The effect of a load resistor and a source impedance on the remaining BJT configura-
tions will not be examined in detail here, although Table 5.1 in Section 5.14 will review
the results for each configuration.

5.13 DETERMINING THE CURRENT GAIN

●
You may have noticed in the previous sections that the current gain was not determined for
each configuration. Earlier editions of this text did have the details of finding that gain, but
in reality the voltage gain is usually the gain of most importance. The absence of the deri-
vations should not cause concern because:
For each transistor configuration, the current gain can be determined directly from the
voltage gain, the defined load, and the input impedance.
The derivation of the equation linking the voltage and current gains can be derived using
the two-port configuration of Fig. 5.60.

Ii Io

+ +
Zi Zo
Vi System Vo RL

– –

FIG. 5.60
Determining the current gain using the voltage gain.

The current gain is defined by

Io
Ai = (5.84)
Ii
Applying Ohm’s law to the input and output circuits results in
Vi Vo
Ii = and Io = -
Zi RL
The minus sign associated with the output equation is simply there to indicate that the polar-
ity of the output voltage is determined by an output current having the opposite direction. By
definition, the input and output currents have a direction entering the two-port configuration.
Substituting into Eq. (5.84) then results in
Vo
-
= - #
Io RL Vo Zi
AiL = =
Ii Vi Vi RL
Zi
and the following important equation:

Zi
AiL = -AvL (5.85)
RL

The value of RL is defined by the location of Vo and Io.

292 BJT AC ANALYSIS To demonstrate the validity of Eq. (5.82), consider the voltage-divider bias configura-
tion of Fig. 5.28.
Using the results of Example 5.2, we find
Vi Vi Vo Vo
Ii = = and Io = - = -
Zi 1.35 k⍀ RL 6.8 k⍀

Vo
a- b
Io 6.8 k⍀ Vo 1.35 k⍀
so that AiL = = = -a ba b
Ii Vi Vi 6.8 k⍀
1.35 k⍀
1.35 k⍀
= -(-368.76)a b = 73.2
6.8 k⍀
Zi 1.35 k⍀
Using Eq. 5.82: AiL = -AvL = -(-368.76)a b = 73.2
RL 6.8 k⍀
which has the same format as the resulting equation above and the same result.
The solution to the current gain in terms of the network parameters will be more com-
plicated for some configurations if a solution is desired in terms of the network parameters.
However, if a numerical solution is all that is desired, it is simply a matter of substituting
the value of the three parameters from an analysis of the voltage gain.
As a second example, consider the common-base bias configuration of Section 5.9. In
this case the voltage gain is
RC
AvL ⬵
re
and the input impedance is
Zi ⬵ RE 7 re ⬵ re
with RL defined as RC due to the location of Io.
The result is the following:
Zi RC re
AiL = -AvL = a - b a b ⬵ -1
RL r e RC
which agrees with the solution of that section because Ic ⬵ Ie. Note, in this case, that the
output current has the opposite direction to that appearing in the networks of that section
due to the minus sign.

5.14 SUMMARY TABLES

●
The last few sections have included a number of derivations for unloaded and loaded BJT
configurations. The material is so extensive that it seemed appropriate to review most of
the conclusions for the various configurations in summary tables for quick comparisons.
Although the equations using the hybrid parameters have not been discussed in detail at
this point, they are included to make the tables complete. The use of hybrid parameters
will be considered in a later section of this chapter. In each case the waveforms included
demonstrate the phase relationship between input and output voltages. They also reveal the
relative magnitude of the voltages at the input and output terminals.
Table 5.1 is for the unloaded situation, whereas Table 5.2 includes the effect of Rs and RL.

5.15 TWO-PORT SYSTEMS APPROACH

●
In the design process, it is often necessary to work with the terminal characteristics of a
device rather then the individual components of the system. In other words, the designer is
handed a packaged product with a list of data regarding its characteristics but has no access
to the internal construction. This section will relate the important parameters determined
for a number of configurations in the previous sections to the important parameters of this
packaged system. The result will be an understanding of how each parameter of the
 TABLE 5.1
Unloaded BJT Transistor Amplifiers

Configuration Zi Zo Av Ai
Fixed-bias: Medium (1 k) Medium (2 k) High (- 200) High (100)
VCC
Io = RB 7 bre = RC 7 r o (RC 7 ro) bRBro
RC = - =
RB re (ro + RC)(RB + bre)
Ii
+ ⬵ bre ⬵ RC
Vo RC ⬵ b
+ Zo
– (RB Ú 10bre) (ro Ú 10RC) ⬵ -
Vi re
Zi (ro Ú 10RC,
–
(ro Ú 10RC) RB Ú 10bre)

Voltage-divider Medium (1 k) Medium (2 k) High (- 200) High (50)

bias: VCC
Io RC = R1 7 R2 7 bre = RC 7 r o RC 7 r o b(R1 7 R2)ro
R1 = - =
Ii
re (ro + RC)(R1 7 R2 + bre)
+ ⬵ RC
+ Zo RC b(R1 7 R2)
Vo (ro Ú 10RC) ⬵ - ⬵
Vi Zi R2 re R1 7 R2 + bre
RE CE
– – (ro Ú 10RC) (ro Ú 10RC)

Unbypassed High (100 k) Medium (2 k) Low (- 5) High (50)

emitter bias: VCC
= RB 7 Zb = RC RC bRB
Io RC = - ⬵ -
RB r e + RE RB + Zb
Ii Zb ⬵ b(re + RE) (any level of ro)
+
+ Zo ⬵ RB 7 bRE ⬵ -
RC
Vo RE
Vi
Zi RE (RE W re)
(RE W re)
– –

Emitter- High (100 k) Low (20 ) Low ( ⬵1) High (- 50)
follower: VCC
= RB 7 Zb = RE 7 r e RE bRB
Ii RB = ⬵ -
RE + r e RB + Zb
Zb ⬵ b(re + RE)
+ ⬵ re
⬵ RB 7 bRE ⬵ 1
Vi Io RE + (RE W re)
Zi Vo
– Zo (RE W re)
–
Common-base: Low (20 ) Medium (2 k) High (200) Low (- 1)
Ii
= RE 7 r e = RC RC ⬵ -1
⬵
+ Io RC + re
Vi Zi
RE
Vo ⬵ re
Zo
VEE VCC
– – (RE W re)

Collector Medium (1 k) Medium (2 k) High (- 200) High (50)

feedback: VCC
Io
RC re ⬵ RC 7 RF RC bRF
RF = ⬵ - =
1 RC re RF + bRC
+ (ro Ú 10RC)
Ii + b RF
(ro Ú 10RC) RF
+ Zo Vo (ro Ú 10RC) ⬵
(RF W RC) RC
Vi Z
o
– –

293
 TABLE 5.2
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

- (RL 储 RC) RB 7 bre RC

re

Including ro:

(RL 7 RC 7 ro)
- RB 7 bre RC 7 r o
re

- (RL 7 RC) R1 7 R2 7 bre RC

re

Including ro:

- (RL 7 RC 7 ro)
R1 7 R2 7 bre RC 7 r o
re

RE = RL 7 RE Rs = Rs 7 R1 7 R2
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

Including ro:
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

- (RL 7 RC) RE 7 r e RC
⬵
re

Including ro:

- (RL 7 RC 7 ro)
⬵ RE 7 r e RC 7 r o
re

VCC

- (RL 7 RC)
R1 7 R2 7 b(re + RE) RC
RC RE
R1
Vo
Rs Vi Including ro:
Zo
- (RL 7 RC)
+ RL R1 7 R2 7 b(re + Re) ⬵ RC
Vs Zi R2 RE
RE
–

294
 TABLE 5.2 (Continued)
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

VCC

- (RL 7 RC)
RC RB 7 b(re + RE1) RC
RB RE1
Vo
Rs Vi

Zo Including ro:
+ RE1 RL
Zi - (RL 7 RC)
Vs RB 7 b(re + RE) ⬵ RC
– REt
RE2 CE

VCC

- (RL 7 RC) RF
RC bre 储 RC
re 兩 Av 兩
RF
Vo

Rs Vi
Zo
Including ro:
+ RL
- (RL 7 RC 7 ro) RF
Vs bre 储 RC 7 RF 7 r o
– Zi re 0 Av 0

VCC

- (RL 7 RC) RF
RC bRE 储 ⬵ RC 7 RF
RE 0 Av 0
RF
Vo

Rs Vi
Zo Including ro:

+ RL - (RL 7 RC) RF
⬵ ⬵ bRE 储 ⬵ RC 7 RF
Vs
Zi RE
L
RE 0 Av 0
–

packaged system relates to the actual amplifier or network. The system of Fig. 5.61 is
called a two-port system because there are two sets of terminals—one at the input and the
other at the output. At this point it is particularly important to realize that
the data surrounding a packaged system is the no-load data.
This should be fairly obvious because the load has not been applied, nor does it come with
the load attached to the package.

Ii Io

+ +
Zi Zo
Vi AvNL Vo

– –

Thévenin

FIG. 5.61
Two-port system.
295
296 BJT AC ANALYSIS For the two-port system of Fig. 5.61 the polarity of the voltages and the direction of
the currents are as defined. If the currents have a different direction or the voltages have
a different polarity from that appearing in Fig. 5.61, a negative sign must be applied.
Note again the use of the label AvNL to indicate that the provided voltage gain will be the
no-load value.
For amplifiers the parameters of importance have been sketched within the boundaries
of the two-port system as shown in Fig. 5.62. The input and output resistance of a packaged
amplifier are normally provided along with the no-load gain. They can then be inserted as
shown in Fig. 5.62 to represent the seated package.

AvNLVi

FIG. 5.62
Substituting the internal elements for the two-port system of Fig. 5.61.

For the no-load situation the output voltage is

Vo = AvNLVi (5.86)

due to the fact that I  0A, resulting in Io Ro = 0V.

The output resistance is defined by Vi  0V. Under such conditions the quantity AvNLVi
is zero volts also and can be replaced by a short-circuit equivalent. The result is

Zo = Ro (5.87)

Finally, the input impedance Zi simply relates the applied voltage to the resulting input
current and

Zi = Ri (5.88)

For the no-load situation, the current gain is undefined because the load current is zero.
There is, however, a no-load voltage gain equal to AvNL.
The effect of applying a load to a two-port system will result in the configuration of
Fig. 5.63. Ideally, all the parameters of the model are unaffected by changing loads and
levels of source resistance. However, for some transistor configurations the applied load
can affect the input resistance, whereas for others the output resistance can be affected by
the source resistance. In all cases, however, by simple definition, the no-load gain is unaf-
fected by the application of any load. In any case, once AvNL, Ri, and Ro are defined for a
particular configuration, the equations about to be derived can be employed.

Av NLVi

FIG. 5.63
Applying a load to the two-port system of Fig. 5.62.
 Applying the voltage-divider rule to the output circuit results in TWO-PORT SYSTEMS 297
RLAvNLVi APPROACH
Vo =
RL + Ro

Vo RL
and AvL = = A (5.89)
Vi RL + Ro vNL

Because the ratio RL >(RL + Ro) is always less than 1, we have further evidence that the
loaded voltage gain of an amplifier is always less than the no-load level.
The current gain is then determined by
Io -Vo >RL Vo Zi
AiL = = = -
Ii Vi >Zi Vi RL

Zi
and AiL = -AvL (5.90)
RL

as obtained earlier. In general, therefore, the current gain can be obtained from the voltage
gain and impedance parameters Zi and RL. The next example will demonstrate the useful-
ness and validity of Eqs. (5.89) and (5.90).
Our attention will now turn to the input side of the two-port system and the effect of an
internal source resistance on the gain of an amplifier. In Fig. 5.64, a source with an internal
resistance has been applied to the basic two-port system. The definitions of Zi and AvNL are
such that:
The parameters Zi and AvNL of a two-port system are unaffected by the internal resis-
tance of the applied source.

Is Ii Io

+ + +
Vs Vi A␷NLVi Vo
Zo
– Zi
– –

FIG. 5.64
Including the effects of the source resistance Rs.

However:
The output impedance may be affected by the magnitude of Rs.
The fraction of the applied signal reaching the input terminals of the amplifier of Fig. 5.64
is determined by the voltage-divider rule. That is,

RiVs
Vi = (5.91)
Ri + Rs

Equation (5.91) clearly shows that the larger the magnitude of Rs, the lower is the voltage
at the input terminals of the amplifier. In general, therefore, as mentioned earlier, for a
particular amplifier, the larger the internal resistance of a signal source, the lower is the
overall gain of the system.
For the two-port system of Fig. 5.64,
Vo = AvNLVi
RiVs
and Vi =
Ri + Rs
298 BJT AC ANALYSIS Ri
so that Vo = AvNL V
Ri + Rs s

Vo Ri
and Avs = = A (5.92)
Vs Ri + Rs vNL

The effects of Rs and RL have now been demonstrated on an individual basis. The next
natural question is how the presence of both factors in the same network will affect the
total gain. In Fig. 5.65, a source with an internal resistance Rs and a load RL have been
applied to a two-port system for which the parameters Zi, AvNL, and Zo have been specified.
For the moment, let us assume that Zi and Zo are unaffected by RL and Rs, respectively.

Is Ii Io

+
+ Zo
Vs RL Vo
–
–

FIG. 5.65
Considering the effects of Rs and RL on the gain of an amplifier.

At the input side we find

RiVs
Eq. (5.91): Vi =
Ri + Rs

Vi Ri
or = (5.93)
Vs Ri + Rs

and at the output side,

RL
Vo = A V
RL + Ro vNL i
Vo RLAvNL RL
or AvL = = = A (5.94)
Vi RL + Ro RL + Ro vNL
For the total gain Avs = Vo >Vs, the following mathematical steps can be performed:

Avs =
Vo
= #
Vo Vi
(5.95)
Vs Vi Vs

and substituting Eqs. (5.93) and (5.94) results in

Avs =
Vo
=
Ri
# RL AvNL (5.96)
Vs Ri + Rs RL + Ro

Because Ii = Vi >Ri, as before,

Ri
AiL = -AvL (5.97)
RL

or, using Is = Vs >(Rs + Ri),

Rs + Ri
Ais = -Avs (5.98)
RL
However, Ii = Is, so Eqs. (5.97) and (5.98) generate the same result. Equation (5.96) TWO-PORT SYSTEMS 299
clearly reveals that both the source and the load resistance will reduce the overall gain of APPROACH
the system.
The two reduction factors of Eq. (5.96) form a product that has to be carefully consid-
ered in any design procedure. It is not sufficient to ensure that Rs is relatively small if the
effect of the magnitude of RL is ignored. For instance, in Eq. (5.96), if the first factor is 0.9
and the second factor is 0.2, the product of the two results in an overall reduction factor
equal to (0.9)(0.2)  0.18, which is close to the lower factor. The effect of the excellent
0.9 level was completely wiped out by the significantly lower second multiplier. If both
were 0.9-level factors, the net result would be (0.9)(0.9)  0.81, which is still quite high.
Even if the first were 0.9 and the second 0.7, the net result of 0.63 would still be respect-
able. In general, therefore, for good overall gain the effects of Rs and RL must be evaluated
individually and as a product.

EXAMPLE 5.12 Determine AvL and Avs for the network of Example 5.11 and compare
solutions. Example 5.1 showed that AvNL = -280, Zi = 1.07 k, and Zo = 3 k. In
Example 5.11, RL = 4.7 k and Rs = 0.3 k.
Solution:
RL
a. Eq. (5.89): AvL = A
RL + Ro vNL
4.7 k
= (-280.11)
4.7 k + 3 k
= ⴚ170.98
as in Example 5.11.
b. Eq. (5.96): Avs =
Ri
# RL AvNL
Ri + Rs RL + Ro

=
1.07 k # 4.7 k (-280.11)
1.07 k + 0.3 k 4.7 k + 3 k
= (0.781)(0.610)(-280.11)
= ⴚ133.45
as in Example 5.11.

EXAMPLE 5.13 Given the packaged (no-entry-possible) amplifier of Fig. 5.66:

a. Determine the gain AvL and compare it to the no-load value with RL = 1.2 k.
b. Repeat part (a) with RL = 5.6 k and compare solutions.
c. Determine Avs with RL = 1.2 k.
Io Io
d. Find the current gain Ai = = with RL = 5.6 k.
Ii Is

Is Rs Ii Io

0.2 kΩ + +
+ AvNL = – 480
Vs Vi Zi = 4 kΩ RL Vo
– Zo = 2 kΩ
– –

FIG. 5.66
Amplifier for Example 5.13.
300 BJT AC ANALYSIS Solution:
RL
a. Eq. (5.89): AvL = A
RL + Ro vNL
1.2 k⍀
= (-480) = (0.375)(-480)
1.2 k⍀ + 2 k⍀
= ⴚ180
which is a dramatic drop from the no-load value.
RL
b. Eq. (5.89): AvL = A
RL + Ro vNL
5.6 k⍀
= (-480) = (0.737)(-480)
5.6 k⍀ + 2 k⍀
= ⴚ353.76
which clearly reveals that the larger the load resistor, the better is the gain.
c. Eq. (5.96): Avs =
Ri
# RL AvNL
Ri + Rs RL + Ro

=
4 k⍀ # 1.2 k⍀ (-480)
4 k⍀ + 0.2 k⍀ 1.2 k⍀ + 2 k⍀
= (0.952)(0.375)(-480)
= ⴚ171.36
which is fairly close to the loaded gain Av because the input impedance is considerably
more than the source resistance. In other words, the source resistance is relatively
small compared to the input impedance of the amplifier.
Io Io Zi
d. AiL = = = -AvL
Ii Is RL
4 k⍀
= -(-353.76)a b = -(-353.76)(0.714)
5.6 k⍀
= 252.6

It is important to realize that when using the two-port equations in some configurations
the input impedance is sensitive to the applied load (such as the emitter-follower and collec-
tor feedback) and in some the output impedance is sensitive to the applied source resistance
(such as the emitter-follower). In such cases the no-load parameters for Zi and Zo have to
first be calculated before substituting into the two-port equations. For most packaged sys-
tems such as op-amps this sensitivity of the input and output parameters to the applied load
or source resistance is minimized to eliminate the need to be concerned about changes from
the no-load levels when using the two-port equations.

5.16 CASCADED SYSTEMS

●
The two-port systems approach is particularly useful for cascaded systems such as that
appearing in Fig. 5.67, where Av1, Av2, Av3, and so on, are the voltage gains of each stage
under loaded conditions. That is, Av1 is determined with the input impedance to Av2 acting
as the load on Av1. For Av2, Av1 will determine the signal strength and source impedance at
the input to Av2. The total gain of the system is then determined by the product of the indi-
vidual gains as follows:

AvT = Av1 # Av2 # Av3 . . . . (5.99)

and the total current gain is given by

Zi 1
AiT = -AvT (5.100)
RL
 No matter how perfect the system design, the application of a succeeding stage or load CASCADED SYSTEMS 301
to a two-port system will affect the voltage gain. Therefore, there is no possibility of a
situation where Av1, Av2, and so on, of Fig. 5.67 are simply the no-load values. The no-load
parameters can be used to determine the loaded gains of each stage, but Eq. (5.99) requires
the loaded values. The load on stage 1 is Zi2, on stage 2 Zi3, on stage 3 Zin, and so on.

Vo = Vi Vo = Vi
1 2 2 3

+ +
Vi Av 1 Av 2 Av 3 Av n RL Vo

– –
Zi = Zi Zo Zi Zo Zi Zo Z in Zon = Zo
1 1 2 2 3 3

FIG. 5.67
Cascaded system.

EXAMPLE 5.14 The two-stage system of Fig. 5.68 employs a transistor emitter-follower
configuration prior to a common-base configuration to ensure that the maximum percentage
of the applied signal appears at the input terminals of the common-base amplifier. In Fig.
5.68, the no-load values are provided for each system, with the exception of Zi and Zo for the
emitter-follower, which are the loaded values. For the configuration of Fig. 5.68, determine:
a. The loaded gain for each stage.
b. The total gain for the system, Av and Avs.
c. The total current gain for the system.
d. The total gain for the system if the emitter-follower configuration were removed.

+
RL Vo
–

FIG. 5.68
Example 5.14.

Solution:
a. For the emitter-follower configuration, the loaded gain is (by Eq. (5.94))
Zi 2 26 
Vo1 = A V = (1) Vi1 = 0.684 Vi1
Zi2 + Zo1 vNL i1 26  + 12 
Vo1
and AVi = = 0.684
Vi1
For the common-base configuration,
RL 8.2 k
Vo2 = AvNL Vi2 = (240) Vi2 = 147.97 Vi2
RL + Ro2 8.2 k + 5.1 k
Vo2
and Av2 = = 147.97
Vi2
b. Eq. (5.99): AvT = Av1Av2
= (0.684)(147.97)
= 101.20
302 BJT AC ANALYSIS Zi 1 (10 k⍀)(101.20)
Eq. (5.91): Avs = AvT =
Zi1 + Rs 10 k⍀ + 1 k⍀
= 92
Zi 1 10 k⍀
c. Eq. (5.100): AiT = -AvT = -(101.20) a b
RL 8.2 k⍀
= ⴚ123.41
ZiCB 26 ⍀
d. Eq. (5.91): Vi = Vs = V = 0.025 Vs
ZiCB + Rs 26 ⍀ + 1 k⍀ s
Vi Vo
and = 0.025 with = 147.97 from above
Vs Vi

and Avs =
Vo
= # = (0.025)(147.97) = 3.7
Vi Vo
Vs Vs Vi
In total, therefore, the gain is about 25 times greater with the emitter-follower configuration
to draw the signal to the amplifier stages. Note, however, that it is also important that the
output impedance of the first stage is relatively close to the input impedance of the second
stage, otherwise the signal would have been “lost” again by the voltage-divider action.

RC-Coupled BJT Amplifiers

One popular connection of amplifier stages is the RC-coupled variety shown in Fig. 5.69 in
the next example. The name is derived from the capacitive coupling capacitor Cc and the
fact that the load on the first stage is an RC combination. The coupling capacitor isolates
the two stages from a dc viewpoint but acts as a short-circuit equivalent for the ac response.
The input impedance of the second stage acts as a load on the first stage, permitting the
same approach to the analysis as described in the last two sections.

EXAMPLE 5.15
a. Calculate the no-load voltage gain and output voltage of the RC-coupled transistor
amplifiers of Fig. 5.69.
b. Calculate the overall gain and output voltage if a 4.7 k⍀ load is applied to the second
stage, and compare to the results of part (a).
c. Calculate the input impedance of the first stage and the output impedance of the second
stage.
+20 V

2.2 kΩ 15 kΩ 2.2 kΩ
15 kΩ CC
Vo
10 μF 10 μF
Vi = 25 μV
Q1 β = 200 Q2 β = 200
10 μF

4.7 kΩ + 4.7 kΩ +
1 kΩ 20 μ F 1 kΩ 20 μ F

FIG. 5.69
RC-coupled BJT amplifier for Example 5.15.

Solution:
a. The dc bias analysis results in the following for each transistor:
VB = 4.8 V, VE = 4.1 V, VC = 11 V, IE = 4.1 mA
 At the bias point, CASCADED SYSTEMS 303
26 mV 26 mV
re = = = 6.34 ⍀
IE 4.1 mA
The loading of the second stage is
Zi2 = R1 7 R2 7 bre
which results in the following gain for the first stage:
RC 7 (R1 7 R2 7 bre)
Av1 = -
re
(2.2 k⍀) 7 [15 k⍀ 7 4.7 k⍀ 7 (200)(6.34 ⍀)]
= -
6.34 ⍀
659.2 ⍀
= - = -104
6.34 ⍀
For the unloaded second stage the gain is
RC 2.2 k⍀
Av2(NL) = - = - = -347
re 6.34 ⍀
resulting in an overall gain of
AvT(NL) = Av1Av2(NL) = (-104)(-347) ⬵ 36.1 : 103
The output voltage is then
Vo = AvT(NL)Vi = (36.1 * 103)(25 mV) ⬵ 902.5 mV
b. The overall gain with the 10-k⍀ load applied is
Vo RL 4.7 k⍀
AvT = = AvT(NL) = (36.1 * 103) ⬵ 24.6 : 103
Vi RL + Zo 4.7 k⍀ + 2.2 k⍀
which is considerably less than the unloaded gain because RL is relatively close to RC.
Vo = AvTVi
= (24.6 * 103)(25 mV)
= 615 mV
c. The input impedance of the first stage is
Zi1 = R1 7 R2 7 bre = 4.7 k⍀ 7 15 k⍀ 7 (200)(6.34 ⍀) = 0.94 k⍀
whereas the output impedance for the second stage is
Zo2 = RC = 2.2 k⍀

Cascode Connection
The cascode configuration has one of two configurations. In each case the collector of the
leading transistor is connected to the emitter of the following transistor. One possible
arrangement appears in Fig. 5.70; the second is shown in Fig. 5.71 in the following example.

Vo

Vi

FIG. 5.70
Cascode configuration.
304 BJT AC ANALYSIS The arrangements provide a relatively high-input impedance with low voltage gain for the
first stage to ensure the input Miller capacitance (to be discussed in Section 9.9) is at a
minimum, whereas the following CB stage provides an excellent high-frequency response.

EXAMPLE 5.16 Calculate the no-load voltage gain for the cascode configuration of Fig. 5.71.

VCC = 18 V

RC
RB 1.8 kΩ
1
6.8 kΩ Vo 2
C1 C = 5 μF
Q2
10 μF
RB
2 Vo 1 (β1 = β2= 200)
5.6 kΩ

Vi 1 Q1
Cs = 5 μF

RB
3
4.7 kΩ RE
CE = 20 μF
1.1 kΩ

FIG. 5.71
Practical cascode circuit for Example 5.16.

Solution: The dc analysis results in

VB1 = 4.9 V, VB2 = 10.8 V, IC1 ⬵ IC2 = 3.8 mA
because IE1 ⬵ IE2 the dynamic resistance for each transistor is
26 mV 26 mV
re = ⬵ = 6.8 
IE 3.8 mA
The loading on the transistor Q1 is the input impedance of the Q2 transistor in the CB
configuration as shown by re in Fig 5.72.
The result is the replacement of RC in the basic no-load equation for the gain of the CB
configuration, with the input impedance of a CB configuration as follows:
RC re
Av1 = - = - = -1
re re
with the voltage gain for the second stage (common base) of
RC 1.8 k
Av2 = = = 265
re 6.8 

Vo2
Vo1 Q2
re

Vi1
Q1

FIG. 5.72
Defining the load of Q1.
The overall no-load gain is
AvT = Av1 Av2 = (-1)(265) = ⴚ265
As expected, in Example 5.16, the CE stage provides a higher input impedance than can
be expected from the CB stage. With a voltage gain of about 1 for the first stage, the
Miller-effect input capacitance is kept quite low to support a good high-frequency response.
A large voltage gain of 265 was provided by the CB stage to give the overall design a good
input impedance level with desirable gain levels.

5.17 DARLINGTON CONNECTION

●
A very popular connection of two bipolar junction transistors for operation as one “super-
beta” transistor is the Darlington connection shown in Fig. 5.73. The main feature of the
Darlington connection is that the composite transistor acts as a single unit with a current
gain that is the product of the current gains of the individual transistors. If the connection
is made using two separate transistors having current gains of b1 and b2, the Darlington American (Pittsburgh, PA; Exeter, NH)
(1906–1997)
connection provides a current gain of
Department Head at Bell Laboratories
bD = b1b2 (5.101) Professor, Department of Electrical and
Computer Engineering, University of
New Hampshire

Dr. Sidney Darlington earned his B.S. in

physics at Harvard, his B.S. in electrical
communication at MIT, and his Ph.D. at
Columbia University. In 1929 he joined
Bell Laboratories, where he was head of
the Circuits and Control Department. Dur-
ing that period he became good friends
with other important contributors such as
Edward Norton and Hendrik Bode. A
holder of 24 U.S. patents, he was awarded
the Presidential Medal of Freedom, the
FIG. 5.73 highest civilian honor in the United States,
in 1945 for his contributions to network
Darlington combination.
design during World War II. An elected
The configuration was first introduced by Dr. Sidney Darlington in 1953. A short biog- member of the National Academy of
Engineering, he also received the IEEE
raphy appears as Fig 5.74.
Edison Medal in 1975 and the IEEE
Medal of Honor in 1981. His U.S. patent
Emitter-Follower Configuration 2 663 806 titled “Semiconductor Signal
Translating Device” was issued on Decem-
A Darlington amplifier used in an emitter-follower configuration appears in Fig. 5.75. The ber 22, 1953, describing how two transis-
primary impact of using the Darlington configuration is an input impedance much larger than tors could be constructed in the Darlington
configuration on the same substrate—
often looked upon as the beginnings of
compound IC construction. Dr. Darlington
was also responsible for the introduction
and development of the Chirp technique,
used throughout the world in waveguide
transmission and radar systems. He is a
primary contributor to the Bell Laborato-
ries Command Guidance System that
guides most of the rockets used today to
Vi β1 place satellites in orbit. It uses a combina-
C1 IB1
+ tion of radar tracking on the ground with
VBE1– β2 inertial control in the rocket itself. Dr.
+ Darlington was an avid outdoorsman as a
VBE2 – Vo
hiker and member of the Appalachian
IE2 C2 Mountain Club. One of his proudest
accomplishments was being able to climb
Mt. Washington at the age of 80.

FIG. 5.74
Sidney Darlington (Courtesy of
AT&T Archives and History Center.)
FIG. 5.75
Emitter-follower configuration with a Darlington amplifier.
305
306 BJT AC ANALYSIS that obtained with a single-transistor network. The current gain is also larger, but the voltage
gain for a single-transistor or Darlington configuration remains slightly less than one.

DC Bias The case current is determined using a modified version of Eq. 4.44. There are
now two base-to-emitter voltage drops to include and the beta of a single transistor is
replaced by the Darlington combination of Eq. 5.101.

VCC - VBE1 - VBE2

IB1 = (5.102)
RB + bD RE

The emitter current of Q1 is equal to the base current of Q2 so that

IE2 = b2IB2 = b2IE1 = b2(b1IE1) = b1b2IB1
resulting in

IC2 ⬵ IE2 = bD IB1 (5.103)

The collector voltage of both transistors is

VC1 = VC2 = VCC (5.104)

the emitter voltage of Q2

VE2 = IE2RE (5.105)

the base voltage of Q1

VB1 = VCC - IB1RB = VE2 + VBE1 + VBE2 (5.106)

the collector-emitter voltage of Q

VCE2 = VC2 - VE2 = VCC - VE2 (5.107)

EXAMPLE 5.17 Calculate the dc bias voltages and currents for the Darlington configura-
tion of Fig. 5.76.

Vi β1 = 50
C1
β2 = 100
Vo
C2

FIG. 5.76
Circuit for Example 5.17.
Solution: DARLINGTON 307
CONNECTION
bD = b1b2 = (50)(100) = 5000
VCC - VBE1 - VBE2 18 V - 0.7 V - 0.7 V
IB1 = =
RB + bD RE 3.3 M + (5000)(390 )
18 V - 1.4 V 16.6 V
= = = 3.16 MA
3.3 M + 1.95 M 5.25 M
IC2 ⬵ IE2 = bD IB1 = (5000)(3.16 mA) = 15.80 mA
VC1 = VC2 = 18 V
VE2 = IE2RE = (15.80 mA)(390 ) = 6.16 V
VB1 = VE2 + VBE1 + VBE2 = 6.16 V + 0.7 V + 0.7 V = 7.56 V
VCE2 = VCC - VE2 = 18 V - 6.16 V = 11.84 V

AC Input Impedance The ac input impedance can be determined using the ac equivalent
network of Fig. 5.77.

Q1

Q2
Zi E1, B2
RB Zi1
Zi2
RE

FIG. 5.77
Finding Zi.

As defined in Fig. 5.77:

Zi2 = b2(re2 + RE)
Zi1 = b1(re1 + Zi2)
so that Zi1 = b1(re1 + b2(re2 + RE))
Assuming RE W re2
and Zi1 = b1(re1 + b2RE)
Since b2RE W re1
Zi1 ⬵ b1b2RE
and since Zi = RB 7 Zi

Zi = RB 7 b1b2RE = RB 7 bD RE (5.108)

For the network of Fig. 5.76

Zi = RB 7 bD RE
= 3.3 M 7 (5000)(390 ) = 3.3 M 7 1.95 M
= 1.38 M⍀
Note in the preceding analysis that the values of re were not compared but dropped com-
pared to much larger quantites. In a Darlington configuration the values of re will be differ-
ent because the emitter current through each transistor will be different. Also, keep in mind
that chances are the beta values for each transistor will be different because thay deal with
different current levels. The fact remains, however, that the product of the two beta values
will equal bD, as indicated on the specification sheet.
308 BJT AC ANALYSIS AC Current Gain The current gain can be determined from the equivalent network of
Fig. 5.78. The output impedance of each transistor is ignored and the parameters for each
transistor are employed.

Ii β 1re1 β 2re2
B1 E1 B2 E2

Io
Ib1 Ib2

RB β 1Ib1 β 2Ib2 RE

C1 C2

FIG. 5.78
Determining Ai for the network of Fig. 5.75.

Solving for the output current: Io = Ib2 + b2Ib2 = (b2 + 1)Ib2

with Ib2 = b1Ib1 + Ib1 = (b1 + 1)Ib1
Then Io = (b2 + 1)(b1 + 1)Ib1
Using the current-divider rule on the input circuit:
RB RB
Ib1 = Ii = I
RB + Zi RB + b1b2RE i
RB
and Io = (b2 + 1)(b1 + 1)a bI
RB + b1b2RE i
Io (b1 + 1)(b2 + 1)RB
so that Ai = =
Ii RB + b1b2RE
Using b1, b2 W 1

Io b1b2RB
Ai = ⬵ (5.109)
Ii RB + b1b2RE

Io bD RB
or Ai = ⬵ (5.110)
Ii RB + bD RE
For Fig. 5.76:
Io bD RB (5000)(3.3 M)
Ai = = =
Ii RB + bD RE 3.3 M + 1.95 M
= 3.14 : 103

AC Voltage Gain The voltage gain can be determined using Fig. 5.77 and the following
derivation:
Vo = IoRE
Vi = Ii(RB 7 Zi)
bD RB RE
RB 储 Zi = RB 储 bD RE =
RB + bD RE
Vo Io RE RE
and An = = = (Ai)a b
Vi Ii (RB 储 Zi) RB 7 Zi

bD RB RE
=
£ R + b R § £ bD RB RE §
B D E
RB + bD RE

and Av ⬵ 1 (in reality less than one) (5.111)

an expected result for the emitter-follower configuration.

AC Output Impedance The output impedance will be determined by going back to Fig. 5.78 DARLINGTON 309
and setting Vi to zero volts as shown in Fig. 5.79. The resistor RB is “shorted out,” resulting CONNECTION
in the configuration of Fig. 5.80. Note in Figs. 5.82 and 5.83 that the output current has
been redefined to match standard nomenclature and properly defined Zo.

Ib1 Ib2 Io

β 1re1 β 2re2 +
Zo
Vi ⫽ 0 V RB β 1Ib1 β 2Ib2 RE Vo

–
FIG. 5.79
Determining Zo.

Ib2 ( β 2 ⫹ 1)Ib2 Io
+ – a

β2re2 Ie +
– Zo
Ib1 β1re1 β 1Ib1 β 2Ib2 RE Vo

+
–
FIG. 5.80
Redrawn of network of Fig. 5.79.

At point a Kirchhoff’s current law will result in Io + (b2 + 1)Ib2 = Ie:

Io = Ie - (b2 + 1)Ib2
Applying Kirchhoff’s voltage law around the entire outside loop will result in
-Ib1b1re1 - Ib2b2re2 - Vo = 0
and Vo = Ib1b1re1 + Ib2b2re2
Substituting Ib2 = (b1 + 1)Ib1
Vo = -Ib1b1re1 - (b1 + 1)Ib1b2re2
= -Ib1[b1re1 + (b1 + 1)b2re2]
Vo
and Ib1 = -
b1re1 + (b1 + 1)b2re2
Vo
with Ib2 = (b1 + 1)Ib1 = (b1 + 1)c - d
b1re1 + (b1 + 1)b2re2
b1 + 1
so that Ib2 = - c dV
b1re1 + (b1 + 1)b2re2 o
(b1 + 1)Vo
Going back Io = Ie - (b2 + 1)Ib2 = Ie - (b2 + 1)a - b
b1re1 + (b1 + 1)b2re2
Vo (b1 + 1)(b2 + 1)Vo
or Io = +
RE b1re1 + (b1 + 1)b2re2
310 BJT AC ANALYSIS Because b1, b2 W 1
Vo b1b2Vo Vo Vo
Io = + = +
RE b1re1 + b1b2re2 RE b1re1 b1b2re2
+
b1b2 b1b2
Vo Vo
Io = + r
RE e1
+ re2
b2
Io which defines the parallel resistance network of Fig. 5.81.
re1
+ In general, RE W a + re2 b so the output impedance is defined by
b2
re1 Zo
⫹ re2 RE Vo re1
2
Zo = + re2 (5.112)
b2
–
Using the dc results, the value of re2 and re1 can be determined as follows.
FIG. 5.81
26 mV 26 mV
Resulting network defined by Zo. re2 = = = 1.65 ⍀
IE2 15.80 mA
IE2 15.80 mA
and IE1 = IB2 = = = 0.158 mA
b2 100
26 mV
so that re1 = = 164.5 ⍀
0.158 mA
The output impedance for the network of Fig. 5.78 is therefore:
re1 164.5 ⍀
Zo ⬵ + re2 = + 1.65 ⍀ = 1.645 ⍀ + 1.65 ⍀ = 3.30 ⍀
b2 100
In general, the output impedance for the configuration of Fig. 5.78 is very low—in the
order of a few ohms at most.

Voltage-Divider Amplifier
DC Bias Let us now investigate the effect of the Darlington configuration in a basic
amplifier configuration as shown in Fig. 5.82. Note that now there is a collector resistor
RC, and the emitter terminal of the Darlington circuit is connected to ground for ac condi-
tions. As noted on Fig. 5.82, the beta of each transistor is provided along with the resulting
voltage from base to emitter.

VCC = 27 V

Io
RC 1.2 kΩ
R1 470 kΩ
Vo

Darlington C2
Pair
Vi
β1 = β 2 = 110.
Ii C1
Zi' VBE = 1.5 V
Zi
R2
220 kΩ
RE 680 Ω CE

FIG. 5.82
Amplifier configuration using a Darlington pair.
 The dc analysis can proceed as follows: DARLINGTON 311
CONNECTION
bD = b1b2 = (110 * 110) = 12,100
R2 220 k(27 V)
VB = V = = 8.61 V
R2 + R1 CC 220 k + 470 k
VE = VB - VBE = 8.61 V - 1.5 V = 7.11 V
VE 7.11 V
IE = = = 10.46 mA
RE 680 
IE 10.46 mA
IB = = = 0.864 MA
bD 12,100
Using the preceding results the values of re2 and re1 can be determined:
26 mV 26 mV
re2 = = = 2.49 ⍀
IE2 10.46 mA
IE2 10.46 mA
IE1 = IB2 = = = 0.095 mA
b2 110
26 mV 26 mV
and re1 = = = 273.7 ⍀
IE1 0.095 mA

AC Input Impedance The ac equivalent of Fig. 5.82 appears as Fig. 5.83. The resistors R1
and R2 are in parallel with the input impedance to the Darlington pair, assuming the second
transistor found by assuming the second transistor acts like an RE load on the first as
shown in Fig. 5.83.
That is, Zi = b1re1 + b1(b2 re2)

Vo
Ii
Io
Vi Q1
Zi
Q2
RC
R1 R2 Q1 β r
2 e2

Zi'
β2re
2

FIG. 5.83
Defining Zi and Zi.

and Zi = b1[re1 + b2re2] (5.113)

For the network of Fig. 5.82:

Zi = 110[273.7  + (110)(2.49 )]
= 110[273.7  + 273.9 ]
= 110[547.6 ]
= 60.24 k⍀
and Zi = R1 7 R2 7 Zi
= 470 k 7 220 k 7 60.24 k
= 149.86 k 7 60.24 k
= 42.97 k⍀
312 BJT AC ANALYSIS AC Current Gain The complete ac equivalent of Fig. 5.82 appears as Fig. 5.84.

Ii Ii' Ib1 β 1Ib1

B1 E1, B2 C1C2
Vo
β 1re Ib2
1 Io

R1 R2 β 2re2 β 2Ib2 RC
Zi Zi'

E2 E2

FIG. 5.84
ac equivalent network for Fig. 5.82.

The output current Io = b1Ib1 + b2Ib2

with Ib2 = (b1 + 1)Ib1
so that Io = b1Ib1 + b2(b1 + 1)Ib1
and with Ib1 = Ii
we find Io = b1Ii + b2(b1 + 1)Ii
Io
and Ai = = b1 + b2(b + 1)
Ii
⬵ b1 + b2b1 = b1(1 + b2)
⬵ b1b2

Io
and finally Ai = = b1b2 = bD (5.114)
Ii

R1 7 R2Ii Ii R1 7 R2
For the original structure: Ii = or =
R1 7 R2 + Zi Ii R1 7 R2 + Zi
Io Io Ii
but Ai = = a ba b
Ii Ii Ii

bD(R1 7 R2)
so that Ai = (5.115)
R1 7 R2 + Zi

(12,100)(149.86 k)
For Fig. 5.82 Ai =
149.86 k + 60.24 k
= 8630.7
Note the significant drop in current gain due to R1 and R2.

AC Voltage Gain The input voltage is the same across R1 and R2 and at the base of the
first transistor as shown in Fig. 5.84.
The result is
Vo Io RC RC
Av = = - = -Ai a b
Vi Ii Zi Zi

bDRC
and Av = - (5.116)
Zi

For the network of Fig. 5.82,

bDRC (12,000)(1.2 k)
Av = - = - = ⴚ241.04
Zi 60.24 k
AC Output Impedence Because the output impedance in RC is parallel with the collector DARLINGTON 313
to emitter terminals of the transistor, we can look back on similar situations and find that CONNECTION
the output impedance is defined by

Zo ⬵ RC 7 ro2 (5.117)
where ro2 is the output resistance of the transistor Q2.

Packaged Darlington Amplifier

Because the Darlington connection is so popular, a number of manufacturers provide
packaged units such as shown in Fig. 5.85. Typically, the two BJTs are constructed on a
single chip rather than separate BJT units. Note that only one set of collector, base, and
emitter terminals is provided for each configuration. These, of course, are the base of the
transistor Q1, the collector of Q1 and Q2, and the emitter of Q2.

C
BE B
(a) (b)

FIG. 5.85
Packaged Darlington amplifiers: (a) TO-92 package;
(b) Super SOT™-3 package.

In Fig. 5.86 some of the ratings for an MPSA28 Fairchild Semiconductor Darlington
amplifier are provided. In particular, note that the maximum collector-to-emitter voltage of
80 V is also the breakdown voltage. The same is true for the collector-to-base and emitter-
to-base voltages, although notice how much lower the maximum ratings are for the base-
to-emitter junction. Because of the Darlington configuration, the maximum current rating
for the collector current has jumped to 800 mA—far exceeding levels we have encountered

Absolute Maximum Ratings

VCES Collector-Emitter Voltage 80 V

VCBO Collector-Base Voltage 80 V
VEBO Emitter-Base Voltage 12 V
IC Collector Current–Continuous 800 mA

Electrical Characteristics

V(BR)CES Collector-Emitter Breakdown Voltage 80 V

V(BR)CBO Collector-Base Breakdown Voltage 80 V
V(BR)EBO Emitter-Base Breakdown Voltage 12 V
ICBO Collector Cutoff Current 100 mA
IEBO Emitter Cutoff Current 100 mA

On Characteristics

hFE DC Current Gain 10,000

VCE(sat) Collector-Emitter Saturation Voltage 1.2 V
VBE(on) Base-Emitter on Voltage 2.0 V

FIG. 5.86
MPSA 28 Fairchild Semiconductor Darlington amplifier ratings.
314 BJT AC ANALYSIS for single-transistor networks. The dc current gain is rated at the high level of 10,000 and
the base-to-emitter potential in the “on” state is 2 V, which certainly exceeds the 1.4 V we
have used for individual transistors. Finally, it is interesting to note that the level of ICEO is
much higher at 500 nA than for a typical single-transistor unit.
In the packaged format the network of Fig. 5.75 would appear as shown in Fig. 5.87.
Using bD and the provided value of VBE (=VBE1 + VBE2), all the equations appearing in
this section can be applied.

+VCC (+18 V)

RB
3.3 MΩ C
MPSA 28 Darlington Amplifier
C1
Vi βD = 10,000
B VBE = 2.0 V
Ii

C2
Zi E
Vo
Io
RE
390 Ω

FIG. 5.87
Darlington emitter-follower circuit.

5.18 FEEDBACK PAIR

●
The feedback pair connection (see Fig. 5.88) is a two-transistor circuit that operates like
the Darlington circuit. Notice that the feedback pair uses a pnp transistor driving an npn
transistor, the two devices acting effectively much like one pnp transistor. As with a Dar-
lington connection, the feedback pair provides very high current gain (the product of the
transistor current gains), high input impedance, low output impedance, and a voltage gain
slightly less than one. Initially, it may appear that it would have a high voltage gain because
the output is taken off the collector with a resistor RC in place. However, the pnp–npn
combination results in terminal characteristics very similar to that of the emitter–follower
FIG. 5.88 configuration. A typical application (see Chapter 12) uses a Darlington and a feedback-pair
Feedback pair connection. connection to provide complementary transistor operation. A practical network employing a
feedback pair is provided in Fig. 5.89 for investigation.

DC Bias
The dc bias calculations that follow use practical simplifications wherever possible to pro-
vide simpler results. From the Q1 base–emitter loop, one obtains
VCC - ICRC - VEB1 - IB1RB = 0
VCC - (b1b2IB1)RC - VEB1 - IB1RB = 0
The base current is then

VCC - VBE1
IB1 = (5.118)
RB + b1b2RC

The collector current of Q1 is

IC1 = b1IB1 = IB2
which is also the base Q2 current. The transistor Q2 collector current is
IC2 = b2IB2 ⬇ IE2
 FEEDBACK PAIR 315

Vo

Vi

FIG. 5.89
Operation of a feedback pair.

so that the current through RC is

IC = IE1 + IC2 ⬇ IB2 + IC2 (5.119)

The voltages VC2 = VE1 = VCC - IC RC (5.120)

and VB1 = IB1 RB (5.121)

with VBC1 = VB1 - VBE2 = VB1 - 0.7 V (5.122)

EXAMPLE 5.18 Calculate the dc bias currents and voltages for the circuit of Fig. 5.89 to
provide Vo at one-half the supply voltage (9 V).
Solution:
18 V - 0.7 V 17.3 V
IB1 = = = 4.45 MA
2 M + (140)(180)(75 ) 3.89 * 106
The base Q2 current is then
IB2 = IC1 = b1IB1 = 140(4.45 mA) = 0.623 mA

resulting in a Q2 collector current of

IC2 = b2IB2 = 180(0.623 mA) = 112.1 mA

and the current through RC is then

Eq. (5.119): IC = IE1 + IC2 = 0.623 mA + 112.1 mA ⬇ IC2 = 112.1 mA
VC2 = VE1 = 18 V - (112.1 mA)(75 )
= 18 V - 8.41 V
= 9.59 V
VB1 = IB1RB = (4.45 mA)(2 M)
= 8.9 V
VBC1 = VB1 - 0.7 V = 8.9 V - 0.7 V
= 8.2 V
316 BJT AC ANALYSIS AC Operation
The ac equivalent circuit for that of Fig. 5.89 is drawn in Fig. 5.90.

Ii Ii' β 1re1
a

+ Io
+
Ib1
Zi Zi' β 1Ib1

RB β 2Ib2 RC
Vi Vo
Ib2
β 2re2

– –
FIG. 5.90
ac equivalent for the network of Fig. 5.89.

Input Impedance, Zi The ac input impedance seen looking into the base of transistor Q1
is determined as follows:
Vi
Zi =
Ii
Applying Kirchhoff’s current law at node a and defining Ic = Io:
Ib1 + b1Ib1 - b2Ib2 + Io = 0
with Ib2 = -b1Ib1 as noted in Fig. 5.90.
The result is Ib1 + b1Ib1 - b2(-b1Ib1) + Io = 0
and Io = -Ib1 - b1Ib1 - b1b2Ib1
or Io = -Ib1(1 + b1) - b1b2Ib1
but b1 W 1
and Io = -b1Ib1 - b1b2Ib1 = -Ib1(b1 + b1b2)
= -Ib1b1(1 + b2)

resulting in: Io ⬵ -b1b2Ib1 (5.123)

Vi - Vo
Now, Ib1 = from Fig. 5.90
b1re1
and Vo = -Io RC = -(-b1b2Ib1)RC = b1b2Ib1RC
Vi - b1b2Ib1RC
so Ib1 =
b1re1
Rearranging: Ib1b1re1 = Vi - b1b2Ib1RC
and Ib1(b1re1 + b1b2RC) = Vi
Vi
so Ib1 = Ii =
b1re1 + b1b2RC
Vi Vi
and Vi = =
Ii Vi
b1re + b1b2RC

so that Zi = b1re1 + b1b2RC (5.124)

In general, b1b2RC W b1re1

and Zi ⬵ b1b2RC (5.125)

 FEEDBACK PAIR 317
with Zi = RB 7 Zi (5.126)

26 mV 26 mV
For the network of Fig. 5.89: re1 = = = 41.73 
IE1 0.623 mA
and Zi = b1re1 + b1b2RC
= (140)(41.73 ) + (140)(180)(75 )
= 5842.2  + 1.89 M
= 1.895 M⍀
where Eq. (5.125) results in Zi ⬵ b1b2RC = (140)(180)(75 ) = 1.89 M⍀, validating
the above approximations.

Current Gain
Defining Ib1 = Ii as shown in Fig. 5.90 will permit finding the current gain Ai = Io >Ii .
Looking back on the derivation of Zi we found Io = -b1b2Ib1 = -b1b2Ii

Io
resulting in Ai = = -b1b2 (5.127)
Ii

The current gain Ai = Io >Ii can be determined using the fact that
Io Ii
Ai =
Io
= #
Ii Ii Ii
RB Ii RB Ii
For the input side: Ii = =
RB + Zi RB + b1b2RC
Io Ii
Substituting: Ai = # = (-b1b2)a RB
b
Ii Ii RB + b1b2RC

Io -b1b2RB
So that Ai = = (5.128)
Ii RB + b1b2RC

The negative sign appears because both Ii and Io are defined as entering the network.
Io
For the network of Fig. 5.89: Ai = = -b1b2
Ii
= -(140)(180)
= ⴚ25.2 : 103
-b1b2RB (140)(180)(2 M)
Ai = = -
RB + b1b2Rc 2 M + 1.89 M
50,400 M
= -
3.89 M
= ⴚ12.96 : 103 (⬵ half of Ai)

Voltage Gain
The voltage gain can quickly be determined using the results obtained above.
Vo -IoRC
That is, Av = =
Vi IiZi
(-b1b2Ii)RC
= -
Ii(b1re1 + b1b2RC)

b2RC
Av = (5.129)
re1 + b2RC
318 BJT AC ANALYSIS which is simply the following if we apply the approximation: b2RC W re1
b2RC
Av ⬵ = 1
b2RC
b2RC (180)(75 )
For the network of Fig. 5.89: Av = =
re1 + b2RC 41.73  + (180)(75 )
13.5 * 103 
=
41.73  + 13.5 * 103 
= 0.997 ⬵ 1 (as indicated above)

Output Impedance
The output impedance Zo is defined in Fig. 5.91 when Vi is set to zero volts.

Vo

+ Io
+
Zo
β 1Ib1 Zo'
Ib1 β 1re1 β 2Ib2 RC
Vo
Ib2
β 2re2

– –
FIG. 5.91
Determining Zo and Zo.

Using the fact that Io = -b1b2Ib1 from calculations above, we find that
Vo Vo
Zo = =
Io -b1b2Ib1
Vo
but Ib1 = -
b1re1
Vo b1re1
and Zo = =
Vo b1b2
-b1b2 a - b
b1re1

re1
so that Zo = (5.130)
b2

re1
with Zo = RC g (5.131)
b2

re1
However, RC W
b2

re1
leaving Zo ⬵ (5.132)
b2

which will be a very low value.

For the network of Fig. 5.89:
41.73 
Zo ⬵ = 0.23 ⍀
180
The preceding analysis shows that the feedback pair connection of Fig. 5.89 provides
operation with voltage gain very near 1 ( just as with a Darlington emitter-follower), a very
high current gain, a very low output impedance, and a high input impedance.
5.19 THE HYBRID EQUIVALENT MODEL THE HYBRID 319
● EQUIVALENT MODEL
The hybrid equivalent model was mentioned in the earlier sections of this chapter as one
that was used in the early years before the popularity of the re model developed. Today
there is a mix of usage depending on the level and direction of the investigation.
The re model has the advantage that the parameters are defined by the actual operating
conditions,
whereas
the parameters of the hybrid equivalent circuit are defined in general terms for any
operating conditions.
In other words, the hybrid parameters may not reflect the actual operating conditions
but simply provide an indication of the level of each parameter to expect for general use.
The re model suffers from the fact that parameters such as the output impedance and the
feedback elements are not available, whereas the hybrid parameters provide the entire set
on the specification sheet. In most cases, if the re model is employed, the investigator will
simply examine the specification sheet to have some idea of what the additional elements
might be. This section will show how one can go from one model to the other and how the
parameters are related. Because all specification sheets provide the hybrid parameters and
the model is still extensively used, it is important to be aware of both models. The hybrid
parameters as shown in Fig. 5.92 are derived from the specification sheet for the 2N4400
transistor described in Chapter 3. The values are provided at a dc collector current of 1 mA
and a collector-to-emitter voltage of 10 V. In addition, a range of values is provided for
each parameter for guidance in the initial design or analysis of a system. One obvious ad-
vantage of the specification sheet listing is the immediate knowledge of typical levels for
the parameters of the device as compared to other transistors.

FIG. 5.92
Hybrid parameters for the 2N4400 transistor.

The description of the hybrid equivalent model will begin with the general two-port
system of Fig. 5.93. The following set of equations (5.131) and (5.132) is only one of
a number of ways in which the four variables of Fig. 5.93 can be related. It is the most
frequently employed in transistor circuit analysis, however, and therefore is discussed in
detail in this chapter.

FIG. 5.93
Two-port system.
320 BJT AC ANALYSIS Vi = h11Ii + h12Vo (5.133)

Io = h21Ii + h22Vo (5.134)

The parameters relating the four variables are called h-parameters, from the word
“hybrid.” The term hybrid was chosen because the mixture of variables (V and I ) in each
equation results in a “hybrid” set of units of measurement for the h-parameters. A clearer
understanding of what the various h-parameters represent and how we can determine their
magnitude can be developed by isolating each and examining the resulting relationship.

h11 If we arbitrarily set Vo = 0 (short circuit the output terminals) and solve for h11 in
Eq. (5.133), we find

Vi
h11 = ` ohms (5.135)
Ii Vo = 0

The ratio indicates that the parameter h11 is an impedance parameter with the units of ohms.
Because it is the ratio of the input voltage to the input current with the output terminals
shorted, it is called the short-circuit input-impedance parameter. The subscript 11 of h11
refers to the fact that the parameter is determined by a ratio of quantities measured at the
input terminals.

h12 If Ii is set equal to zero by opening the input leads, the following results for h12:

Vi
h12 = ` unitless (5.136)
Vo Il = 0

The parameter h12, therefore, is the ratio of the input voltage to the output voltage with
the input current equal to zero. It has no units because it is a ratio of voltage levels and is
called the open-circuit reverse transfer voltage ratio parameter. The subscript 12 of h12
indicates that the parameter is a transfer quantity determined by a ratio of input (1) to out-
put (2) measurements. The first integer of the subscript defines the measured quantity to
appear in the numerator; the second integer defines the source of the quantity to appear in
the denominator. The term reverse is included because the ratio is an input voltage over an
output voltage rather than the reverse ratio typically of interest.

h21 If in Eq. (5.134) Vo is set equal to zero by again shorting the output terminals, the
following results for h21:
Io
h21 = ` unitless (5.137)
Ii Vo = 0

Note that we now have the ratio of an output quantity to an input quantity. The term forward
will now be used rather than reverse as indicated for h12. The parameter h21 is the ratio of
the output current to the input current with the output terminals shorted. This parameter,
like h12, has no units because it is the ratio of current levels. It is formally called the short-
circuit forward transfer current ratio parameter. The subscript 21 again indicates that it
is a transfer parameter with the output quantity (2) in the numerator and the input quantity
(1) in the denominator.

h22 The last parameter, h22, can be found by again opening the input leads to set I1 = 0
and solving for h22 in Eq. (5.134):

Io
h22 = ` siemens (5.138)
Vo Ii = 0

Because it is the ratio of the output current to the output voltage, it is the output conductance
parameter, and it is measured in siemens (S). It is called the open-circuit output admittance
parameter. The subscript 22 indicates that it is determined by a ratio of output quantities.
 Because each term of Eq. (5.133) has the unit volt, let us apply Kirchhoff’s voltage law THE HYBRID 321
“in reverse” to find a circuit that “fits” the equation. Performing this operation results in EQUIVALENT MODEL
the circuit of Fig. 5.94. Because the parameter h11 has the unit ohm, it is represented by a
resistor in Fig. 5.94. The quantity h12 is dimensionless and therefore simply appears as a
multiplying factor of the “feedback” term in the input circuit.
Because each term of Eq. (5.134) has the units of current, let us now apply Kirchhoff’s
current law “in reverse” to obtain the circuit of Fig. 5.95. Because h22 has the units of
admittance, which for the transistor model is conductance, it is represented by the resistor
symbol. Keep in mind, however, that the resistance in ohms of this resistor is equal to the
reciprocal of conductance (1兾h22).
The complete “ac” equivalent circuit for the basic three-terminal linear device is indi-
cated in Fig. 5.96 with a new set of subscripts for the h-parameters. The notation of Fig. FIG. 5.94
5.96 is of a more practical nature because it relates the h-parameters to the resulting ratio ob- Hybrid input equivalent circuit.
tained in the last few paragraphs. The choice of letters is obvious from the following listing:
h11 S input resistance S hi
h12 S reverse transfer voltage ratio S hr
h21 S forward transfer current ratio S hf
h22 S output conductance S ho

FIG. 5.95
Hybrid output equivalent circuit.

FIG. 5.96
Complete hybrid equivalent circuit.

The circuit of Fig. 5.96 is applicable to any linear three-terminal electronic device or system
with no internal independent sources. For the transistor, therefore, even though it has
three basic configurations, they are all three-terminal configurations, so that the resulting
equivalent circuit will have the same format as shown in Fig. 5.96. In each case, the bottom
of the input and output sections of the network of Fig. 5.96 can be connected as shown in
Fig. 5.97 because the potential level is the same. Essentially, therefore, the transistor model
is a three-terminal two-port system. The h-parameters, however, will change with each
configuration. To distinguish which parameter has been used or which is available, a second

FIG. 5.97
Common-emitter configuration: (a) graphical symbol; (b) hybrid equivalent circuit.
322 BJT AC ANALYSIS subscript has been added to the h-parameter notation. For the common-base configuration,
the lowercase letter b was added, whereas for the common-emitter and common-collector
configurations, the letters e and c were added, respectively. The hybrid equivalent network
for the common-emitter configuration appears with the standard notation in Fig. 5.97. Note
that Ii = Ib, Io = Ic, and, through an application of Kirchhoff’s current law, Ie = Ib + Ic.
The input voltage is now Vbe, with the output voltage Vce. For the common-base configura-
tion of Fig. 5.98, Ii = Ie, Io = Ic with Veb = Vi and Vcb = Vo. The networks of Figs. 5.97
and 5.98 are applicable for pnp or npn transistors.

FIG. 5.98
Common-base configuration: (a) graphical symbol; (b) hybrid equivalent circuit.

The fact that both a Thévenin and a Norton circuit appear in the circuit of Fig. 5.96 was
further impetus for calling the resultant circuit a hybrid equivalent circuit. Two additional
transistor equivalent circuits, not to be discussed in this text, called the z-parameter and
y-parameter equivalent circuits, use either the voltage source or the current source, but not
both, in the same equivalent circuit. In Appendix A the magnitudes of the various param-
eters will be found from the transistor characteristics in the region of operation resulting in
the desired small-signal equivalent network for the transistor.
For the common-emitter and common-base configurations, the magnitude of hr and ho
is often such that the results obtained for the important parameters such as Zi, Zo, Av, and
Ai are only slightly affected if hr and ho are not included in the model.
Because hr is normally a relatively small quantity, its removal is approximated by
hr ⬵ 0 and hrVo = 0, resulting in a short-circuit equivalent for the feedback element as
shown in Fig. 5.99. The resistance determined by 1>ho is often large enough to be ignored
in comparison to a parallel load, permitting its replacement by an open-circuit equivalent
for the CE and CB models, as shown in Fig. 5.99.
The resulting equivalent of Fig. 5.100 is quite similar to the general structure of the
common-base and common-emitter equivalent circuits obtained with the re model. In fact,

Ii Io

+ hi +
Vi h f Ii Vo

– –

FIG. 5.99 FIG. 5.100

Effect of removing hre and hoe from the hybird Approximate hybrid equivalent model.
equivalent circuit.
the hybrid equivalent and the re models for each configuration are repeated in Fig. 5.101 THE HYBRID 323
for comparison. It should be reasonably clear from Fig. 5.101a that EQUIVALENT MODEL

hie = bre (5.139)

and hfe = bac (5.140)

From Fig. 5.101b,

hib = re (5.141)

and hfb = -a ⬵ -1 (5.142)

In particular, note that the minus sign in Eq. (5.142) accounts for the fact that the current
source of the standard hybrid equivalent circuit is pointing down rather than in the actual
direction as shown in the re model of Fig. 5.101b.

Ib Ic Ib Ic
b c b c

h ie h fe Ib β re β Ib

e e e e

(a)

Ie Ic Ie Ic
e c e c

hib h f b Ib re α Ie

b b b e

(b)

FIG. 5.101
Hybrid versus re model: (a) common-emitter configuration; (b) common-base configuration.

EXAMPLE 5.19 Given IE = 2.5 mA, hfe = 140, hoe = 20 mS (mmho), and hob = 0.5 mS,
determine:
a. The common-emitter hybrid equivalent circuit.
b. The common-base re model.

Solution:
26 mV 26 mV
a. re = = = 10.4 ⍀
IE 2.5 mA
hie = bre = (140)(10.4 ) = 1.456 k⍀
1 1
ro = = = 50 k⍀
hoe 20 mS
324 BJT AC ANALYSIS Note Fig. 5.102.

b c
Ib
1
h ie 1.456 kΩ 140 Ib = 50 kΩ
h oe

e e

FIG. 5.102
Common-emitter hybrid equivalent circuit for the parameters of Example 5.19.

b. re = 10.4 ⍀
1 1
a ⬵ 1, ro = = = 2 M⍀
hob 0.5 mS
Note Fig. 5.103.

FIG. 5.103
Common-base re model for the parameters of Example 5.19.

A series of equations relating the parameters of each configuration for the hybrid
equivalent circuit is provided in Appendix B. In Section 5.23 it is demonstrated that the
hybrid parameter hfe (bac) is the least sensitive of the hybrid parameters to a change in col-
lector current. Assuming, therefore, that hfe = b is a constant for the range of interest, is
a fairly good approximation. It is hie = bre that will vary significantly with IC and should
be determined at operating levels because it can have a real effect on the gain levels of a
transistor amplifier.

5.20 APPROXIMATE HYBRID EQUIVALENT CIRCUIT

●
The analysis using the approximate hybrid equivalent circuit of Fig. 5.104 for the common-
emitter configuration and of Fig. 5.105 for the common-base configuration is very similar
to that just performed using the re model. A brief overview of some of the most important
configurations will be included in this section to demonstrate the similarities in approach
and the resulting equations.

B C E C
Ib Ie
hie hfe Ib 1/hoe hib hfb Ie 1/hob

E E
B B

FIG. 5.104 FIG. 5.105

Approximate common-emitter hybrid equivalent circuit. Approximate common-base hybrid equivalent circuit.
 Because the various parameters of the hybrid model are specified by a data sheet or APPROXIMATE HYBRID 325
experimental analysis, the dc analysis associated with use of the re model is not an integral EQUIVALENT CIRCUIT
part of the use of the hybrid parameters. In other words, when the problem is presented, the
parameters such as hie, hfe, hib, and so on, are specified. Keep in mind, however, that the
hybrid parameters and components of the re model are related by the following equations, as
discussed earlier in this chapter: hie = bre, hfe = b, hoe = 1>ro, h f b = -a, and hib = re.

Fixed-Bias Configuration
For the fixed-bias configuration of Fig. 5.106, the small-signal ac equivalent network will
appear as shown in Fig. 5.107 using the approximate common-emitter hybrid equivalent
model. Compare the similarities in appearance with Fig. 5.22 and the re model analysis.
The similarities suggest that the analyses will be quite similar, and the results of one can be
directly related to the other.

VCC

RC Io
RB Ii Ic
+ + +
Ii C2 Ib
hie Zi Io
+ hfe Zo
C1 Vi RB hie hfe Ib 1/hoe RC Vo
Vo
Vi Zi
– – – Zo –

FIG. 5.106 FIG. 5.107

Fixed-bias configuration. Substituting the approximate hybrid equivalent circuit into the ac
equivalent network of Fig. 5.106.

Zi From Fig. 5.107,

Zi = RB 7 hie (5.143)

Zo From Fig. 5.107,

Zo = RC 7 1>hoe (5.144)

Av Using R = 1>hoe 7 RC, we obtain

Vo = -Io R = -ICR
= -hfe Ib R
Vi
and Ib =
hie
Vi
with Vo = -hfe R
hie

Vo hie(RC 7 1>hoe)
so that Av = = - (5.145)
Vi hie

A i Assuming that RB W hie and 1>hoe Ú 10RC, we find Ib ⬵ Ii and Io = Ic =

h fe Ib = h fe Ii, and so

Io
Ai = ⬵ hfe (5.146)
Ii
326 BJT AC ANALYSIS
EXAMPLE 5.20 For the network of Fig. 5.108, determine:
a. Zi.
b. Zo.
c. Av.
d. Ai.

8V
Io
2.7 kΩ
330 kΩ
Vo
Vi hfe = 120 Zo
hie = 1.175 kΩ
Ii hoe = 20 μ A/V

Zi

FIG. 5.108
Example 5.20.

Solution:
a. Zi = RB 7 hie = 330 k 7 1.175 k
⬵ hie = 1.171 k⍀
1 1
b. ro = = = 50 k
hoe 20 mA>V
1
Zo = 7 R = 50 k 7 2.7 k = 2.56 k⍀ ⬵ RC
hoe C
hfe(RC 7 1>hoe) (120)(2.7 k 7 50 k)
c. Av = - = - = ⴚ262.34
hie 1.171 k
d. Ai ⬵ hfe = 120

Voltage-Divider Configuration
For the voltage-divider bias configuration of Fig. 5.109, the resulting small-signal ac
equivalent network will have the same appearance as Fig. 5.107, with RB replaced by
R = R1 7 R2.

VCC

Io

RC
R1
Vo
Ii C2
hie
Vi hfe
C1
Zo
R2
Zi RE CE

FIG. 5.109
Voltage-divider bias configuration.
Zi From Fig. 5.107 with RB = R, APPROXIMATE HYBRID 327
EQUIVALENT CIRCUIT
Zi = R1 7 R2 7 hie (5.147)

Zo From Fig. 5.107,

Zo ⬵ RC (5.148)

Av

hfe(RC 7 1>hoe)
Av = - (5.149)
hie

Ai

hfe(R1 7 R2)
Ai = (5.150)
R1 7 R2 + hie

Unbypassed Emitter-Bias Configuration

For the CE unbypassed emitter-bias configuration of Fig. 5.110, the small-signal ac model
will be the same as Fig. 5.30, with bre replaced by hie and bIb by hfeIb. The analysis will
proceed in the same manner.
VCC

Io

RC
RB

Vo

Vi hie
hfe
Ii
Zo

Zi RE

FIG. 5.110
CE unbypassed emitter-bias configuration.

Zi

Zb ⬵ h fe RE (5.151)

and Zi = RB 7 Zb (5.152)

Zo

Zo = RC (5.153)

Av
hfeRC hfeRC
Av = - ⬵ -
Zb hfeRE

RC
and Av ⬵ - (5.154)
RE
328 BJT AC ANALYSIS Ai

hfeRB
Ai = - (5.155)
RB + Zb

Zi
or Ai = -Av (5.156)
RC

Emitter-Follower Configuration
For the emitter-follower of Fig. 5.38, the small-signal ac model will match that of Fig.
5.111, with bre = hie and b = hfe. The resulting equations will therefore be quite similar.

VCC

RB
Ii
hie
Vi hfe
Zi
Vo
Io Zo
RE

FIG. 5.111
Emitter-follower configuration.

Zi

Zb ⬵ hfeRE (5.157)

Zi = RB 7 Zb (5.158)

Zo For Zo, the output network defined by the resulting equations will appear as shown in
Fig. 5.112. Review the development of the equations in Section 5.8 and
hie
Zo = RE 7
1 + hfe
or, because 1 + hfe ⬵ hfe,

hie
Zo ⬵ RE 7 (5.159)
hfe

FIG. 5.112
Defining Zo for the emitter-follower configuration.
Av For the voltage gain, the voltage-divider rule can be applied to Fig. 5.112 as follows: APPROXIMATE HYBRID 329
EQUIVALENT CIRCUIT
RE (Vi)
Vo =
RE + hie >(1 + hfe)
but, since 1 + hfe ⬵ hfe,

Vo RE
Av = ⬵ (5.160)
Vi RE + hie >hfe

Ai

hfe RB
Ai = (5.161)
RB + Zb

Zi
or Ai = -Av (5.162)
RE

Common-Base Configuration
The last configuration to be examined with the approximate hybrid equivalent circuit will be
the common-base amplifier of Fig. 5.113. Substituting the approximate common-base hybrid
equivalent model results in the network of Fig. 5.114, which is very similar to Fig. 5.44.

hib , hfb
Ii Ic

+ Io +
RE RC
Vi Zi Vo Zo
+ –
VEE VCC
– – + –

FIG. 5.113
Common-base configuration.

+ Ii Ie +
Io

Zi Zo
Vi RE hib hfb Ie RC Vo

– –

FIG. 5.114
Substituting the approximate hybrid equivalent circuit into the ac equivalent network
of Fig. 5.113.

We have the following results from Fig. 5.114.

Zi

Zi = RE 7 hib (5.163)

Zo

Zo = RC (5.164)
330 BJT AC ANALYSIS Av
Vo = -IoRC = -(h f b Ie)RC
Vi Vi
with Ie = and Vo = -h f b R
hib hib C

Vo h f b RC
so that Av = = - (5.165)
Vi hib

Ai

Io
Ai = = h f b ⬵ -1 (5.166)
Ii

EXAMPLE 5.21 For the network of Fig. 5.115, determine:

a. Zi.
b. Zo.
c. Av.
d. Ai.

Ii

+ Io
+

Zi 2.2 kΩ hfb = − 0.99 3.3 kΩ

Vi Vo Zo
hib = 14.3 Ω
+ –
4V hob = 0.5 μA/V 10 V
– – + –

FIG. 5.115
Example 5.21.

Solution:
a. Zi = RE 7 hib = 2.2 k 7 14.3  = 14.21 ⍀ ⬵ hib
1 1
b. ro = = = 2 M⍀
hob 0.5 mA>V
1
Zo = 7 R ⬵ RC = 3.3 k⍀
hob C
h f b RC (-0.99)(3.3 k)
c. Av = - = - = 229.91
hib 14.21
d. Ai ⬵ h f b = ⴚ1

The remaining configurations that were not analyzed in this section are left as an exercise
in the problem section of this chapter. It is assumed that the analysis above clearly reveals the
similarities in approach using the re or approximate hybrid equivalent models, thereby
removing any real difficulty with analyzing the remaining networks of the earlier sections.

5.21 COMPLETE HYBRID EQUIVALENT MODEL

●
The analysis of Section 5.20 was limited to the approximate hybrid equivalent circuit with
some discussion about the output impedance. In this section, we employ the complete
equivalent circuit to show the effect of hr and define in more specific terms the effect of ho.
It is important to realize that because the hybrid equivalent model has the same appearance
for the common-base, common-emitter, and common-collector configurations, the equa-
tions developed in this section can be applied to each configuration. It is only necessary to
insert the parameters defined for each configuration. That is, for a common-base configu- COMPLETE HYBRID 331
ration, hfb, hib, and so on, are employed, whereas for a common-emitter configuration, hfe, EQUIVALENT MODEL
hie, and so on, are used. Recall that Appendix A permits a conversion from one set to the
other if one set is provided and the other is required.
Consider the general configuration of Fig. 5.116 with the two-port parameters of particu-
lar interest. The complete hybrid equivalent model is then substituted in Fig. 5.117 using
parameters that do not specify the type of configuration. In other words, the solutions will
be in terms of hi, hr, hf, and ho. Unlike the analysis of previous sections of this chapter,
here the current gain Ai will be determined first because the equations developed will prove
useful in the determination of the other parameters.

Io

+ +
Ii
Rs
Zo
+ Vi Transistor Vo RL
Zi
Vs

– – –

FIG. 5.116
Two-port system.

Ii
Ib Io
+ hi I
+
Rs +
+ Vi hr Vo hf Ib 1/ho Vo RL
Zi Zo
Vs –
– – –

FIG. 5.117
Substituting the complete hybrid equivalent circuit into the two-port system of Fig. 5.116.

Current Gain, Ai ⴝ Io , Ii
Applying Kirchhoff’s current law to the output circuit yields
Vo
Io = hf Ib + I = hf Ii + = hf Ii + hoVo
1>ho
Substituting Vo = -Io RL gives
Io = hf Ii - ho RLIo
Rewriting the equation above, we have
Io + ho RLIo = hf Ii
and Io(1 + ho RL) = hf Ii

Io hf
so that Ai = = (5.167)
Ii 1 + ho RL

Note that the current gain reduces to the familiar result of Ai = hf if the factor hoRL is suf-
ficiently small compared to 1.

Voltage Gain, Av ⴝ Vo , Vi
Applying Kirchhoff’s voltage law to the input circuit results in
Vi = Iihi + hrVo
332 BJT AC ANALYSIS Substituting Ii = (1 + hoRL)Io >hf from Eq. (5.167) and Io = -Vo >RL from above
results in
-(1 + ho RL)hi
Vi = Vo + hrVo
hf RL
Solving for the ratio Vo >Vi yields

Vo -hf RL
Av = = (5.168)
Vi hi + (hiho - hf hr)RL

In this case, the familiar form of Av = -hf RL >hi returns if the factor (hiho - hf hr)RL is
sufficiently small compared to hi.

Input Impedance, Zi ⴝ Vi , Ii
For the input circuit,
Vi = hi Ii + hrVo
Substituting Vo = -Io RL
we have Vi = hi Ii - hr RLIo
Io
Because Ai =
Ii
Io = AiIi
so that the equation above becomes
Vi = hi Ii - hr RLAi Ii
Solving for the ratio Vi >Ii, we obtain
Vi
Zi = = hi - hr RL Ai
Ii
and substituting
hf
Ai =
1 + ho RL

Vi hf hr RL
yields Zi = = hi - (5.169)
Ii 1 + ho RL

The familiar form of Zi = hi is obtained if the second factor in the denominator (hoRL) is
sufficiently smaller than one.

Output Impedance, Zo ⴝ Vo , Io
The output impedance of an amplifier is defined to be the ratio of the output voltage to the
output current with the signal Vs set to zero. For the input circuit with Vs  0,
hrVo
Ii = -
Rs + hi
Substituting this relationship into the equation from the output circuit yields
Io = hf Ii + hoVo
hf hrVo
= - + hoVo
Rs + hi

Vo 1
and Zo = = (5.170)
Io ho - [hf hr >(hi + Rs)]

In this case, the output impedance is reduced to the familiar form Zo = 1>ho for the transis-
tor when the second factor in the denominator is sufficiently smaller than the first.
 COMPLETE HYBRID 333
EXAMPLE 5.22 For the network of Fig. 5.118, determine the following parameters using EQUIVALENT MODEL
the complete hybrid equivalent model and compare to the results obtained using the
approximate model.
a. Zi and Zi.
b. Av.
c. Ai = Io >Ii.
d. Zo (within RC) and Zo (including RC).

Ii Ii'

Zi

' Zo

FIG. 5.118
Example 5.22.

Solution: Now that the basic equations for each quantity have been derived, the order in
which they are calculated is arbitrary. However, the input impedance is often a useful quan-
tity to know, and therefore will be calculated first. The complete common-emitter hybrid
equivalent circuit has been substituted and the network redrawn as shown in Fig. 5.119. A
Thévenin equivalent circuit for the input section of Fig. 5.119 results in the input equivalent
of Fig. 5.120 because ETh ⬵ Vs and RTh ⬵ Rs = 1 k (a result of RB = 470 k being
much greater than Rs = 1 k). In this example, RL = RC, and Io is defined as the current
through RC as in previous examples of this chapter. The output impedance Zo as defined
by Eq. (5.170) is for the output transistor terminals only. It does not include the effects
of RC. Zo is simply the parallel combination of Zo and RL. The resulting configuration of

Ii Ii' Io
Ib
+ 1.6 kΩ +
Zi Z'i Z'o Zo
Rs 1 kΩ +
+ Vi 470 kΩ 2 × 10− 4 Vo 110 Ib 50 kΩ 4.7 kΩ Vo
Vs –
– – –

Thévenin

FIG. 5.119
Substituting the complete hybrid equivalent circuit into the ac equivalent network of Fig. 5.118.
 Ii Ii' hie Io

+ 1.6 kΩ +
Zi Z'i Z'o Zo
Rs 1 kΩ + 1
hre Vo hfe Ib hoe = 50 kΩ
+ Vi 2 × 10− 4 Vo 110 Ib
4.7 kΩ Vo
hoe = 20 μS
Vs –
– – –

FIG. 5.120
Replacing the input section of Fig. 5.119 with a Thévenin equivalent circuit.

Fig. 5.120 is then an exact duplicate of the defining network of Fig. 5.117, and the equa-
tions derived above can be applied.
a. Eq. (5.169):
Vi hfehreRL
Zi = = hie -
Ii 1 + hoeRL
(110)(2 * 10-4)(4.7 k)
= 1.6 k -
1 + (20 mS)(4.7 k)
= 1.6 k - 94.52 
= 1.51 k⍀
versus 1.6 k using simply hie; and
Zi = 470 k 7 Zi ⬵ Zi = 1.51 k⍀
b. Eq. (5.168):
Vo -hfeRL
Av = =
Vi hie + (hiehoe - hfehre)RL
-(110)(4.7 k)
=
1.6 k + [(1.6 k)(20 mS) - (110)(2 * 10-4)]4.7 k
-517 * 103 
=
1.6 k + (0.032 - 0.022)4.7 k
-517 * 103 
=
1.6 k + 47 
= ⴚ313.9
versus -323.125 using Av ⬵ -hfeRL >hie.
c. Eq. (5.167):
Io hfe 110
Ai = = =
Ii 1 + hoe RL 1 + (20 mS)(4.7 k)
110
= = 100.55
1 + 0.094
versus 110 using simply hfe. Because 470 k W Zi, Ii ⬵ Ii and Ai ⬵ 100.55 also.
d. Eq. (5.170):
Vo 1
Zo = =
Io hoe - [hfehre >(hie + Rs)]
1
=
20 mS - [(110)(2 * 10-4)>(1.6 k + 1 k)]
1
=
20 mS - 8.46 mS
1
=
11.54 mS
= 86.66 k⍀
334
 which is greater than the value determined from 1>hoe, 50 k; and COMPLETE HYBRID 335
EQUIVALENT MODEL
Zo = RC 7 Zo = 4.7 k 7 86.66 k = 4.46 k⍀
versus 4.7 k using only RC.

Note from the results above that the approximate solutions for Av and Zi were very close
to those calculated with the complete equivalent model. In fact, even Ai was off by less than
10%. The higher value of Zo only contributed to our earlier conclusion that Zo is often so
high that it can be ignored compared to the applied load. However, keep in mind that when
there is a need to determine the effect of hre and hoe, the complete hybrid equivalent model
must be used, as described earlier.
The specification sheet for a particular transistor typically provides the common-emitter
parameters as noted in Fig. 5.92. The next example will employ the same transistor pa-
rameters appearing in Fig. 5.118 in a pnp common-base configuration to introduce the
parameter conversion procedure and emphasize the fact that the hybrid equivalent model
maintains the same layout.

EXAMPLE 5.23 For the common-base amplifier of Fig. 5.121, determine the following
parameters using the complete hybrid equivalent model and compare the results to those
obtained using the approximate model.
a. Zi
b. Ai
c. Av.
d. Zo

hie = 1.6 kΩ hfe = 110

hre = 2 × 10− 4 hoe = 20 μS
Io

+ +
Ii Ii'
Rs 1 kΩ 3 kΩ 2.2 kΩ

+ Vi Vo
Zi + Z'i Z'o – Zo
Vs 12 V
6V
– – +
– –

FIG. 5.121
Example 5.23.

Solution: The common-base hybrid parameters are derived from the common-emitter
parameters using the approximate equations of Appendix B:
hie 1.6 k
hib ⬵ = = 14.41 ⍀
1 + hfe 1 + 110
Note how closely the magnitude compares with the value determined from
hie 1.6 k
hib = re = = = 14.55 
b 110
hiehoe (1.6 k)(20 mS)
Also, hrb ⬵ - hre = - 2 * 10-4
1 + hfe 1 + 110
= 0.883 : 10 ⴚ 4
-hfe -110
hf b ⬵ = = ⴚ0.991
1 + hfe 1 + 110
hoe 20 mS
hob ⬵ = = 0.18 MS
1 + hfe 1 + 110
 Ii Ii' hib Io
e c
+ 14.41 Ω +
Zi Z'i Ie Z'o Zo
Rs 1 kΩ +
+ 3 kΩ Vi 0.883 × 10− 4 Vo − 0.991Ie hob = 0.18 μ S 2.2 kΩ Vo
hrb Vo hfb Ie
Vs –
– – –
b b
Thévenin

FIG. 5.122
Small-signal equivalent for the network of Fig. 5.121.

Substituting the common-base hybrid equivalent circuit into the network of Fig. 5.121
results in the small-signal equivalent network of Fig. 5.122. The Thévenin network for the
input circuit results in RTh = 3 k 7 1 k = 0.75 k for Rs in the equation for Zo.
a. Eq. (5.169):
Vi hf b hrb RL
Zi = = hib -
Ii 1 + hob RL
(-1.991)(0.883 * 10-4)(2.2 k)
= 14.41  -
1 + (0.18 mS)(2.2 k)
= 14.41  + 0.19 
= 14.60 
versus 14.41  using Zi ⬵ hib; and
Zi = 3 k 7 Zi ⬵ Zi = 14.60 ⍀
b. Eq. (5.167):
Io hfb
Ai = =
Ii 1 + hob RL
-0.991
=
1 + (0.18 mS)(2.2 k)
= -0.991
Because 3 k W Zi, Ii ⬵ Ii and Ai = Io >Ii ⬵ ⴚ1.
c. Eq. (5.168):
Vo -hf b RL
Av = =
Vi hib + (hibhob - hf b hrb)RL
-(-0.991)(2.2 k)
=
14.41  + [(14.41)(0.18 mS) - (-0.991)(0.883 * 10-4)]2.2 k
= 149.25
versus 151.3 using Av ⬵ -hf b RL >hib.
d. Eq. (5.170):
1
Zo =
hob - [hf b hrb >(hib + Rs) 4
1
=
0.18 mS - [(-0.991)(0.883 * 10-4)>(14.41  + 0.75 k)]
1
=
0.295 mS
= 3.39 M⍀
versus 5.56 M using Zo ⬵ 1>hob. For Zo as defined by Fig. 5.122,
Zo = RC 7 Zo = 2.2 k 7 3.39 M = 2.199 k⍀
versus 2.2 k using Zo ⬵ RC.
336
5.22 HYBRID P MODEL HYBRID p MODEL 337
●
The last transistor model to be introduced is the hybrid p model of Fig. 5.123 which
includes parameters that do not appear in the other two models primarily to provide a more
accurate model for high-frequency effects.

ru

B b' C
Cu
rb Ib'
Ib +

Vπ rπ Cπ ro βIb ' = gmVπ

–

E E

FIG. 5.123
Giacoletto (or hybrid p) high-frequency transistor small-signal ac equivalent circuit.

rP, ro, rb, and ru

The resistors rp, ro, rb, and ru are the resistances between the indicated terminals of the
device when the device is in the active region. The resistance rp (using the symbol p to agree
with the hybrid p terminology) is simply bre as introduced for the common-emitter re model.
That is,

rp = bre (5.171)

The output resistance ro is the output resistance normally appearing across an applied
load. Its value, which typically lies between 5 k and 40 k, is determined from the hybrid
parameter hoe, the Early voltage, or the output characteristics.
The resistance rb includes the base contact, base bulk, and base spreading resistance levels.
The first is due to the actual connection to the base. The second includes the resistance from
the external terminal to the active region of the transistor, and the last is the actual resistance
within the active base region. It is typically a few ohms to tens of ohms.
The resistance ru (the subscript u refers to the union it provides between collector and
base terminals) is a very large resistance and provides a feedback path from output to
input circuits in the equivalent model. It is typically larger than bro, which places it in the
megohm range.

CP and Cu
All the capacitors that appear in Fig. 5.123 are stray parasitic capacitors between the vari-
ous junctions of the device. They are all capacitive effects that really only come into play
at high frequencies. For low to mid-frequencies their reactance is very large, and they can
be considered open circuits. The capacitor Cp across the input terminals can range from a
few pF to tens of pF. The capacitor Cu from base to collector is usually limited to a few pF
but is magnified at the input and output by an effect called the Miller effect, to be intro-
duced in Chapter 9.

BIⴕb or gm VP
It is important to note in Fig. 5.123 that the controlled source can be a voltage-controlled
current source (VCCS) or a current-controlled current source (CCCS), depending on the
parameters employed.
Note the following parameter equivalence in Fig. 5.123:

1
gm = (5.172)
re
338 BJT AC ANALYSIS 1
and ro = (5.173)
hoe

rp rp
with ⬵ ⬵ hre (5.174)
rp + ru ru

Take particular note of the fact that the equivalent sources bIb and gmVp are both con-
trolled current sources. One is controlled by a current at another place in the network and
the other by a voltage at the input side of the network. The equivalence between the two
is defined by
1 #
bIb = r bI = gmIbbre = gm(Ibrp) = gmVp
re e b
For the broad range of low- to mid-frequency analysis, the effect of the stray capaci-
tive effects can be ignored due to the very high reactance levels associated with each. The
resistance rb is usually small enough with other series elements to be ignored while the
resistance ru is usually large enough compared to parallel elements to be ignored. The result
is an equivalent network similar to the re model introduced and applied in this chapter.
In Chapter 9, when high-frequency effects are considered, the hybrid p model will be
the model of choice.

5.23 VARIATIONS OF TRANSISTOR PARAMETERS

●
A variety of curves can be drawn to show the variations of the transistor parameters with tem-
perature, frequency, voltage, and current. The most interesting and useful at this stage of the
development include the variations with junction temperature and collector voltage and current.
The effect of the collector current on the re model and hybrid equivalent model is shown
in Fig. 5.124. Take careful note of the logarithmic scale on the vertical and horizontal axes.
Logarithmic scales will be examined in detail in Chapter 9. The parameters have all been
normalized (a process described in detail in Section 9.5) to unity so that the relative change
in magnitude with collector current can easily be determined. On each set of curves, such
as in Figs. 5.124 to 5.126, the operating point at which the parameters were determined
is always indicated. For this particular situation, the quiescent point is at the fairly typical
values of VCE  5.0 V and IC = 1.0 mA. Because the frequency and temperature of operation

1
hoe ( ro)

h ie (␤re)

h re ( r␲u )
r

h fe (␤)

1
hoe ( ro)

FIG. 5.124
Hybrid parameter variations with collector current.
also affect the parameters, these quantities are also indicated on the curves. Figure 5.124 VARIATIONS OF 339
shows the variation of the parameters with collector current. Note that at IC = 1 mA the TRANSISTOR
PARAMETERS
value of all the parameters has been normalized to 1 on the vertical axis. The result is that
the magnitude of each parameter is compared to the values at the defined operating point.
Because manufacturers typically use the hybrid parameters for plots of this type, they are
the curves of choice in Fig. 5.124. However, to broaden the use of the curves the re and
hybrid p equivalent parameters have also been added.
At first glance it is particularly interesting to note that:
The parameter hfe(B) varies the least of all the parameters of a transistor equivalent
circuit when plotted against variations in collector current.
Figure 5.124 clearly reveals that for the full range of collector current the parameter hfe(b)
varies from 0.5 of its Q-point value to a peak of about 1.5 times that value at a current of
about 6 mA. For a transistor with a b of 100, it therefore varies from about 50 to 150. This
seems like quite a bit, but look at hoe, which jumps to almost 40 times its Q-point value at
a collector current of 50 mA.
Figure 5.124 also shows that hoe(1>ro) and hie(bre) vary the most for the chosen current
range. The parameter hie varies from about 10 times its Q-point value down to about one
tenth the Q point value at 50 mA. This variation, however, should be expected because we
know that the value of re is directly related to the emitter current by re = 26 mV>IE. As
IE (⬵IC) increases, the value of re and therefore bre will decrease, as shown in Fig. 5.124.
Keep in mind as you review the curve of hoe versus current that the actual output resis-
tance ro is 1>hoe. Therefore, as the curve increases with current, the value of ro becomes
less and less. Because ro is a parameter that normally appears in parallel with the applied
load, decreasing values of ro can become a critical problem. The fact that ro has dropped to
almost 1/40 of its value at the Q-point could spell a real reduction in gain at 50 mA.
The parameter hre varies quite a bit, but because its Q-point value is usually small enough
to permit ignoring its effect, it is a parameter that is only of concern for collector currents
that are much less, or quite a bit more, than the Q-point level.
This may seem like an extensive description of a set of characteristic curves. However,
experience has revealed that graphs of this nature are too often reviewed without taking the
time to fully appreciate the broad impact of what they are providing. These plots reveal a
lot of information that could be extremely useful in the design process.
Figure 5.125 shows the variation in magnitude of the parameters due to changes in
collector-to-emitter voltage. This set of curves is normalized at the same operating point
as the curves of Fig. 5.124 to permit comparisons between the two. In this case, however,
the vertical scale is in percent rather than whole numbers. The 200% level defines a set of
parameters twice that at the 100% level. A level of 1000% would reflect a 10:1 change.
Note that hfe and hie are relatively steady in magnitude with variations in collector-to-
emitter voltage, whereas for changes in collector current the variation is a great deal more

1
hre ( r␲u )
hoe ( ro) r

hre ( r␲u )
r
1
hoe ( ro)

hie (␤re)
hfe (␤)
hfe (␤)
hie (␤re)

FIG. 5.125
Hybrid parameter variations with collector–emitter potential.
340 BJT AC ANALYSIS significant. In other words, if you want a parameter such as hie(bre) to remain fairly steady,
keep the variation of IC to a minimum while worrying less about variations in the collector-
to-emitter voltage. The variation of hoe and hie remains significant for the indicated range
of collector-to-emitter voltage.
In Fig. 5.126, the variation in parameters is plotted for changes in junction temperature.
The normalization value is taken to be room temperature, T  25°C. The horizontal scale
is now a linear scale rather than the logarithmic scale employed in the two previous figures.
In general:
All the parameters of a hybrid transistor equivalent circuit increase with temperature.

hie (␤re)

hre ( r␲u )
r

hfe (␤)
1
hoe ( ro)

1
hoe ( ro)

hre ( r␲u )
r

hfe (␤)

hie (␤re)

FIG. 5.126
Hybrid parameter variations with temperature.

However, again keep in mind that the actual output resistance ro is inversely related
to hoe, so its value drops with an increase in hoe. The greatest change is in hie, although
note that the range of the vertical scale is considerably less than in the other plots. At a
temperature of 200⬚C the value of hie is almost 3 times its Q-point value, but in Fig. 5.124
parameters jumped to almost 40 times the Q-point value.
Of the three parameters, therefore, the variation in collector current has by far the great-
est effect on the parameters of a transistor equivalent circuit. Temperature is always a factor,
but the effect of the collector current can be significant.

5.24 TROUBLESHOOTING
●
Although the terminology troubleshooting suggests that the procedures to be described are
designed simply to isolate a malfunction, it is important to realize that the same techniques
can be applied to ensure that a system is operating properly. In any case, the testing, check-
ing, and isolating procedures require an understanding of what to expect at various points
in the network in both the dc and ac domains. In most cases, a network operating correctly
in the dc mode will also behave properly in the ac domain.
In general, therefore, if a system is not working properly, first disconnect the ac source
and check the dc biasing levels.
In Fig. 5.127 we have four transistor configurations with specific voltage levels provided
as measured by a DMM in the dc mode. The first test of any transistor network is to simply
measure the base-to-emitter voltage of the transistor. The fact that it is only 0.3 V in this
case suggests that the transistor is not “on” and perhaps sitting in its saturation mode. If this
is a switching design then the result is expected, but if in the amplifier mode there is an open
connection preventing the base voltage from reaching an operating level.
 VCC 20 V 18 V 12 V

RC RC RC
RB RC R1 RB R1

20 V
+ 6V
+ 3V
0.3 V – –
R2 R2
RE RE

(a) (b) (c) (d)

FIG. 5.127
Checking the dc levels to determine if a network is properly biased.

In Fig. 5.127b the fact that the voltage at the collector equals the supply voltage reveals
that there is no drop across the resistor RC and the collector current is zero. The resistor RC
is connected properly because it made the connection from the dc source to the collector.
However, any one of the other elements may not have been connected properly, resulting
in the absence of a base or collector current. In Fig. 5.127c the voltage drop across the
collector-to-emitter voltage is too small compared with the applied dc voltage. Normally
the voltage VCE is in the mid-range of perhaps 6 V to 14 V. A reading of 18 V would cause
the same concern as the reading of 3 V. The fact that the voltage levels exist at all suggests
that all the elements are connected but the value of one or more of the resistive elements
may be wrong. In Fig. 5.127d we find that the voltage at the base is exactly half the supply
voltage. We know from this chapter that the resistance RE will reflect back to the base by
a factor of beta and appear in parallel with R2. The result would be a base voltage less than
half the supply voltage. The measurement suggests that the base lead is not connected to
the voltage divider, causing an even split of the 20-V source.
In a typical laboratory setting, the ac response at various points in the network is checked
with an oscilloscope as shown in Fig. 5.128. Note that the black (gnd) lead of the oscillo-
scope is connected directly to ground and the red lead is moved from point to point in the

VCC

v o (V)
RC
RB
C2
vo
0 t
C1
vi
ve

v i (mV) ve
Rs 0 t

+ 0 t Oscilloscope
RE CE
Vs

(AC-GND-DC switch on AC)

Ground strap

FIG. 5.128
Using the oscilloscope to measure and display various voltages of a BJT amplifier.
341
342 BJT AC ANALYSIS network, providing the patterns appearing in Fig. 5.128. The vertical channels are set in
the ac mode to remove any dc component associated with the voltage at a particular point.
The small ac signal applied to the base is amplified to the level appearing from collector to
ground. Note the difference in vertical scales for the two voltages. There is no ac response
at the emitter terminal due to the short-circuit characteristics of the capacitor at the applied
frequency. The fact that vo is measured in volts and vi in millivolts suggests a sizable gain
for the amplifier. In general, the network appears to be operating properly. If desired, the
dc mode of the multimeter could be used to check VBE and the levels of VB, VCE, and VE to
review whether they lie in the expected range. Of course, the oscilloscope can also be used
to compare dc levels simply by switching to the dc mode for each channel.
A poor ac response can be due to a variety of reasons. In fact, there may be more than
one problem area in the same system. Fortunately, however, with time and experience, the
probability of malfunctions in some areas can be predicted, and an experienced person can
isolate problem areas fairly quickly.
In general, there is nothing mysterious about the general troubleshooting process. If you
decide to follow the ac response, it is good procedure to start with the applied signal and
progress through the system toward the load, checking critical points along the way. An
unexpected response at some point suggests that the network is fine up to that area, thereby
defining the region that must be investigated further. The waveform obtained on the oscil-
loscope will certainly help in defining the possible problems with the system.
If the response for the network of Fig. 5.128 is as appears in Fig. 5.129, the network has
a malfunction that is probably in the emitter area. An ac response across the emitter is unex-
pected, and the gain of the system as revealed by vo is much lower. Recall for this configuration
that the gain is much greater if RE is bypassed. The response obtained suggests that RE is not
bypassed by the capacitor, and the terminal connections of the capacitor and the capacitor itself
should be checked. In this case, a checking of the dc levels will probably not isolate the problem
area because the capacitor has an “open-circuit” equivalent for dc. In general, prior knowledge
of what to expect, familiarity with the instrumentation, and, most important, experience are all
factors that contribute to the development of an effective approach to the art of troubleshooting.

FIG. 5.129
The waveforms resulting from a malfunction in the emitter area.

5.25 PRACTICAL APPLICATIONS

●
Audio Mixer
When two or more signals are to be combined into a single audio output, mixers such as
shown in Fig. 5.130 are employed. The potentiometers at the input are the volume controls
for each channel, with potentiometer R3 included to provide additional balance between
 12 V PRACTICAL 343
APPLICATIONS
v1
470 k R4 R7
R1 R6 470 k 3.3 k
33 k C3
vo
C1 68 F

R3  = 120
1 M 56 F
v2
R5 Zi
470 k
R2 R8 C2 68 F
33 k 1.2 k

re = 11.71 
Zi ~
= re = 1.4 k

FIG. 5.130
Audio mixer.

the two signals. Resistors R4 and R5 are there to ensure that one channel does not load
down the other, that is, to ensure that one signal does not appear as a load to the other,
draw power, and affect the desired balance on the mixed signal.
The effect of resistors R4 and R5 is an important one that should be discussed in some
detail. A dc analysis of the transistor configuration results in re = 11.71 ⍀, which will
establish an input impedance to the transistor of about 1.4 k⍀. The parallel combination of
R6 7 Zi is also approximately 1.4 k⍀. Setting both volume controls to their maximum value
and the balance control R3 to its midpoint result in the equivalent network of Fig. 5.131a.
The signal at v1 is assumed to be a low-impedance microphone with an internal resistance
of 1 k⍀. The signal at v2 is assumed to be a guitar amplifier with a higher internal imped-
ance of 10 k⍀. Because the 470-k⍀ and 500-k⍀ resistors are in parallel for the above
conditions, they can be combined and replaced with a single resistor of about 242 k⍀. Each
source will then have an equivalent such as shown in Fig. 5.131b for the microphone. Ap-
plying Thévenin’s theorem shows that it is an excellent approximation to simply drop the
242 k⍀ and assume that the equivalent network is as shown for each channel. The result
is the equivalent network of Fig. 5.131c for the input section of the mixer. Applying the
superposition theorem results in the following equation for the ac voltage at the base of the
transistor:
(1.4 k⍀ 储 43 k⍀)vs1 (1.4 k⍀ 储 34 k⍀)vs2
vb = +
34 k⍀ + (1.4 k⍀ 储 43 k⍀) 43 k⍀ + (1.4 k⍀ 储 34 k⍀)
-3 -3
= 38 * 10 vs1 + 30 * 10 vs2
With re = 11.71 ⍀, the gain of the amplifier is -RC >re = 3.3 k⍀>11.71 ⍀ = -281.8,
and the output voltage is
vo = -10.7vs1 - 8.45vs2
which provides a pretty good balance between the two signals, even though they have a
10:1 ratio in internal impedance. In general, the system will respond quite well. However,
if we now remove the 33-k⍀ resistors from the diagram of Fig. 5.131c, the equivalent net-
work of Fig. 5.132 results, and the following equation for vb is obtained using the superpo-
sition theorem:
(1.4 k⍀ 储 10 k⍀)vs1 (1.4 k⍀ 储 1 k⍀)vs2
vb = +
1 k⍀ + 1.4 k⍀ 储 10 k⍀ 10 k⍀ + (1.4 k⍀ 储 1 k⍀)
= 0.55vs1 + 0.055vs2
Using the same gain as before, we obtain the output voltage as
vo = 155vs1 + 15.5vs2 ⬵ 155vs1
which indicates that the microphone will be quite loud and clear and the guitar input essen-
tially lost.
 33 k⍀
Microphone 1 k⍀
470 k⍀ 500 k⍀
+
vs1
Amplifier
–
Zi 1.4 k⍀

33 k⍀
Guitar 10 k⍀ 1 k⍀ 1 k⍀
470 k⍀ 500 k⍀
+ + 242 k⍀ ⇒ +
vs2 vs1 vs1

– – –

(a) (b)

Amplifier
R4 33 k⍀ R5 33 k⍀

1 k⍀ 10 k⍀ Zi 1.4 k⍀

+ +
vs1 vs2
– –

(c)

FIG. 5.131
(a) Equivalent network with R3 set at the midpoint and the volume controls on their maximum settings;
(b) finding the Thévenin equivalent for channel 1; (c) substituting the Thévenin equivalent networks into Fig. 5.131a.

Amplifier

1 k⍀ 10 k⍀

Zi 1.4 k⍀
+ +
vs1 vs2
– –

FIG. 5.132
Redrawing the network of Fig. 5.131c with the 33-k⍀
resistors removed.

The importance of the 33-k⍀ resistors is therefore defined. It makes each applied signal
appear to have a similar impedance level so that there is good balance at the output. One
might suggest that the larger resistor improves the balance. However, even though the bal-
ance at the base of the transistor may be better, the strength of the signal at the base of the
transistor will be less, and the output level reduced accordingly. In other words, the choice
of resistors R4 and R5 is a give-and-take situation between the input level at the base of the
transistor and the balance of the output signal.
To demonstrate that the capacitors are truly short-circuit equivalents in the audio range,
substitute a very low audio frequency of 100 Hz into the reactance equation of a 56-mF
capacitor:
1 1
XC = = = 28.42 ⍀
2pfC 2p(100 Hz)(56 mF)
344
A level of 28.42 ⍀ compared to any of the neighboring impedances is certainly small PRACTICAL 345
enough to be ignored. Higher frequencies will have even less effect. APPLICATIONS
A similar mixer will be discussed in connection with the junction field effect transistor
(JFET) in the following chapter. The major difference will be the fact that the input imped-
ance of the JFET can be approximated by an open circuit rather than the rather low-level
input impedance of the BJT configuration. The result will be a higher signal level at the
input to the JFET amplifier. However, the gain of the FET is much less than that of the BJT
transistor, resulting in output levels that are actually quite similar.

Preamplifier
The primary function of a preamplifier is as its name implies: an amplifier used to pick up
the signal from its primary source and then operate on it in preparation for its passage
into the amplifier section. Typically, a preamplifier will amplify the signal, control its vol-
ume, perhaps change its input impedance characteristics, and if necessary determine its route
through the stages to follow—in total, a stage of any system with a multitude of functions.
A preamplifier such as shown in Fig. 5.133 is often used with dynamic microphones
to bring the signal level up to levels that are suitable for further amplification or power
amplifiers. Typically, dynamic microphones are low-impedance microphones because
their internal resistance is determined primarily by the winding of the voice coil. The basic
construction consists of a voice coil attached to a small diaphragm that is free to move
within a permanent magnet. When one speaks into the microphone, the diaphragm moves
accordingly and causes the voice coil to move in the same manner within the magnetic
field. In accord with Faraday’s law, a voltage will be induced across the coil that will carry
the audio signal.

12 V

3.3 k⍀

47 k⍀
vo
10 μF 20 μF

82 k⍀

␤ = 140
20 μF Av ~
= –319.7
Dynamic
microphone
(Rint = 50 ⍀) ~ 1.33 k⍀
Zi =

FIG. 5.133
Preamplifier for a dynamic microphone.

Because it is a low-impedance microphone, the input impedance of the transistor ampli-

fier does not have to be that high to pick up most of the signal. Because the internal imped-
ance of a dynamic microphone may be as low as 20 ⍀ to 100 ⍀, most of the signal would
be picked up with an amplifier having an input impedance as low as 1 to 2 k⍀. This, in
fact, is the case for the preamplifier of Fig. 5.133. For dc biasing conditions, the collector
dc feedback configuration was chosen because of its high stablity characteristics.
In the ac domain, the 10@mF capacitor will assume a short-circuit state (on an approxi-
mate basis), placing the 82-k⍀ resistor across the input impedance of the transistor and the
47 k⍀ across the output of the transistor. A dc analysis of the transistor configuration results
in re = 9.64 ⍀, giving an ac gain determined by
(47 k⍀ 7 3.3 k⍀)
Av = - = ⴚ319.7
9.64 ⍀
which is excellent for this application. Of course, the gain will drop when this pickup stage
of the design is connected to the input of the amplifier section. That is, the input resistance
346 BJT AC ANALYSIS of the next stage will appear in parallel with the 47-k⍀ and 3.3-k⍀ resistors and will drop
the gain below the unloaded level of 319.7.
The input impedance of the preamplifier is determined by
Zi = 82 k⍀ 7 bre = 82 k⍀ 7 (140)(9.64 ⍀) = 82 k⍀ 7 1.34 k⍀ = 1.33 k⍀
which is also fine for most low-impedance dynamic microphones. In fact, for a micro-
phone with an internal impedance of 50 ⍀, the signal at the base would be over 98% of that
available. This discussion is important because if the impedance of the microphone is a
great deal more, say, 1 k⍀, the preamplifier would have to be designed differently to
ensure that the input impedance was at least 10 k⍀ or more.

Random-Noise Generator
There is often a need for a random-noise generator to test the response of a speaker, micro-
phone, filter, and, in fact, any system designed to work over a wide range of frequencies.
A random-noise generator is just as its name implies: a generator that generates sig-
nals of random amplitude and frequency. The fact that these signals are usually totally
unintelligible and unpredictable is the reason that they are simply referred to as noise.
Thermal noise is noise generated due to thermal effects resulting from the interaction
between free electrons and the vibrating ions of a material in conduction. The result is an
uneven flow of electrons through the medium, which will result in a varying potential
across the medium. In most cases, these randomly generated signals are in the microvolt
range, but with sufficient amplification they can wreak havoc on a system’s response. This
thermal noise is also called Johnson noise (named after the original researcher in the area)
or white noise (because in optics, white light contains all frequencies). This type of noise
has a fairly flat frequency response such as shown in Fig. 5.134a, that is, a plot of its power
versus frequency from the very low to the very high end is fairly uniform. A second type
of noise is called shot noise, a name derived from the fact that its noise sounds like a
shower of lead shot hitting a solid surface or like heavy rain on a window. Its source is
pockets of carriers passing through a medium at uneven rates. A third is pink, flicker, or
1 , f noise, which is due to the variation in transit times for carriers crossing various junc-
tions of semiconductor devices. It is called 1 > f noise because its magnitude drops off with
increase in frequency. Its effect is usually the most dramatic for frequencies below 1
kHz, as shown in Fig. 5.134b.

en

50 μV

en
20 μV
20 μV White (Johnson) noise
0
Pink or 1 kHz Shot and thermal
0 5 Hz 500 kHz 1/f noise (Johnson) noise

(a) (b)

FIG. 5.134
Typical noise frequency spectra: (a) white or Johnson; (b) pink, thermal, and shot.

The network of Fig. 5.135 is designed to generate both a white noise and a pink noise.
Rather than a separate source for each, first white noise is developed (level across the entire
frequency spectrum), and then a filter is applied to remove the mid- and high-frequency
components, leaving only the low-frequency noise response. The filter is further designed
to modify the flat response of the white noise in the low-frequency region (to create a 1/f
drop-off) by having sections of the filter “drop in” as the frequency increases. The white
noise is created by leaving the collector terminal of transistor Q1 open and reverse-biasing
the base-to-emitter junction. In essence, the transistor is being used as a diode biased in
the Zener avalanche region. Biasing a transistor in this region creates a very unstable situ-
ation that is conducive to the generation of random white noise. The combination of the
avalanche region with its rapidly changing charge levels, sensitivity of the current level to
 15–30 V

R2 5.6 k⍀
R8 5.6 k⍀
C2
White
Noise
R1 1 ␮F C7
Pink
Noise
56 k⍀ 1 ␮F
R5 R6 R7
390 k⍀ 100 k⍀ 18 k⍀
C3 25 ␮F R4 1 M⍀
C1 Q1
25 ␮F C4 C5 C6 820 pF
R3
5 nF 3 nF
Q2
39 k⍀
Q3
Zi

FIG. 5.135
White- and pink-noise generator.

temperature, and quickly changing impedance levels contributes to the level of noise volt-
age and current generated by the transistor. Germanium transistors are often used because
the avalanche region is less defined and less stable than in silicon transistors. In addition,
there are diodes and transistors designed specifically for random-noise generation.
The source of the noise is not some specially designed generator. It is simply due to the
fact that current flow is not an ideal phenomenon but actually varies with time at a level that
generates unwanted variations in the terminal voltage across elements. In fact, that variation
in flow is so broad that it can generate frequencies that extend across a wide spectrum—a
very interesting phenomenon.
The generated noise current of Q1 will then be the base current for Q2, which will be
amplified to generate a white noise of perhaps 100 mV, which for this design would suggest
an input noise voltage of about 170 mV. Capacitor C1 will have a low impedance throughout
the frequency range of interest to provide a “shorting effect” on any spurious signals in the
air from contributing to the signal at the base of Q1. The capacitor C2 is there to isolate the dc
biasing of the white-noise generator from the dc levels of the filter network to follow. The
39 k⍀ and the input impedance of the next stage create the simple voltage-divider network
of Fig. 5.136. If the 39 k⍀ were not present, the parallel combination of R2 and Zi would
load down the first stage and reduce the gain of Q1 considerably. In the gain equation, R2
and Zi would appear in parallel (discussed in Chapter 9).

C3
R3

+ 25 ␮F 39 k⍀ +
Zi(vo(Q2))
vo(Q2) Zi ~
vi(Q3) =
Zi + 39 k⍀

– –

FIG. 5.136
Input circuit for the second stage.

The filter network is actually part of the feedback loop from collector to base appear-
ing in the collector feedback network of Section 5.10. To describe its behavior, let us first
consider the extremes of the frequency spectrum. For very low frequencies all the capaci-
tors can be approximated by an open circuit, and the only resistance from collector to base
is the 1@M⍀ resistor. Using a beta of 100, we find that the gain of the section is about 280
and the input impedance about 1.28 k⍀. At a sufficiently high frequency all the capacitors
347
348 BJT AC ANALYSIS could be replaced by short circuits, and the total resistance combination between collector
and base would be reduced to about 14.5 k⍀, which would result in a very high unloaded
gain of about 731, more than twice that just obtained with RF = 1 M⍀. Because the 1/f
filter is supposed to reduce the gain at high frequencies, it initially appears as though there
is an error in design. However, the input impedance has dropped to about 19.33 ⍀, which
is a 66-fold drop from the level obtained with RF = 1 M⍀. This would have a significant
impact on the input voltage appearing at the second stage when we consider the voltage-
divider action of Fig. 5.136. In fact, when compared to the series 39-k⍀ resistor, the signal
at the second stage can be assumed to be negligible or at a level where even a gain in excess
of 700 cannot raise it to a level of any consequence. In total, therefore, the effect of dou-
bling the gain is totally lost due to the tremendous drop in Zi, and the output at very high
frequencies can be ignored entirely.
For the range of frequencies between the very low and the very high, the three capacitors
of the filter will cause the gain to drop off with increase in frequency. First, capacitor C4
will be dropped in and cause a reduction in gain (around 100 Hz). Then capacitor C5 will be
included and will place the three branches in parallel (around 500 Hz). Finally, capacitor C6
will result in four parallel branches and the minimum feedback resistance (around 6 kHz).
The result is a network with an excellent random-noise signal for the full frequency
spectrum (white) and the low-frequency spectrum (pink).

Sound-Modulated Light Source

The light from the 12-V bulb of Fig. 5.137 will vary at a frequency and an intensity that are
sensitive to the applied signal. The applied signal may be the output of an acoustical ampli-
fier, a musical instrument, or even a microphone. Of particular interest is the fact that the
applied voltage is 12 V ac rather than the typical dc biasing supply. The immediate ques-
tion, in the absence of a dc supply, is how the dc biasing levels for the transistor will be
established. In actuality, the dc level is obtained through the use of diode D1, which recti-
fies the ac signal, and capacitor C2, which acts as a power supply filter to generate a dc
level across the output branch of the transistor. The peak value of a 12-V rms supply is
about 17 V, resulting in a dc level after the capacitive filtering in the neighborhood of 16 V.
If the potentiometer is set so that R1 is about 320 ⍀, the voltage from base to emitter of the
transistor will be about 0.5 V, and the transistor will be in the “off” state. In this state the
collector and emitter currents are essentially 0 mA, and the voltage across resistor R3 is
approximately 0 V. The voltage at the junction of the collector terminal and the diode is
therefore 0 V, resulting in D2 being in the “off” state and 0 V at the gate terminal of the
silicon-controlled rectifier (SCR). The SCR (see Section 17.3) is fundamentally a diode
whose state is controlled by an applied voltage at the gate terminal. The absence of a volt-
age at the gate means that the SCR and bulb are off.

~ 16 V dc
=
12 V ac
D1 60 Hz
R1
10 k⍀ D
R2 Q1
10 ␮F D2 SCR
C1
+ G S
Amplifier R3 1 k⍀ C2 470 ␮F C3 12-V bulb
output

–
ac dc conversion

FIG. 5.137
Sound-modulated light source. SCR, Silicon-controlled rectifier.

If a signal is now applied to the gate terminal, the combination of the established bias-
ing level and the applied signal can establish the required 0.7-V turn-on voltage, and the
transistor will be turned on for periods of time dependent on the applied signal. When the
transistor turns on, it will establish a collector current through resistor R3 that will establish a SUMMARY 349
voltage from collector to ground. If the voltage is more than the required 0.7 V for diode D2,
a voltage will appear at the gate of the SCR that may be sufficient to turn it on and establish
conduction from the drain to the source of the SCR. However, we must now examine one of
the most interesting aspects of this design. Because the applied voltage across the SCR is ac,
which will vary in magnitude with time as shown in Fig. 5.138, the conduction strength of
the SCR will vary with time also. As shown in the figure, if the SCR is turned on when the
sinusoidal voltage is a maximum, the resulting current through the SCR will be a maximum
also, and the bulb will be its brightest. If the SCR should turn on when the sinusoidal voltage
is near its minimum, the bulb may turn on, but the lower current will result in considerably
less illumination. The result is that the lightbulb turns on in sync with when the input signal
is peaking, but the strength of turn-on will be determined by where one is on the applied 12-V
signal. One can imagine the interesting and varied responses of such a system. Each time one
applies the same audio signal, the response will have a different character.

12-V rms ac signal

Maximum voltage
across bulb—brightest
17 V

Bulb will turn

on but with low
light intensity.
0 t

SCR turns on.

FIG. 5.138
Demonstrating the effect of an ac voltage on
the operation of the SCR of Fig. 5.137.

In the above action, the potentiometer was set below the turn-on voltage of the transis-
tor. The potentiometer can also be adjusted so that the transistor is “just on,” resulting in a
low-level base current. The result is a low-level collector current and insufficient voltage
to forward-bias diode D2 and turn on the SCR at the gate. However, when the system is
set up in this manner, the resultant light output will be more sensitive to lower amplitude
components of the applied signal. In the first case, the system acts more like a peak detector,
whereas in the latter case it is sensitive to more components of the signal.
Diode D2 was included to be sure that there is sufficient voltage to turn on both the diode
and the SCR, in other words, to eliminate the possibility of noise or some other low-level
unexpected voltage on the line turning the SCR on. Capacitor C3 can be inserted to slow
down the response by ensuring the voltage charge across the capacitor before the gate will
reach sufficient voltage to turn on the SCR.

5.26 SUMMARY
●
Important Conclusions and Concepts
1. Amplification in the ac domain cannot be obtained without the application of dc
biasing level.
2. For most applications the BJT amplifier can be considered linear, permitting the use
of the superposition theorem to separate the dc and ac analyses and designs.
3. When introducing the ac model for a BJT:
a. All dc sources are set to zero and replaced by a short-circuit connection to
ground.
b. All capacitors are replaced by a short-circuit equivalent.
c. All elements in parallel with an introduced short-circuit equivalent should be
removed from the network.
d. The network should be redrawn as often as possible.
4. The input impedance of an ac network cannot be measured with an ohmmeter.
350 BJT AC ANALYSIS 5. The output impedance of an amplifier is measured with the applied signal set to
zero. It cannot be measured with an ohmmeter.
6. The output impedance for the re model can be included only if obtained from a data
sheet or from a graphical measurement from the characteristic curves.
7. Elements that were isolated by capacitors for the dc analysis will appear in the ac
analysis due to the short-circuit equivalent for the capacitive elements.
8. The amplification factor (beta, b, or hfe) is the least sensitive to changes in collector
current, whereas the output impedance parameter is the most sensitive. The output
impedance is also quite sensitive to changes in VCE, whereas the amplification factor
is the least sensitive. However, the output impedance is the least sensitive to
changes in temperature, whereas the amplification factor is somewhat sensitive.
9. The re model for a BJT in the ac domain is sensitive to the actual dc operating con-
ditions of the network. This parameter is normally not provided on a specification
sheet, although hie of the normally provided hybrid parameters is equal to bre, but
only under specific operating conditions.
10. Most specification sheets for BJTs include a list of hybrid parameters to establish
an ac model for the transistor. One must be aware, however, that they are provided for
a particular set of dc operating conditions.
11. The CE fixed-bias configuration can have a significant voltage gain characteristic,
although its input impedance can be relatively low. The approximate current gain
is given by simply beta, and the output impedance is normally assumed to be RC.
12. The voltage-divider bias configuration has a higher stability than the fixed-bias
configuration, but it has about the same voltage gain, current gain, and output
impedance. Due to the biasing resistors, its input impedance may be lower than that
of the fixed-bias configuration.
13. The CE emitter-bias configuration with an unbypassed emitter resistor has a larger
input resistance than the bypassed configuration, but it will have a much smaller
voltage gain than the bypassed configuration. For the unbypassed or bypassed situa-
tion, the output impedance is normally assumed to be simply RC.
14. The emitter-follower configuration will always have an output voltage slightly less
than the input signal. However, the input impedance can be very large, making it
very useful for situations where a high-input first stage is needed to “pick up” as much
of the applied signal as possible. Its output impedance is extremely low, making it
an excellent signal source for the second stage of a multistage amplifier.
15. The common-base configuration has a very low input impedance, but it can have a
significant voltage gain. The current gain is just less than 1, and the output imped-
ance is simply RC.
16. The collector feedback configuration has an input impedance that is sensitive to
beta and that can be quite low depending on the parameters of the configuration.
However, the voltage gain can be significant and the current gain of some magni-
tude if the parameters are chosen properly. The output impedance is most often
simply the collector resistance RC.
17. The collector dc feedback configuration uses the dc feedback to increase its stabil-
ity and the changing state of a capacitor from dc to ac to establish a higher voltage
gain than obtained with a straight feedback connection. The output impedance is
usually close to RC and the input impedance relatively close to that obtained with the
basic common-emitter configuration.
18. The approximate hybrid equivalent network is very similar in composition to that
used with the re model. In fact, the same methods of analysis can be applied to both
models. For the hybrid model the results will be in terms of the network parameters
and the hybrid parameters, whereas for the re model they will be in terms of the net-
work parameters and b, re, and ro.
19. The hybrid model for common-emitter, common-base, and common-collector con-
figurations is the same. The only difference will be the magnitude of the parameters
of the equivalent network.
20. The total gain of a cascaded system is determined by the product of the gains of each
stage. The gain of each stage, however, must be determined under loaded conditions.
21. Because the total gain is the product of the individual gains of a cascaded system, the
weakest link can have a major effect on the total gain.
Equations SUMMARY 351

26 mV
re =
IE
Hybrid parameters:
hie = bre, hfe = bac, hib = re, hfb = -a ⬵ -1
CE fixed bias:
Zi ⬵ bre, Zo ⬵ RC
RC Zi
Av = - , Ai = -Av ⬵ b
re RC
Voltage-divider bias:
Zi = R1 7 R2 7 bre, Zo ⬵ RC
RC Zi
Av = - , Ai = -Av ⬵ b
re RC
CE emitter-bias:
Zi ⬵ RB 7 bRE, Zo ⬵ RC
RC bRB
Av ⬵ - , Ai ⬵
RE RB + bRE
Emitter-follower:
Zi ⬵ RB 7 bRE, Zo ⬵ r e
Zi
Av ⬵ 1, Ai = -Av
RE
Common-base:
Zi ⬵ RE 储 re, Zo ⬵ RC
RC
Av ⬵ , Ai ⬵ -1
re
Collector feedback:
re
Zi ⬵ , Zo ⬵ RC 7 RF
1 RC
+
b RF
RC RF
Av = - , Ai ⬵
re RC
Collector dc feedback:
Zi ⬵ RF1 7 bre, Zo ⬵ RC 7 RF2
RF2 7 RC Zi
Av = - , Ai = -Av
re RC
Effect of load impedance:
Vo RL Io Zi
AvL = = A , AiL = = -AvL
Vi RL + Ro vNL Ii RL
Effect of source impedance:
RiVs Vo Ri
Vi = , Avs = = A
Ri + Rs Vs Ri + Rs vNL
Vs
Is =
Rs + Ri
Combined effect of load and source impedance:

AvL =
Vo
=
RL
AvNL, Avs =
Vo
=
Ri
# RL AvNL
Vi RL + Ro Vs Ri + Rs RL + Ro
Io Ri Io Rs + Ri
AiL = = -AvL , Ais = = -Avs
Ii RL Is RL
352 BJT AC ANALYSIS Cascode connection:
Av = Av1Av2
Darlington connection (with RE):
bD = b1b2,
b1b2RB
Zi = RB 7 (b1b2RE), Ai =
(RB + b1b2RE)
re1 Vo
Zo = + re2 Av = ⬇ 1
b2 Vi
Darlington connection (without RE):
b1b2(R1 7 R2)
Zi = R1 储 R2 储 b1(re1 + b1b2re2) Ai =
R1 7 R2 + Zi⬘
where Zi⬘ = b1(re1 + b2re2)
Vo b1b2RC
Zo ⬵ RC 7 ro2 Av = =
Vi Zi⬘
Feedback pair:
-b1b2RB
Zi = RB 7 b1b2RC Ai =
RB + b1b2RC
re1
Zo ⬇ Av ⬵ 1
b2

5.27 COMPUTER ANALYSIS

●
PSpice Windows
BJT Voltage-Divider Configuration The last few chapters have been limited to the dc anal-
ysis of electronic networks using PSpice and Multisim. This section will consider the applica-
tion of an ac source to a BJT network and describe how the results are obtained and interpreted.
Most of the construction of the network of Fig. 5.139 can be accomplished using the
procedures introduced in earlier chapters. The ac source can be found in the SOURCE
library as VSIN. You can scroll down the list of options or simply type in VSIN at the head
of the listing. Once this is selected and placed, a number of labels will appear that define

FIG. 5.139
Using PSpice Windows to analyze the network of Fig. 5.28
(Example 5.2).
the parameters of the source. Double-clicking the source symbol or using the sequence COMPUTER ANALYSIS 353
Edit-Properties will result in the Property Editor dialog box, which lists all the param-
eters appearing on the screen and more. By scrolling all the way to the left, you will find a
listing for AC. Select the blank rectangle under the heading and enter the 1 mV value. Be
aware that the entries can use prefixes such as m (milli) and k (kilo). Moving to the right,
the heading FREQ will appear, in which you can enter 10 kHz. Moving again to PHASE,
you will find the default value is 0, so it can be left alone. It represents the initial phase angle
for the sinusoidal signal. Next you will find VAMPL, which is set at 1 mV, also followed
by VOFF at 0 V. Now that each of the properties has been set, we have to decide what to
display on the screen to define the source. In Fig. 5.139 the only labels are Vs and 1 mV,
so a number of items have to be deleted and the name of the source has to be modified. For
each quantity simply return to the heading and select it for modification. If you choose AC,
select Display to obtain the Display Properties dialog box. Select Value Only because we
prefer not to have the label AC appear. Leave all the other choices blank. An OK, and you
can move to the other parameters within the Property Editor dialog box. We do not want
the FREQ, PHASE, VAMPL and VOFF labels to appear with their values, so in each case
select Do Not Display. To change V1 to Vs, simply go to the Part Reference, and after
selecting it, type in Vs. Then go to Display and select Value Only. Finally, to apply all the
changes, select Apply and exit the dialog box; the source will appear as shown in Fig. 5.139.
The ac response for the voltage at a point in the network is obtained using the VPRINT1
option found in the SPECIAL library. If the library does not appear, simply select Add
Library followed by special.olb. When VPRINT1 is chosen, it will appear on the screen
as a printer with three labels: AC, MAG, and PHASE. Each has to be set to an OK status
to reflect the fact that you desire this type of information about the voltage level. This is
accomplished by simply clicking on the printer symbol to obtain the dialog box and setting
each to OK. For each entry select Display and choose Name and Label. Finally, select
Apply and exit the dialog box. The result appears in Fig. 5.139.
The transistor Q2N2222 can be found under the EVAL library by typing it under the
Part heading or simply scrolling through the possibilities. The levels of Is and b can be
set by first selecting the Q2N2222 transistor to make it red and then applying the sequence
Edit-PSpice Model to obtain the PSpice Model Editor Lite dialog box and changing Is to
2E-15A and Bf to 90. The level of Is is the result of numerous runs of the network to find
the value that would result in VBE being closest to 0.7 V.
Now that all the components of the network have been set, it is time to ask the computer
to analyze the network and provide some results. If improper entries were made, the com-
puter will quickly respond with an error listing. First select the New Simulation Profile
key to obtain the New Simulation dialog box. Then, after entering Name as OrCAD 5-1,
select Create and the Simulation Settings dialog box will appear. Under Analysis type,
select AC Sweep/Noise and then under AC Sweep Type choose Linear. The Start Fre-
quency is 10 kHz, the End Frequency is 10 kHz, and the Total Points is 1. An OK, and
the simulation can be initiated by selecting the Run PSpice key (white arrow). A schematic
will result with a graph that extends from 5 kHz to 15 kHz with no vertical scale. Through
the sequence View-Output File the listing of Fig. 5.140 can be obtained. It starts with a list
of all the elements of the network and their settings followed by all the parameters of the
transistor. In particular, note the level of IS and BF. Next the dc levels are provided under
the SMALL SIGNAL BIAS SOLUTION, which match those appearing on the schematic
of Fig. 5.139. The dc levels appear on Fig. 5.139 due to the selection of the V option. Also
note that VBE = 2.624 V - 1.924 V = 0.7 V, as stated above, due to the choice of Is.
The next listing, OPERATING POINT INFORMATION, reveals that even though
beta of the BJT MODEL PARAMETERS listing was set at 90, the operating conditions
of the network resulted in a dc beta of 48.3 and an ac beta of 55. Fortunately, however, the
voltage-divider configuration is less sensitive to changes in beta in the dc mode, and the
dc results are excellent. However, the drop in ac beta had an effect on the resulting level
of Vo: 296.1 mV versus the handwritten solution (with ro = 50 k⍀) of 324.3 mV—a 9%
difference. The results are certainly close, but probably not as close as one would like. A
closer result (within 7%) could be obtained by setting all the parameters of the device except
Is and beta to zero. However, for the moment, the impact of the remaining parameters has
been demonstrated, and the results will be accepted as sufficiently close to the handwritten
levels. Later in this chapter, an ac model for the transistor will be introduced with results
354 BJT AC ANALYSIS **** CIRCUIT DESCRIPTION

******************************************************************************************************

*Analysis directives:
.AC LIN 1 10kHz 10kHz
.OP
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
* source ORCAD 5-1
Q_Q1 N00286 N00282 N00319 Q2N2222
R_R1 N00282 N00254 56k TC=0,0
R_R2 0 N00282 8.2k TC=0,0
R_R3 N00286 N00254 6.8k TC=0,0
R_R4 0 N00319 1.5k TC=0,0
V_VCC N00254 0 22Vdc
C_C1 0 N00319 20uF TC=0,0
V_Vs N00342 0 AC 1mV
+SIN 0V 1mV 10kHz 0 0 0
. PRINT AC
+ VM ([N00286])
+ VP ([N00286])
C_C2 N00342 N00282 10uF TC=0,0
.END

**** BJT MODEL PARAMETERS

******************************************************************************************************

Q2N2222
NPN
LEVEL 1
IS 2.000000E-15
BF 90
NF 1
VAF 74.03
IKF .2847
ISE 14.340000E-15
NE 1.307
BR 6.092
NR 1
ISS 0
RB 10
RE 0
RC 1
CJE 22.010000E-12
VJE .75
MJE .377
CJC 7.306000E-12
VJC .75
MJC .3416

XCJC 1
CJS 0
VJS .75
TF 411.100000E-12
XTF 3
VTF 1.7
ITF .6
TR 46.910000E-09
XTB 1.5
KF 0
AF 1
CN 2.42
D .87

**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C

******************************************************************************************************

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

(N00254) 22.0000 (N00282) 2.6239 (N00286) 13.4530 (N00319) 1.9244
(N00342) 0.0000

VOLTAGE SOURCE CURRENTS

NAME CURRENT
V_VCC -1.603E-03
V_Vs 0.000E+00

TOTAL POWER DISSIPATION 3.53E-02 WATTS

**** OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C

******************************************************************************************************

**** BIPOLAR JUNCTION TRANSISTORS

NAME Q_Q1
MODEL Q2N2222
IB 2.60E-05
IC 1.26E-03
VBE 6.99E-01
VBC -1.08E+01
VCE 1.15E+01
BETADC 4.83E+01
GM 4.84E-02
RPI 1.14E+03
RX 1.00E+01
RO 6.75E+04
CBE 5.78E-11
CBC 2.87E-12
CJS 0.00E+00
BETAAC 5.50E+01
CBX/CBX2 0.00E+00
FT/FT2 1.27E+08

**** AC ANALYSIS TEMPERATURE = 27.000 DEG C

******************************************************************************************************

FREQ VM(N00286) VP(N00286)

1.000E+04 2.961E-01 -1.780E+02

FIG. 5.140
Output file for the network of Fig. 5.139.

that will be an exact match with the handwritten solution. The phase angle is ⫺178° versus
the ideal of ⫺180°, a very close match.
A plot of the voltage at the collector of the transistor can be obtained by setting up a new
simulation process to calculate the value of the desired voltage at a number of data points.
The more points, the more accurate is the plot. The process is initiated by returning to the
Simulation Settings dialog box and under Analysis type selecting Time Domain(Transient). COMPUTER ANALYSIS 355
Time domain is chosen because the horizontal axis will be a time axis, requiring that the
collector voltage be determined at a specified time interval to permit the plot. Because the
period of the waveform is 1>10 kHz = 0.1 ms = 100 ms, and it would be convenient to
display five cycles of the waveform, the Run to time(TSTOP) is set at 500 ms. The Start
saving data after point is left at 0 s and under Transient option, the Maximum step
size is set at 1 ms to ensure 100 data points for each cycle of the waveform. An OK, and a
SCHEMATIC window will appear with a horizontal axis broken down in units of time
but with no vertical axis defined. The desired waveform can then be added by first select-
ing Trace followed by Add Trace to obtain the Add Trace dialog box. In the provided
listing V(Q1:c) is selected as the voltage at the collector of the transistor. The instant it is
selected it will appear as the Trace Expression at the bottom of the dialog box. Referring to
Fig. 5.139, we find that because the capacitor CE will essentially be in the short-circuit state
at 10 kHz, the voltage from collector to ground is the same as that across the output terminals
of the transistor. An OK, and the simulation can be initiated by selecting the Run PSpice key.
The result will be the waveform of Fig. 5.141 having an average value of about 13.45 V,
which corresponds exactly with the bias level of the collector voltage in Fig. 5.139.
The range of the vertical axis was chosen automatically by the computer. Five full
cycles of the output voltage are displayed with 100 data points for each cycle. The data
points appear in Fig. 5.139 because the sequence Tools-Options-Mark Data Points
was applied. The data points appear as small dark circles on the plot curve. Using the
scale of the graph, we see that the peak-to-peak value of the curve is approximately
13.76 V - 13.16 V = 0.6 V = 600 mV, resulting in a peak value of 300 mV. Because a
1-mV signal was applied, the gain is 300, or very close to the calculator solution of 296.1.

FIG. 5.141
Voltage vC for the network Fig. 5.139.

If a comparison is to be made between the input and output voltages on the same screen,
the Add Y-Axis option under Plot can be used. After you select it, choose the Add Trace
icon and select V(Vs:+) from the provided list. The result is that both waveforms will ap-
pear on the same screen as shown in Fig. 5.142, each with its own vertical scale.
If two separate graphs are preferred, we can start by selecting Plot followed by Add Plot
to Window after the graph of Fig. 5.141 is in place. The result will be a second set of axes
waiting for a decision about which curve to plot. Using Trace-Add Trace-V(Vs:+) will
result in the graphs of Fig. 5.143. The SEL g (from SELECT) appearing next to one of
the plots defines the “active” plot.
356 BJT AC ANALYSIS

Vs
VC

VC (dc) ⫽ 13.43 V
Vs ⫽ 0 V

FIG. 5.142
The voltages vC and vs for the network of Fig. 5.139.

Vs

VC

FIG. 5.143
Two separate plots of vC and vs in Fig. 5.139.

The last operation to be introduced in this coverage of graph displays is the use of
the cursor option. The result of the sequence Trace-Cursor-Display is a line at the dc
level of the graph of Fig. 5.144 intersecting with a vertical line. The level and time both
appear in the small dialog box in the bottom right corner of the screen. The first number
for Cursor 1 is the time intersection and the second is the voltage level at that instant. A
left-click of the mouse will provide control of the intersecting vertical and horizontal lines
at this level. Clicking on the vertical line and holding down on the clicker will allow you to
move the intersection horizontally along the curve, simultaneously displaying the time and
voltage level in the data box at the bottom right of the screen. If it is moved to the first peak COMPUTER ANALYSIS 357
of the waveform, the time appears as 75.194 ms with a voltage level of 13.753 V, as shown
in Fig. 5.144. On right-clicking of the mouse, a second intersection, defined by Cursor 2,
will appear, which can be moved in the same way with its time and voltage appearing in the
same dialog box. Note that if Cursor 2 is placed close to the negative peak, the difference
in time is 49.61 ms (as displayed in the same box), which is very close to one-half the period
of the waveform. The difference in magnitude is 591 mV, which is very close to the 600 mV
obtained earlier.

Cursor 1

Cursor 2

FIG. 5.144
Demonstrating the use of cursors to read specific points on a plot.

Voltage-Divider Configuration—Controlled Source Substitution The results obtained

for any analysis using the transistors provided in the PSpice listing will always be some-
what different from those obtained with an equivalent model that only includes the effect
of beta and re. This was clearly demonstrated for the network of Fig. 5.139. If a solution is
desired that is limited to the approximate model used in the hand calculations, then the
transistor must be represented by a model such as appearing in Fig. 5.145.

B C B C B GAIN = β C
F1
Ib βre βre

βre βIb Ib βIb Ib βIb

E E E

FIG. 5.145
Using a controlled source to represent the transistor of Fig. 5.139.
358 BJT AC ANALYSIS For Example 5.2, b is 90, with bre = 1.66 k. The current-controlled current source
(CCCS) is found in the ANALOG library as part F. After selection, an OK, and the graphi-
cal symbol for the CCCS will appear on the screen as shown in Fig. 5.146. Because it does
not appear within the basic structure of the CCCS, it must be added in series with the
controlling current that appears as an arrow in the symbol. Note the added 1.66-k resis-
tor, labeled beta-re in Fig. 5.146. Double-clicking on the CCCS symbol will result in the
Property Editor dialog box, in which the GAIN can be set to 90. It is the only change to
be made in the listing. Then select Display followed by Name and Value and exit (x) the
dialog box. The result is the GAIN ⴝ 90 label appearing in Fig. 5.146.

FIG. 5.146
Substituting the controlled source of Fig. 5.145 for the transistor
of Fig. 5.139.

A simulation and the dc levels of Fig. 5.146 will appear. The dc levels do not match
the earlier results because the network is a mix of dc and ac parameters. The equivalent
model substituted in Fig. 5.146 is a representation of the transistor under ac conditions,
not dc biasing conditions. When the software package analyzes the network from an ac
viewpoint it will work with an ac equivalent of Fig. 5.146, which will not include the dc
parameters. The Output File will reveal that the output collector voltage is 368.3 mV, or
a gain of 368.3, essentially an exact match with the handwritten solution of 368.76. The
effects of ro could be included by simply placing a resistor in parallel with the controlled
source.

Darlington Configuration Although PSpice does have two Darlington pairs in the
library, individual transistors are employed in Fig. 5.147 to test the solution to Exam-
ple 5.17. The details of setting up the network have been covered in the preceding sec-
tions and chapters. For each transistor Is is set to 100E-18 and b to 89.4. The applied
frequency is 10 kHz. A simulation of the network results in the dc levels appearing in
Fig. 5.147a and the Output File in Fig. 5.147b. In particular, note that the voltage drop
between base and emitter for both transistors is 10.52 V - 9.148 V = 1.37 V com-
pared to the 1.6 V assumed in the example. Recall that the drop across Darlington pairs
is typically about 1.6 V and not simply twice that of a single transistor, or
2(0.7 V) = 1.4 V. The output voltage of 99.36 mV is very close to the 99.80 mV
obtained in Section 5.17.
 **** BJT MODEL PARAMETERS

***************************************************************************************************************

Q2N3904
NPN
LEVEL 1
IS 100.000000E-18
BF 89.4
NF 1
BR 1
NR 1
CN 2.42
D .87

**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C

***************************************************************************************************************

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

N00218) 0.0000 (N00225) 18.0000 (N00243) 8.9155 (N00250) 9.6513
(N00291) 0.0000 (N02131) 8.0632

**** AC ANALYSIS TEMPERATURE = 27.000 DEG C

***************************************************************************************************************

FREQ VM(N00291)

1.000E+04 9.936E-02

(a) (b)

FIG. 5.147
(a) Design Center schematic of Darlington network; (b) output listing for circuit of part (a) (edited).

Multisim
Collector Feedback Configuration Because the collector feedback configuration gen-
erated the most complex equations for the various parameters of a BJT network, it seems
appropriate that Multisim be used to verify the conclusions of Example 5.9. The net-
work appears as shown in Fig. 5.148 using the “virtual” transistor from the Transistor
family toolbar. Recall from the previous chapter that transistors are obtained by first
selecting the Transistor keypad appearing as the fourth option over on the component

FIG. 5.148
Network of Example 5.9 redrawn using Multisim.
359
360 BJT AC ANALYSIS toolbar. Once chosen, the Select a Component dialog box will appear; under the Fam-
ily heading, select TRANSISTORS_VIRTUAL followed by BJT_NPN_VIRTUAL.
Following an OK the symbols and labels will appear as shown in Fig. 5.148. We
must now check that the beta value is 200 to match the example under investigation.
This can be accomplished using one of two paths. In Chapter 4 we used the EDIT-
PROPERTIES sequence, but here we will simply double-click on the symbol to obtain
the TRANSISTORS_VIRTUAL dialog box. Under Value, select Edit Model to obtain
the Edit Model dialog box (the dialog box has a different appearance from that obtained
with the other route and requires a different sequence to change its parameters). The
value of BF appears as 100, which must be changed to 200. First select the BF line to
make it blue all the way across. Then place the cursor directly over the 100 value and
select it to isolate it as the quantity to be changed. After deleting the 100, type in the
desired 200 value. Then click the BF line directly under the Name heading and the
entire line will be blue again, but now with the 200 value. Then choose Change Part
Model at the bottom left of the dialog box and the TRANSISTORS-VIRTUAL dialog
box will appear again. Select OK and b  200 will be set for the virtual transistor. Note
the asterisk next to the BJT label to indicate the parameters of the device have been
changed from the default values. The label Bf ⴝ 100 was set using Place-Text as
described in the previous chapter.
This will be the first opportunity to set up an ac source. First, it is important to real-
ize that there are two types of ac sources available, one whose value is in rms units, the
other with its peak value displayed. The option under Power Sources uses rms values,
whereas the ac source under Signal Sources uses peak values. Because meters display
rms values, the Power Sources option will be used here. Once Source is selected, the
Select a Component dialog box will appear. Under the Family listing select POWER_
SOURCES and then select AC_POWER under the Component listing. An OK, and
the source will appear on the screen with four pieces of information. The label V1 can
be deleted by first double-clicking on the source symbol to obtain the AC_POWER
dialog box. Select Display and disengage Use Schematic Global Settings. To remove
the label V1, disengage the Show RefDes option. An OK, and the V1 will disappear
from the screen. Next the value has to be set at 1 mV, a process initiated by selecting
Value in the AC_POWER dialog box and then changing the Voltage (RMS) to 1 mV.
The units of mV can be set using the scroll keys to the right of the magnitude of the
source. After you change the Voltage to 1 mV, an OK will place this new value on the
screen. The frequency of 1000 Hz can be set in the same way. The 0-degree phase shift
happens to be the default value.
The label Bf ⴝ 200 is set in the same way as described in Chapter 4. The two multi-
meters are obtained using the first option at the top of the right vertical toolbar. The meter
faces appearing in Fig. 5.148 were obtained by simply double-clicking on the multimeter
symbols on the schematic. Both were set to read voltages, the magnitudes of which will be
in rms units.
After simulation the results of Fig. 5.148 appear. Note that the meter XMM1 is not read-
ing the 1 mV expected. This is due to the small drop in voltage across the input capacitor
at 1 kHz. Certainly, however, it is very close to 1 mV. The output of 245.166 mV quickly
reveals that the gain of the transistor configuration is about 245.2, which is a very close
match with the 240 obtained in Example 5.9.

Darlington Configuration Applying Multisim to the network of Fig. 5.147 with a pack-
aged Darlington amplifier results in the printout of Fig. 5.149. For each transistor the
parameters were changed to Is ⴝ 100E-18 A and Bf ⴝ 89.4 using the technique described
earlier. For practice purposes the ac signal source was employed rather than the power
source. The peak value of the applied signal is set at 100 mV, but note that the multimeter
reads the effective or rms value of 99.991 mV. The indicators reveal that the base voltage
of Q1 is 7.736 V, and the emitter voltage of Q2 is 6.193 V. The rms value of the output
voltage is 99.163 mV, resulting in a gain of 0.99 as expected for the emitter follower con-
figuration. The collector current is 16 mA with a base current of 1.952 mA, resulting in a
bD of about 8200.
 PROBLEMS 361

FIG. 5.149
Network of Example 5.9 redrawn using Multisim.

PROBLEMS
●
*Note: Asterisks indicate more difficult problems.
5.2 Amplification in the AC Domain
1. a. What is the expected amplification of a BJT transistor amplifier if the dc supply is set to
zero volts?
b. What will happen to the output ac signal if the dc level is insufficient? Sketch the effect on
the waveform.
c. What is the conversion efficiency of an amplifier in which the effective value of the current
through a 2.2-k load is 5 mA and the drain on the 18-V dc supply is 3.8 mA?
2. Can you think of an analogy that would explain the importance of the dc level on the resulting
ac gain?
3. If a transistor amplifier has more than one dc source, can the superposition theorem be applied
to obtain the response of each dc source and algebraically add the results?

5.3 BJT Transistor Modeling

4. What is the reactance of a 10@mF capacitor at a frequency of 1 kHz? For networks in which the
resistor levels are typically in the kilohm range, is it a good assumption to use the short-circuit
equivalence for the conditions just described? How about at 100 kHz?
5. Given the common-base configuration of Fig. 5.150, sketch the ac equivalent using the nota-
tion for the transistor model appearing in Fig. 5.7.

FIG. 5.150
Problem 5.
5.4 The re Transistor Model
6. a. Given an Early voltage of VA  100 V, determine ro if VCEQ = 8 V and ICQ = 4 mA.
b. Using the results of part (a), find the change in IC for a change in VCE of 6 V at the same
Q-point as part (a).
362 BJT AC ANALYSIS 7. For the common-base configuration of Fig. 5.18, an ac signal of 10 mV is applied, resulting in
an ac emitter current of 0.5 mA. If a  0.980, determine:
a. Zi.
b. Vo if RL = 1.2 k.
c. Av = Vo>Vi.
d. Zo with ro   .
e. Ai = Io >Ii.
f. Ib.
8. Using the model of Fig. 5.16, determine the following for a common-emitter amplifier if
b  80, IE(dc) = 2 mA, and ro = 40 k.
a. Zi.
b. Ib.
c. Ai = Io >Ii = IL >Ib if RL = 1.2 k.
d. Av if RL = 1.2 k.
9. The input impedance to a common-emitter transistor amplifier is 1.2 k with b  140,
ro = 50 k, and RL = 2.7 k. Determine:
a. re.
b. Ib if Vi = 30 mV.
c. Ic.
d. Ai = Io>Ii = IL >Ib.
e. Av = Vo>Vi.
10. For the common-base configuration of Fig. 5.18, the dc emitter current is 3.2 mA and a is 0.99.
Determine the following if the applied voltage is 48 mV and the load is 2.2 k.
a. re.
b. Zi.
c. Ic.
d. Vo.
e. Av.
f. Ib.

5.5 Common-Emitter Fixed-Bias Configuration

11. For the network of Fig. 5.151:
a. Determine Zi and Zo.
b. Find Av.
c. Repeat parts (a) and (b) with ro = 20 k.
12. For the network of Fig. 5.152, determine VCC for a voltage gain of Av = - 160.

12 V

VCC

4.7 kΩ
2.2 kΩ
220 kΩ Io 1 MΩ
Vo
Vo

β = 90
Vi Zo Vi ro = ∞ Ω
Ii β = 60
ro = 40 kΩ
Zi

FIG. 5.151 FIG. 5.152

Problem 11. Problem 12.

*13. For the network of Fig. 5.153:

a. Calculate IB, IC, and re.
b. Determine Zi and Zo.
c. Calculate Av.
d. Determine the effect of ro = 30 k on Av.
14. For the network of Fig. 5.153, what value of RC will cut the voltage gain to half the value
obtained in problem 13?
 12 V PROBLEMS 363

5.6 kΩ
Io
Vo

Vi Zo
Ii β = 100
390 kΩ gos = 25 μS

Zi
8V

FIG. 5.153
Problem 13.
5.6 Voltage-Divider Bias
15. For the network of Fig. 5.154:
a. Determine re.
b. Calculate Zi and Zo.
c. Find Av.
d. Repeat parts (b) and (c) with ro = 25 k.
VCC = 16 V

3.9 kΩ
39 kΩ Io
Vo
1 μF 1 μF
Zo
Vi
β = 100
Ii ro = 50 kΩ

4.7 kΩ
Zi
1.2 kΩ 10 μF

FIG. 5.154
Problem 15.
16. Determine VCC for the network of Fig. 5.155 if Av = - 160 and ro = 100 k.
17. For the network of Fig. 5.156:
a. Determine re.
b. Calculate VB and VC.
VCC = 20 V
c. Determine Zi and Av = Vo>Vi.
VCC

3.3 kΩ 4.7 kΩ
82 kΩ 220 kΩ
VC
Vo Vo
CC CC
VB
Vi β = 100 Vi β = 180
CC gos = 20 μS CC gos = 30 μS

Zi
5.6 kΩ 56 kΩ
1 kΩ CE 2.2 kΩ CE

FIG. 5.155 FIG. 5.156

Problem 16. Problem 17.
364 BJT AC ANALYSIS 18. For the network of Fig. 5.157:
a. Determine re.
b. Find the dc voltages VB, VCB, and VCE.
c. Determine Zi and Zo.
d. Calculate Av  Vo>Vi.

Vo Zo
β = 70
ro = 60 k⍀
24 V

3.3 k⍀ 2.2 k⍀

12 V
Vi
27 k⍀

68 k⍀ Zi

FIG. 5.157
Problem 18.

5.7 CE Emitter–Bias Configuration

19. For the network of Fig. 5.158:
a. Determine re.
b. Find Zi and Zo.
c. Calculate Av.
d. Repeat parts (b) and (c) with ro = 20 k.
20. Repeat Problem 19 with RE bypassed. Compare results.
21. For the network of Fig. 5.159, determine RE and RB if Av = - 10 and re = 3.8 . Assume that
Zb = bRE.

20 V

20 V

2.2 kΩ 8.2 kΩ
Io
390 kΩ RB
Vo Vo

β = 140 β = 120
Vi Vi
ro = 100 kΩ gos = 10 μS
Ii

1.2 kΩ Zo RE
Zi

FIG. 5.158 FIG. 5.159

Problems 19 and 20. Problem 21.

*22. For the network of Fig. 5.160:

a. Determine re.
b. Find Zi and Av.
23. For the network of Fig. 5.161:
a. Determine re.
b. Calculate VB, VCE, and VCB.
c. Determine Zi and Zo.
d. Calculate Av  Vo>Vi.
e. Determine Ai  Io>Ii.
 22 V PROBLEMS 365

5.6 kΩ
330 kΩ Io
16 V
Vo
Ii CC
Io
Vi β = 80
CC ro = 40 kΩ 430 k⍀
4.7 k⍀

Zi Vo
1.2 kΩ
Vi β = 200
gos = 20 μS

120 k⍀
0.47 kΩ CE 1.2 k⍀

FIG. 5.160 FIG. 5.161

Problem 22. Problem 23.

5.8 Emitter-Follower Configuration 16 V

24. For the network of Fig. 5.162:

a. Determine re and bre.
b. Find Zi and Zo.
c. Calculate Av. 270 kΩ

Vi β = 110
ro = 50 kΩ
Ii
Vo
Io
Zi
2.7 kΩ
Zo

FIG. 5.162
Problem 24.
*25. For the network of Fig. 5.163:
a. Determine Zi and Zo.
b. Find Av.
c. Calculate Vo if Vi = 1 mV.
*26. For the network of Fig. 5.164:
a. Calculate IB and IC. VCC = 20 V
b. Determine re.
c. Determine Zi and Zo.
d. Find Av.
12 V
56 kΩ
Ii
β = 120
Vi β = 200
ro = 40 kΩ Vi
gos = 20 μS
Ii
Vo Vo
390 kΩ Io Io
Zi 8.2 kΩ
5.6 kΩ 2 kΩ
Zo

−8 V

FIG. 5.163 FIG. 5.164

Problem 25. Problem 26.
366 BJT AC ANALYSIS 5.9 Common-Base Configuration
27. For the common-base configuration of Fig. 5.165:
a. Determine re.
b. Find Zi and Zo.
c. Calculate Av.
*28. For the network of Fig. 5.166, determine Av.

8V

3.6 kΩ
Io
Vo
+6 V −10 V

β = 75
gos = 5 μS
6.8 kΩ 4.7 kΩ
Ii Io
Vi
Vi Vo
Ii
3.9 kΩ
Zi α = 0.998 Zo
gos = 10 μS
−5 V

FIG. 5.165 FIG. 5.166

Problem 27. Problem 28.

5.10 Collector Feedback Configuration

29. For the collector feedback configuration of Fig. 5.167:
a. Determine re.
b. Find Zi and Zo.
c. Calculate Av.
*30. Given re = 10 , b  200, Av = - 160, and Ai = 19 for the network of Fig. 5.168, deter-
mine RC, RF, and VCC.
*31. For the network of Fig. 5.49:
a. Derive the approximate equation for Av.
b. Derive the approximate equations for Zi and Zo.
c. Given RC = 2.2 k, RF = 120 k, RE = 1.2 k, b  90, and VCC = 10 V, calculate
the magnitudes of Av, Zi, and Zo using the equations of parts (a) and (b).

12 V VCC
Io

3.9 kΩ RC
220 kΩ RF
Vo Vo

Zo re = 10 Ω
Vi Vi
β = 200
β = 120
Ii ro = 80 kΩ
ro = 40 kΩ

Zi

FIG. 5.167 FIG. 5.168

Problem 29. Problem 30.

5.11 Collector DC Feedback Configuration

32. For the network of Fig. 5.169:
a. Determine Zi and Zo.
b. Find Av.
 9V PROBLEMS 367
Io

1.8 kΩ
39 kΩ 22 kΩ
Vo
1 μF
10 μ F
Zo
Ii
β = 80
Vi
gos = 22 μS
1 μF

Zi

FIG. 5.169
Problems 32 and 33.

33. Repeat problem 32 with the addition of an emitter resistor RE  0.68 k.

5.12–5.15 Effect of RL and Rs and Two-Port Systems Approach

*34. For the fixed-bias configuration of Fig. 5.170:
a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in place.
c. Calculate the gain AvL = Vo>Vi.
d. Determine the current gain AiL = Io>Ii.

18 V

3.3 kΩ
680 kΩ
1.8 μF Io
Vo
1.8 μF
Vi β = 100
Ii RL 4.7 kΩ
Zo

Zi

FIG. 5.170
Problems 34 and 35.

35. a. Determine the voltage gain AvL for the network of Fig. 5.170 for RL = 4.7 k, 2.2 k, and
0.5 k. What is the effect of decreasing levels of RL on the voltage gain?
b. How will Zi, Zo, and AvNL change with decreasing values of RL?
*36. For the network of Fig. 5.171:
a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in place.
c. Determine Av = Vo>Vi.
d. Determine Avs = Vo>Vs.
e. Change Rs to 1 k and determine Av. How does Av change with the level of Rs?
f. Change Rs to 1 k and determine Avs. How does Avs change with the level of Rs?
g. Change Rs to 1 k and determine AvNL, Zi, and Zo. How do they change with the change in Rs?
h. For the original network of Fig. 5.171 calculate Ai  Io>Ii.
368 BJT AC ANALYSIS 12 V

Io

3 kΩ
1 MΩ
1 μF
Vo
Ii Rs 1 μF
Vi
β = 180
+ 0.6 kΩ
Zo
Vs Zi
–

FIG. 5.171
Problem 36.

*37. For the network of Fig. 5.172:

a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in
place.
c. Determine AvL and Avs.
d. Calculate AiL.
e. Change RL to 5.6 k and calculate Avs. What is the effect of increasing levels of RL on the
gain?
f. Change Rs to 0.5 k (with RL at 2.7 k) and comment on the effect of reducing Rs on
Av s .
g. Change RL to 5.6 k and Rs to 0.5 k and determine the new levels of Zi and Zo. How are
the impedance parameters affected by changing levels of RL and Rs?

24 V

4.3 kΩ
560 kΩ
10 μ F Io
Vo
Ii Rs 10 μF
Vi
β = 80
+ 1 kΩ
RL 2.7 kΩ
Vs Zo
Zi
–

FIG. 5.172
Problem 37.

38. For the voltage-divider configuration of Fig. 5.173:

a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in
place.
c. Calculate the gain AvL.
d. Determine the current gain AiL.
e. Determine AvL, AiL, and Zo using the re model and compare solutions.
39. a. Determine the voltage gain AvL for the network of Fig. 5.173 with RL = 4.7 k, 2.2 k,
and 0.5 k. What is the effect of decreasing levels of RL on the voltage gain?
b. How will Zi, Zo, and AvNL change with decreasing levels of RL?
 PROBLEMS 369

FIG. 5.173
Problems 38 and 39.

40. For the emitter-stabilized network of Fig. 5.174:

a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.63 with the values determined in part (a).
c. Determine AvL and Avs.
d. Change Rs to 1 k. What is the effect on AvNL, Zi, and Zo?
e. Change Rs to 1 k and determine AvL and Avs. What is the effect of increasing levels of Rs
on AvL and Avs?
f. Determine Ai  Io>Ii.

Io

Ii

FIG. 5.174
Problem 40.

*41. For the network of Fig. 5.175:

a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.63 with the values determined in part (a).
c. Determine AvL and Avs.
d. Change Rs to 1 k and determine AvL and Avs. What is the effect of increasing levels of Rs
on the voltage gains?
e. Change Rs to 1 k and determine AvNL, Zi, and Zo. What is the effect of increasing levels of
Rs on the parameters?
f. Change RL to 5.6 k and determine AvL and Avs. What is the effect of increasing levels of
RL on the voltage gains? Maintain Rs at its original level of 0.6 k.
Io
g. Determine Ai = with RL = 2.7 k and Rs = 0.6 k.
Ii
370 BJT AC ANALYSIS

Ii
Io

FIG. 5.175
Problem 41.

*42. For the common-base network of Fig. 5.176:

a. Determine Zi, Zo, and AvNL.
b. Sketch the two-port model of Fig. 5.63 with the parameters of part (a) in place.
c. Determine AvL and Avs.
d. Determine AvL and Avs using the re model and compare with the results of part (c).
e. Change Rs to 0.5 k and RL to 2.2 k and calculate AvL and Avs. What is the effect of
changing levels of Rs and RL on the voltage gains?
f. Determine Zo if Rs changed to 0.5 k with all other parameters as appearing in Fig. 5.176.
How is Zo affected by changing levels of Rs?
g. Determine Zi if RL is reduced to 2.2 k. What is the effect of changing levels of RL on the
input impedance?
h. For the original network of Fig. 5.176 determine Ai  Io>Ii.

FIG. 5.176
Problem 42.

5.16 Cascaded Systems

*43. For the cascaded system of Fig. 5.177 with two identical stages, determine:
a. The loaded voltage gain of each stage.
b. The total gain of the system, Av and Avs.
c. The loaded current gain of each stage.
d. The total current gain of the system AiL = Io >Ii.
e. How Zi is affected by the second stage and RL.
f. How Zo is affected by the first stage and Rs.
g. The phase relationship between Vo and Vi.
 Ii Rs 1 μF V 1 μF Io PROBLEMS 371
i Vo
CE amplifier CE amplifier
+ 0.6 kΩ
Zi = 1 kΩ Zi = 1 kΩ
Vs RL 2.7 kΩ
Zo = 3.3 kΩ Zo = 3.3 kΩ Zo
– Zi
Av NL = – 420 Av NL = – 420

Zo Zi
1 2

FIG. 5.177
Problem 43.

*44. For the cascaded system of Fig. 5.178, determine:

a. The loaded voltage gain of each stage.
b. The total gain of the system, AvL and Avs.
c. The loaded current gain of each stage.
d. The total current gain of the system.
e. How Zi is affected by the second stage and RL.
f. How Zo is affected by the first stage and Rs.
g. The phase relationship between Vo and Vi.

Ii Rs Vi 10 μF Io Vo
Emitter - follower CE amplifier
+ 1 kΩ 10 μF
Zi = 50 kΩ Z i = 1.2 kΩ
Vs RL 2.2 kΩ
Zo = 20 Ω Zo = 4.6 kΩ
– Zi Zo
Av ≅ 1 Av = – 640
NL NL

Zo Zi
1 2

FIG. 5.178
Problem 44.

45. For the BJT cascade amplifier of Fig. 5.179, calculate the dc bias voltages and collector current
for each stage.
46. a. Calculate the voltage gain of each stage and the overall ac voltage gain for the BJT cascade
amplifier circuit of Fig. 5.179.
b. Find AiT = Io >Ii.

Io

Ii

FIG. 5.179
Problems 45 and 46.
372 BJT AC ANALYSIS 47. For the cascode amplifier circuit of Fig. 5.180, calculate the dc bias voltages VB1, VB2, and VC2.
*48. For the cascode amplifier circuit of Fig. 5.180, calculate the voltage gain Av and output voltage Vo.
49. Calculate the ac voltage across a 10-k load connected at the output of the circuit in Fig. 5.180.

+20 V

1.5 kΩ
1 μF
7.5 kΩ
Vo
50 μ F Q2
β = 200

6.2 kΩ
10 μ F Q1
Vi β = 100
10 mV

3.9 kΩ
1 kΩ 100 μF

FIG. 5.180
Problems 47 and 49.
5.17 Darlington Connection
50. For the Darlington network of Fig. 5.181:
a. Determine the dc levels of VB1, VC1, VE2, VCB1, and VCE2.
b. Find the currents IB1, IB2, and IE2.
c. Calculate Zi and Zo.
d. Determine the voltage gain Av  Vo/Vi and current gain Ai  Io>Ii.

Vi β1 = 50, β 2 = 120
Ii VBE1 = VBE2 = 0.7 V

Io
10 μF

FIG. 5.181
Problems 50 through 53.
51. Repeat problem 50 with a load resistor of 1.2 k.
52. Determine Av  Vo>Vs for the network of Fig. 5.181 if the source has an internal resistance of
1.2 k and the applied load is 10 k.
53. A resistor RC  470  is added to the network of Fig. 5.181 along with a bypass capacitor
CE  5 mF across the emitter resistor. If bD  4000, VBET = 1.6 V, and ro1 = ro2 = 40 k
for a packaged Darlington amplifier:
a. Find the dc levels of VB1, VE2, and VCE2.
b. Determine Zi and Zo.
c. Determine the voltage gain Av  Vo>Vi if the output voltage Vo is taken off the collector
terminal via a coupling capacitor of 10 mF.
5.18 Feedback Pair PROBLEMS 373
54. For the feedback pair of Fig. 5.182:
a. Calculate the dc voltages VB1, VB2, VC1, VC2, VE1, and VE2.
b. Determine the dc currents IB1, IC1, IB2, IC2, and IE2.
c. Calculate the impedances Zi and Zo.
d. Find the voltage gain Av = Vo>Vi.
e. Determine the current gain Ai = Io>Ii.

Io

68 Ω

Ii

Zo
Zi

FIG. 5.182
Problems 54 and 55.

55. Repeat problem 54 if a 22- resistor is added between VE2 and ground.
56. Repeat problem 54 if a load resistance of 1.2 k is introduced.

5.19 The Hybrid Equivalent Model

57. Given IE (dc) = 1.2 mA, b  120, and ro  40 k, sketch the following:
a. Common-emitter hybrid equivalent model.
b. Common-emitter re equivalent model.
c. Common-base hybrid equivalent model.
d. Common-base re equivalent model.
58. Given hie = 2.4 k, hfe = 100, hre = 4 * 10-4, and hoe = 25 mS, sketch the following:
a. Common-emitter hybrid equivalent model.
b. Common-emitter re equivalent model.
c. Common-base hybrid equivalent model.
d. Common-base re equivalent model.
59. Redraw the common-emitter network of Fig. 5.3 for the ac response with the approximate
hybrid equivalent model substituted between the appropriate terminals.
60. Redraw the network of Fig. 5.183 for the ac response with the re model inserted between the
appropriate terminals. Include ro.
61. Redraw the network of Fig. 5.184 for the ac response with the re model inserted between the
appropriate terminals. Include ro.
62. Given the typical values of hie = 1 k, hre = 2 * 10-4, and Av = - 160 for the input con-
figuration of Fig. 5.185:
a. Determine Vo in terms of Vi.
b. Calculate Ib in terms of Vi.
c. Calculate Ib if hreVo is ignored.
d. Determine the percentage difference in Ib using the following equation:
Ib(without hre) - Ib(with hre)
% difference in Ib = * 100%
Ib(without hre)
e. Is it a valid approach to ignore the effects of hreVo for the typical values employed in this
example?
 Vo

Vo

FIG. 5.183 FIG. 5.184

Problem 60. Problem 61.

FIG. 5.185
Problems 62 and 64.

63. Given the typical values of RL = 2.2 k and hoe = 20 mS, is it a good approximation to
ignore the effects of 1>hoe on the total load impedance? What is the percentage difference in
total loading on the transistor using the following equation?
RL - RL 7 (1>hoe)
% difference in total load = * 100%
RL
64. Repeat Problem 62 using the average values of the parameters of Fig. 5.92 with Av = - 180.
65. Repeat Problem 63 for RL = 3.3 k and the average value of hoe in Fig. 5.92.

5.20 Approximate Hybrid Equivalent Circuit

66. a. Given b  120, re  4.5 , and ro = 40 k, sketch the approximate hybrid equivalent
circuit.
b. Given hie = 1 k, hre = 2 * 10-4, hfe = 90, and hoe = 20 mS, sketch the re model.
67. For the network of Problem 11:
a. Determine re.
b. Find hfe and hie.
c. Find Zi and Zo using the hybrid parameters.
d. Calculate Av and Ai using the hybrid parameters.
e. Determine Zi and Zo if hoe = 50 mS.
f. Determine Av and Ai if hoe = 50 mS.
g. Compare the solutions above with those of Problem 9. (Note: The solutions are available in
Appendix E if Problem 11 was not performed.)
68. For the network of Fig. 5.186:
a. Determine Zi and Zo.
b. Calculate Av and Ai.
c. Determine re and compare bre to hie.
374
 18 V PROBLEMS 375

2.2 kΩ
68 kΩ
Io
Vo
Ii
5 μF
Vi hfe = 180
Zo hie = 2.75 kΩ
5 μF
hoe = 25 μS

12 kΩ
Zi 1.2 kΩ 10 μF

FIG. 5.186
Problem 68.

*69. For the common-base network of Fig. 5.187:

a. Determine Zi and Zo.
b. Calculate Av and Ai.
c. Determine a, b, re, and ro.

hfb = −0.992
hib = 9.45 Ω
hob = 1 μ A/V
Ii

+ 10 μ F
Io
10 μF +
1.2 kΩ 2.7 kΩ
Vi + – Vo
Zi 4V 12 V Zo
– +
– –

FIG. 5.187
Problem 69.

5.21 Complete Hybrid Equivalent Model

*70. Repeat parts (a) and (b) of Problem 68 with hre = 2 * 10-4 and compare results.
*71. For the network of Fig. 5.188, determine:
a. Zi.
b. Av.
c. Ai = Io>Ii.
d. Zo.
*72. For the common-base amplifier of Fig. 5.189, determine:
a. Zi.
b. Ai.
c. Av.
d. Zo.
376 BJT AC ANALYSIS 20 V

2.2 kΩ
470 kΩ Io
Vo
Ii 5 μF
1 kΩ hfe = 140
+ Zo hie = 0.86 kΩ
+ 5 μF hre = 1.5 × 10− 4
hoe = 25 μS
Vs Vi
1.2 kΩ 10 μ F
–
Zi
–
FIG. 5.188
Problem 71.

hib = 9.45 Ω
hfb = −0.997
hob = 0.5 μ A/V
hrb = 1 × 10− 4
Ii
0.6 kΩ Io

5 μF + 5 μF +
+
1.2 kΩ 2.2 kΩ
Vs Vi Vo
Zi + – Zo
– 4V 14 V
– +
– –

FIG. 5.189
Problem 72.
5.22 Hybrid P Model
73. a. Sketch the Giacoletto (hybrid p) model for a common-emitter transistor if rb = 4 ,
Cp = 5 pF, Cu = 1.5 pF, hoe = 18 mS, b  120, and re = 14.
b. If the applied load is 1.2 k and the source resistance is 250 , draw the approximate
hybrid p model for the low- and mid-frequency range.

5.23 Variations of Transistor Parameters

For Problems 74 through 80, use Figs. 5.124 through 5.126.
74. a. Using Fig. 5.124, determine the magnitude of the percentage change in hfe for an IC change
from 0.2 mA to 1 mA using the equation
hfe(0.2 mA) - hfe(1 mA)
% change = ` ` * 100%
hfe(0.2 mA)
b. Repeat part (a) for an IC change from 1 mA to 5 mA.
75. Repeat Problem 74 for hie (same changes in IC).
76. a. If hoe = 20 mS at IC = 1 mA on Fig. 5.124, what is the approximate value of hoe at
IC = 0.2 mA?
b. Determine its resistive value at 0.2 mA and compare to a resistive load of 6.8 k. Is it a
good approximation to ignore the effects of 1>hoe in this case?
77. a. If hoe = 20 mS at IC = 1 mA of Fig. 5.124, what is the approximate value of hoe at
IC = 10 mA?
b. Determine its resistive value at 10 mA and compare to a resistive load of 6.8 k. Is it a
good approximation to ignore the effects of 1>hoe in this case?
78. a. If hre = 2 * 10-4 at IC = 1 mA on Fig. 5.124, determine the approximate value of hre at
0.1 mA.
b. For the value of hre determined in part (a), can hre be ignored as a good approximation if
Av = 210?
 79. a. Based on a review of the characteristics of Fig. 5.124, which parameter changed the least PROBLEMS 377
for the full range of collector current?
b. Which parameter changed the most?
c. What are the maximum and minimum values of 1>hoe? Is the approximation 1>hoe 储 RL ⬵ RL
more appropriate at high or low levels of collector current?
d. In which region of current spectrum is the approximation hreVce ⬵ 0 the most appropriate?
80. a. Based on a review of the characteristics of Fig. 5.126, which parameter changed the most
with increase in temperature?
b. Which changed the least?
c. What are the maximum and minimum values of hfe? Is the change in magnitude signifi-
cant? Was it expected?
d. How does re vary with increase in temperature? Simply calculate its level at three or four
points and compare their magnitudes.
e. In which temperature range do the parameters change the least?

5.24 Troubleshooting
*81. Given the network of Fig. 5.190:
a. Is the network properly biased?
b. What problem in the network construction could cause VB to be 6.22 V and obtain the given
waveform of Fig. 5.190?

VCC = 14 V

RC 2.2 kΩ ve (V)
vi (mV)
R1 150 kΩ
10 μ F
0 t vo 0 t
10 μ F C2
VB = 6.22 V
β = 70 ve
C1
+
VBE = 0.7 V
Rs – 0 t

+ R2 39 kΩ
RE 1.5 kΩ 10 μ F
Vs

FIG. 5.190
Problem 81.

5.27 Computer Analysis

82. Using PSpice Windows, determine the voltage gain for the network of Fig. 5.25. Display the
input and output waveforms.
83. Using PSpice Windows, determine the voltage gain for the network of Fig. 5.32. Display the
input and output waveforms.
84. Using PSpice Windows, determine the voltage gain for the network of Fig. 5.44. Display the
input and output waveforms.
85. Using Multisim, determine the voltage gain for the network of Fig. 5.28.
86. Using Multisim, determine the voltage gain for the network of Fig. 5.39.
87. Using PSpice Windows, determine the level of Vo for Vi = 1 mV for the network of Fig. 5.69.
For the capacitive elements assume a frequency of 1 kHz.
88. Repeat Problem 87 for the network of Fig. 5.71.
89. Repeat Problem 87 for the network of Fig. 5.82.
90. Repeat Problem 87 using Multisim.
91. Repeat Problem 87 using Multisim.