USOO661 1220B1

(12) United States Patent (10) Patent No.: US 6,611,220 B1

Snyder (45) Date of Patent: Aug. 26, 2003

(54) ARCHITECTURE FOR DECIMATION 5,202.687 A 4/1993 Distinti ...................... 341/158

ALGORTHM 6,144,327 A 11/2000 Distinti et al. .............. 341/126
6,281,718 B1 * 8/2001 Page et al................... 327/106
(75) Inventor: Warren Snyder, Snohomish, WA (US)
(73) Assignee: Cypress Semiconductor Corporation, * cited by examiner
San Jose, CA (US)
(*) Notice: Subject to any disclaimer, the term of this Primary Examiner-Peguy Jean Pierre
patent is extended or adjusted under 35 ASSistant Examiner Joseph Lauture
U.S.C. 154(b) by 0 days. (74) Attorney, Agent, or Firm Wagner, Murabito, & Hao
LLP
(21) Appl. No.: 09/973,535 (57) ABSTRACT
(22) Filed: Oct. 9, 2001
A new architecture for implementing a digital algorithm
Related U.S. Application Data Such as a decimation algorithm is described. The new
(60) visional application No. 60/243,708, filed on Oct. 26, decimator circuit is well Suited for digital circuits Such as a
7 delta-Sigma (or Sigma-delta) analog-to-digital converter. In
(51) Int. Cl.' .................................................. H03N 3/00 particular, the new decimator circuit incorporates a general
(52) U.S. Cl. ................ ... 341/143: 341/144 purpose architecture which enables a wide range of flex
(58) Field of Search ................................. 341/143, 144, ibility to change and modify the decimation algorithm
341/118, 120; 708/313 performed by the decimator circuit. Moreover, the new
(56) References Cited decimator circuit can be fabricated in a Smaller chip area
than previously possible.
U.S. PATENT DOCUMENTS
5,196.850 A * 3/1993 Duffy et al. ................ 341/143 21 Claims, 2 Drawing Sheets

300 13 TO 168 CONVERTER FROM SYSTEM REGISTER

FROMANALOG
BLOCKS

DECIMATOR
200

- 264
REGISTER
220 <

STATE
MACHINE
250

PROGRAMMING
257
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1 2
ARCHITECTURE FOR DECIMATION SUMMARY OF THE INVENTION
ALGORTHM
A new architecture for implementing a digital algorithm
RELATED U.S. APPLICATION Such as a decimation algorithm is described. The new
This application claims priority to the copending provi decimator circuit is well Suited for digital circuits Such as a
sional patent application, Ser. No. 60/243,708, entitled delta-Sigma (or Sigma-delta) analog-to-digital converter. In
“Advanced Programmable Microcontroller Device,” with particular, the new decimator circuit incorporates a general
filing date Oct. 26, 2000, and assigned to the assignee of the purpose architecture which enables a wide range of flex
present application. ibility to change and modify the decimation algorithm
BACKGROUND OF THE INVENTION performed by the decimator circuit. Moreover, the new
1. Field of the Invention
decimator circuit can be fabricated in a Smaller chip area
than previously possible.
The present invention generally relates to digital circuits. Instead of having multiple discrete circuit stages as in the
More particularly, the present invention relates to the field of conventional decimator circuit, the decimator circuit of the
circuit architectures for implementing decimation algo 15 present invention includes a multiplexer, an adder, and a
rithms.
2. Related Art
random access memory (RAM), whereas a plurality of
Signals control the operation of the multiplexer, the adder,
The technology environment for digital Signal processing and the RAM Such that in a clock cycle at least a portion of
(DSP) is rapidly changing. DSP performance continues to a Stage of the decimation algorithm is performed. In an
increase at a fairly constant rate acroSS the industry, and the embodiment, a State machine is operative to generate the
complexity of DSP peripherals is also expanding. The per plurality of Signals for controlling operation of the
formance goal of a DSP architecture is to perform as many multiplexer, the adder, and the RAM. Alternatively, a con
arithmetic operations as possible in the Smallest number of troller is operative to generate the plurality of Signals for
clock cycles. But whereas DSP-centric applications have controlling operation of the multiplexer, the adder, and the
traditionally employed processors designed for DSP tasks, a 25 RAM.
complementary, and competing, technology has emerged. These and other advantages of the present invention will
Microcontroller suppliers are offering DSP-specific func no doubt become apparent to those of ordinary skill in the art
tionality to their architectures. after having read the following detailed description of the
The analog-to-digital converter (ADC) converts an exter preferred embodiments which are illustrated in the drawing
nal analog signal (typically relative to voltage) to a digital figures.
representation. Devices such as a microcontroller or DSP
processor that have a ADC can be used for instrumentation, BRIEF DESCRIPTION OF THE DRAWINGS
environmental data logging, or any other application that The accompanying drawings, which are incorporated in
lives in an analog World. An Overwhelming variety of ADCs and form a part of this Specification, illustrate embodiments
exist on the market today, with differing resolutions, 35
of the invention and, together with the description, Serve to
bandwidths, accuracies, architectures, packaging, power explain the principles of the present invention.
requirements, and temperature ranges, as well as hosts of
Specifications, covering a broad range of performance needs. FIG. 1 illustrates a conventional delta-sigma ADC, show
One popular ADC architecture is the delta-Sigma (or ing a conventional decimator.
sigma-delta) ADC. FIG. 1 illustrates a conventional delta 40 FIG. 2 illustrates a decimator circuit in accordance with
sigma ADC 100. As illustrated in FIG. 1, the conventional an embodiment of the present invention, showing the deci
delta-sigma ADC 100 has an analog block (not shown) mator circuit implemented in a delta-Sigma ADC.
which performs the analog-to-digital conversion and gener The drawings referred to in this description should not be
ates an output stream of 1S (or high) and OS (or low). understood as being drawn to Scale except if specifically
Moreover, the conventional delta-Sigma ADC 100 has a 45 noted.
filter 20 which converts the output 10 of the analog block
(not shown) into a digital value 50 having a format suitable DETAILED DESCRIPTION OF THE
for the microcontroller, DSP processor, etc. INVENTION
The filter 20 includes a (1 bit to Y bits) converter 30 and Reference will now be made in detail to the preferred
a conventional decimator 40. The (1 bit to Y bits) converter 50 embodiments of the present invention, examples of which
30 generates a Y-bit output of +1 values or -1 values, are illustrated in the accompanying drawings. While the
depending on whether the output 10 of the analog block (not invention will be described in conjunction with the preferred
shown) is 1 or 0 (high or low). embodiments, it will be understood that they are not
The conventional decimator 40 performs a decimation intended to limit the invention to these embodiments. On the
algorithm using a plurality of discrete circuit Stages 50A, 55 contrary, the invention is intended to cover alternatives,
50B, and 50C which are synchronously clocked with the modifications and equivalents, which may be included
Signal CLK. Typically, these discrete circuit stages 50A, within the spirit and scope of the invention as defined by the
50B, and 50C perform either an integration operation or a appended claims. Furthermore, in the following detailed
differentiation operation. Moreover, each of the discrete description of the present invention, numerous specific
circuit stages 50A, 50B, and 50C typically includes an adder 60 details are Set forth in order to provide a thorough under
and at least one register for implementing an accumulator standing of the present invention. However, it will be
type of circuit. The circuit architecture for the conventional recognized by one of ordinary skill in the art that the present
decimator 40 is inefficient in terms of circuit area and cost. invention may be practiced without these specific details. In
Moreover, the circuit architecture for the conventional deci other instances, well known methods, procedures,
mator 40 does not provide flexibility to change the decima 65 components, and circuits have not been described in detail
tion algorithm once the conventional decimator 40 had been as not to unnecessarily obscure aspects of the present
fabricated. invention.
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FIG. 2 illustrates a decimator circuit 200 in accordance decimation algorithm can have various implementations. In
with an embodiment of the present invention, showing the FIG. 1, the conventional decimator circuit 40 typically
decimator circuit 200 implemented in a delta-sigma ADC includes M integrator Stages cascaded with M differentiator
300. A new architecture for implementing a digital algorithm Stages, whereas these stage are Synchronously clocked and
Such as a decimation algorithm is depicted in FIG. 2. The whereas each Stage typically includes an adder and at least
decimator circuit 200 is well Suited for digital circuits such one register to perform either the integration operation or the
as a delta-Sigma (or Sigma-delta) analog-to-digital converter differentiation operation.
300. In particular, the decimator circuit 200 incorporates a Unlike the conventional decimator circuit 40 of FIG. 1
general purpose architecture which enables a wide range of which utilizes multiple adders, the decimator circuit 200
flexibility to change and modify the decimation algorithm (FIG. 2) of the present invention utilizes a single adder 230.
performed by the decimator circuit 200. Moreover, the new The input 268 to the adder 230 is multiplexed to provide
decimator circuit 200 can be fabricated in a smaller chip area flexibility. Rather than utilizing a plurality of registers for
than previously possible. In addition, the decimator circuit Storing an accumulator value of each Stage of the decimation
200 decomposes the Synchronously clocked multiple stages algorithm, the decimator circuit 200 (FIG. 2) of the present
(as illustrated in FIG. 1) of the decimation algorithm into a 15 invention utilizes a RAM 240 having a plurality of memory
Single discrete architecture characterized by Several clock locations or words, whereas theses memory locations or
cycles, whereas in a clock cycle at least a portion of a stage words can Store accumulator values corresponding to dif
of the decimation algorithm is performed. ferent stages of the decimation algorithm. The RAM 240
As illustrated in FIG. 2, the delta-sigma ADC 300 has a provides a more Space efficient implementation of data
plurality of analog blocks (not shown), each performs the Storage than the plurality of registers of the conventional
analog-to-digital conversion of Separate external analog decimator circuit 40 (FIG. 1).
Signal and generates an output stream of 1S (or high) and 0 Rather than performing the multiple Stages of the deci
s (or low). The output 510 and 520 of each analog block is mation algorithm in a Single clock cycle as in the conven
coupled to the multiplexed inputs of the multiplexer 500 (or tional decimator circuit 40 (FIG. 1), the decimator circuit
mux 3). The signal 530 from a system register determines 25 200 (FIG. 2) of the present invention uses several clock
which one of the multiplexed inputs is coupled to the cycles to perform the multiple Stages of the decimation
multiplexer output 540. The signal 530 may be of a length algorithm, whereas in a clock cycle at least a portion of a
greater than one bit. In order to convert the multiplexer Stage of the decimation algorithm is performed. In essence,
output 540 into a digital value having a format suitable for data is moved through the multiple Stages of the decimation
the microcontroller, DSP processor, etc., the delta-Sigma algorithm in Several clock cycles rather than in one clock
ADC 300 has a (1 bit to 16 bits) converter 400 and a cycle. The decimator circuit 200 (FIG. 2) of the present
decimator circuit 200. The (1 bit to 16 bits) converter 400 invention can be clocked at a higher rate than the conven
receives the multiplexer output 540 and is coupled to the tional decimator circuit 40 (FIG. 1) to prevent performance
decimator circuit 200. Moreover, the (1 bit to 16 bits) degradation in a system in which the decimator circuit 200
converter 400 has a multiplexer 410 (or mux 1) that has a 35 (FIG. 2) of the present invention is incorporated to take
first multiplexed input 420 and a second multiplexed input advantage of the decimator circuit's 200 chip area efficiency
430. The multiplexer 410 generates a 16-bit output of +1 relative to the conventional decimator circuit 40 (FIG. 1).
values or -1 values via multiplexer output 260, depending Referring to FIG. 2, the decimator circuit 200 includes the
on whether the multiplexer output 540 of mux 3 is 1 or 0 multiplexer 210 (or mux 2). The multiplexer 210 has a first
(high or low). The decimator circuit 200 receives the mul 40 16-bit multiplexed input coupled to the output port RPB of
tiplexer output 260. It should be understood that the delta the RAM 240. The multiplexer 210 has a second 16-bit
sigma ADC 300 can have other configurations. multiplexed input coupled to the input Signal generated at
Instead of having multiple discrete circuit stages as in the the multiplexer output 260 of mux 1. The multiplexer 210
conventional decimator circuit 40 of FIG. 1, the decimator has a multiplexer output 264 for outputting the Selected one
circuit 200 of the present invention includes a multiplexer 45 of the first and Second multiplexed inputs based on the Signal
210, an adder 230, and a random access memory (RAM) Sig 1. Moreover, the multiplexer 210 includes an inversion
240, whereas a plurality of Signals (e.g., Sig 1, Sig 2, circuit 215 which generates a negative version of the
Sig 3, etc.) control the operation of the multiplexer 210, the Selected one of the first and Second multiplexed inputs at the
adder 230, and the RAM 240 such that in a clock cycle at multiplexer output 264 based on the Signal Sig 2. The
least a portion of a stage of the decimation algorithm is 50 Signal Sig 1 is a Selection signal for Selecting one of the
performed. In an embodiment, the decimator circuit 200 first and second multiplexed inputs of the multiplexer 210.
includes a State machine 250 which is operative to generate The Signal Sig 2 is an inversion Signal for indicating
the plurality of Signals (e.g., Sig 1, Sig 2, Sig 3, etc.) for whether to generate a negative version of the Selected one of
controlling operation of the multiplexer 210, the adder 230, the first and Second multiplexed inputs at the multiplexer
and the RAM 240. Alternatively, the decimator circuit 200 55 output 264.
The decimator circuit 200 further includes an adder 230
includes a controller (not shown) which is operative to and a register 220 which prevents race conditions Since a
generate the plurality of signals (e.g., Sig 1, Sig 2, Sig 3,
etc.) for controlling operation of the multiplexer 210, the memory location or word of the RAM 240 will be read from
adder 230, and the RAM 240. and written to in a clock cycle of the decimator circuit 200.
The response of the decimator algorithm used in filtering
60 The adder 230 has a first 16-bit input coupled to the output
applications, Such as in a delta-Sigma ADC, can be described port RPA of the RAM 240. The adder 230 has a second
S.
16-bit input coupled to the output of the register 220 whose
input is coupled to the multiplexer output 264 of muX 2.
The adder 230 has an adder output 272 coupled to the input
65 port WPA of the RAM 240. Moreover, the adder 230 has a
whereas M is the order of the decimation filter and L is the carry-in port CI coupled to the output of a first flip-flop. 234
level of decimation. Moreover, this response shows that the whose input is coupled to the Signal Sig 3, whereas the
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signal Sig 3 is a carry-in signal for the adder 230. The adder between the stage 050A of FIG. 1 and the converter 30 of
230 has a carry-out port CO coupled to the input of a second FIG. 1. The mux 2210 receives the input signal from the
flip-flop. 236 whose output provides the Signal Sig 4, multiplexer output 260. The state machine 250 (1) generates
whereas the Signal Sig 4 is a carry-out Signal of the adder the Signal Sig 1 to cause the muX 2 to Select the input
230. The first flip-flop. 234 and the register 220 are clocked signal from the multiplexer output 260 rather than the output
by the clock signal W'. The second flip-flop. 236 is clocked port RPB 246 from the RAM 240 and (2) generates the
by the clock signal W. Signal Sig 2 to indicate to the inversion circuit 215 that no
The decimator circuit 200 further includes the RAM 240 inversion is required. Moreover, the multiplexer output 264
having a plurality of memory locations or words. The of the mux 2 210 is clocked into the register 220. In
memory locations or words Store values representing accu addition, the State machine 250 (1) generates the signal
mulator values. In an embodiment, the RAM 240 has 2 Sig 3 representing the carry-in signal CI for the adder 230
words, each word being 16 bits in length, whereas k is 2. If and (2) generates the Signal Sig 5 representing a first
address signal for a memory location or word for the address
k is greater than 2, the RAM 240 has more than four words; port AA for enabling reading at the output port RPA244 and
thus, allowing more complex decimation algorithms, which for enabling writing from the input port WPA. The adder 230
require additional clock cycles, to be performed. The RAM 15
adds the output from the register 220 with the value of the
240 has the input port (or write port) WPA coupled to the memory location or word at the output port RPA244 of the
adder output 272, the output port (or read port) RPA 244 RAM 240. Moreover, the adder output 272 (representing an
coupled to an input of the adder 230, and the output port (or accumulator value) of the adder 230 is written to the
read port) RPB 246 coupled to the first multiplexed input of memory location or word corresponding to the first address
the muX 2. Signal Sig 5 provided at the address port AA by the State
Moreover, the RAM 240 includes a first address port AA machine 250. The state machine 250 receives the signal
for Selecting one of the plurality of memory locations or Sig 4 representing the carry-out signal CO of the adder
words to couple to the output port (or read port) RPA 244 230.
and to the input port (or write port) WPA, whereas the signal In a second clock cycle, the decimator circuit 200 adds a
Sig 5 is coupled to the first address port AA. In essence, the 25 previous accumulator value Stored in a memory location or
address at the first address port AA provides the memory word to a next accumulator value Stored in a another
location or word that is read from at the output port RPA and memory location or word. In essence, the Second clock cycle
that is written to from the input port WPA. The signal Sig 5 accounts for the interaction between the stage 050A of
is a first address signal. In addition, the RAM 240 includes FIG. 1 and the stage 150B of FIG. 1. The state machine
a Second address port AB for Selecting one of the plurality 250 (1) generates the signal Sig 1 to cause the mux 2210
of memory locations or words to couple to the output port to select the output port RPB 246 from the RAM 240 rather
(or read port) RPB 246, whereas the signal Sig 6 is coupled than the input signal from the multiplexer output 260, (2)
to the Second address port AB. The signal Sig 6 is a second generates the Signal Sig 6 representing a Second address
address signal. The RAM 240 is clocked by the clock signal Signal for a memory location or word (representing a pre
W. Moreover, the signal Reset is coupled to the RAM 240 35 vious accumulator value) for the address port AB for
and to the first and second flip-flops 234 and 236. enabling reading at the output port RPB 246, and (3)
Continuing with FIG. 2, in an embodiment the decimator generates the Signal Sig 2 to indicate to the inversion
circuit 200 also includes a state machine 250 which is circuit 215 whether inversion is required, whereas inversion
operative to generate the plurality of Signals (e.g., Sig 1, is required for differentiation operations of the decimation
Sig 2, Sig 3, Sig 5, and Sig. 6) for controlling operation 40 algorithm and whereas non-inversion is required for inte
of the multiplexer 210, the adder 230, and the RAM 240 gration operations of the decimation algorithm. Moreover,
Such that to perform the decimation algorithm. Moreover, the multiplexer output 264 of the mux 2210 is clocked into
the state machine 250 receives the signal Sig 4, which is a the register 220. In addition, the state machine 250 (1)
carry-out signal of the adder 230, from the second flip generates the Signal Sig 3 representing the carry-in signal
flop. 236. The state machine 250 includes a terminal 257 for 45 CI for the adder 230 and (2) generates the signal Sig 5
receiving programming information for programming the representing a first address signal for a memory location or
state machine 250. The state machine 250 is clocked by the word (representing a next accumulator value) for the address
clock signal W and is coupled to the Signal Reset. It should port AA for enabling reading at the output port RPA244 and
be understood that the state machine 250 can be replaced by for enabling writing from the input port WPA. The adder 230
a controller. The state machine 250 in each clock cycle 50 adds the output from the register 220 with the value of the
generates the proper values for the Signals Sig 1, Sig 2, memory location or word at the output port RPA244 of the
Sig 3, Sig 5, and Sig 6. Moreover, the decimation algo RAM 240. Moreover, the adder output 272 (representing an
rithm performed by the decimator circuit 200 can be accumulator value) of the adder 230 is written to the
changed or modified by reprogramming the State machine memory location or word corresponding to the first address
250 so that to generate a different sequence of values for the 55 Signal Sig 5 provided at the address port AA by the State
Signals Sig 1, Sig 2, Sig 3, Sig 5, and Sig 6. machine 250. The state machine 250 receives the signal
In practice, the decimator circuit 200 is clocked (e.g., Sig 4 representing the carry-out signal CO of the adder
clock signals W and W) at a higher rate than the rate at 230.
which the data associated with the analog block is clocked This proceSS continues until every stage of the decimation
into the decimator circuit 200 via the (1 bit to 16 bits) 60 algorithm is performed. If a particular Stage generates more
converter 400. than a 16 bit width value, two or more words of the RAM
According to an embodiment, in a first clock cycle of the 240 may be required; thus, increasing the number of clock
decimator circuit 200 the (1 bit to 16 bits) converter 400 cycles required to perform the particular stage of the deci
provides a 16-bit output of +1 values or -1 values via the mation algorithm. Moreover, when the (1 bit to 16 bits)
multiplexer output 260, depending on whether the multi 65 converter 400 provides a new 16-bit output of +1 values or
plexer output 540 of mux 3500 is 1 or 0 (high or low). In -1 values via the multiplexer output 260, the process Starts
essence, the first clock cycle accounts for the interaction again as described above.
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The foregoing descriptions of specific embodiments of the 8. A decimator circuit comprising:
present invention have been presented for purposes of a multiplexer having a plurality of multiplexed inputs and
illustration and description. They are not intended to be a multiplexer output for outputting one of Said multi
exhaustive or to limit the invention to the precise forms plexed inputs, wherein one of Said multiplexed inputs
disclosed, and obviously many modifications and variations is coupled to a input signal;
are possible in light of the above teaching. The embodiments an adder having a first input, a Second input, and an adder
were chosen and described in order to best explain the output, wherein Said Second input receives one of Said
principles of the invention and its practical application, to multiplexed inputs outputted by Said multiplexer out
thereby enable others skilled in the art to best utilize the put; and
invention and various embodiments with various modifica a random access memory (RAM) having a plurality of
tions as are Suited to the particular use contemplated. It is memory locations, a first output port coupled to Said
intended that the scope of the invention be defined by the first input of Said adder, a Second output port coupled
Claims appended hereto and their equivalents. to one of Said multiplexed inputs of Said multiplexer, an
What is claimed is: input port coupled to Said adder output, a first address
1. A circuit comprising: 15 port for Selecting one of Said memory locations to
couple to Said first output port and to Said input port,
a multiplexer having a plurality of multiplexed inputs and and a Second address port for Selecting one of Said
a multiplexer output for outputting one of Said multi memory locations to couple to Said Second output port,
plexed inputs, wherein one of Said multiplexed inputs wherein said multiplexer, said adder, and said RAM
is coupled to a input signal; perform in a clock cycle at least a portion of a Stage of
an adder having a first input, a Second input, and an adder a decimation algorithm.
output, wherein Said Second input receives one of Said 9. A decimator circuit as recited in claim 8 further
multiplexed inputs outputted by Said multiplexer out comprising a State machine operative to generate a plurality
put; and of Signals for controlling operation of Said multiplexer, Said
a random access memory (RAM) having a plurality of 25 adder, and Said RAM Such that to perform Said decimation
memory locations, a first output port coupled to Said algorithm.
first input of Said adder, a Second output port coupled 10. A decimator circuit as recited in claim 9 wherein said
to one of Said multiplexed inputs of Said multiplexer, an plurality of Signals includes a Selection signal for Selecting
input port coupled to Said adder output, a first address one of Said multiplexed inputs of Said multiplexer, an
port for Selecting one of Said memory locations to inversion Signal for indicating whether to generate a nega
couple to Said first output port and to Said input port, tive version of Said Selected one of Said multiplexed inputs
and a Second address port for Selecting one of Said at Said multiplexer output, a carry-in signal for Said adder, a
memory locations to couple to Said Second output port, first address signal for said first address port of said RAM,
wherein said multiplexer, said adder, and said RAM and a Second address Signal for Said Second address port of
perform in a clock cycle at least a portion of a Stage of 35 said RAM.
a digital algorithm. 11. A decimator circuit as recited in claim 8 further
2. A circuit as recited in claim 1 wherein Said digital comprising a controller operative to generate a plurality of
algorithm is a decimation algorithm, and further comprising Signals for controlling operation of Said multiplexer, Said
a State machine operative to generate a plurality of Signals adder, and Said RAM Such that to perform Said decimation
for controlling operation of Said multiplexer, Said adder, and 40 algorithm.
Said RAM Such that to perform Said decimation algorithm. 12. A decimator circuit as recited in claim 11 wherein Said
3. A circuit as recited in claim 2 wherein Said plurality of plurality of Signals includes a Selection signal for Selecting
Signals includes a Selection Signal for Selecting one of Said one of Said multiplexed inputs of Said multiplexer, an
multiplexed inputs of Said multiplexer, an inversion Signal inversion Signal for indicating whether to generate a nega
for indicating whether to generate a negative version of Said 45 tive version of Said Selected one of Said multiplexed inputs
Selected one of Said multiplexed inputs at Said multiplexer at Said multiplexer output, a carry-in signal for Said adder, a
output, a carry-in signal for Said adder, a first address Signal first address signal for said first address port of said RAM,
for said first address port of said RAM, and a second address and a Second address Signal for Said Second address port of
Signal for Said Second address port of Said RAM. said RAM.
4. A circuit as recited in claim 1 wherein Said digital 50 13. A decimator circuit as recited in claim 8 further
algorithm is a decimation algorithm, and further comprising comprising a register disposed between Said multiplexer
a controller operative to generate a plurality of Signals for output and Said Second input of Said adder.
controlling operation of Said multiplexer, Said adder, and 14. A decimator circuit as recited in claim 8 wherein said
Said RAM Such that to perform Said decimation algorithm. input Signal has one of a +1 value and a -1 value.
5. A circuit as recited in claim 4 wherein said plurality of 55 15. A delta-Sigma analog-to-digital converter comprising:
Signals includes a Selection Signal for Selecting one of Said a decimator circuit including:
multiplexed inputs of Said multiplexer, an inversion Signal a multiplexer having a plurality of multiplexed inputs
for indicating whether to generate a negative version of Said and a multiplexer output for Outputting one of Said
Selected one of Said multiplexed inputs at Said multiplexer multiplexed inputs, wherein one of Said multiplexed
output, a carry-in signal for Said adder, a first address Signal 60 inputS is coupled to a input signal;
for said first address port of said RAM, and a second address an adder having a first input, a Second input, and an
Signal for Said Second address port of Said RAM. adder output, wherein Said Second input receives one
6. A circuit as recited in claim 1 further comprising a of Said multiplexed inputs outputted by Said multi
register disposed between Said multiplexer output and Said plexer output; and
Second input of Said adder. 65 a random access memory (RAM) having a plurality of
7. A circuit as recited in claim 1 wherein Said input Signal memory locations, a first output port coupled to Said
has one of a +1 value and a -1 value. first input of Said adder, a Second output port coupled
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to one of Said multiplexed inputs of Said multiplexer, 18. A delta-Sigma analog-to-digital converter as recited in
an input port coupled to Said adder output, a first claim 15 wherein Said decimator circuit further comprises a
address port for Selecting one of Said memory loca controller operative to generate a plurality of Signals for
tions to couple to Said first output port and to Said controlling operation of Said multiplexer, Said adder, and
input port, and a Second address port for Selecting Said RAM Such that to perform Said decimation algorithm.
one of Said memory locations to couple to Said 19. A delta-Sigma analog-to-digital converter as recited in
Second output port, wherein Said multiplexer, Said claim 18 wherein Said plurality of Signals includes a Selec
adder, and Said RAM perform in a clock cycle at tion signal for Selecting one of Said multiplexed inputs of
least a portion of a Stage of a decimation algorithm. Said multiplexer, an inversion Signal for indicating whether
16. A delta-Sigma analog-to-digital converter as recited in to generate a negative version of Said Selected one of Said
claim 15 wherein Said decimator circuit further comprises a multiplexed inputs at Said multiplexer output, a carry-in
State machine operative to generate a plurality of Signals for Signal for Said adder, a first address signal for Said first
controlling operation of Said multiplexer, Said adder, and address port of Said RAM, and a Second address signal for
Said RAM Such that to perform Said decimation algorithm. said second address port of said RAM.
17. A delta-Sigma analog-to-digital converter as recited in 15 20. A delta-Sigma analog-to-digital converter as recited in
claim 16 wherein Said plurality of Signals includes a Selec claim 15 wherein Said decimator circuit further comprises a
tion signal for Selecting one of Said multiplexed inputs of register disposed between said multiplexer output and Said
Said multiplexer, an inversion signal for indicating whether Second input of Said adder.
to generate a negative version of Said Selected one of Said 21. A delta-Sigma analog-to-digital converter as recited in
multiplexed inputs at Said multiplexer output, a carry-in claim 15 wherein Said input Signal has one of a +1 value and
Signal for Said adder, a first address signal for Said first a -1 value.
address port of Said RAM, and a Second address signal for
said second address port of said RAM.