CD54HC85, CD74HC85, CD54HCT85, CD74HCT85

SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022

CDx4HC85, CDx4HCT85 High-Speed CMOS Logic 4-Bit Magnitude Comparator

1 Features 2 Description
• Buffered inputs and outputs The ’HC85 and ’HCT85 are high speed magnitude
• Typical propagation delay: 13 ns (data to output at comparators that use silicon-gate CMOS technology
VCC = 5 V, CL = 15 pF, TA = 25℃) to achieve operating speeds similar to LSTTL with the
• Serial or parallel expansion without external gating low power consumption of standard CMOS integrated
• Fanout (over temperature range) circuits.
– Standard outputs: 10 LSTTL loads These 4-bit devices compare two binary, BCD, or
– Bus driver outputs: 15 LSTTL loads other monotonic codes and present the three possible
• Wide operating temperature range: –55℃ to 125℃ magnitude results at the outputs (A > B, A < B, and
• Balanced propagation delay and transition times A = B). The 4-bit input words are weighted (A0 to
• Significant power reduction compared to LSTTL A3 and B0 to B3), where A3 and B3 are the most
Logic ICs significant bits.
• HC types
– 2 V to 6 V operation Device Information
(1)
– High noise immunity: NIL = 30%, NIH = 30% of PART NUMBER PACKAGE BODY SIZE (NOM)
VCC at VCC = 5 V CD54HC85F3A CDIP (16) 24.38 mm × 6.92 mm
• HCT types CD54HCT85F3A CDIP (16) 24.38 mm × 6.92 mm
– 4.5 V to 5.5 V operation CD74HC85M SOIC (16) 9.90 mm × 3.90 mm
– Direct LSTTL input logic compatibility, CD74HCT85M SOIC (16) 9.90 mm × 3.90 mm
VIL = 0.8 V (max), VIH = 2 V (min)
CD74HC85E PDIP (16) 19.31 mm × 6.35 mm
– CMOS input compatibility, II ≤ 1 μA at VOL, VOH
CD74HCT85E PDIP (16) 19.31 mm × 6.35 mm
CD74HC85NS SO (16) 6.20 mm × 5.30 mm
CD74HC85PW TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
SCHS136F – AUGUST 1997 – REVISED FEBRUARY 2022 www.ti.com

Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram........................................... 9
2 Description.......................................................................1 7.3 Device Functional Modes..........................................10
3 Revision History.............................................................. 2 8 Power Supply Recommendations................................11
4 Pin Configuration and Functions...................................3 9 Layout............................................................................. 11
5 Specifications.................................................................. 4 9.1 Layout Guidelines..................................................... 11
5.1 Absolute Maximum Ratings(1) .................................... 4 10 Device and Documentation Support..........................12
5.2 Recommended Operating Conditions ........................4 10.1 Receiving Notification of Documentation Updates..12
5.3 Thermal Information....................................................4 10.2 Support Resources................................................. 12
5.4 Electrical Characteristics.............................................5 10.3 Trademarks............................................................. 12
5.5 Switching Specifications............................................. 6 10.4 Electrostatic Discharge Caution..............................12
6 Parameter Measurement Information............................ 7 10.5 Glossary..................................................................12
7 Detailed Description........................................................9 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 9 Information.................................................................... 12

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2003) to Revision F (February 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1

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4 Pin Configuration and Functions

J, N, D, NS, or PW package
16-Pin CDIP, PDIP, SOIC, SO, or TSSOP
Top View

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5 Specifications
5.1 Absolute Maximum Ratings(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA
IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA
ICC Continuous current through VCC or GND ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
Lead temperature (Soldering 10s) (SOIC - lead tips only) 300 °C

(1) Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.

5.2 Recommended Operating Conditions

MIN MAX UNIT
HC types 2 6
VCC Supply voltage range V
HCT types 4.5 5.5
VI, VO Input or output voltage 0 VCC V
2V 1000
Input rise and fall time 4.5 V 500 ns
6V 400
TA Temperature range –55 125 ℃

5.3 Thermal Information

D (SOIC) N (PDIP) NS (SO) PW (TSSOP)
THERMAL METRIC 16 PINS 16 PINS 16 PINS 16 PINS UNIT
RθJA Junction-to-ambient thermal
(1) 73 67 64 108 °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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5.4 Electrical Characteristics

TEST 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER VCC (V) UNIT
CONDITIONS(1) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 1.5 1.5 1.5
High level input
VIH 4.5 3.15 3.15 3.15 V
voltage
6 4.2 4.2 4.2
2 0.5 0.5 0.5
Low level input
VIL 4.5 1.35 1.35 1.35 V
voltage
6 1.8 1.8 1.8
IOH = – 20 μA 2 1.9 1.9 1.9
High level output
IOH = – 20 μA 4.5 4.4 4.4 4.4
voltage
VOH IOH = – 20 μA 6 5.9 5.9 5.9 V
High level output IOH = – 4 mA 4.5 3.98 3.84 3.7
voltage IOH = – 5.2 mA 6 5.48 5.34 5.2
IOL = 20 μA 2 0.1 0.1 0.1
Low level output
IOL = 20 μA 4.5 0.1 0.1 0.1
voltage V
VOL IOL = 20 μA 6 0.1 0.1 0.1
Low level output IOL = 4 mA 4.5 0.26 0.33 0.4
voltage IOL = 5.2 mA 6 0.26 0.33 0.4 V
Input leakage
II 6 ±0.1 ±1 ±1 μA
current
ICC Supply current VI = VCC or GND 6 8 80 160 μA
HCT TYPES
High level input 4.5 to
VIH 2 2 2 V
voltage 5.5
Low level input 4.5 to
VIL 0.8 0.8 0.8 V
voltage 5.5
High level output
IOH = – 20 μA 4.5 4.4 4.4 4.4
voltage
VOH V
High level output
IOH = – 4 μA 4.5 3.98 3.84 3.7
voltage

Low level output

IOL = 20 μA 4.5 0.1 0.1 0.1
voltage
VOL V
Low level output
IOL = 4 μA 4.5 0.26 0.33 0.4
voltage
Input leakage
II VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA
current
ICC Supply current VI = VCC or GND 5.5 8 80 160 μA
A0 - A3, B0 - B3 and 4.5 to
100 540 675 735 μA
ΔICC Additional supply (A = B) IN(3) 5.5
(2) current per input pin (A > B) IN, (A < B) 4.5 to
100 360 450 490 μA
IN(3) 5.5

(1) VI = VIH or VIL, unless otherwise noted.

(2) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
(3) Inputs held at VCC – 2.1.

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5.5 Switching Specifications

Input tr, tf = 6 ns
25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER VCC (V) UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation delay, 2 195 245 295
(3)
tPLH, tPHL An, Bn to (A > B) OUT, 4.5 16 39 47 59 ns
(A < B) OUT 6 33 42 50
2 175 240 265
(3)
tPLH, tPHL An, Bn to (A = B) OUT 4.5 14 35 44 53 ns
6 30 37 45
2 140 175 210
(A > B) IN, (A < B) IN, (A = B) IN (3)
tPLH, tPHL 4.5 11 28 35 42 ns
to (A > B) OUT, (A < B) OUT
6 24 30 36
2 120 150 180
(3)
tPLH, tPHL (A > B) IN to (A = B) OUT 4.5 9 24 30 36 ns
6 20 26 31
CPD Power dissipation capacitance(1) (2) 5 24 pF
2 75 95 110
tTLH, tTHL Output transition times (Figure 6-1) 4.5 15 19 22 ns
6 13 16 19
CIN Input capacitance 10 10 10 pF
HCT TYPES
Propagation delay, (3)
tPLH, tPHL 4.5 15 37 46 56 ns
An, Bn to (A > B) OUT, (A < B) OUT
(3)
tPLH, tPHL An, Bn to (A = B) OUT 4.5 17 40 50 60 ns
(A > B) IN, (A < B) IN, (A = B) IN (3)
tPLH tPHL 4.5 12 30 38 45 ns
to (A > B) OUT, (A < B) OUT
(3)
tPLH, tPHL (A > B) IN to (A = B) OUT 4.5 13 31 39 47 ns
tTLH, tTHL Output transition times (Figure 6-1) 4.5 15 19 22 ns
CPD Power dissipation capacitance(1) (2) 5 26 pF
CIN Input capacitance 10 10 10 pF

(1) CPD is used to determine the dynamic power consumption, per gate/package.
(2) PD = VCC 2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
(3) CL = 15 pF and VCC = 5 V.

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6 Parameter Measurement Information

Figure 6-1. HC and HCU Transition Times and

Figure 6-2. HCT Transition Times and Propagation
Propagation Delay Times, Combination Logic
Delay Times, Combination Logic

Figure 6-3. Series Cascading - Comparing 12-Bit Words

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Figure 6-4. Parallel Cascading - Comparing 12-Bit Words

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7 Detailed Description
7.1 Overview
The ’HC85 and ’HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to
achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated
circuits.
These 4-bit devices compare two binary, BCD, or other monotonic codes and present the three possible
magnitude results at the outputs (A > B, A < B, and A = B). The 4-bit input words are weighted (A0 to A3
and B0 to B3), where A3 and B3 are the most significant bits.
The devices are expandable without external gating, in both serial and parallel fashion. The upper part of the
truth table indicates operation using a single device or devices in a serially expanded application. The parallel
expansion scheme is described by the last three entries in the truth table.
7.2 Functional Block Diagram

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7.3 Device Functional Modes

Table 7-1. Truth Table(1)
COMPARING INPUTS CASCADING INPUTS OUTPUTS
A3, B3 A2, B2 A1, B1 A0, B0 A>B A<B A=B A>B A<B A=B
SINGLE DEVICE OR SERIES CASCADING
A3 > B3 X X X X X X H L L
A3 < B3 X X X X X X L H L
A3 = B3 A2 >B2 X X X X X H L L
A3 = B3 A2 < B2 X X X X X L H L
A3 = B3 A2 = B2 A1 > B1 X X X X H L L
A3 = B3 A2 = B2 A1 < B1 X X X X L H L
A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L
A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H
PARALLEL CASCADING
A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H
A3 = B3 A2 = B2 A1 = B1 A0 = B0 H H L L L L
A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L L H H L

(1) H = high voltage level, L = low voltage level, X = don’t care

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8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8867201EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8867201EA Samples
& Green CD54HCT85F3A
8601301EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8601301EA Samples
& Green CD54HC85F3A
CD54HC85F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8601301EA Samples
& Green CD54HC85F3A
CD54HCT85F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8867201EA Samples
& Green CD54HCT85F3A
CD74HC85E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC85E Samples

CD74HC85EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC85E Samples

CD74HC85M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC85M Samples

CD74HC85NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC85M Samples

CD74HC85PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HJ85 Samples

CD74HCT85E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT85E Samples

CD74HCT85M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT85M Samples

CD74HCT85MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT85M Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2023

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC85, CD54HCT85, CD74HC85, CD74HCT85 :

• Catalog : CD74HC85, CD74HCT85

• Military : CD54HC85, CD54HCT85

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC85M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC85M96 SOIC D 16 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
CD74HC85NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC85NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC85PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC85PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC85PWR TSSOP PW 16 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC85M96 SOIC D 16 2500 356.0 356.0 35.0
CD74HC85M96 SOIC D 16 2500 366.0 364.0 50.0
CD74HC85NSR SO NS 16 2000 356.0 356.0 35.0
CD74HC85NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC85PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC85PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC85PWR TSSOP PW 16 2000 366.0 364.0 50.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

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TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC85E N PDIP 16 25 506 13.97 11230 4.32
CD74HC85E N PDIP 16 25 506 13.97 11230 4.32
CD74HC85EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC85EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HCT85E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT85E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT85M D SOIC 16 40 507 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

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 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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