a Low Cost ␮P

Supervisory Circuits
ADM705/ADM706/ADM707/ADM708
FEATURES FUNCTIONAL BLOCK DIAGRAMS
Guaranteed RESET Valid with VCC = 1 V
190 ␮A Quiescent Current
Precision Supply-Voltage Monitor
WATCHDOG
WATCHDOG WATCHDOG
4.65 V (ADM705/ADM707) INPUT (WDI) TRANSITION
TIMER WATCHDOG
DETECTOR OUTPUT (WDO)
4.40 V (ADM706/ADM708)
200 ms Reset Pulsewidth VCC RESET AND
Debounced TTL/CMOS Manual Reset Input (MR) WATCHDOG
TIMEBASE
Independent Watchdog Timer—1.6 sec Timeout 250␮A
(ADM705/ADM706)
MR RESET
Active High Reset Output (ADM707/ADM708) GENERATOR
RESET
Voltage Monitor for Power-Fail or Low Battery VCC
Warning 4.65V*
Superior Upgrade for MAX705–MAX708 ADM705/
POWER-FAIL ADM706
INPUT (PFI) POWER-FAIL
APPLICATIONS 1.25V OUTPUT (PFO)
Microprocessor Systems
Computers *VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)

Controllers
Intelligent Instruments
VCC
Critical ␮P Monitoring
Automotive Systems 250␮A RESET
Critical ␮P Power Monitoring MR RESET RESET
GENERATOR
VCC
4.65V* ADM707/
GENERAL DESCRIPTION POWER-FAIL ADM708
The ADM705/ADM706/ADM707/ADM708 are low cost µP INPUT (PFI) POWER-FAIL
OUTPUT (PFO)
1.25V
supervisory circuits. They are suitable for monitoring the 5 V power
supply/battery and can also monitor microprocessor activity. *VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)

The ADM705/ADM706 provide the following functions:

1. Power-on reset output during power-up, power-down, and
brownout conditions. The RESET output remains operational Two supply-voltage monitor levels are available. The ADM705/
with VCC as low as 1 V. ADM707 generate a reset when the supply voltage falls below
2. Independent watchdog timeout, WDO, that goes low if the 4.65 V, while the ADM706/ADM708 require that the supply
watchdog input has not been toggled within 1.6 seconds. fall below 4.40 V before a reset is issued.
3. A 1.25 V threshold detector for power-fail warning, low battery All parts are available in 8-lead DIP and SOIC packages.
detection, or to monitor a power supply other than 5 V.
4. An active low debounced manual reset input (MR).
The ADM707/ADM708 differ in that:
1. A watchdog timer function is not available.
2. An active high reset output in addition to the active low
output is available.

REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
ADM705–ADM708–SPECIFICATIONS (V CC = 4.75 V to 5.5 V, TA = TMIN to TMAX, unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions/Comments

VCC Operating Voltage Range 1.0 5.5 V
Supply Current 190 250 µA
Reset Threshold 4.5 4.65 4.75 V ADM705, ADM707
4.25 4.40 4.50 V ADM706, ADM708
Reset Threshold Hysteresis 40 mV
Reset Pulsewidth 160 200 280 ms
RESET Output Voltage VCC – 1.5 V ISOURCE = 800 µA
0.4 V ISINK = 3.2 mA
0.3 V VCC = 1 V, ISINK = 50 µA
0.3 V VCC = 1.2 V, ISINK = 100 µA
RESET Output Voltage VCC – 1.5 V ADM707, ADM708, ISOURCE = 800 µA
0.4 V ADM707, ADM708, ISINK = 1.2 mA
Watchdog Timeout Period (tWD) 1.00 1.60 2.25 sec
WDI Pulsewidth (tWP) 50 ns VIL = 0.4 V, VIH = VCC × 0.8
WDI Input Threshold
Logic Low 0.8 V
Logic High 3.5 V
WDI Input Current 50 150 µA WDI = VCC
–150 –50 µA WDI = 0 V
WDO Output Voltage VCC – 1.5 V ISOURCE = 800 µA
0.4 V ISINK = 1.2 mA
MR Pull-Up Current 100 250 600 µA MR = 0 V
MR Pulsewidth 150 ns
MR Input Threshold 0.8 V
2.0 V
MR to Reset Output Delay 250 ns
PFI Input Threshold 1.2 1.25 1.3 V
PFI Input Current –25 +0.01 +25 nA
PFO Output Voltage VCC – 1.5 V ISOURCE = 800 µA
0.4 V ISINK = 3.2 mA
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE

(TA = 25°C, unless otherwise noted.)
Model Temperature Range Package Option
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V ADM705AN –40°C to +85°C N-8
Input Current ADM705AR –40°C to +85°C SO-8
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA ADM706AN –40°C to +85°C N-8
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA ADM706AR –40°C to +85°C SO-8
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA ADM707AN –40°C to +85°C N-8
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . 727 mW ADM707AR –40°C to +85°C SO-8
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
ADM708AN –40°C to +85°C N-8
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . 470 mW
ADM708AR –40°C to +85°C SO-8
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.

–2– REV. C
 ADM705–ADM708
PIN FUNCTION DESCRIPTIONS

Pin Number
ADM705 ADM707
ADM706 ADM708
Mnemonic DIP, SOIC DIP, SPOC Function
MR 1 1 Manual Reset Input. When taken below 0.8 V, a RESET is gener-
ated. MR can be driven from TTL, CMOS logic, or from a manual
reset switch as it is internally debounced. An internal 250 µA pull-up
current holds the input high when floating.
VCC 2 2 5 V Power Supply Input
GND 3 3 0 V. Ground reference for all signals
PFI 4 4 Power-Fail Input. PFI is the noninverting input to the power-fail
comparator. When PFI is less than 1.25 V, PFO goes low. If unused,
PFI should be connected to GND or VCC.
PFO 5 5 Power-Fail Output. PFO is the output from the power-fail comparator.
It goes low when PFI is less than 1.25 V.
WDI 6 N/A Watchdog Input. WDI is a three-level input. If WDI remains either high
or low for longer than the watchdog timeout period, the watchdog output
WDO goes low. The timer resets with each transition at the WDI input.
Either a high-to-low or a low-to-high transition will clear the counter.
The internal timer is also cleared whenever reset is asserted. The
watchdog timer is disabled when WDI is left floating or connected to
a three-state buffer.
NC N/A 6 No Connect
RESET 7 7 Logic Output. RESET goes low for 200 ms when triggered. It can be
triggered either by VCC being below the reset threshold or by a low
signal on the manual reset (MR) input. RESET will remain low
whenever VCC is below the reset threshold (4.65 V in ADM705, 4.4 V
in ADM706). It remains low for 200 ms after VCC goes above the
reset threshold or MR goes from low to high. A watchdog timeout
will not trigger RESET unless WDO is connected to MR.
WDO 8 N/A Logic Output. The Watchdog Output, WDO, goes low if the internal
watchdog timer times out as a result of inactivity on the WDI input. It
remains low until the watchdog timer is cleared. WDO also goes low
during low line conditions. Whenever VCC is below the reset threshold,
WDO remains low. As soon as VCC goes above the reset threshold,
WDO goes high immediately.
RESET N/A 8 Logic Output. RESET is an active high output suitable for systems
that use active high RESET logic. It is the inverse of RESET.

PIN CONFIGURATIONS

DIP, SOIC DIP, SOIC

MR 1 8 WDO MR 1 8 RESET
VCC 2 ADM705/ 7 RESET VCC 2 ADM707/ 7 RESET
ADM706 ADM708
GND 3 TOP VIEW 6 WDI GND 3 TOP VIEW 6 NC
(Not to Scale) (Not to Scale)
PFI 4 5 PFO PFI 4 5 PFO

NC = NO CONNECT

REV. C –3–
ADM705–ADM708
VCC VRT VRT
WATCHDOG WATCHDOG
WATCHDOG
INPUT (WDI) TRANSITION WATCHDOG
TIMER OUTPUT (WDO)
DETECTOR tRS tRS

VCC RESET
RESET AND
WATCHDOG
TIMEBASE
250␮A
MR MR EXTERNALLY
MR DRIVEN LOW
RESET RESET
GENERATOR
VCC
WDO
4.65V*
ADM705/
POWER-FAIL ADM706
INPUT (PFI) POWER-FAIL Figure 3. RESET, MR, and WDO Timing
OUTPUT (PFO)
1.25V
Watchdog Timer (ADM705/ADM706)
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706) The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in an
Figure 1. ADM705/ADM706 Functional Block Diagram indefinite loop. An output line on the processor is used to toggle
the Watchdog Input (WDI) line. If this line is not toggled
VCC within the timeout period (1.6 sec), the watchdog output
250␮A RESET
(WDO) goes low. The WDO output may be connected to a
MR
nonmaskable interrupt (NMI) on the processor; therefore, if the
RESET RESET watchdog timer times out, an interrupt is generated. The inter-
GENERATOR
VCC rupt service routine should then be used to rectify the problem.
4.65V* ADM707/ If a RESET signal is required when a timeout occurs, the WDO
ADM708
POWER-FAIL
POWER-FAIL
output should be connected to the manual reset input (MR).
INPUT (PFI)
OUTPUT (PFO)
1.25V The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. It is also cleared by RESET
*VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
going low; therefore, the watchdog timeout period begins after
RESET goes high.
Figure 2. ADM707/ADM708 Functional Block Diagram
When VCC falls below the reset threshold, WDO is forced low
CIRCUIT INFORMATION whether or not the watchdog timer has timed out. Normally,
Power-Fail RESET Output this would generate an interrupt, but it is overridden by RESET
RESET is an active low output that provides a RESET signal to going low.
the microprocessor whenever the VCC input is below the reset The watchdog monitor can be deactivated by floating the
threshold. An internal timer holds RESET low for 200 ms after Watchdog Input (WDI). The WDO output can now be used as
the voltage on VCC rises above the threshold. This is intended as a low line output since it will only go low when VCC falls below
a power-on RESET signal for the microprocessor. It allows time the reset threshold.
for both the power supply and the microprocessor to stabilize
after power-up. The RESET output is guaranteed to remain tWP tWD tWD tWD
valid (low) with VCC as low as 1 V. This ensures that the micro-
WDI
processor is held in a stable shutdown condition as the power
supply voltage ramps up.
WDO
In addition to RESET, an active high RESET output is also
available on the ADM707/ADM708. This is the complement of
RESET and is useful for processors requiring an active high RESET RESET EXTERNALLY
TRIGGERED BY MR
RESET signal. tRS
Manual Reset (ADM707/ADM708)
Figure 4. Watchdog Timing
The manual reset input (MR) allows other reset sources, such as
a manual reset switch, to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible, so it may also be
driven by any logic reset output.

–4– REV. C
 ADM705–ADM708
Power-Fail Comparator
The power-fail comparator is an independent comparator that  R2 + R 3 
may be used to monitor the input power supply. The comparator’s [
VH = 1.25 1 +   R1]
 R2 × R 3 
inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.  1.25 VCC – 1.25 
VL = 1.25 + R1  – 
This input may be used to monitor the input power supply via  R2 RE 
a resistive divider network. When the voltage on the PFI input
 R1 + R2 
drops below 1.25 V, the comparator output (PFO) goes low, VMID = 1.25  
indicating a power failure. For early warning of power failure,  R2 
the comparator may be used to monitor the preregulator input
simply by choosing an appropriate resistive divider network. Valid RESET Below 1 V VCC
The PFO output can be used to interrupt the processor so that The ADM70x family of products is guaranteed to provide a
a shutdown procedure is implemented before the power is lost. valid reset level with VCC as low as 1 V; please refer to the Typi-
cal Performance Characteristics. As VCC drops below 1 V, the
INPUT
POWER
internal transistor will not have sufficient drive to hold it ON so
R1 1.25V – PFO
the voltage on RESET will no longer be held at 0 V. A pull-down
POWER-FAIL
+ OUTPUT
resistor as shown in Figure 7 may be connected externally to
POWER-FAIL PFI hold the line low if it is required.
R2 INPUT ADM70x

ADM70x
Figure 5. Power-Fail Comparator
Adding Hysteresis to the Power-Fail Comparator RESET

For increased noise immunity, hysteresis may be added to the GND R1

power-fail comparator. Since the comparator circuit is noninvert-
ing, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure 6. Figure 7. RESET Valid Below 1 V
When PFO is low, Resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, Resistor R3 sources
current into the PFI summing junction. This results in differing
trip levels for the comparator. Further noise immunity may be
achieved by connecting a capacitor between PFI and GND.

7V TO 15V 5V
ADM663
INPUT POWER

VCC
R1
1.25V – PFO
TO ␮P NMI
+
PFI
R2 ADM70x

R3

5V

PFO

0V
0V VL VH
VIN

Figure 6. Adding Hysteresis to the Power-Fail Comparator

REV. C –5–
ADM705–ADM708–Typical Performance Characteristics

VCC = 5V
TA = 25ⴗC
A! 4.50V 1.3V

VCC 100 PFI

90
1.2V

4.4V

10
0%
PFO
RESET
1V 1V 500msHo
0V

500ns/DIV

TPC 1. RESET Output Voltage vs. Supply Voltage TPC 4. PFI Comparator Deassertion Response Time

VCC = VRT
TA = 25ⴗC 5V
A1 4.50V
RESET
VCC 100 5V
90
RESET RESET

10
0%

0V
1V 1V 500msHo

0V

100ns/DIV

TPC 2. ADM707/ADM708 RESET Output Voltage vs. TPC 5. RESET, RESET Assertion
Supply Voltage

VCC = 5V VCC = VRT

5V
TA = 25ⴗC TA = 25ⴗC
RESET
1.3V 5V
PFI RESET
1.2V

5V

PFO
0V

0V 0V

500ns/DIV 100ns/DIV

TPC 3. PFI Comparator Assertion Response Time TPC 6. RESET, RESET Deassertion

–6– REV. C
 ADM705–ADM708
TA = 25ⴗC RESET RESET
5V ADM705/ ␮P
VCC ADM706
5V 4V WDI I/O LINE
MR WDO
GND

RESET Figure 9. RESET from WDO

Monitoring Additional Supply Levels
It is possible to use the power-fail comparator to monitor a
0V second supply as shown in Figure 10. The two sensing resistors,
R1 and R2, are selected so that the voltage on PFI drops below
2␮s/DIV
1.25 V at the minimum acceptable input supply. The PFO
output may be connected to the MR input so that a RESET is
TPC 7. ADM705/ADM707 RESET Response Time generated when the supply drops out of tolerance. In this case, if
either supply drops out of tolerance, a RESET will be generated.

VX 5V

VCC
APPLICATIONS RESET RESET
A typical operating circuit is shown in Figure 8. The unregulated ADM705/
R1 ␮P
dc input supply is monitored using the PFI input via the resistive ADM706
PFI
divider network. Resistors R1 and R2 should be selected so that
MR PFO
when the supply voltage drops below the desired level (e.g., 8 V), R2
GND
the voltage on PFI drops below the 1.25 V threshold thereby
generating an interrupt to the µP. Monitoring the preregulator
input gives additional time to execute an orderly shutdown Figure 10. Monitoring 5 V and an Additional Supply, VX
procedure before power is lost. ␮Ps with Bidirectional RESET
In order to prevent contention for microprocessors with
ADM666 5V
a bidirectional reset line, a Current Limiting Resistor should
UNREGULATED
IN GND OUT be inserted between the ADM70x RESET output pin and the
DC µP reset pin. This will limit the current to a safe level if there are
conflicting output reset levels. A suitable resistor value is 4.7 kΩ.
VCC RESET RESET VCC
If the reset output is required for other uses, it should be buffered
WDI I/O LINE
as shown in Figure 11.
R1 ADM705/
␮P
ADM706
PFI WDO NMI 5V BUFFERED
MR PFO INTERRUPT RESET
R2 GND
VCC
MANUAL
RESET ADM70x ␮P
RESET RESET

Figure 8. Typical Application Circuit GND GND

Microprocessor activity is monitored using the WDI input. This

is driven using an output line from the processor. The software Figure 11. Bidirectional I-O RESET
routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled, WDO goes low
and a nonmaskable interrupt is generated. This interrupt routine
may be used to clear the problem.
If, in the event of inactivity on the WDI line, a system reset is
required, the WDO output should be connected to the MR
input as shown in Figure 9.

REV. C –7–
ADM705–ADM708
OUTLINE DIMENSIONS
8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
Dimensions shown in millimeters and (inches)

10.92 (0.4299)
8.84 (0.3480)

C00088–0–8/02 (C)
8 5
7.11 (0.2799)
6.10 (0.2402)
1 4

PIN 1 8.25 (0.3248)

2.54 (0.1000) 7.62 (0.3000)
BSC

5.33 1.52 (0.0598) 4.95 (0.1949)

(0.2098) 0.38 (0.0150) 2.93 (0.1154)
MAX
( 3.30
4.06 (0.1598) (0.1299) 0.38 (0.0150)
2.93 (0.1154) MIN 0.20 (0.0079)
0.56 (0.0220) SEATING
1.77 (0.0697) PLANE
0.36 (0.0142)
1.15 (0.0453)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

8-Lead Small Outline Package [SOIC]

(R-8)
Dimensions shown in millimeters and (inches)

5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2440)
3.80 (0.1497) 1 4 5.80 (0.2284)

PIN 1
1.27 (0.0500) 0.50 (0.0196)
1.75 (0.0688) ⴛ 45ⴗ
BSC 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
0.10 (0.0040)
0.51 (0.0201) 8ⴗ
COPLANARITY 0.33 (0.0130) 0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.10 SEATING 0.41 (0.0160)
PLANE 0.19 (0.0075)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA

PRINTED IN U.S.A.

Revision History
Location Page
8/02—Data Sheet changed from REV. B to REV. C.
Removed RM-8 (µSOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Updated N-8 and R-8 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

–8– REV. C