NOT RECOMMENDED FOR NEW DESIGNS

DATASHEET
RECOMMENDED REPLACEMENT PART
ISL8014A
ISL8014 FN6576
4A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator Rev 4.00
November 23, 2009

The ISL8014 is a high efficiency, monolithic, Features

synchronous step-down DC/DC converter that can
deliver up to 4A continuous output current from a 2.7V • High Efficiency Synchronous Buck Regulator with
to 5.5V input supply. It uses a current control up to 97% Efficiency
architecture to deliver very low duty cycle operation at • Power-Good (PG) Output with a 1ms Delay
high frequency with fast transient response and • 2.7V to 5.5V Supply Voltage
excellent loop stability.
• 3% Output Accuracy Over-Temperature/Load/Line
The ISL8014 integrates a pair of low ON-resistance • 4A Output Current
P-Channel and N-Channel internal MOSFETs to
• Pin Compatible to ISL8013
maximize efficiency and minimize external component
count. The 100% duty-cycle operation allows less than • Start-up with Pre-Biased Output
400mV dropout voltage at 4A output current. High • Internal Soft-Start - 1ms
1MHz pulse-width modulation (PWM) switching • Soft-Stop Output Discharge During Disabled
frequency allows the use of small external components • 35µA Quiescent Supply Current in PFM Mode
and SYNC input enables multiple ICs to synchronize
• Selectable Forced PWM Mode and PFM Mode
out of phase to reduce ripple and eliminate beat
frequencies. • External Synchronization up to 4MHz
• Less than 1µA Logic Controlled Shutdown Current
The ISL8014 can be configured for discontinuous or
forced continuous operation at light load. Forced • 100% Maximum Duty Cycle
continuous operation reduces noise and RF • Internal Current Mode Compensation
interference while discontinuous mode provides high • Peak Current Limiting and Hiccup Mode Short
efficiency by reducing switching losses at light loads. Circuit Protection
Fault protection is provided by internal hiccup mode • Over-Temperature Protection
current limiting during short circuit and overcurrent • Small 16 Ld 4mmx4mm QFN
conditions, an output over voltage comparator and • Pb-Free (RoHS Compliant)
over-temperature monitor circuit. A power good output
voltage monitor indicates when the output is in
regulation.
Applications
• DC/DC POL Modules
The ISL8014 is offered in a space saving 4x4 QFN lead
• µC/µP, FPGA and DSP Power
free package with exposed pad lead frames for low
thermal. • Plug-in DC/DC Modules for Routers and Switchers
• Portable Instruments
The ISL8014 offers a 1ms Power-Good (PG) timer at
power-up. When shutdown, ISL8014 discharges the • Test and Measurement Systems
output capacitor. Other features include internal • Li-ion Battery Powered Devices
soft-start, internal compensation, overcurrent • Small Form Factor (SFP) Modules
protection, and thermal shutdown. • Bar Code Readers
The ISL8014 is offered in a 16 Ld 4mmx4mm QFN
package with 1mm maximum height. The complete
converter occupies less than 0.4in2 area.

FN6576 Rev 4.00 Page 1 of 17

November 23, 2009
ISL8014

Ordering Information
TEMP.
PART NUMBER PART RANGE PACKAGE PKG.
(Notes 1, 2, 3) MARKING (°C) (Pb-Free) DWG. #

ISL8014IRZ 80 14IRZ -40 to +85 16 Ld 4x4 QFN L16.4x4

NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8014. For more information on MSL please see
techbrief TB363.

Pin Configuration
ISL8014
(16 LD QFN)
NC TOP VIEW

NC
LX

LX
16 15 14 13

VIN 1 12 PGND

VIN 2 11 PGND

VDD 3 10 SGND

SYNCH 4 9 SGND

5 6 7 8
VFB
EN

NC

PG

Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION

1, 2 VIN Input supply voltage. Connect a 10µF ceramic capacitor to power ground.
3 VDD Input supply voltage for the analog circuitry. Connect to VIN pin.

5 EN Regulator enable pin. Keep the EN voltage low in disabled state until VIN settles or is
above 2.5V. Enable the output when driven to high. Shut down the chip and discharge
output capacitor when driven to low. Do not connect directly to VIN or leave this pin
floating.

7 PG 1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal
for the output voltage.

4 SYNCH Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect
to logic low or ground for PFM mode. Connect to an external function generator for
synchronization with the negative edge trigger. Do not leave this pin floating.

14, 15 LX Switching node connection. Connect to one terminal of the inductor.

11, 12 PGND Power ground

9, 10 SGND Signal ground.

8 VFB Buck regulator output feedback. Connect to the output through a resistor divider for
adjustable output voltage. For 0.8V output voltage, connect this pin to the output.

6, 13, 16 NC No connect.

- Exposed Pad The exposed pad must be connected to the SGND pin for proper electrical performance.
Place as much vias as possible under the pad connecting to SGND plane for optimal
thermal performance.

FN6576 Rev 4.00 Page 2 of 17

November 23, 2009
ISL8014

Typical Application

L OUTPUT
INPUT 2.7V TO 5.5V 1.5µH 1.8V
VIN LX
C2
2 x 22µF
C1 VDD C3
2 x 22µF PGND R2 47pF
124k
R1
100k ISL8014

PG
VFB

R3
EN 100k

SYNCH SGND

FIGURE 1. TYPICAL APPLICATION DIAGRAM

Block Diagram
SYNCH

SOFT
Soft 27pF SHUTDOWN
START
SHUTDOWN
390k
-
EN OSCILLATOR VIN
BANDGAP 0.8V
+
+
EAMP
COMP PWM/PFM
- - LOGIC
CONTROLLER LX
3pF PROTECTION
DRIVER
+
PGND
VFB

SLOPE
Slope
6k
COMP +
CSA
-
+
OCP
- 1.4V
+
0.736V -
+
SKIP 0.5V
-
PG
1ms
DELAY ZERO-CROSS
SGND SENSING

-
SCP
0.2V
+

FIGURE 2. FUNCTIONAL BLOCK DIAGRAM

FN6576 Rev 4.00 Page 3 of 17

November 23, 2009
ISL8014

Absolute Maximum Ratings (Reference to GND) Thermal Information

VIN, VDD . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms) Thermal Resistance (Typical, Notes 4, 5)JA (°C/W)JC (°C/W)
EN, SYNCH, PG . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V 16 Ld 4x4 QFN Package . . . . . . . 39 3
LX . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms) Junction Temperature Range . . . . . . . . . . -55°C to +125°C
VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
Recommended Operating Conditions http://www.intersil.com/pbfree/Pb-FreeReflow.asp
VIN Supply Voltage Range . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.

NOTE:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended
operating conditions and the typical specification are measured at the following conditions:
TA = -40°C to +85°C, VIN = 3.6V, EN = VDD, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS

INPUT SUPPLY

VDD Undervoltage Lockout VUVLO Rising, no load - 2.5 2.7 V

Threshold
Falling, no load 2.2 2.4 - V

Quiescent Supply Current IVIN SYNCH = GND, no load at the output - 35 - µA

SYNCH = GND, no load at the output - 30 45 µA

and no switches switching

SYNCH = VDD, FS = 1MHz, no load at - 6.5 10 mA

the output

Shut Down Supply Current ISD VIN = 5.5V, EN = low - 0.1 2 µA

OUTPUT REGULATION

Reference Voltage VREF 0.790 0.8 0.810 V

VFB Bias Current IVFB VFB = 0.75V - 0.1 - µA

Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) - 0.2 - %/V

Soft-Start Ramp Time Cycle - 1 - ms

OVERCURRENT PROTECTION

Current Limit Blanking Time tOCON - 17 - Clock pulses

Overcurrent and Auto Restart tOCOFF - 4 - SS cycle

Period

Switch Current Limit ILIMIT (Note 6) 4.9 6.0 7.1 A

Peak Skip Limit ISKIP (Note 6) - 1.3 - A

COMPENSATION

Error Amplifier - 20 - µA/V

Trans-Conductance

Trans-Resistance RT 0.17 0.20 0.23 

FN6576 Rev 4.00 Page 4 of 17

November 23, 2009
ISL8014

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended
operating conditions and the typical specification are measured at the following conditions:
TA = -40°C to +85°C, VIN = 3.6V, EN = VDD, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS

LX

P-Channel MOSFET VIN = 5V, IO = 200mA - 50 75 m

ON-Resistance
VIN = 2.7V, IO = 200mA - 70 100 m

N-Channel MOSFET VIN = 5V, IO = 200mA - 50 75 m

ON-Resistance
VIN = 2.7V, IO = 200mA - 70 100 m

LX Maximum Duty Cycle - 100 - 

PWM Switching Frequency fS 0.80 1.0 1.20 MHz

LX Minimum On-Time SYNCH = High - - 140 ns

PG

Output Low Voltage Sinking 1mA - - 0.3 V

Delay Time (Rising Edge) 0.65 1 1.35 ms

PG Pin Leakage Current PG = VIN = 3.6V - 0.01 0.1 µA

PGOOD Rising Threshold Percentage of regulation voltage 89 92 95 %

PGOOD Falling Threshold Percentage of regulation voltage 85 88 91 %

PGOOD Delay Time (Falling Edge) - 15 - µs

EN, SYNCH

Logic Input Low - - 0.4 V

Logic Input High 1.4 - - V

Synch Logic Input Leakage ISYNCH Pulled up to 5.5V - 0.1 1 µA

Current

Enable Logic Input Leakage IEN - 0.1 1 µA

Current

Thermal Shutdown - 140 - °C

Thermal Shutdown Hysteresis - 25 - °C

NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.

FN6576 Rev 4.00 Page 5 of 17

November 23, 2009
ISL8014

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A).

100 100

90 90
EFFICIENCY (%)

EFFICIENCY (%)
2.5VOUT-PWM 2.5VOUT-PFM
80 80
1.8VOUT-PWM 1.8VOUT-PFM 1.5VOUT-PFM1.2VOUT-PFM
1.5VOUT-PWM
70 70
1.2VOUT-PWM
60 60

50 50

40 40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)

100 100

90 90
EFFICIENCY (%)
EFFICIENCY (%)

80 2.5VOUT-PWM 80
1.8VOUT-PWM 1.5VOUT-PWM 1.2VOUT-PFM
1.5VOUT-PFM
70 3.3VOUT-PWM 70 2.5VOUT-PFM 1.8VOUT-PFM
1.2VOUT-PWM
3.3VOUT-PFM
60 60

50 50

40 40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD (1MHz 5VIN PWM) FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PFM)

2.00 125
POWER DISSIPATION (W)

3.3VIN-PWM
POWER DISSIPATION (mW)

1.75

1.50 100

1.25
5VIN-PFM 75
1.00

0.75 50
3.3VIN-PFM
0.50 5VIN-PWM
25
0.25

0.00 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT LOAD (A) VIN (V)

FIGURE 7. POWER DISSIPATION vs LOAD (1MHz, FIGURE 8. POWER DISSIPATION WITH NO LOAD vs
VOUT = 1.8V) VIN (PWM VOUT = 1.8V)

FN6576 Rev 4.00 Page 6 of 17

November 23, 2009
ISL8014

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)

0.25 1.24
POWER DISSIPATION (mW)

1.23

OUTPUT VOLTAGE (V)

0.20
1.22 3.3V 3.3VIN-PWM
IN-PFM

0.15 1.21

1.20
0.10 1.19
5VIN-PWM
1.18 5VIN-PFM
0.05
1.17

0 1.16
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VIN (V) OUTPUT LOAD (A)

FIGURE 9. POWER DISSIPATION WITH NO LOAD vs FIGURE 10. VOUT REGULATION vs LOAD (1MHz,
VIN (PFM VOUT = 1.8V) VOUT = 1.2V)

1.55 1.83
1.54 1.82 3.3V
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

3.3VIN-PFM 3.3VIN-PWM IN-PFM

1.53 3.3VIN-PWM
1.81
1.52 1.80
1.51 1.79
1.50 5VIN-PWM 1.78
5VIN-PFM 5VIN-PWM
1.49 1.77
5VIN-PFM
1.48 1.76
1.47 1.75
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD (1MHz, FIGURE 12. VOUT REGULATION vs LOAD (1MHz,
VOUT = 1.5V) VOUT = 1.8V)

2.52 3.36

2.51 3.35 4.5VIN-PWM

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

3.3VIN-PFM 5VIN-PWM
3.3VIN-PWM
2.50 3.34

2.49 3.33

2.48 3.32

2.47 5VIN-PWM 3.31

4.5VIN-PFM
2.46 3.30 5VIN-PFM

2.45 5VIN-PFM 3.29

2.44 3.28
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, FIGURE 14. VOUT REGULATION vs LOAD (1MHz,
VOUT = 2.5V) VOUT = 3.3V)

FN6576 Rev 4.00 Page 7 of 17

November 23, 2009
 ISL8014

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)

1.830 1.830

1.820 1.820

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

4A LOAD PWM 0A LOAD PWM 4A LOAD

1.810 1.810
0A LOAD
1.800 1.800

1.790 1.790

1.780 1.780

1.770 1.770

1.760 1.760

1.750 1.750
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN FIGURE 16. OUTPUT VOLTAGE REGULATION vs VIN
(PWM VOUT = 1.8 ) (PFM VOUT = 1.8V)

LX 2V/DIV LX 2V/DIV

VOUT RIPPLE 20mV/DIV

VOUT RIPPLE 20mV/DIV

IL 0.5A/DIV
IL 0.5A/DIV

FIGURE 17. STEADY STATE OPERATION AT NO LOAD FIGURE 18. STEADY STATE OPERATION AT NO LOAD
(PWM) (PFM)

LX 2V/DIV

LX 2V/DIV
VOUT RIPPLE 50mV/DIV

IL 2A/DIV

IL 1A/DIV
VOUT RIPPLE 20mV/DIV

FIGURE 19. STEADY STATE OPERATION WITH FULL FIGURE 20. MODE TRANSITION CCM TO DCM
LOAD

FN6576 Rev 4.00 Page 8 of 17

November 23, 2009
ISL8014

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)

LX 2V/DIV VOUT RIPPLE 50mV/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

IL 1A/DIV

FIGURE 21. MODE TRANSITION DCM TO CCM FIGURE 22. LOAD TRANSIENT (PWM)

LX 2V/DIV
EN 5V/DIV

VOUT 0.5V/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV

IL 1A/DIV
PG 5V/DIV

FIGURE 23. LOAD TRANSIENT (PFM) FIGURE 24. SOFT-START WITH NO LOAD (PWM)

EN 5V/DIV EN 5V/DIV

VOUT 0.5V/DIV

VOUT 0.5V/DIV IL 1A/DIV

IL 1A/DIV

PG 5V/DIV

PG 5V/DIV

FIGURE 25. SOFT-START AT NO LOAD (PFM) FIGURE 26. SOFT-START WITH PRE-BIASED 1V

FN6576 Rev 4.00 Page 9 of 17

November 23, 2009
ISL8014

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)

EN 2V/DIV

EN 5V/DIV

VOUT 0.5V/DIV
VOUT 0.5V/DIV
IL 2A/DIV

PG 5V/DIV IL 1A/DIV

PG 5V/DIV

FIGURE 27. SOFT-START AT FULL LOAD FIGURE 28. SOFT-DISCHARGE SHUTDOWN

LX 2V/DIV

LX 2V/DIV

IL 1A/DIV

SYNCH 2V/DIV
SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

VOUT RIPPLE 20mV/DIV
IL 1A/DIV

FIGURE 30. STEADY STATE OPERATION AT FULL

FIGURE 29. STEADY STATE OPERATION AT NO LOAD
LOAD WITH FREQUENCY = 2MHz
WITH FREQUENCY = 2MHz

LX 2V/DIV
LX 2V/DIV

IL 1A/DIV
SYNCH 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 0.5A/DIV VOUT RIPPLE 20mV/DIV

FIGURE 31. STEADY STATE OPERATION AT NO LOAD FIGURE 32. STEADY STATE OPERATION AT FULL
WITH FREQUENCY = 4MHz LOAD (PWM) WITH FREQUENCY = 4MHz

FN6576 Rev 4.00 Page 10 of 17

November 23, 2009
ISL8014

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,
C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 4A). (Continued)

LX 2V/DIV

LX 2V/DIV

VOUT 1V/DIV
IL 2A/DIV
VOUT 0.5V/DIV
PG 5V/DIV

PG 5V/DIV IL 2A/DIV

FIGURE 33. OUTPUT SHORT CIRCUIT FIGURE 34. OUTPUT SHORT CIRCUIT RECOVERY

5.500

5.375
OUTPUT CURRENT (A)

5.250 OCP_3.3VIN

5.125

5.000

4.875
OCP_5VIN
4.750

4.625

4.500
-50 -25 0 25 50 75 100
TEMPERATURE (°C)

FIGURE 35. OUTPUT CURRENT LIMIT vs TEMPERATURE

Theory of Operation and the slope compensation for the current loop stability.
The gain for the current sensing circuit is typically
The ISL8014 is a step-down switching regulator
200mV/A. The control reference for the current loops
optimized for battery-powered handheld applications.
comes from the error amplifier's (EAMP) output.
The regulator operates at 1MHz fixed switching
frequency under heavy load conditions to allow smaller The PWM operation is initialized by the clock from the
external inductors and capacitors to be used for minimal oscillator. The P-Channel MOSFET is turned on at the
printed-circuit board (PCB) area. At light load, the beginning of a PWM cycle and the current in the
regulator reduces the switching frequency, unless forced MOSFET starts to ramp up. When the sum of the current
to the fixed frequency, to minimize the switching loss and amplifier CSA and the slope compensation (237mV/µs)
to maximize the battery life. The quiescent current when reaches the control reference of the current loop, the
the output is not loaded is typically only 35µA. The PWM comparator COMP sends a signal to the PWM logic
supply current is typically only 0.1µA when the regulator to turn off the P-MOSFET and turn on the N-Channel
is shut down. MOSFET. The N-MOSFET stays on until the end of the
PWM cycle. Figure 36 shows the typical operating
PWM Control Scheme waveforms during the PWM operation. The dotted lines
Pulling the SYNCH pin HI (>2.5V) forces the converter illustrate the sum of the slope compensation ramp and
into PWM mode, regardless of output current. The the current-sense amplifier’s CSA output.
ISL8014 employs the current-mode pulse-width
modulation (PWM) control scheme for fast transient The output voltage is regulated by controlling the VEAMP
response and pulse-by-pulse current limiting. Figure 2 voltage to the current loop. The bandgap circuit outputs
shows the block diagram. The current loop consists of the a 0.8V reference voltage to the voltage loop. The
oscillator, the PWM comparator, current sensing circuit feedback signal comes from the VFB pin. The soft-start
block only affects the operation during the start-up and

FN6576 Rev 4.00 Page 11 of 17

November 23, 2009
ISL8014

will be discussed separately. The error amplifier is a capacitor. When the output voltage drops to the nominal
transconductance amplifier that converts the voltage voltage, the P-MOSFET will be turned on again at the
error signal to a current output. The voltage loop is rising edge of the internal clock as it repeats the previous
internally compensated with the 27pF and 390k RC operations.
network. The maximum EAMP voltage output is precisely
The regulator resumes normal PWM mode operation
clamped to 1.6V.
when the output voltage drops 1.5% below the nominal
VEAMP voltage.

VCSA Synchronization Control

The frequency of operation can be synchronized up to
DUTY 4MHz by an external signal applied to the SYNCH pin.
CYCLE The falling edge on the SYNCH triggers the rising edge of
the LX pulse. Make sure that the minimum on time of the
IL LX node is greater than 140ns.
Overcurrent Protection
VOUT The overcurrent protection is realized by monitoring the
CSA output with the OCP comparator, as shown in
Figure 2. The current sensing circuit has a gain of
FIGURE 36. PWM OPERATION WAVEFORMS 200mV/A, from the P-MOSFET current to the CSA output.
When the CSA output reaches 1.4V, which is equivalent
SKIP Mode to 5.7A for the switch current, the OCP comparator is
Pulling the SYNCH pin LO (<0.4V) forces the converter tripped to turn off the P-MOSFET immediately. The
into PFM mode. The ISL8014 enters a pulse-skipping overcurrent function protects the switching converter
mode at light load to minimize the switching loss by from a shorted output by monitoring the current flowing
reducing the switching frequency. Figure 37 illustrates through the upper MOSFET.
the skip-mode operation. A zero-cross sensing circuit Upon detection of overcurrent condition, the upper
shown in Figure 2 monitors the N-MOSFET current for MOSFET will be immediately turned off and will not be
zero crossing. When 8 consecutive cycles of the inductor turned on again until the next switching cycle. Upon
current crossing zero are detected, the regulator enters detection of the initial overcurrent condition, the
the skip mode. During the eight detecting cycles, the overcurrent fault counter is set to 1. If, on the
current in the inductor is allowed to become negative. subsequent cycle, another overcurrent condition is
The counter is reset to zero when the current in any cycle detected, the OC fault counter will be incremented. If
does not cross zero. there are 17 sequential OC fault detections, the regulator
Once the skip mode is entered, the pulse modulation will be shut down under an overcurrent fault condition.
starts being controlled by the SKIP comparator shown in An overcurrent fault condition will result in the regulator
Figure 2. Each pulse cycle is still synchronized by the attempting to restart in a hiccup mode within the delay of
PWM clock. The P-MOSFET is turned on at the clock's four soft-start periods. At the end of the fourth soft-start
rising edge and turned off when the output is higher than wait period, the fault counters are reset and soft-start is
1.5% of the nominal regulation or when its current attempted again. If the overcurrent condition goes away
reaches the peak Skip current limit value. Then the during the delay of four soft-start periods, the output will
inductor current is discharging to 0A and stays at zero. resume back into regulation point after hiccup mode
The internal clock is disabled.The output voltage reduces expires.
gradually due to the load current discharging the output
PWM PFM

CLOCK

8 CYCLES PFM CURRENT LIMIT

IL
LOAD CURRENTT
0

NOMINAL +1.5%

VOUT

NOMINAL

FIGURE 37. SKIP MODE OPERATION WAVEFORMS

FN6576 Rev 4.00 Page 12 of 17

November 23, 2009
ISL8014

Short-Circuit Protection
The short-circuit protection SCP comparator monitors the VIN
VFB pin voltage for output short-circuit protection. When

V (VOLTS)
the VFB is lower than 0.2V, the SCP comparator forces
EN
the PWM oscillator frequency to drop to 1/3 of the normal 2.5V
operation value. This comparator is effective during
start-up or an output short-circuit event.
<400mV
PG T t (TIME)
During power-up, the open-drain power good output FIGURE 39. CIRCUIT IMPLEMENTATION WITH VIN
holds low for about 1ms after VOUT reaches the SLEW RATE
regulation voltage. The PG output also serves as a 1ms Let T equal the rise time of VIN. Select the ratio of R5 and
delayed the Power Good signal when the pull-up resistor R4 such that the voltage is 1.4V (minimum enable logic
R1 is installed. high threshold) when VIN is equal to or greater than
2.5V. Set R5 between 10k to 100k, and use Equation 1
Soft Start-Up to determine R4:
The soft-start-up reduces the inrush current during the R 5   V IN – 1.4V 
start-up. The soft-start block outputs a ramp reference to R 4 = --------------------------------------------
- (EQ. 1)
1.4V
the input of the error amplifier. This voltage ramp limits
the inductor current as well as the output voltage speed Where VIN is greater than or equal to 2.5V.
so that the output voltage rises in a controlled fashion.
When VFB is less than 0.2V at the beginning of the Then select C such that the equivalent time constant is at
soft-start, the switching frequency is reduced to 1/3 of least 2x the rise time, T. This will delay the EN voltage
the nominal value so that the output can start up enough so that the overall EN voltage is less than 400mV
smoothly at light load condition. During soft-start, the IC by the time VIN reaches 2.5V. Use Equation 2 to get C:
operates in the SKIP mode to support pre-biased output 2T
C  -------------------- (EQ. 2)
condition. R 4  R 5

UVLO
Where T is the rise time of VIN
When the input voltage is below the undervoltage lock-
out (UVLO) threshold, the regulator is disabled. To adjust As an example, let VIN = 5V with rise time, T = 10ms.
the voltage level of power on and UVLO, use a resistive Then R4 = 56.2k, R5 = 71.5k, and C = 0.68µF are
divider across EN. The input voltage programming used to insure that VIN was >2.5V and the EN voltage
resistor R4 will depend on on the bottom resistor R5, as was <400mV.
referred to in Figure 38. The value of R5 is typically
between 10k and 100k. Discharge Mode (Soft-Stop)
VIN
When a transition to shutdown mode occurs or the VIN
UVLO is set, the outputs discharge to GND through an
internal 100 switch.
R4
+ EN Power MOSFETs
- 1V
C
The power MOSFETs are optimized for best efficiency.
R5
The ON-resistance for the P-MOSFET is typically 50m
and the ON-resistance for the N-MOSFET is typically
50m.
FIGURE 38. EXTERNAL RESISTOR DIVIDER 100% Duty Cycle
The ISL8014 features 100% duty cycle operation to
Enable maximize the battery life. When the battery voltage
The enable (EN) input allows the user to control the drops to a level that the ISL8014 can no longer maintain
turning on or off the regulator for purposes such as the regulation at the output, the regulator completely
power-up sequencing. When the regulator is enabled, turns on the P-MOSFET. The maximum dropout voltage
there is typically a 600µs delay for waking up the under the 100% duty-cycle operation is the product of
bandgap reference and then the soft-start-up begins. It the load current and the ON-resistance of the P-MOSFET.
is recommended that the EN voltage should be kept logic
low (less than 400mV), until VIN reaches 2.5V. Refer to
Figures 38 and 39 for suggested circuit implementation
with VIN slew rate.

FN6576 Rev 4.00 Page 13 of 17

November 23, 2009
ISL8014

Thermal Shut-Down In Table 1, the minimum output capacitor value is given

The ISL8014 has built-in thermal protection. When the for the different output voltage to make sure that the
internal temperature reaches +140°C, the regulator is whole converter system is stable. Additional output
completely shut down. As the temperature drops to capacitance should be added for better performances in
+115°C, the ISL8014 resumes operation by stepping applications where high load transient or low output
through the soft-start. ripple is required. It is recommended to check the
system level performance along with the simulation
Applications Information model.
Output Voltage Selection
Output Inductor and Capacitor Selection
The output voltage of the regulator can be programmed
To consider steady state and transient operations,
via an external resistor divider that is used to scale the
ISL8014 typically uses a 1.5µH output inductor. The
output voltage relative to the internal reference voltage
higher or lower inductor value can be used to optimize
and feed it back to the inverting input of the error
the total converter system performance. For example, for
amplifier. Refer to Figure 1.
higher output voltage 3.3V application, in order to
decrease the inductor current ripple and output voltage The output voltage programming resistor, R3, will depend
ripple, the output inductor value can be increased. It is on the value chosen for the feedback resistor and the
recommended to set the ripple inductor current desired output voltage of the regulator. The value for the
approximately 30% of the maximum output current for feedback resistor is typically between 10k and 100k
optimized performance. The inductor ripple current can as shown in Equation 4.
be expressed as shown in Equation 3: R 2  0.8V
R 3 = ---------------------------------- (EQ. 4)
 VO  V OUT – 0.8V
V O   1 – --------- (EQ. 3)
 V IN If the output voltage desired is 0.8V, then R3 is left
I = -------------------------------------
L  fS unpopulated and R2 is shorted. There is a leakage
current from VIN to LX. It is recommended to preload the
The inductor’s saturation current rating needs to be at output with 10µA minimum. For better performance, add
least larger than the peak current. The ISL8014 protects 47pF in parallel with R2 (100k
the typical peak current 6A. The saturation current needs
be over 7A for maximum output current application.
Input Capacitor Selection
The main functions for the input capacitor are to provide
ISL8014 uses internal compensation network and the decoupling of the parasitic inductance and to provide
output capacitor value is dependent on the output filtering function to prevent the switching current flowing
voltage. The ceramic capacitor is recommended to be back to the battery rail. Two 22µF X5R or X7R ceramic
X5R or X7R. The recommended X5R or X7R minimum capacitors are a good starting point for the input
output capacitor values are shown in Table 1. capacitor selection.
TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT

VOUT COUT L
(V) (µF) (µH)
0.8 2 x 22 1.0~2.2
1.2 2 x 22 1.0~2.2
1.5 2 x 22 1.5~3.3
1.8 2 x 22 1.5~3.3
2.5 2 x 22 1.5~3.3
3.3 2 x 22 2.2~4.7
3.6 2 x 22 2.2~4.7

FN6576 Rev 4.00 Page 14 of 17

November 23, 2009
ISL8014

Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.

DATE REVISION CHANGE

11/23/09 FN6576.4 Updated on page 13 in UVLO section, last sentence from “...programming resistor R5..., The
value of R4...” to “...programming resistor R4..., The value of R5...”. Replaced Figure 38,
Removed Equation after Figure 38. Reworded last sentence in Enable section from “It is
necessary to keep the voltage on the EN low until Vin is greater than 2.5V” to “It is
recommended that the EN voltage should be kept logic low (less than 400mV), until VIN
reaches 2.5V. Refer to Figure 39 for suggested circuit implementation with VIN slew rate.
Added Figure 39. Added Equations 1 and 2 and referencing text.
Added Revision History and Products information.
Moved Soft-Start section to read after PG section on page 13, changed "R4" to "R5" in last
sentence of UVLO section, added reference of both Figures 38 and 39 in Enable section.

09/10/09 FN6576.3 9/10/09:

Page 6; Revised last sentence of EN section from:
"Do not leave this pin floating." TO:"Do not connect directly to VIN or leave this pin floating."
9/2/09:
Page 2: Order Info: Added MSL link to Order Info per new standard
Page 2: Revised Typical Application Diagram
Pages 4-5: Per new Intersil standard: Added "Boldface limits apply over the operating
temperature range, -40°C to +85°C." to common conditions of Electrical Specs table. Bolded
MIN MAX columns where applicable. Moved "Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested." from common conditions of Electrical Specs
table to note in Min Max columns.
Page 6: Added following sentence to EN pin description:
" Keep the EN voltage low in disabled state until Vin settle or above 2.5V."
Revised "FIGURE 37. SKIP MODE OPERATION WAVEFORMS
Page 14: Added FIGURE 38. EXTERNAL RESISTOR DIVIDER graphic and following sentence to
UVLO section:
"To adjust the voltage level of power on and UVLO, use a resistive divider across EN. The input
voltage programming resistor R5 will depend on on the bottom resistor R4, as referred to in
Figure 38. The value of R4 is typically between 10kohm and 100kohm."
Added equation 1 to UVLO section:
Added following sentence to Enable section:
"It is necessary to keep the voltage of the EN low until Vin is greater than 2.5V."

08/04/08 FN6576.2 Added to VIN, VDD and LX in Abs Max Rating (DC) or 7V (20ms). Added Intersil Standards as
follows: Added to Electrical Specs conditions at top over-temp note. Updated POD L16.4x4 to
latest version.

12/20/07 FN6576.1 Removed the MIN and MAX value of "Peak Skip Limit " in the EC table at page 4.
Replaced the Trans-Resistance (RT) value "0.18" into "0.17" for MIN and "0.22" into "0.23" for
MAX in the EC table on page 4.

11/28/07 FN6576.0 Initial Release to web

FN6576 Rev 4.00 Page 15 of 17

November 23, 2009
ISL8014

Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell
phones, handheld products, and notebooks. Intersil's product families address power management and analog
signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective
device information page on intersil.com: ISL8014
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php

© Copyright Intersil Americas LLC 2007-2009. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN6576 Rev 4.00 Page 16 of 17

November 23, 2009
 ISL8014

Package Outline Drawing

L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08

4X 1.95
4.00 A 12X 0.65
B 6
13 16 PIN #1 INDEX AREA

6
PIN 1
INDEX AREA 1
12

4.00
2 . 10 ± 0 . 15

9
4

(4X) 0.15
8 5
TOP VIEW +0.15 0.10 M C A B
16X 0 . 60
-0.10 4 0.28 +0.07 / -0.05
BOTTOM VIEW

SEE DETAIL "X"

0.10 C C
1.00 MAX
BASE PLANE

( 3 . 6 TYP ) SEATING PLANE

0.08 C
SIDE VIEW
( 2 . 10 ) ( 12X 0 . 65 )

( 16X 0 . 28 ) C 0 . 2 REF 5

( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

FN6576 Rev 4.00 Page 17 of 17

November 23, 2009
Mouser Electronics

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