Electrical Engineering Department – ITU

EE233L: Digital Logic Design Lab

Course Instructor: Mr. Hussnain Riaz Dated:

Lab Engineer 1: Engr. Muhammad Umair Shoaib Semester: Fall 2021

Lab Engineer 2: Session: EE20

LAB 6 Behavioral Modeling in Verilog: Implementation of Decoders

In-lab Marks Scaled Viva Marks Total Marks

Name Roll Number
(35) (10) (5) (15)

Checked on: ____________________________

Signature: ______________________________

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EE233L: Digital Logic Design Lab

Behavioral Modeling in Verilog: Implementation of Decoders

6.1. Introduction
This lab exercise introduces students to an important standardized combinational logic circuit: the decoder. The
implementation of Boolean functions using decoders is detailed in theory and practiced in lab tasks using behavioral
modeling style of Verilog. Cascading decoders to build larger sized decoders is also covered in one lab task.

6.2. Objectives
This lab exercise will enable students to achieve the following:
 Familiarize with the decoder structure and understand what is meant by the size of a decoder
 Design larger size decoders by cascading small size decoders
 Relate the output of decoders to the already learnt concepts of minterms and thus use decoders with a few extra gate
circuitry to implement Boolean functions
 Learn how to use behavioral modeling style of Verilog

6.3. Conduct of Lab

This lab experiment has to be performed using the ModelSim PE Student Edition, installed in Embedded Lab PCs.
Bring printout of this lab manual when you come to perform the lab.
You can work and get evaluated in groups of two. However, manual submission has to be separate.
If there is difficulty in understanding any aspect of the lab, please seek help from the lab engineer or the TA.
If a lab task contains an instruction to show working to lab engineer, make sure that the lab engineer evaluates and marks
on your manual for that task. If your manual is unmarked for this task, it can result in marks deduction.
Complete the lab within the allocated time. Late submissions will be marked zero.
Print the codes and screenshots of simulation results of all tasks and attach these to your lab manual. Submit complete
manual to the lab engineer no later than 24 hours after the lab.

6.4. Theory and Background

6.4.1. Decoders
An n-bit binary number can be used to represent 2 n values. A binary decoder is a multiple-output combinational circuit that
converts binary information from n input lines to a maximum of 2 n unique output lines. If there are unused combinations in
n-bit coded input, then there can be fewer than 2 n output lines.
Table 6.1 shows the truth table of the outputs of a 3-to-8 (=23) decoder that is shown in Figure 6.1:
Table 6.1: Truth table of a 3-to-8 decoder

Inputs Outputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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Figure 6.1: A 3-to-8 line decoder and its truth table

Only one output line of a binary decoder can be 1, while all other output lines remain zero. An n-to-2n decoder actually
provides all the minterms of the n-bit input. Outputs of a combinational logic circuit can be represented in sum-of-minterms
form; hence decoder outputs (that are actually minterms) can be used to implement any combinational circuit by ORing the
required minterms. Hence a combinational circuit with n-bit input and m-bit output can be implemented using an n-to-2n
decoder and m number of OR gates with multiple inputs.
6.4.1.1. Enable input and decoder cascading
A decoder may be provided with an additional input to enable or disable its operation. This additional input is called “enable”
input. When this input is not enabled, all of the 2n outputs of an n-bit decoder are 0. Decoders with enable inputs can be
combined to build a larger decoder circuit. For example, two 2-to-4 line decoders can be connected together to give a 3-to-8
line decoder, as shown below:

Figure 6.2: 3-to-8 line decoder using two 2-to-4 line decoder

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EE233L: Digital Logic Design Lab

6.4.2. Implementation of a decoder using dataflow modeling

A decoder can be implemented using dataflow modeling using the ‘?’ conditional operator. The syntax of the conditional
operator “?” is as follows:
condition ? value_if_true : value_if_false
Let’s look at each line of the following code of a 2-to-4 decoder based on dataflow modeling:
module Decoder_2_to_4(X, Y, En, D);
input X, Y, En;
output [3:0] D;
assign D = En ? (X ? (Y ? 4'h8 : 4'h4) :(Y ? 4'h2 : 4'h1)): 4'h0;
endmodule
module Decoder_2_to_4 (X, Y, En, D); This line declares the module of 2-to-4 line decoder that has 4 ports X, Y, En
and D.
input X, Y, En; This line declares X, Y and En as inputs of the decoder. X and Y are the inputs to be decoded and En is
the enable of the decoder.
output [3:0] D; This line declares D as a vector output of size 4. This is the 4-bit decoded output.
assign D = En ? (X ? (Y ? 4'h8 : 4'h4) :(Y ? 4'h2 : 4'h1)): 4'h0; This line uses the conditional operator ? to check various
conditions and assigns binary values to D accordingly. The first condition that is checked is the value of En input. If this
is equal to 0, all bits of the output D are assigned 0. If En is equal to 1, then in another conditional operation, the value
of X is checked for 0 or 1. For both values of X, Y is checked again and D is assigned 4-bit value accordingly. Note that
the values assigned to D are written in hex, specified by the use of ‘h. However, the number of bits that precedes ‘h is
still written as 4.
endmodule This line marks the end of this module.
This code is simulated using the following test bench from which the timing diagrams of Figure 6.3 are obtained.
module Test_decoder();
reg X, Y, En;
wire [3:0] D;
Decoder_2_to_4 my_dec(X, Y, En, D);
initial begin
En = 0; X = 0; Y = 0; #100
En = 0; X = 0; Y = 1; #100
En = 1; X = 1; Y = 0; #100
En = 1; X = 1; Y = 1;
end
endmodule

Figure 6.3: Timing diagram of 2-to-4 decoder

6.4.3. Behavioral modeling in Verilog

Behavioral modeling style lies at the highest level of abstraction in Verilog. It is similar to dataflow modeling in syntax. The
only difference is the introduction of the notion of time and the sequence of code execution. Let’s look at the following code
that implements a 2-to-4 line decoder using behavioral modeling in Verilog:
module Decoder_2_to_4(X, Y, En, D);
input X, Y, En;

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output reg [3:0] D;

always @ (X, Y, En) begin
case ({X,Y,En})
3'b001: D = 4'h1;
3'b011: D = 4'h2;
3'b101: D = 4'h4;
3'b111: D = 4'h8;
default: D = 4'h0;
endcase
end
endmodule
module Decoder_2_to_4(X, Y, En, D); This is the module declaration.
input X, Y, En; This line declares X, Y and En as scalar inputs.
output reg [3:0] D; This line declares a vector output D of 4 bits. Notice that the data type of output is not a net but a
register. This has been done so that D can be updated inside an ‘always’ block. Only reg or integer data types can be
stored with new values inside always or initial blocks.
always @ (X, Y, En) begin An ‘always’ block has been created in this line. An always block, like the initial block, is a
timing block that is used in behavioral modeling. The always block runs all the time in contrast to the initial block that
you have used previously in test benches, which runs only once. The always blocks needs to have trigger signals to let
it know when to run In our case there are three signals, X, Y and En. The always block is expected to be executed
completely whenever one of these signals changes value. The list of trigger signals is called the sensitivity list of the
always block. Similar to an initial block, the always block cannot drive wire data types either; only registers (reg) or
integer data types can be driven inside an always block.
case ({X, Y, En}) This line marks the start of a case statement inside our always block. Inside the parenthesis following
the case keyword, is the expression that will be check against the different conditions listed inside this case statement.
This expression can be an n-bit variable. In our case, we have used the braces to concatenate the three 1-bit variables X,
Y and En. The order of values of X, Y and En will be retained in the concatenated expression.
3'b001: D = 4'h1; This line and the next three lines define four cases of the input expression {X, Y, En} and assign
values to D accordingly.
default: D = 4’h0; This line defines the default case which will be executed when none of the above four have been
found to match the input expression {X, Y, En}.
endcase This keyword marks the end of case statement.
end This keyword marks the end of the always block. This is the Verilog equivalent of the closing brace } in C and other
programming languages.
endmodule This line marks the end of the module.
When tested with the test bench provided in 6.4.2, the simulation results are the same as in Figure 6.3.

6.5. Lab Tasks

6.5.1. Task 1: Cascading decoders [Marks: 13]

Write Verilog code for a 1-to-2-line decoder with enable input using the “?” operator of dataflow modeling.
[2]
Write Verilog code for a 3-to-8-line decoder with enable input using behavioral modeling. [3]
Draw the design diagram of a 4-to-16-line decoder using two 3-to-8-line decoders and one 1-to-2-line decoder in the
space given below: [2]

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EE233L: Digital Logic Design Lab

Write Verilog code that implements your design of 4-to-16-line decoder with enable input using the already coded 3-to-
8-line and 1-to-2-line decoders in a hierarchical pattern. [2]
Write test bench module to simulate your 4-to-16-line decoder for an arbitrary set (at least eight in number) of input
combinations. Make sure to test the enable of your decoder. [2]
Show your code and simulation waveforms to the lab engineer to obtain credit. [2]
Take clear screenshots of the code of all modules of this task and the simulation timing waveforms, and paste them in a
WORD file such that all fit on no more than two pages. Make sure that screenshots are legible.

6.5.2. Task 2: Boolean function implementation using decoders [Marks: 7]

You are given a 4-variable Boolean function F.
F(A, B, C, D) = ∑ m (0, 1, 3, 5, 7, 12, 11, 14, 15)
Implement this function in Verilog using the 4-to-16 line decoder constructed in Task 1. [3]
Write a test bench module to simulate the above module for all input combinations of F. Complete the truth table of F
in Table 6.2. [2]
Table 6.2: Truth table of F as observed in decoder implementation

A B C D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0

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 LAB 6

1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Show your code and simulation waveforms to the lab engineer to obtain credit. [2]
Take clear screenshots of the code of all modules of this task and the simulation timing waveforms, and paste them in
your WORD file such that all fit on no more than two pages. Make sure that screenshots are legible.

6.5.3. Analysis [Marks: 5]

How is the size of a decoder specified? Give examples. [1]

Search the internet for two ICs of 7400 series that implement a decoder. Also mention the decoder ICs along with their
names (numbers). [1]

How can you use a 2-to-4 decoder as a 1-to-2 decoder? Draw circuit diagram to support your answer. [2]

How many 4-to-16 decoders will be required to implement a 6-to-64 decoder? [1]

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EE233L: Digital Logic Design Lab

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 LAB 6

Assessment Rubric for Lab 6

Method:
Lab report evaluation and instructor observation during lab sessions.
Outcome assessed:
a. Ability to conduct experiments as well as to analyze and interpret data (P)
b. Ability to function in a team and adhere to rules and guidelines (A)
c. Ability to use techniques, skills and modern engineering tools necessary for engineering practice (P)
Performance Exceeds expectation Meets expectation Does not meet expectation Marks
(4 – 5) (2 – 3) (0 – 1)
1. Realization Conceptually understands the Needs guidance to understand the Incapable of understanding the
of topic under study and develops purpose of the experiment and to purpose of the experiment and
experiment the experimental setup develop the required setup consequently fails to develop the
(a) – Task 1, accordingly required setup
2, 3
2. Teamwork Actively engages and cooperates Cooperates with other group Distracts or discourages other
(b) with other group members in an members in a reasonable manner group members from conducting
effective manner the experiments
3. Sets up hardware/software Makes minor errors in Unable to set up experimental
Conducting properly according to the hardware/software setup and setup, and perform the procedure
experiment requirement of experiment and observation of output of experiment
(a, c) – Task examines the output carefully
1, 2, 3
4. Laboratory Observes lab safety rules; Observes safety rules and Disregards lab safety and
safety and handles the development board disciplinary guidelines with disciplinary rules
disciplinary and other components with care minor deviations
rules (b) and adheres to the lab
disciplinary guidelines aptly
5. Data Completes data collection from Completes data collection with Fails at collecting data by giving
collection (c) the experiment setup by giving minor errors and enters data in proper inputs and observing
– Task 1, 2, 3 proper inputs and observing the lab report with slight deviations output states of experiment setup,
outputs, complies with the from provided guidelines unable to fill the lab report
instructions regarding data entry properly
in manual
6. Data Analyzes the data obtained from Analyzes data with minor error Unable to establish the
analysis (a, c) experiment thoroughly and and correlates it with theoretical relationship between practical
accurately verifies it with values reasonably. Attempts to and theoretical values and lacks
theoretical understanding, account for any discrepancy in the theoretical understanding to
accounts for any discrepancy in data from theory explain any discrepancy in data
data from theory with sound
explanation, where asked
7. Computer Successfully uses lab PC and Requires assistance in looking Does not know how to use
use (c) – internet to look for relevant for IC datasheets and carrying computer to look up datasheets
Task 1, 2, 3 datasheets, carry out calculations, out calculation and simulation or carry out calculation and
or verify results using simulation tasks simulation tasks
Obtained (out of 35):

Lab engineer’s signature:

_____________________________

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