EX.

NO:06 DESIGN AND IMPLEMENTATION OF DECODER AND PRIORITY ENCODER

USING FPGA
DATE:

Aim
To design, simulate and implement decoder and priority encoder in FPGA using Verilog HDL

Software Required
 Vivado 2014.4

Hardware Required
 Nexys A7: FPGA Trainer Board

Theory

Decoder

A decoder is a device which does the reverse of an encoder, undoing the encoding so that
the original information can be retrieved. The same method is used to encode and just reversed in
order to get decoder.

In digital electronics, a decoder can take the form of a multiple-input, multiple-output

logic circuit that converts coded inputs into coded outputs, where the input and output codes are
different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the decoder
to function, otherwise its outputs assume a single "disabled" output code word. Decoding is
necessary in applications such as data multiplexing, 7 segment display and memory address
decoding
2:4 Decoder with and without Enable signal

Structural/Gate level modeling Dataflow modeling

Logic Diagram : without enable Logic Diagram : with enable

Truth Table Truth Table

Input Output Input Output

A0 A1 D3 D2 D1 D0 E A0 A1 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 0 0 1
0 1 0 0 1 0 1 0 1 0 0 1 0
1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 1 0 0 0 1 1 1 1 0 0 0
0 X X 0 0 0 0

Program Program
module decoder_2_to_4( module decoder_2_to_4(
input a0, input a0,
input a1, input a1,
output d0, input e,
output d1, output d0,
output d2, output d1,
output d3 ); output d2,
wire an0, an1; output d3 );
not n1(an0,a0); assign d0= (~a1) & (~a0) & en;
n2 (an1,a1); assign d1= (~a1) & a0 & en;
and a1 (d0,an0,an1); assign d2= a1 & (~ a0) & en;
a2 (d1,a0,an1); assign d3= a1 & a0 & en;
a3 (d2,an0,a1); end module
a4 (d3,a0,a1);
endmodule
Priority Encoder

An encoder is a digital circuit that performs inverse operation of a decoder. An encoder

n
has 2 input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal
digit and three output that generate the corresponding binary code. In encoder it is assumed that
only one input has a value are zero the outputs are zero. The zero outputs can also be generated
when D0 =1.

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a
smaller number of outputs. The output of a priority encoder is the binary representation of the
ordinal number starting from zero of the most significant input bit. They are often used to control
interrupt requests by acting on the highest priority request. It includes priority function. If two or
more inputs are equal to 1 at the same time, the input having the highest priority will take
precedence. Internal hardware will check this condition and priority is set.
 Test bench Program Test bench Program
module tb_decoder_2_to_4(); module tb_decoder_2_to_4();
reg tb_a0, tb_a1; reg tb_a0, tb_a1, tb_en;
wire tb_d0,tb_d1,tb_d2,tb_d3; wire tb_d0,tb_d1,tb_d2,tb_d3;
decoder_2_to_4 dut decoder_2_to_4 dut
(.a0(tb_a0),.a1(tb_a1),.d0(tb_d0), (.a0(tb_a0),.a1(tb_a1),.en(tb_en),
.d1(tb_d1),.d2(tb_d2),.d3(tb_d3)); .d0(tb_d0),.d1(tb_d1),.d2(tb_d2),.d3(tb_d3));
initial begin initial begin
tb_a0=0; tb_a1=0; #10 tb_a0=0; tb_a1=0; tb_en=1; #10
tb_a0=0; tb_a1=1; #10 tb_a0=0; tb_a1=1; tb_en=1; #10
tb_a0=1; tb_a1=0; #10 tb_a0=1; tb_a1=0; tb_en=1; #10
tb_a0=1; tb_a1=1; #10 tb_a0=1; tb_a1=1; tb_en=1; #10
$stop; $stop;
end end
endmodule endmodule

3:8 decoder using Behavioral Modeling

Logic Diagram

Truth Table

Input Output
Enable In[2] In[1] In[0] Out[7] Out[6] Out[5] Out[4] Out[3] Out[2] Out[1] Out[0]
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
0 X X X 0 0 0 0 0 0 0 0
Procedure

1. Double Click on “ vivado2014.4”

2. Clickcreate new project
3. Clicknext
4. Enter your project name,and click, next.,
5. Select “RTL project” and click next.,
6. Click create file
7. Select your file type as Verilog
8. Enter your “file name” and click ok.,
9. Clicknext.,
10. Click next.,
11. Create xdc file
11.a, Clickcreate file.,
11.b. Enter your “xdc name” and click ok.,
12. Clicknext.,
13. Select your ic details.,(ex:Nexys A7” xc7a100tcpg324-1”)
14. Click finish.,
15. Enter your input and output details and click ok, else click cancel directly enter your program and
declare your input output
16. Goto project manager and click your verilog file under Design Sources.,
17. Enter your program and save file.,
 Program Test bench Program
module decoder_using_case (binary_in , module tb_decoder_using_case ();
decoder_out , enable); reg [2:0] tb_binary_in ;
input [2:0] binary_in ; input enable ; reg tb_enable ;
output [7:0] decoder_out ; wire [7:0] tb_decoder_out ;
reg [7:0] decoder_out ; decoder_using_case dut (.binary_in(tb_binary_in),.
always @ (enable or binary_in) enable(tb_enable),.decoder_out(tb_decoder_out));
begin initial begin
decoder_out = 0; tb_enable=1;tb_binary_in=2'b000; #10
if (enable) begin tb_enable=1;tb_binary_in=2'b001; #10
case (binary_in) tb_enable=1;tb_binary_in=2'b010; #10
3'b000 : decoder_out = 8'h01; tb_enable=1;tb_binary_in=2'b011; #10
3'b001 : decoder_out = 8'h02; tb_enable=1;tb_binary_in=2'b100; #10
3'b010 : decoder_out = 8'h04; tb_enable=1;tb_binary_in=2'b101; #10
3'b011 : decoder_out = 8'h08; tb_enable=1;tb_binary_in=2'b110; #10
3'b100 : decoder_out = 8'h10; tb_enable=1;tb_binary_in=2'b111; #10
3'b101 : decoder_out = 8'h20; $stop;
3'b110 : decoder_out = 8'h40; end
3'b111 : decoder_out = 8'h80; endmodule
default : decoder_out = 8'h00;
endcase end end endmodule

RTL Schematics

Output
Steps for Test bench creation

18. Goto project manager  right click on Simulation SourcesSelect Add or create simulation sources,
19. Click on Create File  Select your file type as Verilog
20. Enter your “file name” and click Finish.,
21. Goto project manager and click your verilog file under Simulation Sources.,
22. Enter your program and save file.,
23. Click on”run synthesis”Running synthesis.,
Priority Encoder

Block Diagram Logic Diagram

Truth Table
D[0] D[1] D[2] D[3] Y[1] Y[0] V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

Program Test bench Program

module priorityencoder(Y, Din, En); module tb_priorityencoder();
input [3:0] Din; reg [3:0] tb_Din;
input En; reg tb_En;
output [1:0]Y; wire [1:0]tb_Y;
reg [1:0]Y; priorityencoder dut (.Din(tb_Din),
always @ ( En or Din) .En(tb_En),.Y(tb_Y));
begin initial begin
if (En) tb_En=1; tb_Din= 4'b0001;
begin
#10
casex (Din)
tb_En=1;tb_Din= 4'b001x;
4'b0001: Y = 2'b00;
#10
4'b001x: Y = 2'b01;
tb_En=1;tb_Din= 4'b01xx;
4'b01xx: Y = 2'b10;
4'b1xxx: Y = 2'b11;
#10
default: $display("Error!"); tb_En=1;tb_Din= 4'b1xxx;
endcase #10
end $stop;
end end
endmodule endmodule
Steps for Simulation

24. After successful synthesis completion, close the pop-up window and select Simulation  Run
Behavioural Simulation is enough to see output waveform If we run through testbench program.
25. Else After the Run Behavioral Simulation, Force the value for inputs by Force Constant option and
save the waveform
26. Run the simulation by clicking on Run for amount of time previously set
Output of simulation is verified with the help of waveform
RTL Schematic

Output

Implemented 2:4 Decoder

in Nexys A7: FPGA Trainer
Board

Output : 0100

Input en: 1
in: 10
en input
Steps for Implementation

1. Click open synthesis design and click ok.,

2. Create floor plan details
a. Clickconstraints wizard
b. Click define target
c. Select your xdc file and click ok.,
d. Click schematic(F4)
e. ClickI/O Ports
f. Enter your pin details.,
g. Select I/O STDLVCMOS33
h. Clicksave, and yes,
3. Clickrun implementation
4. ClickGenerate Bitstream and click “open target”
5. Opentargetopen new target.,
6. ClickAuto connect.,
7. Clickprogram deviceselect your device
Clickprogram
 Implemented 3:8 Decoder
in Nexys A7: FPGA Trainer
Board

Output : 00100000

Input enable: 1
binary_in: 101
en input

Implemented Priority
Encoder in Nexys A7: FPGA
Trainer Board

Output : 11

Input En: 1
binary_in: 1XXX

en input
Result
Thus the simulation of decoder and priority encoder were done, implemented in Nexys A7 FPGA
Trainer Board and outputs were verified

Inference from the Result:

Practice Question

Implement and verify 4:16 decoder using 3:8 decoders in FPGA