SiS782DN

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Vishay Siliconix
N-Channel 30 V (D-S) MOSFET with Schottky Diode
PowerPAK® 1212-8 Single
FEATURES
D
D 8 • SkyFET® monolithic TrenchFET® power
D 7
D 6 MOSFET and Schottky diode
5
• Low thermal resistance PowerPAK® package
with small size and low 1.07 mm profile
• 100 % Rg and UIS tested
3. 1
3
m 2 S • Material categorization: for definitions of compliance
m 3 S
mm 4 S please see www.vishay.com/doc?99912
1 3.3 G
Top View Bottom View
APPLICATIONS D
PRODUCT SUMMARY
• Notebook PC
VDS (V) 30
- System power, memory
RDS(on) max. () at VGS = 10 V 0.0095
• Buck converter Schottky
RDS(on) max. () at VGS = 4.5 V 0.0120 G Diode
Qg typ. (nC) 9.5 • Synchronous rectifier
switch
ID (A) e 16
Single plus integrated S
Configuration
Schottky (SkyFET) N-Channel MOSFET

ORDERING INFORMATION
Package PowerPAK 1212-8
Lead (Pb)-free and halogen-free SiS782DN-T1-GE3

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 30
V
Gate-source voltage VGS ± 20
TC = 25 °C 16 e
TC = 70 °C 16 e
Continuous drain current (TJ = 150 °C) ID
TA = 25 °C 14.5 a, b
TA = 70 °C 11.5 a, b
A
Pulsed drain current (t = 300 μs) IDM 50
TC = 25 °C 16 e
Continuous source-drain diode current IS
TA = 25 °C 4 a, b
Single pulse avalanche current IAS 15
L = 0.1 mH
Single pulse avalanche energy EAS 11.25 mJ
TC = 25 °C 41
TC = 70 °C 26
Maximum power dissipation PD W
TA = 25 °C 3.6 a, b
TA = 70 °C 2.3 a, b
Operating junction and storage temperature range TJ, Tstg -50 to +150
°C
Soldering recommendations (peak temperature) c, d 260

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum junction-to-ambient a, f t  10 s RthJA 28 34
°C/W
Maximum junction-to-case (drain) Steady state RthJC 2.4 3
Notes
a. Surface mounted on 1" x 1" FR4 board
b. t = 10 s
c. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection
d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
e. Package limited
f. Maximum under steady state conditions is 81 °C/W

S11-1177-Rev. A, 13-Jun-11 1 Document Number: 67954

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SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0, ID = 1 mA 30 - -
V
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 1 - 2.3
Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
VDS = 30 V, VGS = 0 V - 0.028 0.200
Zero gate voltage drain current IDSS mA
VDS = 30 V, VGS = 0 V, TJ = 100 °C - 2.5 20
On-state drain current a ID(on) VDS  5 V, VGS = 10 V 30 - - A
VGS = 10 V, ID = 10 A - 0.0079 0.0095
Drain-source on-state resistance a RDS(on) 
VGS = 4.5 V, ID = 7 A - 0.0096 0.0120
Forward transconductance a gfs VDS = 10 V, ID = 10 A - 43 - S
Dynamic b
Input capacitance Ciss - 1025 -
Output capacitance Coss VDS = 15 V, VGS = 0 V, f = 1 MHz - 251 - pF
Reverse transfer capacitance Crss - 100 -
VDS = 15 V, VGS = 10 V, ID = 10 A - 20.3 30.5
Total gate charge Qg
- 9.5 14.3
nC
Gate-source charge Qgs VDS = 15 V, VGS = 4.5 V, ID = 10 A - 2.8 -
Gate-drain charge Qgd - 3.2 -
Gate resistance Rg f = 1 MHz 0.2 0.9 1.8 
Turn-on delay time td(on) - 11 22
Rise time tr VDD = 15 V, RL = 1.5  - 22 48
Turn-off delay time td(off) ID  10 A, VGEN = 4.5 V, Rg = 1  - 13 26
Fall time tf - 11 22
ns
Turn-on delay time td(on) - 8 16
Rise time tr VDD = 15 V, RL = 1.5  - 13 26
Turn-off delay time td(off) ID  10 A, VGEN = 10 V, Rg = 1  - 14 28
Fall time tf - 9 18
Drain-Source Body Diode Characteristics
Continuous source-drain diode current IS TC = 25 °C - - 16
A
Pulse diode forward current a ISM - - 50
Body diode voltage VSD IS = 2 A - 0.44 0.55 V
Body diode reverse recovery time trr - 18 35 ns
Body diode reverse recovery charge Qrr IF = 5 A, di/dt = 100 A/μs, - 7.5 15 nC
Reverse recovery fall time ta TJ = 25 °C - 10 -
ns
Reverse recovery rise time tb - 8 -
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %
b. Guaranteed by design, not subject to production testing


Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

S11-1177-Rev. A, 13-Jun-11 2 Document Number: 67954

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

50 10

VGS = 10 V thru 4 V
40 8
ID - Drain Current (A)

ID - Drain Current (A)

30 6

VGS = 3 V
20 4 TC = 25 °C

TC = - 55 °C
10 2

TC = 125 °C
VGS = 2 V
0 0
0 0.5 1 1.5 2 2.5 0 1 2 3 4 5
VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

0.011 1500

0.010 1200
RDS(on) - On-Resistance (Ω)

Ciss
VGS = 4.5 V
C - Capacitance (pF)

0.009 900

0.008 600
VGS = 10 V Coss
Crss
0.007 300

0.006 0
0 10 20 30 40 50 0 4 8 12 16 20
ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current and Gate Voltage Capacitance

10 1.8

ID = 10 A ID = 10 A
VGS = 10 V
RDS(on) - On-Resistance (Normalized)

1.6
VGS - Gate-to-Source Voltage (V)

1.4
6 VDS = 15 V VGS = 4.5 V

1.2
VDS = 10 V
4 VDS = 20 V
1.0

2
0.8

0 0.6
0 3.4 6.8 10.2 13.6 17.0 - 50 - 25 0 25 50 75 100 125 150
Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

S11-1177-Rev. A, 13-Jun-11 3 Document Number: 67954

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

100 0.040

ID = 10 A

10 TJ = 150 °C 0.032

RDS(on) - On-Resistance (Ω)

IS - Source Current (A)

TJ = 25 °C
1 0.024

0.1 0.016 TJ = 125 °C

0.01 0.008
TJ = 25 °C

0.001 0
0.0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10
VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)

Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

10-1 120

10-2
30 V 96
IR - Reverse Current (A)

10-3
20 V 72
Power (W)

10-4

48
10-5
10 V
24
10-6

10-7 0
0 25 50 75 100 125 150 0.001 0.01 0.1 1 10
TJ - Temperature (°C) Time (s)

Reverse Current (Schottky) Single Pulse Power, Junction-to-Ambient

100

IDM Limited
100 μs
ID Limited
10
ID - Drain Current (A)

1 ms
10 ms
1
100 ms
Limited by RDS(on)*
1s
0.1 10 s

DC
TC = 25 °C
Single Pulse BVDSS Limited
0.01
0.01 0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified

Safe Operating Area, Junction-to-Ambient

S11-1177-Rev. A, 13-Jun-11 4 Document Number: 67954

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

55

44

ID - Drain Current (A)

33

22

Package Limited
11

0
0 25 50 75 100 125 150
TC - Case Temperature (°C)

Current Derating a

50 2.0

40 1.6

30 1.2
Power (W)
Power (W)

20 0.8

10 0.4

0 0.0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
TC - Case Temperature (°C) TA - Ambient Temperature (°C)

Power, Junction-to-Case Power, Junction-to-Ambient

Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit

S11-1177-Rev. A, 13-Jun-11 5 Document Number: 67954

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Duty Cycle = 0.5

Normalized Effective Transient

0.2
Thermal Impedance

Notes:
0.1
0.1 PDM

0.05 t1
t2
t1
1. Duty Cycle, D =
0.02 t2
2. Per Unit Base = RthJA = 81 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
0.0001 0.001 0.01 0.1 1 10 100 1000
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

1
Duty Cycle = 0.5
Normalized Effective Transient

0.2
Thermal Impedance

0.1

0.1 0.05
0.02

Single Pulse

0.01
0.0001 0.001 0.01 0.1 1 10
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Case

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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?67954.

S11-1177-Rev. A, 13-Jun-11 6 Document Number: 67954

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 Package Information
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Vishay Siliconix
PowerPAK® 1212-8, (Single / Dual)

L
H E2 K

D4
W E4

θ
M
8
1 1

e
Z
2

D1

D2

D5
2

D
3

4 5 4

b
θ
L1 E3
θ θ A1
Backside view of single pad
L
H K
A

E2
E4
c

D2 D3(2x) D4
2
1
E1 Detail Z D1
E 2

D5
Notes 3

K1
1. Inch will govern
2 Dimensions exclusive of mold gate burrs D2
4

b
3. Dimensions exclusive of mold flash and cutting burrs

E3
Backside view of dual pad

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 0.00 - 0.05 0.000 - 0.002
b 0.23 0.30 0.41 0.009 0.012 0.016
c 0.23 0.28 0.33 0.009 0.011 0.013
D 3.20 3.30 3.40 0.126 0.130 0.134
D1 2.95 3.05 3.15 0.116 0.120 0.124
D2 1.98 2.11 2.24 0.078 0.083 0.088
D3 0.48 - 0.89 0.019 - 0.035
D4 0.47 typ. 0.0185 typ
D5 2.3 typ. 0.090 typ
E 3.20 3.30 3.40 0.126 0.130 0.134
E1 2.95 3.05 3.15 0.116 0.120 0.124
E2 1.47 1.60 1.73 0.058 0.063 0.068
E3 1.75 1.85 1.98 0.069 0.073 0.078
E4 0.034 typ. 0.013 typ.
e 0.65 BSC 0.026 BSC
K 0.86 typ. 0.034 typ.
K1 0.35 - - 0.014 - -
H 0.30 0.41 0.51 0.012 0.016 0.020
L 0.30 0.43 0.56 0.012 0.017 0.022
L1 0.06 0.13 0.20 0.002 0.005 0.008
 0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 typ. 0.005 typ.
ECN: S16-2667-Rev. M, 09-Jan-17
DWG: 5882

Revison: 09-Jan-17 1 Document Number: 71656

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 AN822
Vishay Siliconix

PowerPAK® 1212 Mounting and Thermal Considerations

Johnson Zhao

MOSFETs for switching applications are now available The PowerPAK 1212-8 has a footprint area compara-
with die on resistances around 1 mΩ and with the ble to TSOP-6. It is over 40 % smaller than standard
capability to handle 85 A. While these die capabilities TSSOP-8. Its die capacity is more than twice the size
represent a major advance over what was available of the standard TSOP-6’s. It has thermal performance
just a few years ago, it is important for power MOSFET an order of magnitude better than the SO-8, and 20
packaging technology to keep pace. It should be obvi- times better than TSSOP-8. Its thermal performance is
ous that degradation of a high performance die by the better than all current SMT packages in the market. It
package is undesirable. PowerPAK is a new package will take the advantage of any PC board heat sink
technology that addresses these issues. The PowerPAK capability. Bringing the junction temperature down also
1212-8 provides ultra-low thermal impedance in a increases the die efficiency by around 20 % compared
small package that is ideal for space-constrained with TSSOP-8. For applications where bigger pack-
applications. In this application note, the PowerPAK ages are typically required solely for thermal consider-
1212-8’s construction is described. Following this, ation, the PowerPAK 1212-8 is a good option.
mounting information is presented. Finally, thermal
and electrical performance is discussed. Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
THE PowerPAK PACKAGE The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
The PowerPAK 1212-8 package (Figure 1) is a deriva-
space constraints.
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
PowerPAK 1212 SINGLE MOUNTING
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is To take the advantage of the single PowerPAK 1212-8’s
mounted on. The PowerPAK 1212-8 thus translates thermal performance see Application Note 826,
the benefits of the PowerPAK SO-8 into a smaller Recommended Minimum Pad Patterns With Outline
package, with the same level of thermal performance. Drawing Access for Vishay Siliconix MOSFETs. Click
(Please refer to application note “PowerPAK SO-8 on the PowerPAK 1212-8 single in the index of this
Mounting and Thermal Considerations.”) document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.

Figure 1. PowerPAK 1212 Devices

Document Number 71681 www.vishay.com

03-Mar-06 1
AN822
Vishay Siliconix

PowerPAK 1212 DUAL

To take the advantage of the dual PowerPAK 1212-8’s ture profile used, and the temperatures and time
thermal performance, the minimum recommended duration, are shown in Figures 2 and 3. For the lead
land pattern can be found in Application Note 826, (Pb)-free solder profile, see http://www.vishay.com/
Recommended Minimum Pad Patterns With Outline doc?73257.
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an Ramp-Up Rate + 6 °C /Second Maximum
area of about 0.3 to 0.5 in2 of will yield little improve- Temperature at 155 ± 15 °C 120 Seconds Maximum
ment in thermal performance. Temperature Above 180 °C 70 - 180 Seconds
Maximum Temperature 240 + 5/- 0 °C
Time at Maximum Temperature 20 - 40 Seconds
REFLOW SOLDERING
Ramp-Down Rate + 6 °C/Second Maximum
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
Figure 2. Solder Reflow Temperature Profile
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-

10 s (max)
210 - 220 °C

3 ° C/s (max) 4 ° C/s (max)

183 °C
140 - 170 °C

50 s (max)

3° C/s (max) 60 s (min) Reflow Zone

Pre-Heating Zone

Maximum peak temperature at 240 °C is allowed.

Figure 3. Solder Reflow Temperatures and Time Durations

www.vishay.com Document Number 71681

2 03-Mar-06
 AN822
Vishay Siliconix

TABLE 1: EQIVALENT STEADY STATE PERFORMANCE

Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8
Configuration Single Dual Single Dual Single Dual Single Dual Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90 2.4 5.5 1.8 5.5

PowerPAK 1212 Standard SO-8 Standard TSSOP-8 TSOP-6

49.8 °C 85 °C 149 °C 125 °C

2.4 °C/W 20 °C/W 52 °C/W 40 °C/W

PC Board at 45 °C

Figure 4. Temperature of Devices on a PC Board

THERMAL PERFORMANCE

Introduction Spreading Copper

A basic measure of a device’s thermal performance is Designers add additional copper, spreading copper, to
the junction-to-case thermal resistance, Rθjc, or the the drain pad to aid in conducting heat from a device. It
junction to- foot thermal resistance, Rθjf. This parameter is helpful to have some information about the thermal
is measured for the device mounted to an infinite heat performance for a given area of spreading copper.
sink and is therefore a characterization of the device Figure 5 and Figure 6 show the thermal resistance of a
only, in other words, independent of the properties of the PowerPAK 1212-8 single and dual devices mounted on
object to which the device is mounted. Table 1 shows a a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
comparison of the PowerPAK 1212-8, PowerPAK SO-8, nal layers and the backside layer are solid copper. The
standard TSSOP-8 and SO-8 equivalent steady state internal layers were chosen as solid copper to model the
performance. large power and ground planes common in many appli-
By minimizing the junction-to-foot thermal resistance, the cations. The top layer was cut back to a smaller area and
MOSFET die temperature is very close to the tempera- at each step junction-to-ambient thermal resistance
ture of the PC board. Consider four devices mounted on measurements were taken. The results indicate that an
a PC board with a board temperature of 45 °C (Figure 4). area above 0.2 to 0.3 square inches of spreading copper
Suppose each device is dissipating 2 W. Using the junc- gives no additional thermal performance improvement.
tion-to-foot thermal resistance characteristics of the A subsequent experiment was run where the copper on
PowerPAK 1212-8 and the other SMT packages, die the back-side was reduced, first to 50 % in stripes to
temperatures are determined to be 49.8 °C for the Pow- mimic circuit traces, and then totally removed. No signif-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for icant effect was observed.
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.

Document Number 71681 www.vishay.com

03-Mar-06 3
AN822
Vishay Siliconix

105 130

Spreading Copper (sq. in.) 120 Spreading Copper (sq. in.)

95
110
85
100

RthJ A (°C/W)
RthJA (°C/W)

75 90

80
65 50 % 100 %
70
100 %
55 0%
50 % 60
0%
45 50

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance

CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK The PowerPAK 1212-8 combines small size with attrac-
1212-8 uses the same packaging technology and has tive thermal characteristics. By minimizing the thermal
been shown to have the same level of thermal perfor- rise above the board temperature, PowerPAK simplifies
mance while having a footprint that is more than 40 % thermal design considerations, allows the device to run
smaller than the standard TSSOP-8. cooler, keeps rDS(ON) low, and permits the device to
Recommended PowerPAK 1212-8 land patterns are handle more current than a same- or larger-size MOS-
provided to aid in PC board layout for designs using this FET die in the standard TSSOP-8 or SO-8 packages.
new package.

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4 03-Mar-06
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parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.

Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

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Revision: 01-Jan-2022 1 Document Number: 91000