LM 5145

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LM5145
SNVSAI4 – JUNE 2017
LM5145 6-V to 75-V Synchronous Buck DC-DC Controller With Wide Duty Cycle Range
1 Features 2 Applications
1• Versatile Synchronous Buck DC-DC Controller • Remote Radio Unit (RRU) and BTS
– Wide Input Voltage Range of 6 V to 75 V • Networking and Computing Power
– Adjustable Output Voltage From 0.8 V to 60 V • Non-Isolated PoE and IP Cameras
• Meets EN55022 / CISPR 22 EMI Standards • Industrial Motor Drives
• Lossless RDS(on) or Shunt Current Sensing
• Switching Frequency From 100 kHz to 1 MHz 3 Description
The LM5145 75-V synchronous buck controller is
– SYNC In and SYNC Out Capability designed to regulate from a high input voltage source
• 40-ns Minimum On-Time for High VIN / VOUT Ratio or from an input rail subject to high voltage transients,
• 140-ns Minimum Off-Time for Low Dropout minimizing the need for external surge suppression
• 0.8-V Reference With ±1% Feedback Accuracy components. A high-side switch minimum on-time of
40 ns facilitates large step-down ratios, enabling the
• 7.5-V Gate Drivers for Standard VTH MOSFETs direct step-down conversion from a 48 V nominal
– 14-ns Adaptive Dead-Time Control input to low-voltage rails for reduced system
– 2.3-A Source and 3.5-A Sink Capability complexity and solution cost. The LM5145 continues
to operate during input voltage dips as low as 6 V, at
– Low-Side Soft-Start for Prebiased Start-Up nearly 100% duty cycle if needed, making it well
• Adjustable Soft-Start or Optional Voltage Tracking suited for high-performance industrial control, robotic,
• Fast Line and Load Transient Response datacom, and RF power amplifier applications.
– Voltage-Mode Control With Line Feedforward Forced-PWM (FPWM) operation eliminates frequency
– High Gain-Bandwidth Error Amplifier variation to minimize EMI, while a user-selectable
diode emulation feature lowers current consumption
• Precision Enable Input and Open-Drain Power at light-load conditions. Cycle-by-cycle overcurrent
Good Indicator for Sequencing and Control protection is accomplished by measuring the voltage
• Inherent Protection Features for Robust Design drop across the low-side MOSFET or by using an
– Hiccup Mode Overcurrent Protection optional current sense resistor. The adjustable
switching frequency as high as 1 MHz can be
– Input UVLO With Hysteresis synchronized to an external clock source to eliminate
– VCC and Gate Drive UVLO Protection beat frequencies in noise-sensitive applications.
– Thermal Shutdown Protection With Hysteresis
Device Information(1)
• VQFN-20 Package With Wettable Flanks
PART NUMBER PACKAGE BODY SIZE (NOM)
• Create a Custom Design Using the LM5145 With
LM5145 VQFN (20) 3.50 mm × 4.50 mm
WEBENCH® Power Designer
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit and Efficiency Performance, VOUT = 5 V

VIN EN
VIN
VOUT
VIN EN/UVLO Q1
SYNC In SYNCIN HO
RC2 SYNC Out SYNCOUT

RFB1 CC1 BST
LF
CC3 COMP CBST VOUT
RC1 CC2 SW
FB LM5145 Q2
LO
RT CIN COUT
RFB2 VCC
RRT SS/TRK
CSS CVCC
AGND PGND
PGOOD ILIM GND
PG RILIM
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5145
SNVSAI4 – JUNE 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 25
2 Applications ........................................................... 1 9 Application and Implementation ........................ 27
3 Description ............................................................. 1 9.1 Application Information............................................ 27
4 Revision History..................................................... 2 9.2 Typical Applications ................................................ 36
5 Description (continued)......................................... 3 10 Power Supply Recommendations ..................... 52
6 Pin Configuration and Functions ......................... 4 11 Layout................................................................... 53
6.1 Wettable Flanks ........................................................ 5 11.1 Layout Guidelines ................................................. 53
11.2 Layout Example .................................................... 56
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6 12 Device and Documentation Support ................. 58
7.2 ESD Ratings.............................................................. 6 12.1 Device Support .................................................... 58
7.3 Recommended Operating Conditions....................... 7 12.2 Documentation Support ........................................ 58
7.4 Thermal Information .................................................. 7 12.3 Related Links ........................................................ 59
7.5 Electrical Characteristics........................................... 7 12.4 Receiving Notification of Documentation Updates 59
7.6 Switching Characteristics ........................................ 10 12.5 Community Resources.......................................... 59
7.7 Typical Characteristics ............................................ 11 12.6 Trademarks ........................................................... 59
12.7 Electrostatic Discharge Caution ............................ 59
8 Detailed Description ............................................ 16
12.8 Glossary ................................................................ 59
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 17
Information ........................................................... 59
4 Revision History
DATE REVISION NOTES
June 2017 * Initial release
SPACER
2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LM5145

LM5145
www.ti.com SNVSAI4 – JUNE 2017
5 Description (continued)
The LM5145 voltage-mode controller drives external high-side and low-side N-channel power switches with
robust 7.5-V gate drivers suitable for standard-threshold MOSFETs. Adaptively-timed gate drivers with 2.3-A
source and 3.5-A sink capability minimize body diode conduction during switching transitions, reducing switching
losses and improving thermal performance when driving MOSFETs at high input voltage and high frequency. The
LM5145 can be powered from the output of the switching regulator or another available source, further improving
efficiency.
A 180° out-of-phase clock output relative to the internal oscillator at SYNCOUT is ideal for cascaded or multi-
channel power supplies to reduce input capacitor ripple current and EMI filter size. Additional features of the
LM5145 include a configurable soft-start, an open-drain Power Good monitor for fault reporting and output
monitoring, monotonic start-up into prebiased loads, integrated VCC bias supply regulator and bootstrap diode,
external power supply tracking, precision enable input with hysteresis for adjustable line undervoltage lockout
(UVLO), hiccup-mode overload protection, and thermal shutdown protection with automatic recovery.
The LM5145 controller is offered in a 3.5-mm × 4.5-mm thermally-enhanced, 20-pin VQFN package with
additional spacing for high-voltage pins and wettable flanks for optical inspection of solder joint fillets.
Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 3

LM5145
6 Pin Configuration and Functions
RGY Package
20-Pin VQFN With Wettable Flanks
Top View
EN/UVLO
VIN
20
1
RT 2 19 SW
SS/TRK 3 18 HO
COMP 4 17 BST
FB 5 Exposed 16 NC
Pad
(EP)
AGND 6 15 EP
SYNCOUT 7 14 VCC
SYNCIN 8 13 LO
NC 9 12 PGND
10
11
PGOOD
ILIM
Connect Exposed Pad on bottom to AGND and PGND on the PCB.
Pin Functions
PIN
TYPE (1) DESCRIPTION
NO. NAME
Enable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the
controller is in the shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V
and less than 1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin
grounded, and no switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK
1 EN/UVLO I
pin is allowed to ramp and pulse-width modulated gate drive signals are delivered to the HO and LO pins. A
10-μA current source is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO
resistor divider to provide hysteresis. Hysteresis can be adjusted by varying the resistance of the external
divider.
Oscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and
2 RT I the AGND. The recommended maximum oscillator frequency is 1 MHz. An RT pin resistor is required even
when using the SYNCIN pin to synchronize to an external clock.
Soft-start and voltage tracking pin. An external capacitor and an internal 10-μA current source set the ramp
rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the
SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V,
the amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby
and fault conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB
3 SS/TRK I
falls due to a load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery
when the fault is removed. Voltage tracking can be implemented by connecting a low impedance reference
between 0 V and 0.8 V to the SS/TRK pin. The 10-µA SS/TRK charging current flows into the reference
and produces a voltage error if the impedance is not low. Connect a minimum capacitance from SS/TRK to
AGND of 2.2 nF.
Low impedance output of the internal error amplifier. The loop compensation network should be connected
4 COMP O
between the COMP pin and the FB pin.
Feedback connection to the inverting input of the internal error amplifier. A resistor divider from the output
5 FB I
to this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V.
(1) P = Power, G = Ground, I = Input, O = Output.


LM5145
Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NO. NAME
6 AGND P Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.
Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-
side FET gate drive. Connect SYNCOUT of the master LM5145 to the SYNCIN pin of a second LM5145 to
7 SYNCOUT O operate two controllers at the same frequency with 180° interleaved high-side FET switch turnon
transitions. Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating
from an external clock that is different from the free-running frequency set by the RT resistor.
Dual function pin for providing an optional clock input and for enabling diode emulation by the low-side
MOSFET. Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode
emulation by the low-side MOSFET is disabled when the controller is synchronized to an external clock,
and negative inductor current can flow in the low-side MOSFET with light loads. A continuous logic low
state at the SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode
8 SYNCIN I
emulation results in DCM operation at light loads, which improves efficiency. A logic high state at the
SYNCIN pin disables diode emulation producing forced-PWM (FPWM) operation. During soft-start when
SYNCIN is high or a clock signal is present, the LM5145 operates in diode emulation mode until the output
is in regulation, then gradually increases the SW zero-cross threshold, resulting in a gradual transition from
DCM to FPWM.
9 NC — No electrical connection.
Power Good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin
10 PGOOD O
is within a specified tolerance window centered at 0.8 V.
Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an
external resistor programs the threshold voltage for valley current limiting. The opposite end of the
11 ILIM I
threshold adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing
or to a current sense resistor connected to the source of the low-side FET.
Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-
12 PGND P
side MOSFET or the ground side of a shunt resistor.
Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through
13 LO P
a short, low inductance path.
Output of the 7.5-V bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as
close to the controller as possible. Controller bias can be supplied from an external supply that is greater
14 VCC O than the internal VCC regulation voltage. Use caution when applying external bias to ensure that the
applied voltage is not greater than the minimum VIN voltage and does not exceed the VCC pin maximum
operating rating, see Recommended Operating Conditions.
15 EP — Pin internally connected to exposed pad of the package. Electrically isolated.
16 NC — No electrical connection.
Bootstrap supply for the high-side gate driver. Connect to the bootstrap capacitor. The bootstrap capacitor
supplies current to the high-side FET gate and should be placed as close to controller as possible. If an
17 BST O
external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the
cathode of the diode to the BST pin and anode to VCC.
High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low
18 HO P
inductance path.
Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-
19 SW P
side MOSFET and the drain terminal of the low-side MOSFET using short, low inductance paths.
20 VIN P Supply voltage input for the VCC LDO regulator.
Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal
— EP —
resistance.
6.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high
reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins
and terminals that are easily viewed. It is therefore difficult to determine visually whether or not the package is
successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve
the issue of side-lead wetting of leadless packaging. The LM5145 is assembled using a 20-pin VQFN package
with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and
manufacturing costs.

LM5145
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted). (1)
MIN MAX UNIT
VIN –0.3 105
SW –1 105
SW (20-ns transient) –5 105
ILIM –1 105
Input voltages V
EN/UVLO –0.3 105
VCC –0.3 14
FB, COMP, SS/TRK, RT –0.3 6
SYNCIN –0.3 14
BST –0.3 115
BST to VCC 105
BST to SW –0.3 14
Output voltages V
VCC to BST (20-ns transient) 7
LO (20-ns transient) –3
PGOOD –0.3 14
Operating junction temperature, TJ 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

LM5145
7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted). (1)
MIN NOM MAX UNIT
VIN 6 75
SW –1 75
VI Input voltages ILIM –1 75 V
External VCC bias rail 8 13
EN/UVLO 0 75
BST –0.3 88
BST to VCC 75
VO Output voltages V
BST to SW 5 13
PGOOD 13
ISINK, SYNCOUT –1 1
Sink/source currents mA
ISRC PGOOD 2
TJ Operating junction temperature –40 125 °C
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
7.4 Thermal Information

LM5145
(1)
THERMAL METRIC RGY (VQFN) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 36.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 28 °C/W
RθJB Junction-to-board thermal resistance 11.8 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 11.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated. (1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Operating input voltage range 6 75 V
IQ-RUN Operating input current, not switching VEN/UVLO = 1.5 V, VSS/TRK = 0 V 1.8 2.1 mA
IQ-STBY Standby input current VEN/UVLO = 1 V 1.75 2 mA
IQ-SDN Shutdown input current VEN/UVLO = 0 V, VVCC < 1 V 13.5 16 µA
VCC REGULATOR
VSS/TRK = 0 V, 9 V ≤ VVIN ≤ 75 V,
VVCC VCC regulation voltage 7.3 7.5 7.7 V
0 mA < IVCC ≤ 20 mA
VVCC-LDO VIN to VCC dropout voltage VVIN = 6 V, VSS/TRK = 0 V, IVCC = 20 mA 0.25 0.63 V
ISC-LDO VCC short-circuit current VSS/TRK = 0 V, VVCC = 0 V 40 50 70 mA
VVCC-UV VCC undervoltage threshold VVCC rising 4.8 4.93 5.2 V
VVCC-UVH VCC undervoltage hysteresis Rising threshold – falling threshold 0.26 V
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in Thermal Information.
LM5145
Electrical Characteristics (continued)

range unless otherwise stated. VIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1)(2)
VVCC-EXT Minimum external bias supply voltage Voltage required to disable VCC regulator 8 V
External VCC input current, not
IVCC VSS/TRK = 0 V, VVCC = 13 V 2.1 mA
switching
ENABLE AND INPUT UVLO
VSDN Shutdown to standby threshold VEN/UVLO rising 0.42 V
VSDN-HYS Shutdown threshold hysteresis EN/UVLO rising – falling threshold 50 mV
VEN Standby to operating threshold VEN/UVLO rising 1.164 1.2 1.236 V
Standby to operating hysteresis
IEN-HYS VEN/UVLO = 1.5 V 9 10 11 µA
current
ERROR AMPLIFIER
VREF FB reference voltage FB connected to COMP 792 800 808 mV
IFB-BIAS FB input bias current VFB = 0.8 V –0.1 0.1 µA
VCOMP-OH COMP output high voltage VFB = 0 V, COMP sourcing 1 mA 5 V
VCOMP-OL COMP output low voltage COMP sinking 1 mA 0.3 V
AVOL DC gain 94 dB
GBW Unity gain bandwidth 6.5 MHz
SOFT-START AND VOLTAGE TRACKING
ISS SS/TRK capacitor charging current VSS/TRK = 0 V 8.5 10 12 µA
RSS SS/TRK discharge FET resistance VEN/UVLO = 1 V, VSS/TRK = 0.1 V 11 Ω
VSS-FB SS/TRK to FB offset –15 15 mV
VSS-CLAMP SS/TRK clamp voltage VSS/TRK – VFB, VFB = 0.8 V 115 mV
POWER GOOD INDICATOR
FB upper threshold for PGOOD high
PGUTH % of VREF, VFB rising 106% 108% 110%
to low
FB lower threshold for PGOOD high
PGLTH % of VREF, VFB falling 90% 92% 94%
to low
PGHYS_U PGOOD upper threshold hysteresis % of VREF 3%
PGHYS_L PGOOD lower threshold hysteresis % of VREF 2%
TPG-RISE PGOOD rising filter FB to PGOOD rising edge 25 µs
TPG-FALL PGOOD falling filter FB to PGOOD falling edge 25 µs
VPG-OL PGOOD low state output voltage VFB = 0.9 V, IPGOOD = 2 mA 150 mV
IPG-OH PGOOD high state leakage current VFB = 0.8 V, VPGOOD = 13 V 100 nA
OSCILLATOR
FSW1 Oscillator Frequency – 1 RRT = 100 kΩ 100 kHz
FSW2 Oscillator Frequency – 2 RRT = 25 kΩ 380 400 420 kHz
FSW3 Oscillator Frequency – 3 RRT = 12.5 kΩ 780 kHz
SYNCHRONIZATION INPUT AND OUTPUT
SYNCIN external clock frequency
FSYNC % of nominal frequency set by RRT –20% +50%
range
VSYNC-IH Minimum SYNCIN input logic high 2 V
VSYNC-IL Maximum SYNCIN input logic low 0.8 V
RSYNCIN SYNCIN input resistance VSYNCIN = 3 V 20 kΩ
TSYNCI-PW SYNCIN input minimum pulsewidth Minimum high state or low state duration 50 ns
VSYNCO-OH SYNCOUT high state output voltage ISYNCOUT = –1 mA (sourcing) 3 V
VSYNCO-OL SYNCOUT low state output voltage ISYNCOUT = 1 mA (sinking) 0.4 V
Delay from HO rising to SYNCOUT VSYNCIN = 0 V, TS = 1/FSW,
TSYNCOUT TS/2 – 140 ns
leading edge FSW set by RRT

LM5145
Electrical Characteristics (continued)

range unless otherwise stated. VIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated.(1)(2)
Delay from SYNCIN leading edge to
TSYNCIN 50% to 50% 150 ns
HO rising
BOOTSTRAP DIODE AND UNDERVOLTAGE THRESHOLD
VBST-FWD Diode forward voltage, VCC to BST VCC to BST, BST pin sourcing 20 mA 0.75 0.9 V
BST to SW quiescent current, not
IQ-BST VSS/TRK = 0 V, VSW = 48 V, VBST = 54 V 80 µA
switching
VBST-UV BST to SW undervoltage detection VBST – VSW falling 3.4 V
VBST-HYS BST to SW undervoltage hysteresis VBST – VSW rising 0.42 V
PWM CONTROL
TON(MIN) Minimum controllable on-time VBST – VSW = 7 V, HO 50% to 50% 40 60 ns
TOFF(MIN) Minimum off-time VBST – VSW = 7 V, HO 50% to 50% 140 200 ns
DC100kHz FSW = 100 kHz, 6 V ≤ VVIN ≤ 60 V 98% 99%
Maximum duty cycle
DC400kHz FSW = 400 kHz, 6 V ≤ VVIN ≤ 60 V 90% 94%
Ramp valley voltage (COMP at 0%
VRAMP(min) 300 mV
duty cycle)
kFF PWM feedforward gain (VIN / VRAMP) 6 V ≤ VVIN ≤ 75 V 15 V/V
OVERCURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING
IRS ILIM source current, RSENSE mode Low voltage detected at ILIM 90 100 110 µA
IRDSON ILIM source current, RDS(on) mode SW voltage detected at ILIM, TJ = 25°C 180 200 220 µA
IRSTC ILIM current tempco RDS-ON mode 4500 ppm/°C
IRDSONTC ILIM current tempco RSENSE mode 0 ppm/°C
VILIM-TH ILIM comparator threshold at ILIM –8 –2 3.5 mV
SHORT-CIRCUIT PROTECT (SCP) – DUTY CYCLE CLAMP
Clamp offset voltage – no current
VCLAMP-OS CLAMP to COMP steady state offset voltage 0.2 + VVIN/75 V
limiting
VCLAMP-MIN Minimum clamp voltage CLAMP voltage with continuous current limiting 0.3 + VVIN/150 V
HICCUP MODE FAULT PROTECTION
Clock cycles with current limiting before hiccup
CHICC-DEL Hiccup mode activation delay 128 cycles
off-time activated
Clock cycles with no switching followed by
CHICCUP Hiccup mode off-time after activation 8192 cycles
SS/TRK release
DIODE EMULATION
Zero-cross detect (ZCD) soft-start ZCD threshold measured at SW pin
VZCD-SS 0 mV
ramp 50 clock cycles after first HO pulse
Zero-cross detect disable threshold ZCD threshold measured at SW pin
VZCD-DIS 200 mV
(CCM) 1000 clock cycles after first HO pulse
VDEM-TH Diode emulation zero-cross threshold Measured at SW with VSW rising –5 0 5 mV
GATE DRIVERS
RHO-UP HO high-state resistance, HO to BST VBST – VSW = 7 V, IHO = –100 mA 1.5 Ω
RHO-DOWN HO low-state resistance, HO to SW VBST – VSW = 7 V, IHO = 100 mA 0.9 Ω
RLO-UP LO high-state resistance, LO to VCC VBST – VSW = 7 V, ILO = –100 mA 1.5 Ω
RLO-DOWN LO low-state resistance, LO to PGND VBST – VSW = 7 V, ILO = 100 mA 0.9 Ω
IHOH, ILOH HO, LO source current VBST – VSW = 7 V, HO = SW, LO = AGND 2.3 A
IHOL, ILOL HO, LO sink current VBST – VSW = 7 V, HO = BST, LO = VCC 3.5 A
THERMAL SHUTDOWN
TSD Thermal shutdown threshold TJ rising 175 °C
TSD-HYS Thermal shutdown hysteresis 20 °C

LM5145
7.6 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted).
THO-TR
HO, LO rise times VBST – VSW = 7 V, CLOAD = 1 nF, 20% to 80% 7 ns
TLO-TR
THO-TF
HO, LO fall times VBST – VSW = 7 V, CLOAD = 1 nF, 80% to 20% 4 ns
TLO-TF
THO-DT HO turnon dead time VBST – VSW = 7 V, LO off to HO on, 50% to 50% 14 ns
TLO-DT LO turnon dead time VBST – VSW = 7 V, HO off to LO on, 50% to 50% 14 ns

LM5145
7.7 Typical Characteristics

VVIN = 48 V, RRT = 25 kΩ, SYNCIN tied to VCC, EN/UVLO tied to VIN (unless otherwise noted).
100 100
95 90
80
90
Efficiency (%)
Efficiency (%)
70
85
60
80
VIN = 12V 50 VIN = 12V
75 VIN = 24V VIN = 24V
VIN = 36V 40 VIN = 36V
VIN = 48V VIN = 48V
70 VIN = 60V 30 VIN = 60V
VIN = 75V VIN = 75V
65 20
0 5 10 15 20 0.1 0.5 1 5 10 20
Output Current (A) Output Current (A)
VOUT = 5 V VSYNCIN = VVCC FSW = 230 kHz VOUT = 5 V VSYNCIN = 0 V FSW = 230 kHz
See Figure 46 RRT = 43.2 kΩ See Figure 46 RRT = 43.2 kΩ
Figure 1. Efficiency vs Load, CCM Figure 2. Efficiency vs Load, DCM

100 100
95
95
90
Efficiency (%)
Efficiency (%)
90
85
85
80
VIN = 14V
VIN = 18V VIN = 36V
80 VIN = 24V VIN = 48V
75
VIN = 36V VIN = 60V
VIN = 48V VIN = 75V
75 70
0 2 4 6 8 10 0 1 2 3 4 5
Output Current (A) Output Current (A)
VOUT = 12 V FSW = 400 kHz VOUT = 24 V FSW = 440 kHz
See Figure 59 RRT = 24.9 kΩ See Figure 72 RRT = 22.6 kΩ
Figure 3. Efficiency vs Load, CCM Figure 4. Efficiency vs Load, CCM

100 0.808
0.806
80
0.804
Feedback Voltage (V)
Efficiency (%)
60 0.802
0.8
40 0.798
VIN = 6V
VIN = 12V 0.796
20 VIN = 24V
VIN = 36V 0.794
VIN = 48V
0 0.792
0 2 4 6 8 10 -40 -25 -10 5 20 35 50 65 80 95 110 125
Output Current (A) Junction Temperature (°C)
VOUT = 1.1 V FSW = 300 kHz
See Figure 85 RRT = 33.2 kΩ
Figure 5. Efficiency vs Load, CCM Figure 6. FB Voltage vs Junction Temperature

LM5145
Typical Characteristics (continued)

160 40
VIN Shutdown Quiescent Current (PA)

140
Min On-Time, Min Off-Time (ns)
120 30
100
80 20
60
40 10
20
TOFF(min) TON(min) 40°C 25°C 125°C
0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 0 20 40 60 80 100
Junction Temperature (°C) Input Voltage (V)
VSW = 0 V VEN/UVLO = 0 V
Figure 7. TON(min) and TOFF(min) vs Junction Temperature Figure 8. IQ-SHD vs Input Voltage
2.2 2.2
VIN Operating Quiescent Current (mA)

VIN Standby Quiescent Current (mA)
2 2
1.8 1.8
1.6 1.6
40°C 25°C 125°C 40°C 25°C 125°C

1.4 1.4
0 20 40 60 80 100 0 20 40 60 80 100
Input Voltage (V) Input Voltage (V)
VSW = 0 V VEN/UVLO = 1 V VSW = 0 V VEN/UVLO = VVIN VSS/TRK = 0 V
Figure 9. IQ-STANDBY vs Input Voltage Figure 10. IQ-OPERATING (Nonswitching) vs Input Voltage
4 0.6
Switching (mA)
VIN Operating Quiescent Current (mA)
3.75 0.5
3.5 0.4
VIN Operating Current
3.25 0.3
3 0.2
2.75 0.1
40°C 25°C 125°C VCC = 8V

2.5 0
0 20 40 60 80 100 0 20 40 60 80 100
Input Voltage (V) Input Voltage (V)
VSW = 0 V HO, LO Open VSW = 0 V VVCC = VBST = VILIM VFB = 0 V
Figure 11. IQ-OPERATING (Switching) vs Input Voltage Figure 12. VIN Quiescent Current With External VCC Applied

LM5145

350 25
300
20
ILIM Current Source (PA)
250
Deadtime (ns)
15
200
150
10
100
5
50 RDS-ON Mode HO to LO
RSENSE Mode LO to HO
0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C) Junction Temperature (°C)
VSW = 0 V
Figure 13. ILIM Current Source vs Junction Temperature Figure 14. Dead Time vs Junction Temperature
5.2 4
5 3.8
VCC UVLO Threshold (V)
BST UVLO Threshold (V)
4.8 3.6
4.6 3.4
4.4 3.2
Rising Rising
Falling Falling
4.2 3
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 15. VCC UVLO Thresholds vs Junction Temperature Figure 16. BST UVLO Thresholds vs Junction Temperature
98 110
PGOOD OVP Thresholds (V)
PGOOD UVP Thresholds (V)
96 108
94 106
92 104
90 102
Rising Rising
Falling Falling
88 100
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 17. PGOOD UVP Thresholds vs Junction Figure 18. PGOOD OVP Thresholds vs Junction
Temperature Temperature

LM5145

1.3 0.5
1.25 0.45
EN Standby Threshold (V)

EN Threshold (V)
1.2 0.4
1.15 0.35
1.1 0.3
Rising
Falling
1.05 0.25
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 19. EN/UVLO Threshold vs Junction Temperature Figure 20. EN Standby Thresholds vs Junction Temperature
1000 420
800
Switching Frequency (kHz)
Switching Frequency (kHz)

410
600
400
400
390
200 VIN = 6V
VIN = 48V
VIN = 100V
0 380
0 10 20 30 40 50 60 70 80 90 100 -40 -25 -10 5 20 35 50 65 80 95 110 125
RT Resistance (k:) Junction Temperature (°C)
VSW = 0 V
Figure 21. Oscillator Frequency vs RT Resistance Figure 22. Oscillator Frequency vs Junction Temperature
1 4
LO, HO Gate Driver Peak Current (A)
BST Diode Forward Voltage (V)
3.5
0.9
3
0.8
2.5
0.7
2
0.6
1.5
Source
VCC = 8V Sink
0.5 1
0 10 20 30 40 50 6 7 8 9 10 11 12 13
BST Diode Forward Current (mA) VCC Voltage (V)
Figure 23. BST Diode Forward Voltage vs Current Figure 24. Gate Driver Peak Current vs VCC Voltage

LM5145

1.6 1.6
1.4 1.4
HO Gate Driver RDS(on) (:)
LO Gate Driver RDS(on) (:)

1.2 1.2
1 1
0.8 0.8
High State High State
Low State Low State
0.6 0.6
6 7 8 9 10 11 12 13 6 7 8 9 10 11 12 13
VCC Voltage (V) VCC Voltage (V)
Figure 25. HO Driver Resistance vs VCC Voltage Figure 26. LO Driver Resistance vs VCC Voltage
7.75 7
7.5 6
7.25
5
VCC Voltage (V)
VCC Voltage (V)
7
4
6.75
3
6.5
2
6.25
6 1
40°C 25°C 125°C 40°C 25°C 125°C
5.75 0
0 20 40 60 80 100 0 10 20 30 40 50 60
Input Voltage (V) VCC Current (mA)
VSS/TRK = 0 V VIN = 6 V
Figure 27. VCC Voltage vs Input Voltage Figure 28. VCC vs ICC Characteristic
8 11
7 10.8
10.6
6
Soft-Start Current (PA)
10.4
VCC Voltage (V)
5
10.2
4 10
3 9.8
9.6
2
9.4
1 9.2
40°C 25°C 125°C
0 9
0 10 20 30 40 50 60 -40 -25 -10 5 20 35 50 65 80 95 110 125
VCC Current (mA) Junction Temperature (°C)
VIN = 12 V
Figure 29. VCC vs ICC Characteristic Figure 30. SS/TRK Current Source vs Junction Temperature

LM5145
8 Detailed Description
8.1 Overview
The LM5145 is a 75-V synchronous buck controller that features all of the functions necessary to implement a
high efficiency step-down power supply with output voltage ranging from 0.8 V to 60 V. The voltage-mode control
architecture uses input feedforward for excellent line transient response over a wide VIN range. Voltage-mode
control supports the wide duty cycle range for high input voltage and low dropout applications as well as when a
high voltage conversion ratio (for example, 10-to-1) is required. Current sensing for cycle-by-cycle current limit
can be implemented with either the low-side FET RDS(on) or a current sense resistor. The operating frequency is
programmable from 100 kHz to 1 MHz. The LM5145 drives external high-side and low-side NMOS power
switches with robust 7.5-V gate drivers suitable for standard threshold MOSFETs. Adaptive dead-time control
between the high-side and low-side drivers is designed to minimize body diode conduction during switching
transitions. An external bias supply can be connected to the VCC pin to improve efficiency in high-voltage
applications. A user-selectable diode emulation feature enables discontinuous conduction mode operation for
improved efficiency and lower dissipation at light-load conditions.
8.2 Functional Block Diagram
VIN VCC
7.5 V LDO +
REGULATOR VCC
± 7.5 V
UVLO
VCC ENABLE ± BST
SHUTDOWN
+ VVCC-UV
0.4 V +
EN/UVLO ± ENABLE
LOGIC BST_UV
1.2 V
±
+ 5 µs STANDBY ³1´ D R
± FILTER +
VSW +
VBST-UV
CL Q
kFF*VIN THERMAL
HYSTERESIS
SHUTDOWN
RT OSCILLATOR & LEVEL DRIVER HO

CLK SHIFT
FEEDFORWARD
SYNCOUT RAMP
GENERATOR
kFF*VIN + 0.3 V ADAPTIVE SW

DEADTIME
RAMP PWM
PEAK PWM DELAY VCC
LOGIC
SYNCIN DETECT COMPARATOR
FILTER FPWM 0.3 V
+ DRIVER LO
COMP ±
PGND
ERROR
AMP
FB ±
115 mV
± +
+ 0.8 V +
+
±
+ ZERO CROSS
± DETECTION
CLAMP
SS/TRK
COMP
CLAMP
STANDBY MODULATOR
HICCUP
CLK
COUNTERS
SUPERVISORY RDS(on) or ILIM
COMPARATORS ± 0.8 V + 8% Resistor Sensing LO
PGOOD +
25 µs FB LO
OCP ± ILIM
delay
±
+ AGND
+ 0.8 V - 8% CURRENT LIMIT
COMPARATOR
Copyright © 2017, Texas Instruments Incorporated

LM5145
8.3 Feature Description

8.3.1 Input Range (VIN)
The LM5145 operational input voltage range is from 6 V to 75 V. The device is intended for step-down
conversions from 12-V, 24-V, 48-V, 60-V and 72-V unregulated, semiregulated, and fully-regulated supply rails.
The application circuit of Figure 31 shows all the necessary components to implement an LM5145-based wide-
VIN step-down regulator using a single supply. The LM5145 uses an internal LDO subregulator to provide a 7.5-V
VCC bias rail for the gate drive and control circuits (assuming the input voltage is higher than 7.5 V plus the
necessary subregulator dropout specification).
RUV2 RUV1
VOUT
VIN
1 20
RC2 CBST
RFB1 RRT EN/UVLO VIN Q1
2 RT BST 17
CC3
3 SS/TRK HO 18
CC1
RC1 CSS
LF
4 COMP SW 19
5 FB NC 16 VOUT
CC2
LM5145 Q2
6 AGND EP 15
RFB2 SYNC
out 7 SYNCOUT CIN COUT
VCC 14
8 SYNCIN LO 13
SYNC 12
ILIM PGND GND
9 NC
PGOOD
optional 10 11
CVCC
RPG
PG RILIM
CILIM
Figure 31. Schematic Diagram for VIN Operating Range of 6 V to 75 V
In high voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 105 V during line or load transient events. Voltage ringing on the VIN pin that exceeds the
Absolute Maximum Ratings can damage the IC. Use high-quality ceramic input capacitors to minimize ringing.
An RC filter from the input rail to the VIN pin (for example, 4.7 Ω and 0.1 µF) provides supplementary filtering at
the VIN pin.
8.3.2 Output Voltage Setpoint and Accuracy (FB)

The reference voltage at the FB pin is set at 0.8 V with a feedback system accuracy over the full junction
temperature range of ±1%. Junction temperature range for the device is –40°C to +125°C. While dependent on
switching frequency and load current levels, the LM5145 is generally capable of providing output voltages in the
range of 0.8 V to a maximum of 60 V or slightly less than VIN, whichever is lower. The DC output voltage
setpoint during normal operation is set by the feedback resistor network, RFB1 and RFB2, connected to the output.
8.3.3 High-Voltage Bias Supply Regulator (VCC)

The LM5145 contains an internal high-voltage VCC regulator that provides a bias supply for the PWM controller
and its gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an input voltage
source up to 75 V. The output of the VCC regulator is set to 7.5 V. However, when the input voltage is below the
VCC setpoint level, the VCC output tracks VIN with a small voltage drop. Connect a ceramic decoupling capacitor
between 1 µF and 5 µF from VCC to AGND for stability.

LM5145
Feature Description (continued)

The VCC regulator output has a current limit of 40 mA (minimum). At power up, the regulator sources current into
the capacitor connected to the VCC pin. When the VCC voltage exceeds its rising UVLO threshold of 4.93 V, the
output is enabled (if EN/UVLO is above 1.2 V) and the soft-start sequence begins. The output remain active until
the VCC voltage falls below its falling UVLO threshold of 4.67 V (typical) or if EN/UVLO goes to a standby or
shutdown state.
Internal power dissipation of the VCC regulator can be minimized by connecting the output voltage or an auxiliary
bias supply rail (up to 13 V) to VCC using a diode DVCC as shown in Figure 32. A diode in series with the input
prevents reverse current flow from VCC to VIN if the input voltage falls below the external VCC rail.
LM5145
Required if VIN < VCC(EXT)
DVIN DVCC
VIN 20 VIN VCC 14 VCC-EXT
6 V to 75 V 8 V to 13 V
CVIN CVCC
0.1 PF 2.2 PF
AGND
6
Figure 32. VCC Bias Supply Connection From VOUT or Auxiliary Supply
Note that a finite bias supply regulator dropout voltage exists and is manifested to a larger extent when driving
high gate charge (QG) power MOSFETs at elevated switching frequencies. For example, at VVIN = 6 V, the VCC
voltage is 5.8 V with a DC operating current, IVCC, of 20 mA. Such a low gate drive voltage may be insufficient to
fully enhance the power MOSFETs. At the very least, MOSFET on-state resistance, RDS(ON), may increase at
such low gate drive voltage.
Here are the main considerations when operating at input voltages below 7.5 V:
• Increased MOSFET RDS(on) at lower VGS, leading to Increased conduction losses and reduced OCP setpoint.
• Increased switching losses given the slower switching times when operating at lower gate voltages.
• Restricted range of suitable power MOSFETs to choose from (MOSFETs with RDS(on) rated at VGS = 4.5 V
become mandatory).
8.3.4 Precision Enable (EN/UVLO)

The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by the
resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a
comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the
EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way to
enable the operation of the LM5145 is to connect EN/UVLO directly to VIN. This allows self start-up of the
LM5145 when VCC is within its valid operating range. However, many applications benefit from using a resistor
divider RUV1 and RUV2 as shown in Figure 33 to establish a precision UVLO level.
Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turnon and turnoff
voltages.
VIN(on) VIN(off)
RUV1
IHYS (1)
VEN
RUV2 RUV1 ˜
VIN(on) VEN (2)

LM5145
LM5145 vcc
VIN
10 A
RUV1
EN/UVLO
1
RUV2
Remote 1.2V Enable
Shutdown Comparator
Figure 33. Programmable Input Voltage UVLO Turnon and Turnoff
The LM5145 enters a low IQ shutdown mode when EN/UVLO is pulled below approximately 0.4 V. The internal
LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the
LM5145. The LM5145 operates in standby mode when the EN/UVLO voltage is between the hard shutdown and
precision enable (standby) thresholds.
8.3.5 Power Good Monitor (PGOOD)

The LM5145 provides a PGOOD flag pin to indicate when the output voltage is within a regulation window. Use
the PGOOD signal as shown in Figure 34 for start-up sequencing of downstream converters, fault protection, and
output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than
13 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease
the voltage from a higher voltage pullup rail.
VIN(on) = 15 V
VIN(off) = 10 V
VOUT(MASTER) = 5 V VOUT(SLAVE) = 3.3 V
LM5145 LM5145
RUV1
499 k PGOOD 10 PGOOD 10
RFB1 RPG RFB3
1 EN/UVLO 20 k 20 k 1 EN/UVLO 20 k
RUV2 FB FB
5 0.8 V 5 0.8 V
43.2 k
RFB2 RFB4
3.83 k 6.34 k
Regulator #1 Regulator #2
Start-up based on Sequential Start-up
Input Voltage UVLO based on PGOOD
Figure 34. Master-Slave Sequencing Implementation Using PGOOD and EN/UVLO
When the FB voltage exceeds 94% of the internal reference VREF, the internal PGOOD switch turns off and
PGOOD can be pulled high by the external pullup. If the FB voltage falls below 92% of VREF, the internal PGOOD
switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. Similarly, when
the FB voltage exceeds 108% of VREF, the internal PGOOD switch turns on, pulling PGOOD low. If the FB
voltage subsequently falls below 105% of VREF, the PGOOD switch is turned off and PGOOD is pulled high.
PGOOD has a built-in deglitch delay of 25 µs.

LM5145

8.3.6 Switching Frequency (RT, SYNCIN)
There are two options for setting the switching frequency, FSW, of the LM5145, thus providing a power supply
designer with a level of flexibility when choosing external components for various applications. To adjust the
frequency, use a resistor from the RT pin to AGND, or synchronize the LM5145 to an external clock signal
through the SYNCIN pin.
8.3.6.1 Frequency Adjust

Adjust the LM5145 free-running switching frequency by using a resistor from the RT pin to AGND. The switching
frequency range is from 100 kHz to 1 MHz. The frequency set resistance, RRT, is governed by Equation 3. E96
standard-value resistors for common switching frequencies are given in Table 1.
4
10
RRT ª¬k: º¼
FSW ª¬kHz º¼ (3)
Table 1. Frequency Set Resistors

SWITCHING FREQUENCY FREQUENCY SET RESISTANCE
(kHz) (kΩ)
100 100
200 49.9
250 40.2
300 33.2
400 24.9
500 20
750 13.3
1000 10
8.3.6.2 Clock Synchronization

Apply an external clock synchronization signal to the LM5145 to synchronize switching in both frequency and
phase. Requirements for the external clock SYNC signal are:
• Clock frequency range: 100 kHz to 1 MHz
• Clock frequency: –20% to +50% of the free-running frequency set by RRT
• Clock maximum voltage amplitude: 13 V
• Clock minimum pulse width: 50 ns
VSW 10 V/DIV
VSYNCIN
2 V/DIV
1 Ps/DIV
Figure 35. Typical 400-kHz SYNCIN and SW Voltage Waveforms

LM5145
Figure 35 shows a clock signal at 400 kHz and the corresponding SW node waveform (VIN = 48 V, VOUT = 5 V,
free-running frequency = 280 kHz). The SW voltage waveform is synchronized with respect to the rising edge of
SYNCIN. The rising edge of the SW voltage is phase delayed relative to SYNCIN by approximately 100 ns.
8.3.7 Configurable Soft-Start (SS/TRK)

After the EN/UVLO pin exceeds its rising threshold of 1.2 V, the LM5145 begins charging the output to the DC
level dictated by the feedback resistor network. The LM5145 features an adjustable soft-start (set by a capacitor
from the SS/TRK pin to GND) that determines the charging time of the output. A 10-µA current source charges
this soft-start capacitor. Soft-start limits inrush current as a result of high output capacitance to avoid an
overcurrent condition. Stress on the input supply rail is also reduced. The soft-start time, tSS, for the output
voltage to ramp to its nominal level is set by Equation 4.
CSS ˜ VREF
t SS
ISS
where
• CSS is the soft-start capacitance
• VREF is the 0.8-V reference
• ISS is the 10-µA current sourced from the SS/TRK pin. (4)
More simply, calculate CSS using Equation 5.
CSS ¬ªnF ¼º 12.5 ˜ t SS ¬ªms ¼º (5)
The SS/TRK pin is internally clamped to VFB + 115 mV to allow a soft-start recovery from an overload event. The
clamp circuit requires a soft-start capacitance greater than 2 nF for stability and has a current limit of
approximately 2 mA.
8.3.7.1 Tracking
The SS/TRK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This
tracking is achieved by simply dividing down the output voltage of the master with a simple resistor network.
Coincident, ratiometric, and offset tracking modes are possible.
If an external voltage source is connected to the SS/TRK pin, the external soft-start capability of the LM5145 is
effectively disabled. The regulated output voltage level is reached when the SS/TRACK pin reaches the 0.8-V
reference voltage level. It is the responsibility of the system designer to determine if an external soft-start
capacitor is required to keep the device from entering current limit during a start-up event. Likewise, the system
designer must also be aware of how fast the input supply ramps if the tracking feature is enabled.
SS/TRK
160mV/DIV
94% VOUT 92% VOUT
VOUT 1V/DIV
PGOOD
2V/DIV
10 ms/DIV
Figure 36. Typical Output Voltage Tracking and PGOOD Waveforms

LM5145
Figure 36 shows a triangular voltage signal directly driving SS/TRK and the corresponding output voltage
tracking response. Nominal output voltage here is 5 V, with oscilloscope channel scaling chosen such that the
waveforms overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 94% (rising) and
92% (falling) of the nominal output voltage setpoint.
Two practical tracking configurations, ratiometric and coincident, are shown in Figure 37. The most common
application is coincident tracking, used in core versus I/O voltage tracking in DSP and FPGA implementations.
Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the
slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the output voltage of the slave
to a fraction of the output voltage of the master during start-up.
VOUTMASTER = 3.3 V
Slave Regulator #1 Slave Regulator #2

Ratiometric Tracking VOUTSLAVE1 = 1.8 V Coincident Tracking VOUTSLAVE2 = 1.2 V
LM5145 LM5145
RTRK1 RFB1 RTRK3 RFB3
26.7 k 12.5 k 10 k 10 k
3 SS/TRK FB 5 0.8 V 3 SS/TRK FB 5 0.8 V
RTRK2 CSS1 RTRK4 CSS2

RFB2 RFB4
10 k 20 k
2.2 nF 10 k 2.2 nF 20 k
SYNCIN SYNCIN
8 8
SYNCOUT
from Master
Figure 37. Tracking Implementation With Master, Ratiometric Slave, and Coincident Slave Rails
For coincident tracking, connect the SS/TRK input of the slave regulator to a resistor divider from the output
voltage of the master that is the same as the divider used on the FB pin of the slave. In other words, simply
select RTRK3 = RFB3 and RTRK4 = RFB4 as shown in Figure 37. As the master voltage rises, the slave voltage rises
identically (aside from the 80-mV offset from SS/TRK to FB when VFB is below 0.8 V). Eventually, the slave
voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the
SS/TRK input continues to 115 mV above FB, and no longer controls the output voltage.
In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRK voltage being too
close to the 0.8-V reference voltage, the final value of the SS/TRK voltage of the slave should be at least 100 mV
above FB.
8.3.8 Voltage-Mode Control (COMP)

The LM5145 incorporates a voltage-mode control loop implementation with input voltage feedforward to eliminate
the input voltage dependence of the PWM modulator gain. This configuration allows the controller to maintain
stability throughout the entire input voltage operating range and provides for optimal response to input voltage
transient disturbances. The constant gain provided by the controller greatly simplifies loop compensation design
because the loop characteristics remain constant as the input voltage changes, unlike a buck converter without
voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage
amplitude to maintain constant modulator gain. The input voltage feedforward gain, kFF, is 15, equivalent to the
input voltage divided by the ramp amplitude, VIN/VRAMP. See Control Loop Compensation for more detail.

LM5145
8.3.9 Gate Drivers (LO, HO)

The LM5145 gate driver impedances are low enough to perform effectively in high output current applications
where large die-size or paralleled MOSFETs with correspondingly large gate charge, QG, are used. Measured at
VVCC = 7.5 V, the low-side driver of the LM5145 has a low impedance pulldown path of 0.9 Ω to minimize the
effect of dv/dt induced turnon, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side
driver has 1.5-Ω and 0.9-Ω pullup and pulldown impedances, respectively, for faster switching transition times,
lower switching loss, and greater efficiency.
The high-side gate driver works in conjunction with an integrated bootstrap diode and external bootstrap
capacitor, CBST. When the low-side MOSFET conducts, the SW voltage is approximately at 0 V and CBST is
charged from VCC through the integrated boot diode. Connect a 0.1-μF or larger ceramic capacitor close to the
BST and SW pins.
Furthermore, there is a proprietary adaptive dead-time control on both switching edges to prevent shoot-through
and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery losses.
8.3.10 Current Sensing and Overcurrent Protection (ILIM)

The LM5145 implements a lossless current sense scheme designed to limit the inductor current during an
overload or short-circuit condition. Figure 38 portrays the popular current sense method using the on-state
resistance of the low-side MOSFET. Meanwhile, Figure 39 shows an alternative implementation with current
shunt resistor, RS. The LM5145 senses the inductor current during the PWM off-time (when LO is high).
VIN VIN
Q1 Q1
HO HO LF
LF VOUT
VOUT
SW
SW
RILIM Q2
ILIM LO
COUT
COUT ILIM
Q2 RILIM
LO RS
GND GND
Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated
Figure 38. MOSFET RDS(on) Current Sensing Figure 39. Shunt Resistor Current Sensing
The ILIM pin of the LM5145 sources a reference current that flows in an external resistor, designated RILIM, to
program of the current limit threshold. A current limit comparator on the ILIM pin prevents further SW pulses if
the ILIM pin voltage goes below GND. Figure 40 shows the implementation.
Resistor RILIM is tied to SW to use the RDS(on) of the low-side MOSFET as a sensing element (termed RDS-ON
mode). Alternatively, RILIM is tied to a shunt resistor connected at the source of the low-side MOSFET (termed
RSENSE mode). The LM5145 detects the appropriate mode at start-up and sets the source current amplitude and
temperature coefficient (TC) accordingly.
The ILIM current with RDS-ON sensing is 200 µA at 27°C junction temperature and incorporates a TC of +4500
ppm/°C to generally track the RDS(on) temperature variation of the low-side MOSFET. Conversely, the ILIM
current is a constant 100 µA in RSENSE mode. This controls the valley of the inductor current during a steady-
state overload at the output. Depending on the chosen mode, select the resistance of RILIM using Equation 6.

LM5145
- IOUT 'IL 2
° I ˜ RDS(on)Q2 , RDS(on) sensing
° RDSON
RILIM ®
° IOUT 'IL 2
° ˜ RS , shunt sensing
¯ IRS
where
• ΔIL is the peak-to-peak inductor ripple current
• RDS(on)Q2 is the on-state resistance of the low-side MOSFET
• IRDSON is the ILIM pin current in RDS-ON mode
• RS is the resistance of the current-sensing shunt element, and
• IRS is the ILIM pin current in RSENSE mode. (6)
Given the large voltage swings of ILIM in RDS-ON mode, a capacitor designated CILIM connected from ILIM to
PGND is essential to the operation of the valley current limit circuit. Choose this capacitance such that the time
constant RILIM · CILIM is approximately 6 ns.
VIN
CLK S Q
ValleyPWM
R Q
COMP
PWML HO
Q1
Error Amp IRAMP
FB LF
PWM Comp S Q
Gate SW VOUT
+ Driver
VREF + R Q
VRAMP PWM
Latch Q2
LO
COUT
RILIM
ILIM
IRDSON(TJ)
+
± 300 mV
+ CILIM
PWM Aux
COMP +
ILIM
Clamp VCLAMP PGND GND
comparator
Modulator
Figure 40. OCP Setpoint Defined by Current Source IRDSON and Resistor RILIM in RDS-ON Mode
Note that current sensing with a shunt component is typically implemented at lower output current levels to
provide accurate overcurrent protection. Burdened by the unavoidable efficiency penalty, PCB layout, and
additional cost implications, this configuration is not usually implemented in high-current applications (except
where OCP setpoint accuracy and stability over the operating temperature range are critical specifications).

LM5145
8.3.11 OCP Duty Cycle Limiter

Short
Applied
CLAMP
COMP Many
cycles
RAMP
300 mV
ILIM Threshold
Inductor Current
CLK
PWML
ValleyPWM
PWML terminated by PWML terminated by

VRAMP > VCOMP VRAMP > VCLAMP
Figure 41. OCP Duty Cycle Limiting Waveforms
In addition to valley current limiting, the LM5145 uses a proprietary duty-cycle limiter circuit to reduce the PWM
on-time during an overcurrent condition. As shown in Figure 40, an auxiliary PWM comparator along with a
modulated CLAMP voltage limits how quickly the on-time increases in response to a large step in the COMP
voltage that typically occurs with a voltage-mode control loop architecture.
As depicted in Figure 41, the CLAMP voltage, VCLAMP, is normally regulated above the COMP voltage to provide
adequate headroom during a response to a load-on transient. If the COMP voltage rises quickly during an
overloaded or shorted output condition, the on-time pulse terminates thereby limiting the on-time and peak
inductor current. Moreover, the CLAMP voltage is reduced if additional valley current limit events occur, further
reducing the average output current.
If the overcurrent condition exists for 128 continuous clock cycles, a hiccup event is triggered and SS is pulled
low for 8192 clock cycles before a soft-start sequence is initiated.
8.4 Device Functional Modes

8.4.1 Shutdown Mode
The EN/UVLO pin provides ON / OFF control for the LM5145. When the EN/UVLO voltage is below 0.37 V
(typical), the device is in shutdown mode. Both the internal bias supply LDO and the switching regulator are off.
The quiescent current in shutdown mode drops to 13.5 μA (typical) at VIN = 48 V. The LM5145 also includes
undervoltage protection of the internal bias LDO. If the internal bias supply voltage is below its UVLO threshold
level, the switching regulator remains off.
8.4.2 Standby Mode

The internal bias supply LDO has a lower enable threshold than the switching regulator. When the EN/UVLO
voltage exceeds 0.42 V (typical) and is below the precision enable threshold (1.2 V typically), the internal LDO is
on and regulating. Switching action and output voltage regulation are disabled in standby mode.

LM5145
Device Functional Modes (continued)

8.4.3 Active Mode
The LM5145 is in active mode when the VCC voltage is above its rising UVLO threshold of 5 V and the
EN/UVLO voltage is above the precision EN threshold of 1.2 V. The simplest way to enable the LM5145 is to tie
EN/UVLO to VIN. This allows self start-up of the LM5145 when the input voltage exceeds the VCC threshold plus
the LDO dropout voltage from VIN to VCC.
8.4.4 Diode Emulation Mode

The LM5145 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current
flow in the low-side MOSFET. When configured for diode emulation, the low-side MOSFET is switched off when
reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this
configuration is lower power loss at no-load and light-load conditions, the disadvantage being slower light-load
transient response.
The diode emulation feature is configured with the SYNCIN pin. To enable diode emulation and thus achieve
discontinuous conduction mode (DCM) operation at light loads, connect the SYNCIN pin to AGND or leave
SYNCIN floating. If forced PWM (FPWM) continuous conduction mode (CCM) operation is desired, tie SYNCIN
to VCC either directly or using a pullup resistor. Note that diode emulation mode is automatically engaged to
prevent reverse current flow during a prebias start-up. A gradual change from DCM to CCM operation provides
monotonic start-up performance.
8.4.5 Thermal Shutdown

The LM5145 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical),
thermal shutdown occurs.
When entering thermal shutdown, the device:
1. Turns off the low-side and high-side MOSFETs;
2. Pulls SS/TRK and PGOOD low;
3. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of
20°C (typical).
This is a non-latching protection, and, as such, the device will cycle into and out of thermal shutdown if the fault
persists.

LM5145
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

9.1.1 Design and Implementation
To expedite the process of designing of a LM5145-based regulator for a given application, please use the
LM5145 Quickstart Calculator available as a free download, as well as numerous LM5145 reference designs
populated in TI Designs™ reference design library, or the designs provided in Typical Applications. The LM5145
is also WEBENCH® Designer enabled.
9.1.2 Power Train Components

Comprehensive knowledge and understanding of the power train components are key to successfully completing
a synchronous buck regulator design.
9.1.2.1 Inductor
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 40%
of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 7 based on a
peak inductor current given by Equation 8.
VOUT §V VOUT ·
LF ˜ ¨ IN ¸
VIN © 'IL ˜ FSW ¹ (7)
'IL
IL(peak) IOUT
2 (8)
Check the inductor datasheet to ensure that the saturation current of the inductor is well above the peak inductor
current of a particular design. Ferrite designs have very low core loss and are preferred at high switching
frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core
loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core
materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not
to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally deceases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
9.1.2.2 Output Capacitors

Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series
resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient
response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and
noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact
footprint for transient loading events.
Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by Equation 9.

LM5145
Application Information (continued)

'IL
COUT t
2 2
8 ˜ FSW 'VOUT RESR ˜ 'IL
(9)
Figure 42 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to
match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of
charge in the output capacitor, which must be replenished as rapidly as possible during and after the load step-
up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current
adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
diL VOUT
dt LF
'IOUT inductor current, iL(t)
'QC
IOUT2
load current,
iOUT(t)
diOUT 'IOUT
dt tramp
inductor current, iL(t)
IOUT2
'QC
diL VIN VOUT
'IOUT
dt LF load current, iOUT(t)
IOUT1
tramp
Figure 42. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 48-V input to low output voltage (for example, 5 V), it should be recognized
that the load-off transient represents worst-case. In that case, the steady-state duty cycle is approximately 10%
and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –VOUT/L.
Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The
surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete
this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its
nominal level following the load step. In this scenario, a large output capacitance can be advantageously
employed to absorb the excess charge and limit the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger than
2
LF ˜ 'IOUT
COUT t 2 2
VOUT 'VOVERSHOOT VOUT (10)
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors
have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some
parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and
ESL contributions at the switching frequency, and the capacitive impedance component dominates. However,
depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite
significantly with applied DC voltage and operating temperature.

LM5145

Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary to
meet the output ripple specification. One to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a
common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the load-off
transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and
ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance
provides low-frequency energy storage to cope with load transient demands.
9.1.2.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-
frequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in
the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and
the source of the low-side MOSFET. The input capacitor RMS current is given by Equation 11.
§ 2 'IL ·
2
ICIN,rms D ˜ ¨ IOUT ˜ 1 D ¸
¨ 12 ¸
© ¹ (11)
The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the
capacitors should be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT −
IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by Equation 12.
IOUT ˜ D ˜ 1 D
'VIN IOUT ˜ RESR
FSW ˜ CIN (12)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 13.
D ˜ 1 D ˜ IOUT
CIN t
FSW ˜ 'VIN RESR ˜ IOUT (13)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with
high-Q ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2-μF 100-V X7R
ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current
rating and operating temperature.
9.1.2.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC-DC regulator performance. A MOSFET with low on-
state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition
times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate charge and
output charge (QG and QOSS respectively), and vice versa. As a result, the product RDS(on) × QG is commonly
specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power dissipation
does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in an LM5145 application are as follows:
• RDS(on) at VGS = 7.5 V;
• Drain-source voltage rating, BVDSS, typically 60 V, 80 V or 100 V, depending on maximum input voltage;

LM5145

• Gate charge parameters at VGS = 7.5 V;
• Output charge, QOSS, at the relevant input voltage;
• Body diode reverse recovery charge, QRR;
• Gate threshold voltage, VGS(th), derived from the plateau in the QG vs. VGS plot in the MOSFET data sheet.
With a MOSFET Miller plateau voltage typically in the range of 3 V to 5 V, the 7.5-V gate drive amplitude of
the LM5145 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt shoot-through
when off.
The MOSFET-related power losses are summarized by the equations presented in Table 2, where suffixes 1 and
2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple
current is considered, second-order loss modes, such as those related to parasitic inductances and SW node
ringing, are not included. Consult the LM5145 Quickstart Calculator to assist with power loss calculations.
Table 2. Buck Regulator MOSFET Power Losses

POWER LOSS MODE HIGH-SIDE MOSFET LOW-SIDE MOSFET
§ 2
2
'IL· § 2 'IL ·
2
MOSFET Pcond1 D ˜ ¨ IOUT ¸ ˜ RDS(on)1 Pcond2 Dc ˜ ¨ IOUT ¸ ˜ RDS(on)2
Conduction (1) (2) ¨ 12 ¸ ¨ 12 ¸
© ¹ © ¹
ª§ 'IL · § 'IL · º
MOSFET Switching Psw1 VIN ˜ FSW «¨ IOUT ¸ ˜ tR ¨ IOUT ¸ ˜ tF » Negligible
¬© 2 ¹ © 2 ¹ ¼
MOSFET Gate Drive (3) PGate1 VCC ˜ FSW ˜ QG1 PGate2 VCC ˜ FSW ˜ QG2
MOSFET Output PCoss FSW ˜ VIN ˜ Qoss2 Eoss1 Eoss2
Charge (4)
Body Diode ª§ 'IL · § 'IL · º

N/A PcondBD VF ˜ FSW «¨ IOUT ¸ ˜ t dt1 ¨ IOUT ¸ ˜ t dt2 »
Conduction ¬© 2 ¹ © 2 ¹ ¼
Body Diode PRR VIN ˜ FSW ˜ QRR2
Reverse Recovery (5)
(1) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance.
(2) D' = 1–D is the duty cycle complement.
(3) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally-added series gate resistance and the
relevant driver resistance of the LM5145.
(4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the
inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance
of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this is offset by the stored energy Eoss2 on Coss2.
(5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition speed
and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically
incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances
conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of
the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the
net loss attributed to body diode reverse recovery.
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D
interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just
commutates from the channel to the body diode or vice versa during the transition dead-times. The LM5145, with
its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses
scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM5145 is well suited to drive TI's comprehensive portfolio of NexFET™ power
MOSFETs.

LM5145
9.1.3 Control Loop Compensation

The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue
dashed rings in the schematic embedded in Table 3.
The compensation network typically employed with voltage-mode control is a Type-III circuit with three poles and
two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation
strategy uses two compensator zeros to counteract the LC double pole, one compensator pole located to nullify
the output capacitor ESR zero, with the remaining compensator pole located at one-half switching frequency to
attenuate high frequency noise. The resistor divider network to FB determines the desired output voltage. Note
that the lower feedback resistor, RFB2, has no impact on the control loop from an AC standpoint because the FB
node is the input to an error amplifier and is effectively at AC ground. Hence, the control loop is designed
irrespective of output voltage level. The proviso here is the necessary output capacitance derating with bias
voltage and temperature.
Table 3. Buck Regulator Poles and Zeros (1) (2)

VIN
Power Stage
Q1
&L &o
D
Adaptive VOUT
Gate LF
&ESR
RDAMP IOUT
Driver RESR
Q2
Modulator RL
COUT
PWM Ramp
VRAMP GND
Compensator
Error
Amp VREF CC3 &p2 RC2
COMP +
+ FB
PWM
Comparator
CC1 &z1 RC1
RFB1 &z2
RFB2
CC2 &p1
POWER STAGE POLES POWER STAGE ZEROS COMPENSATOR POLES COMPENSATOR ZEROS
1 1 1 1
Zo ZESR Zp1 Zz1
§ 1 RESR RL · RESR ˜ COUT RC2 ˜ CC3 RC1 ˜ CC1
LF ˜ COUT ¨ ¸
© 1 RESR RDAMP ¹ LF 1 1 1
1 ZL Zp2 # Zz2
# RDAMP RC1 ˜ (CC1 CC2 ) RC1 ˜ CC2 (RFB2 RC2 ) ˜ CC3
LF ˜ COUT
(1) RESR represents the ESR of the output capacitor COUT.

(2) RDAMP = D · RDS(on)high-side + (1–D) · RDS(on) low-side + RDCR, shown as a lumped element in the schematic, represents the effective series
damping resistance.
The small-signal open-loop response of a buck regulator is the product of modulator, power train and
compensator transfer functions. The power stage transfer function can be represented as a complex pole pair
associated with the output LC filter and a zero related to the ESR of the output capacitor. The DC (and low
frequency) gain of the modulator and power stage is VIN/VRAMP. The gain from COMP to the average voltage at
the input of the LC filter is held essentially constant by the PWM line feedforward feature of the LM5145 (15 V/V
or 23.5 dB).

LM5145
Complete expressions for small-signal frequency analysis are presented in Table 4. The transfer functions are
denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by
its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio
susceptibility.
Table 4. Buck Regulator Small-Signal Analysis

TRANSFER FUNCTION EXPRESSION
vÖ comp (s) vÖ o (s) Ö
d(s)
Open-loop transfer function Tv (s) ˜ ˜ Gc (s) ˜ Gvd (s) ˜ FM
vÖ o (s) Ö
d(s) vÖ comp (s)
s
1
vÖ o (s) ZESR
Gvd (s) VIN
Duty-cycle-to-output transfer function Ö
d(s) vÖ in (s)0 s s
2
Öi (s) 0
o
1 2
QoZo Zo
§ Zz1 · § s ·
vÖ comp (s) ¨1 s ¸ ¨1 Z ¸
© ¹© z2 ¹
Compensator transfer function (1) Gc (s) K mid
vÖ o (s) § s ·§ s ·
¨1 ¸¨ 1 ¸
¨ Zp1 ¸¨ Zp2 ¸
© ¹© ¹
Ö
d(s) 1
Modulator transfer function FM
vÖ comp (s) VRAMP
(1) Kmid = RC1/RFB1 is the mid-band gain of the compensator. By expressing one of the compensator zeros in inverted zero format, the mid-
band gain is denoted explicitly.
An illustration of the open-loop response gain and phase is given in Figure 43. The poles and zeros of the
system are marked with x and o symbols, respectively, and a + symbol indicates the crossover frequency. When
plotted on a log (dB) scale, the open-loop gain is effectively the sum of the individual gain components from the
modulator, power stage, and compensator (see Figure 44). The open-loop response of the system is measured
experimentally by breaking the loop, injecting a variable-frequency oscillator signal and recording the ensuing
frequency response using a network analyzer setup.
40 0
Loop Complex
Gain LC Double
Pole
Crossover -45
20 Frequency, fc
Compensator Loop
Loop Compensator Poles
-90 Phase
Gain 0 Zeros (°)
(dB) Loop
Phase
NM
-20 -135
Output
Capacitor
ESR Zero
-40 -180
1 10 100 1000
Frequency (kHz)
Figure 43. Typical Buck Regulator Loop Gain and Phase With Voltage-Mode Control
If the pole located at ωp1 cancels the zero located at ωESR and the pole at ωp2 is located well above crossover,
the expression for the loop gain, Tv(s) in Table 4, can be manipulated to yield the simplified expression given in
Equation 14.

LM5145
2
VIN Zo
Tv (s) RC1 ˜ CC3 ˜ ˜
VRAMP s (14)
Essentially, a multi-order system is reduced to a single-order approximation by judicious choice of compensator
components. A simple solution for the crossover frequency, denoted as fc in Figure 43, with Type-III voltage-
mode compensation is derived as shown in Equation 15 and Equation 16.
V
Zc 2 S ˜ fc Zo ˜ K mid ˜ IN
VRAMP (15)
fc 1 RC1
K mid ˜
fo kFF RFB1 (16)
40
Loop Gain Modulator Compensator
Gain Gain
20
Gain
(dB)
0
-20
Filter Gain
-40
1 10 fc 100 1000
Frequency (kHz)
Figure 44. Buck Regulator Constituent Gain Components
The loop crossover frequency is usually selected between one-tenth to one-fifth of switching frequency. Inserting
an appropriate crossover frequency into Equation 15 gives a target for the mid-band gain of the compensator,
Kmid. Given an initial value for RFB1, RFB2 is then selected based on the desired output voltage. Values for RC1,
RC2, CC1, CC2 and CC3 are calculated from the design expressions listed in Table 5, with the premise that the
compensator poles and zeros are set as follows: ωz1 = 0.5·ωo, ωz2 = ωo, ωp1 = ωESR, ωp2 = ωSW/2.
Table 5. Compensation Component Selection

RESISTORS CAPACITORS
RFB1 2
RFB2 CC1
VOUT VREF 1 Zz1 ˜ RC1
1
RC1 K mid ˜ RFB1 CC2
Zp2 ˜ RC1
1 1
RC2 CC3
Zp1 ˜ CC3 Zz2 ˜ RFB1
Referring to the bode plot in Figure 43, the phase margin, indicated as φM, is the difference between the loop
phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase
boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole (hence why
CC1 is scaled by a factor of 2 above). This helps mitigate the phase dip associated with the LC filter, particularly
at light loads when the Q-factor is higher and the phase dip becomes especially prominent. The ramification of
low phase in the frequency domain is an under-damped transient response in the time domain.

LM5145
The power supply designer now has all the necessary expressions to optimally position the loop crossover
frequency while maintaining adequate phase margin over the required line, load and temperature operating
ranges. The LM5145 Quickstart Calculator is available to expedite these calculations and to adjust the bode plot
as needed.
9.1.4 EMI Filter Design

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An
underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the
filter output impedance must be less than the absolute value of the converter input impedance.
2
VIN(min)
ZIN
PIN
(17)
The EMI filter design steps are as follows:
• Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the
existing capacitance at the input of the switching converter;
• Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a
high current design;
• Calculate input filter capacitor CF.
LIN
VIN Q1
LF
CD
VOUT
CF CIN
Q2 COUT
RD
GND GND
Figure 45. Buck Regulator With π-Stage EMI Filter
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by Equation 18.
§ I ·
Attn 20log ¨ 2 PEAK ˜ 1 9 ¸ ˜ VLQ S ˜ 'MAX 9MAX
¨ S ˜F ˜ C ¸
© SW IN ¹ (18)
VMAX is the allowed dBμV noise level for the applicable EMI standard, for example EN55022 Class B. CIN is the
existing input capacitance of the buck regulator, DMAX is the maximum duty cycle, and IPEAK is the peak inductor
current. For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI
filter capacitance CF from Equation 19.
2
§ Attn ·
1 ¨ 10 40 ¸
CF ¨ ¸
LIN ¨ 2S ˜ FSW ¸
¨ ¸
© ¹ (19)
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop
gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the
filter is given by Equation 20.

LM5145
1
fres
2S ˜ LIN ˜ CF (20)
The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD should
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added damping is
needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and
CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 21.
CD t 4 ˜ CIN (21)
Select the damping resistor RD using Equation 22.
LIN
RD
CIN (22)

LM5145
9.2 Typical Applications
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of
an LM5145-powered implementation, please refer to TI Designs reference design library.
9.2.1 Design 1 – 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications
Figure 46 shows the schematic diagram of a 5-V, 20-A buck regulator with a switching frequency of 230 kHz. In
this example, the target half-load and full-load efficiencies are 93.5% and 92.5%, respectively, based on a
nominal input voltage of 48 V that ranges from 7 V to 72 V. The switching frequency is set by means of a
synchronization input signal at 230 kHz, and the free-running switching frequency (in the event that the
synchronization signal is removed) is set at 200 kHz by resistor RRT. In terms of control loop performance, the
target loop crossover frequency is 35 kHz with a phase margin greater than 50°. The output voltage soft-start
time is 4 ms.
RUV2 RUV1
11.3 k 49.9 k
VIN = 7 V to 72 V
CVIN
0.1 F
VOUT
U1
1 20 CBST
RC2 RRT
0.1 F
1k RFB1 49.9 k EN/UVLO VIN Q1
23.2 k 2 RT BST 17
CC3 CSS
1.8 nF RC1 CC1 3 SS/TRK HO 18
11 k 4.7 nF 47 nF LF
4 COMP SW 19 3.3 H
VOUT = 5 V
5 FB NC 16
CC2 150 pF
LM5145 Q2
6 AGND EP 15
RFB2
4.42 k SYNC Out 7 SYNCOUT CIN COUT CBULK
VCC 14
7 u 4.7 F 7 u 47 F 220 F
8 SYNCIN LO 13
SYNC In 12
ILIM PGND
9 NC
PGOOD
GND
230 kHz 10 11
CVCC
2.2 F
RPG
PGOOD 20 k RILIM
CILIM 422
15 pF
Figure 46. Application Circuit #1 With LM5145 48-V to 5-V, 20-A Buck Regulator at 230 kHz
NOTE
This and subsequent design examples are provided herein to showcase the LM5145
controller in several different applications. Depending on the source impedance of the
input supply bus, an electrolytic capacitor may be required at the input to ensure stability,
particularly at low input voltage and high output current operating conditions. See Power
Supply Recommendations for more detail.

LM5145
9.2.1.1 Design Requirements

The intended input, output, and performance-related parameters pertinent to this design example are shown in
Table 6.
Table 6. Design Parameters

DESIGN PARAMETER VALUE
Input voltage range (steady state) 7 V to 72 V
Input transient voltage (peak) 80 V
Output voltage and current 5 V, 20 A
Input voltage UVLO thresholds 6.5 V on, 6 V off
Switching frequency (SYNC in) 230 kHz
Output voltage regulation ±0.5%
Load transient peak voltage deviation < 100 mV
9.2.1.2 Detailed Design Procedure

The design procedure for an LM5145-based regulator for a given application is streamlined by using the LM5145
Quickstart Calculator available as a free download, or by availing of TI's WEBENCH® Power Designer. Such
tools are complemented by the availability of an LM5145 evaluation module (EVM) design, numerous PSPICE
models, as well as several LM5145 reference designs populated in the TI Designs reference design library.
The selected buck converter powertrain components are cited in Table 7, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching
power loss, as discussed in detail in Power MOSFETs.
The current limit setpoint in this design is set at 25 A based on the resistor RILIM and the 4-mΩ RDS(on) of the low-
side MOSFET (typical at TJ = 25°C and VGS = 7.5 V). This design uses a low-DCR, metal-powder inductor, and
composite ceramic–polymer electrolytic output capacitor implementation.
Table 7. List of Materials for Design 1

REFERENCE
QTY SPECIFICATION MANUFACTURER PART NUMBER
DESIGNATOR
TDK C3225X7R2A225M230AB
CIN 7 2.2 µF, 100 V, X7R, 1210, ceramic Murata GRM32ER72A225KA35L
Kemet C1210C225K1RACTU
Murata GRM32ER71A476KE15L
Taiyo Yuden LMK325B7476MM-TR
COUT 7 47 µF, 10 V, X7R, 1210, ceramic
AVX 1210ZC476KAT2A
Kemet C1210C476M8RAC7800
COUT(BULK) 1 220 µF, 6.3 V, 10 mΩ, polymer electrolytic Murata ECASD60J227M010K00
3.3 µH, 3.75 mΩ, 40 A, 13.45 × 12.6 × 6.3 mm Cyntec CMLS136E-3R3MS
LF 1
3.3 µH, 5.7 mΩ, 32 A, 12.5 × 12.5 × 6.2 mm Würth Electronik 744373965033
Q1 1 80 V, 12 mΩ, high-side MOSFET, SON 5 × 6 Infineon BSC117N08NS5
Q2 1 80 V, 4 mΩ, low-side MOSFET, SON 5 × 6 Infineon BSC037N08NS5
U1 1 Wide VIN synchronous buck controller Texas Instruments LM5145RGYR
9.2.1.3 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5145 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.

LM5145
In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.4 Application Curves
100
95
SW 10V/DIV
90 SYNCOUT
1V/DIV
Efficiency (%)
85
80
VIN = 12V
75 VIN = 24V
VIN = 36V
VIN = 48V
70 VIN = 60V
VIN = 75V
65
0 5 10 15 20 2 Ps/DIV
Output Current (A)
VIN = 48 V IOUT = 5 A
Figure 47. Efficiency and Power Loss vs IOUT and VIN Figure 48. SYNCOUT and SW Node Voltages
VIN 10V/DIV
VOUT 1V/DIV
VIN 2V/DIV
VOUT 1V/DIV
PGOOD PGOOD
2V/DIV IOUT 5A/DIV
2V/DIV
IOUT 5A/DIV
1 ms/DIV 400 Ps/DIV
VIN step to 48 V 0.25-Ω Load VIN 48 V to 6 V 0.25-Ω Load
Figure 49. Start-Up, 20-A Resistive Load Figure 50. Shutdown Through Input UVLO, 20-A Resistive
Load

LM5145
VOUT 1V/DIV
VOUT 1V/DIV
IOUT 5A/DIV
IOUT 5A/DIV
ENABLE PGOOD ENABLE

1V/DIV 2V/DIV 1V/DIV
PGOOD
2V/DIV
1 ms/DIV 40 Ps/DIV
VIN = 48 V 0.25-Ω Load VIN = 48 V 0.25-Ω Load
Figure 51. ENABLE ON, 20-A Resistive Load Figure 52. ENABLE OFF, 20-A Resistive Load
VOUT 200m/DIV VOUT 500m/DIV
IOUT 5A/DIV IOUT 5A/DIV
40 Ps/DIV 40 Ps/DIV
VIN = 48 V VIN = 48 V
Figure 53. Load Transient Response, 10 A to 20 A to 10 A Figure 54. Load Transient Response, 0 A to 20 A to 0 A
VOUT 50mV/DIV VOUT 50mV/DIV
VIN 20V/DIV
VIN 20V/DIV
20 ms/DIV 20 ms/DIV
IOUT = 10 A IOUT = 10 A
Figure 55. Line Transient Response, 12 V to 72 V Figure 56. Line Transient Response, 72 V to 12 V

LM5145
VOUT 1V/DIV SW 10V/DIV
VOUT
50mV/DIV
PGOOD
2V/DIV
VIN
10V/DIV
2 ms/DIV 2 Ps/DIV
VIN = 48 V IOUT = 0 A VIN = 48 V IOUT = 0 A
Figure 57. Pre-Biased Start-Up Figure 58. SW Node and Output Ripple Voltages

LM5145
9.2.2 Design 2 – High Density, 12-V, 10-A Rail With LDO Low-Noise Auxiliary Output for RF Power
Applications
Figure 59 shows the schematic diagram of a 400-kHz, 12-V output, 10-A synchronous buck regulator intended
for RF power applications.
An auxiliary 10-V, 800-mA rail to power noise-sensitive circuits is available using the LP38798 ultra-low noise
LDO as a post-regulator. The internal pull-up of the EN pin of the LP38798 facilitates direct connection to the
PGOOD of the LM5145 for sequential start-up control.
RUV2 RUV1
7.5 k 80.6 k
VIN = 14.4 V to 48 V
CVIN
VOUT
0.1 F
U1
RC2 RRT 1 20 RBST
100 RFB1 24.9 k 2.2
EN/UVLO VIN
33.2 k 2 RT BST 17
CC3 CSS Q1
680 pF
RC1 CC1 3 SS/TRK HO 18
15 k 3.3 nF 33 nF LF
CBST
4 COMP SW 19 4.7 H
0.1 F VOUT1 = 12 V
5 FB NC 16
CC2 56 pF
LM5145
6 AGND EP 15
RFB2
Q2
2.37 k 7 SYNCOUT CIN COUT
SYNC Out VCC 14
5 u 4.7 F 5 u 47 F
SYNC In 8 SYNCIN LO 13
12
ILIM PGND
9 NC
PGOOD
10 11 GND
D1
CVCC
2.2 F
CILIM RILIM
402
10 pF U2
VOUT2 = 10V
VOUT1 1 IN OUT 18
2 IN OUT 17
CLDO_IN 3 IN(CP) OUT(FB) 16 CV2

CCP RT
1 F 1 F
4 CP SET 15 73.5 k
10 nF
5 EN FB 14 RB
10 k
6 GND(CP) GND 13
LP38798SD-ADJ
Figure 59. Application Circuit #2 With LM5145 48-V to 12-V Synchronous Buck Regulator at 400 kHz

LM5145

The required input, output, and performance parameters for this application example are shown in Table 8.

Input voltage range (steady state) 14.4 V to 48 V
Input UVLO thresholds 14 V on, 13.2 V off
Switching frequency 400 kHz
Output voltage regulation ±1%
Load transient peak voltage deviation, 5-A load step < 120 mV

A high power density, high-efficiency regulator solution is realized by using TI NexFET™ Power MOSFETs, such
as CSD18563Q5A (60-V, 6-mΩ MOSFET in a SON 5-mm × 6-mm package), together with a low-DCR inductor
and all-ceramic capacitor design. The design occupies 30 mm × 15 mm on a single-sided PCB. The overcurrent
(OC) setpoint in this design is set at 14 A based on the resistor RILIM and the 6-mΩ RDS(on) of the low-side
MOSFET (typical at TJ = 25°C and VGS = 7.5 V). The 12-V output is connected to VCC through a diode, D1, to
reduce IC bias power dissipation.
The selected buck converter powertrain components are cited in Table 9, including power MOSFETs, buck
inductor, input and output capacitors, and ICs. Using the LM5145 Quickstart Calculator, compensation
components are selected based on a target loop crossover frequency of 40 kHz and phase margin greater than
55°. The output voltage soft-start time is 4 ms based on the selected soft-start capacitance, CSS, of 33 nF.

REFERENCE
DESIGNATOR
TDK C3225X7S2A475M
CIN 5 4.7 µF, 100 V, X7S, 1210, ceramic Murata GRM32DC72A475KE01L
Taiyo Yuden HMK325C7475MN-TE
Murata GRM32ER61C476KE15K
5 47 µF, 16 V, X5R, 1210, ceramic
Würth Electronik 885012109011
COUT Murata GRM32ER71E226KE15L
7 22 µF, 25 V, X7R, 1210, ceramic Taiyo Yuden TMK325B7226MM-TR
TDK C3225X7R1E226M
4.7 µH, 7.8 mΩ, 25 A, 13.45 × 12.6 × 6.3 mm Cyntec CMLS136E-4R7MS
LF 1 4.7 µH, 6.5 mΩ, 27 A, 12.5 × 12.5 × 6.2 mm Würth Electronik WE-LHMI 744373965047
4.7 µH, 9.75 mΩ, 25 A, 11.3 × 10 × 6 mm Coilcraft XAL1060-472ME
Q1, Q2 2 60 V, 6 mΩ, MOSFET, SON 5 × 6 Texas Instruments CSD18563Q5A
Ultra-low noise and high-PSRR LDO for RF and
U2 1 Texas Instruments LP38798SD-ADJ
analog circuits, 4-mm × 4-mm 12-pin WSON
As shown in Figure 59, a 2.2-Ω resistor in series with CBST is used to slow the turn-on transition of the high-side
MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of
Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and
100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate
any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI
and Voltage Stress by Minimizing Inductive Parasitics for more detail.

LM5145
9.2.2.2.1 Application Curves
100
VSW 10 V/DIV
95 VSYNCOUT
1 V/DIV
Efficiency (%)
90
85
VIN = 14V
VIN = 18V
80 VIN = 24V
VIN = 36V
VIN = 48V
75
0 2 4 6 8 10 1 Ps/DIV
Output Current (A)
Figure 60. Efficiency vs IOUT and VIN Figure 61. SYNCOUT and SW Node Voltages
VOUT 2V/DIV VOUT 2V/DIV
VIN 10V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
VIN 10V/DIV
PGOOD
2V/DIV
PGOOD
2V/DIV
1 ms/DIV 400 Ps/DIV
VIN step to 48 V 1.2-Ω Load 1.2-Ω Load
Load
VOUT 2V/DIV
VOUT 2V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
ENABLE PGOOD ENABLE

1 ms/DIV 100 Ps/DIV PGOOD 2V/DIV
VIN = 48 V 1.2-Ω Load VIN = 48 V 1.2-Ω Load

LM5145
VOUT 200m/DIV
VOUT 100m/DIV
100 Ps/DIV 100 Ps/DIV
VIN = 48 V VIN = 48 V
Figure 66. Load Transient Response, 5 A to 10 A to 5 A Figure 67. Load Transient Response, 0 A to 10 A to 0 A

VIN 10V/DIV
VIN 10V/DIV
2 ms/DIV 2 ms/DIV
VOUT 2V/DIV VSW 10 V/DIV
VSYNCIN
1 V/DIV
PGOOD
ENABLE 2V/DIV
1V/DIV
1 ms/DIV 400 ns/DIV
Figure 70. Pre-Biased Start-Up Figure 71. SW Node and SYNCIN Voltages

LM5145
9.2.3 Design 3 – 150-W, Regulated 24-V Rail for Commercial Drone Applications With Output Voltage
Tracking Feature
Figure 72 shows the schematic diagram of a 150-W, regulated 24-V buck regulator for commercial drone
applications with output voltage tracking feature.
VTRACK RUV2 RUV1
8.87 k 200 k
RTRK1 VIN = 28 V to 75 V
13.3 k CVIN
0.1 F
VOUT
RTRK2
2.49 k
U1
1 20 CBST
RC2 RRT
0.1 F
1k RFB1 22.6 k EN/UVLO VIN Q1
72.3 k 2 RT BST 17
CC3
RC1 CC1 SS/TRK
390 pF 3 HO 18
41.2 k 1 nF LF
4 COMP SW 19 15 H
VOUT = 24 V
5 FB NC 16
CC2 18 pF
LM5145 Q2
6 AGND EP 15
RFB2
2.49 k SYNC Out 7 SYNCOUT CIN COUT
VCC 14
5 u 2.2 F 7 u 10 F
SYNC In 8 SYNCIN LO 13
12
ILIM PGND
9 NC
PGOOD
GND
10 11
CVCC
2.2 F
RPG
PGOOD 20 k RILIM
CILIM 499
10 pF
Figure 72. Application Circuit #3 With LM5145 48-V to 24-V Buck Regulator at 440 kHz

The intended input, output, and performance parameters are shown in Table 10 for this implementation example
that derives power from large battery packs common to commercial drone and electric forklift applications.

Input voltage range (steady state) 28 V to 75 V
Load transient peak voltage deviation, 2.5-A load step < 100 mV

LM5145

Resistors RTRK1 and RTRK2 connected to the SS/TRK pin of the LM5145 define a ratiometric tracking start-up
sequence from a master power supply, VTRACK. The output voltage ramps from 0 V to its nominal 24-V setpoint
as the master supply ramps from 0 V to 5 V. See Tracking for more detail.
The selected buck converter power stage components are cited in Table 11. Note that additional input or output
capacitance can be included in this design as needed, but adjust the compensation circuit components if COUT
changes by availing of the LM5145 Quickstart Calculator.

REFERENCE
DESIGNATOR
TDK C3225X7S2A475M
CIN 5 2.2 µF, 100 V, X7R, 1210, ceramic Murata GRM32DC72A475KE01L
AVX 12101C225KAT2A
TDK C3225X7R1H106M
COUT 7 10 µF, 50 V, X7R, 1210, ceramic Murata GRM32ER71H106KA12L
AVX 12105C106KAT2A
15 µH, 24 mΩ, 10 A, 13.45 × 12.6 × 5.8 mm Cyntec CMLB136T-150MS
LF 1 15 µH, 24.4 mΩ, 10 A, 13.5 × 12.5 × 6.2 mm Würth Electronik WE LHMI 744373965150
15 µH, 18.6 mΩ, 15.5 A, 10.5 × 11.8 × 10.2 mm Coilcraft XAL1010-153ME
Q1, Q2 2 100 V, 13 mΩ, MOSFET, SON 5 × 6 Texas Instruments CSD19534Q5A
100
95 VSYNCOUT VSW 10 V/DIV

1 V/DIV
90
Efficiency (%)
85
80
VIN = 36V
75 VIN = 48V
VIN = 60V
VIN = 75V
70
0 1 2 3 4 5 1 Ps/DIV
Output Current (A)
Figure 73. Efficiency vs IOUT and VIN Figure 74. SW Node and SYNCOUT Voltages

LM5145
VOUT 5V/DIV
VIN 10V/DIV
VOUT 5V/DIV
VIN 20V/DIV

PGOOD
2V/DIV
PGOOD
2V/DIV
2 ms/DIV 200 Ps/DIV
VIN ramped to 60 V 5-Ω Load VIN 85 V to 48 V 5-Ω Load
Load
VOUT 5V/DIV
VOUT 5V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
ENABLE PGOOD ENABLE
1 ms/DIV 100 Ps/DIV PGOOD 2V/DIV
VIN = 60 V 5-Ω Load VIN = 60 V 5-Ω Load
VOUT 100m/DIV VOUT 200m/DIV
IOUT 2A/DIV
IOUT 2A/DIV
100 Ps/DIV 100 Ps/DIV
VIN = 48 V VIN = 48 V
Figure 79. Load Transient Response, 2.5 A to 5 A to 2.5 A Figure 80. Load Transient Response, 0 A to 5 A to 0 A

LM5145
VIN 20V/DIV VIN 20V/DIV
1 ms/DIV 10 ms/DIV
VSW 10 V/DIV
VOUT 5V/DIV
VSYNCIN
1 V/DIV
ENABLE PGOOD
1V/DIV 2V/DIV
1 ms/DIV IOUT 2A/DIV 400 ns/DIV
Figure 83. Pre-Biased Start-Up Figure 84. SW Node and SYNCIN Voltages at 600 kHz

LM5145
9.2.4 Design 4 – Powering a Multicore DSP From a 24-V or 48-V Rail
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's
Power House blog series.
Figure 85 shows the schematic diagram of a 10-A synchronous buck regulator for a DSP core voltage supply.
CVIN 0.1 F D1
VOUT VIN = 6 V to 48 V
U1
CBST
RC2 RRT 1 20
0.1 F
100 RFB1 33.2 k EN/UVLO VIN
6.81 k 2 RT BST 17
CC3 Q1
RC1 CC1 CSS
2.7 nF 3 SS/TRK HO 18
2.32 k 10 nF 47 nF LF
4 COMP SW 19 1 H
5 FB NC 16
CC2 470 pF
LM5145 Core voltage
6 AGND EP 15 0.9 V ± 1.1 V
RFB2 Q2
SYNC CIN Step resolution
18.2 k 7 SYNCOUT
Out VCC 14 5 u 2.2 F 6.4 mV
SYNC 8 SYNCIN LO 13
In
12
ILIM PGND
9 NC
PGOOD
10 11 VAUX = 8 V to 13 V
COUT
CILIM RILIM
CVCC 4 x 100 F
249
22 pF
2.2 F
U3
RPU1:4
U2 DVDD18 CVDD
1 GND VIDS 10 VCNTL[3]
3.3 V 2 IDAC_OUT VIDC 9 VCNTL[2] TMS320C667x

KeyStone¥
3 VDD VIDB 8 VCNTL[1] Multicore
DSP
4 EN VIDA 7 VCNTL[0]
5 MODE SET 6
RSET GND
LM10011SD 182 k
Figure 85. Application Circuit #4 With LM5145 DSP Core Voltage Supply

LM5145

For this application example, the intended input, output, and performance parameters are listed in Table 12.

Input voltage range (steady-state) 6 V to 48 V
Output voltage and current 0.9 V to 1.1 V, 10 A
Load transient peak voltage deviation, 10-A step < 120 mV

The schematic diagram of a 300-kHz, 24-V nominal input, 10-A regulator powering a KeyStone™ DSP is given in
Figure 85. This high step-down ratio design leverages the low 40-ns minimum controllable on-time of the LM5145
controller to achieve stable, efficient operation at very low duty cycles. 60-V power MOSFETs, such as TI's
CSD18543Q3A and CSD18531Q5A NexFET devices, are used together with a low-DCR, metal-powder inductor,
and ceramic output capacitor implementation. An external rail between 8 V and 13 V powers VCC to minimize
bias power dissipation, and a blocking diode connected to the VIN pin is used as recommended in Figure 32.
The important components for this design are listed in Table 13.

REFERENCE
DESIGNATOR
Murata GRM31CR72A225MA73L
5 2.2 µF, 100 V, X7R, 1206, ceramic
CIN Samsung CL31B225KCHSNNE
3 4.7 µF, 80 V, X7R, 1210, ceramic Murata GRM32ER71K475KE14L
Murata GRM32EC70J107ME15L
100 µF, 6.3V, X7S, 1210, ceramic
Taiyo Yuden JMK325AC7107MM-P
COUT 4 Murata GRM31CR60J107ME39K
100 µF, 6.3V, X5R, 1206, ceramic TDK C3216X5R0J107M
Würth Electronik 885012108005
1 µH, 5.6 mΩ, 16 A, 6.95 × 6.6 × 2.8 mm Cyntec CMLE063T-1R0MS
1 µH, 5.5 mΩ, 12 A, 6.65 × 6.45 × 3.0 mm Würth Electronik WE XHMI 74439344010
LF 1
1 µH, 7.9 mΩ, 16 A, 6.5 × 6.0 × 3.0 mm Panasonic ETQP3M1R0YFN
1 µH, 6.95 mΩ, 18 A, 6.76 × 6.56 × 3.1 mm Coilcraft XEL6030-102ME
Q1 1 60 V, 8.5 mΩ, high-side MOSFET, SON 3 × 3 Texas Instruments CSD18543Q3A
Q2 1 60 V, 4 mΩ, low-side MOSFET, SON 5 × 6 Texas Instruments CSD18531Q5A
U2 1 6- or 4-bit VID voltage programmer, WSON-10 Texas Instruments LM10011SD
U3 1 KeyStone™ DSP Texas Instruments TMS320C667x
The regulator output current requirements are dependent upon the baseline and activity power consumption of
the DSP in a real-use case. While baseline power is highly dependent on voltage, temperature and DSP
frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To
this end, the IDAC_OUT pin of the LM10011 connects to the LM5145 FB pin to allow continuous optimization of
the core voltage. The SmartReflex-enabled DSP provides 6-bit information using the VCNTL open-drain I/Os to
command the output voltage setpoint with 6.4-mV step resolution. (1)
(1) Refer to Hardware Design Guide for Keystone I Devices (SPRAB12) and How to Optimize Your DSP Power Budget for further detail.

LM5145
100
VOUT 0.2V/DIV
80 VIN 5V/DIV
Efficiency (%)
60
40
IOUT 5A/DIV
VIN = 6V
VIN = 12V
20 VIN = 24V PGOOD
VIN = 36V 2V/DIV
VIN = 48V
0
0 2 4 6 8 10 1 ms/DIV
Output Current (A)
VOUT = 1.1 V VAUX = 8 V VIN step to 24 V 0.11-Ω Load
Figure 86. Efficiency vs IOUT and VIN Figure 87. Start-Up, 10-A Resistive Load
VOUT 0.2V/DIV
VOUT 100m/DIV
ENABLE 1V/DIV
IOUT 5A/DIV
PGOOD
IOUT 2V/DIV
2A/DIV
1 ms/DIV 40 Ps/DIV
VIN = 24 V 0.11-Ω Load VIN = 24 V
Figure 88. ENABLE ON and OFF, 10-A Resistive Load Figure 89. Load Transient Response, 0 A to 10 A to 0 A

LM5145
10 Power Supply Recommendations

The LM5145 buck controller is designed to operate from a wide input voltage range from 6 V to 75 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions tables. In addition, the input supply must be capable of delivering the required input current
to the fully-loaded regulator. Estimate the average input current with Equation 23.
VOUT ˜ IOUT
IIN
VIN ˜ K
where
• η is the efficiency (23)
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special
care is required to achieve stable performance. The parasitic inductance and resistance of the input cables may
have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at
VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip
during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false
UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the
input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The
moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage
overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps
to hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for
DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching
regulator.

LM5145
11 Layout
11.1 Layout Guidelines

Proper PCB design and layout is important in a high current, fast switching circuit (with high current and voltage
slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must be
considered before designing a PCB layout using the LM5145. The high-frequency power loop of the buck
converter power stage is denoted by #1 in the shaded area of Figure 90. The topological architecture of a buck
converter means that particularly high di/dt current flows in the components of loop #1, and it becomes
mandatory to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important are
the gate drive loops of the low-side and high-side MOSFETs, denoted by #2 and #3, respectively, in Figure 90.
VIN
LM5145
CIN #1
BST High frequency
VCC 14 17
power loop
CBST
HO Q1
High-side
18
gate driver LF
#2
SW
19 VOUT
VCC
14
CVCC
Q2 COUT
Low-side LO
13
gate driver
#3
PGND
12 GND
Figure 90. DC-DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops
11.1.1 Power Stage Layout

1. Input capacitors, output capacitors, and MOSFETs are the constituent components in the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective
heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,
small-signal components are typically placed on the bottom side (component side). At least one inner plane
should be inserted, connected to ground, to shield and isolate the small-signal traces from noisy power
traces and lines.
2. The DC-DC converter has several high-current loops. Minimize the area of these loops in order to suppress
generated switching noise and parasitic loop inductance and optimize switching performance.
– Loop #1: The most important loop to minimize the area of is the path from the input capacitor(s) through
the high- and low-side MOSFETs, and back to the capacitor(s) through the ground connection. Connect
the input capacitor(s) negative terminal close to the source of the low-side MOSFET (at ground).
Similarly, connect the input capacitor(s) positive terminal close to the drain of the high-side MOSFET (at
VIN). Refer to loop #1 of Figure 90.
– Another loop, not as critical though as loop #1, is the path from the low-side MOSFET through the
inductor and output capacitor(s), and back to source of the low-side MOSFET through ground. Connect
the source of the low-side MOSFET and negative terminal of the output capacitor(s) at ground as close
as possible.
3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, should be short and
wide. However, the SW connection is a source of injected EMI and thus should not be too large.

LM5145
Layout Guidelines (continued)

4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including
pad geometry and solder paste stencil design.
5. The SW pin connects to the switch node of the power conversion stage, and it acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop #1 in Figure 90 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (>100 MHz) ringing on
the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input
voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the
SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to
GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
11.1.2 Gate Drive Layout

The LM5145 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time
control and low-impedance output stages capable of delivering large peak currents with very fast rise and fall
times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the gate
drive command, thereby increasing MOSFET switching times. The following loops are important:
• Loop #2: high-side MOSFET, Q1. During the high-side MOSFET turn on, high current flows from the boot
capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop #2 of Figure 90.
• Loop #3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop #3 of Figure 90.
The following circuit layout guidelines are strongly recommended when designing with high-speed MOSFET gate
drive circuits.
1. Connections from gate driver outputs, HO and LO, to the respective gate of the high-side or low-side
MOSFET should be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or
wider traces. Use via(s), if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO
and SW gate traces as a differential pair from the LM5145 to the high-side MOSFET, taking advantage of
flux cancellation.
2. Minimize the current loop path from the VCC and BST pins through their respective capacitors as these
provide the high instantaneous current, up to 3.5 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the BST and SW pins of the LM5145 to minimize the area of
loop #2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and
PGND pins of the LM5145 to minimize the area of loop #3 associated with the low-side driver.
3. Placing a 2-Ω to 10-Ω resistor in series with the BST capacitor, as shown in Figure 59, slows down the high-
side MOSFET turnon transition, serving to reduce the voltage ringing and peak amplitude at the SW node at
the expense of increased MOSFET turnon power loss.
11.1.3 PWM Controller Layout

With the proviso to locate the controller as close as possible to the MOSFETs to minimize gate driver trace runs,
the components related to the analog and feedback signals, current limit setting and temperature sense are
considered in the following:
1. Separate power and signal traces, and use a ground plane to provide noise shielding.
2. Place all sensitive analog traces and components such as COMP, FB, RT, ILIM and SS/TRK away from
high-voltage switching nodes such as SW, HO, LO or BST to avoid mutual coupling. Use internal layer(s) as

LM5145
Layout Guidelines (continued)

ground plane(s). Pay particular attention to shielding the feedback (FB) trace from power traces and
components.
3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or
the bulk capacitor at the converter side.
4. Connect the ILIM setting resistor from the drain of the low-side MOSFET to ILIM and make the connections
as close as possible to the LM5145. The trace from the ILIM pin to the resistor should avoid coupling to a
high-voltage switching net.
5. Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the
GND pin. Locate these capacitors as close as possible to the LM5145.
11.1.4 Thermal Design and Layout

The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by:
• average gate drive current requirements of the power MOSFETs;
• switching frequency;
• operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation);
• thermal characteristics of the package and operating environment.
For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The LM5145 controller is
available in a small 3.5-mm × 4.5-mm 20-pin VQFN (RGY) PowerPAD™ package to cover a range of application
requirements. The thermal metrics of this package are summarized in Thermal Information. The application
report IC Package Thermal Metrics (SPRA953) provides detailed information regarding the thermal information
table.
The 20-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the LM5145 device (ground). This allows a
significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,
thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM5145 is
soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the
thermal resistance to a very low value. Wide traces of the copper tying in the no-connect pins of the LM5145
(pins 9 and 16) and connection to this thermal land helps to dissipate heat.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the
PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow
but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pad of the high-side MOSFET is
normally connected to a VIN plane for heat sinking. The drain pad of the low-side MOSFET is tied to the SW
plane, but the SW plane area is purposely kept relatively small to mitigate EMI concerns.
11.1.5 Ground Plane Design

As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended. A
ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the
control circuitry. Connect the PGND pin to the system ground plane using an array of vias under the exposed
pad. Also connect the PGND directly to the return terminals of the input and output capacitors. The PGND net
contains noise at the switching frequency and can bounce because of load current variations. The power traces
for PGND, VIN and SW can be restricted to one side of the ground plane. The other side of the ground plane
contains much less noise and is ideal for sensitive analog trace routes.

LM5145
11.2 Layout Example

Figure 91 shows an example PCB layout based on the LM5145EVM-HD-20A 20-A design. The power
component connections are made on the top layer with wide, copper-filled areas. A power ground plane is placed
on layer 2 with 6 mil (0.15 mm) spacing to the top layer. The small area of buck regulator hot loop is denoted by
the white border in Figure 91.
The LM5145 is located on the bottom side with a surrounding analog ground plane for sensitive analog
components as shown in Figure 92. The analog ground plane (AGND) and power ground plane (PGND) are
connected at a single point directly under the IC (at the die attach pad or DAP). Refer to the LM5145 EVM User's
Guide (SNVU545) for more detail.
LF VOUT
Cout3
Cout1
Cout2
Cout4
Output
Inductor Low-side Capacitors
MOSFET
G GND
SW Q2
Copper S Input
D
Capacitors
G S
Power
Cin3
Cin2
Loop
Cin1
D
Q1
High-side
VIN
MOSFET
Legend
Top Layer Copper Layer 2 GND Plane Top Solder
Figure 91. LM5145 Power Stage PCB Layout

LM5145
Layout Example (continued)
To VOUT CILIM
To
RBODE
PG
RILIM To SW
O
O
D
RC2
RFB1 10 11 PGND
To Gate of
CVCC
9 12
Low-side
CC3
LM5145
MOSFET
RFB2 AGND
RTRIM RBOOT To Gate of
2 19 High-side
CC2 1 20
CBOOT MOSFET
RC1
To Source of
CC1 High-side
CVIN MOSFET
RVIN
RUV2
RRT
CSS
RUV1 To VIN
Legend
Bottom Layer Copper Layer 3 GND Plane Bottom Solder
Figure 92. LM5145 Controller PCB Layout (Viewed From Top)

LM5145
12 Device and Documentation Support
12.1 Device Support

12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support

For development support see the following:
• LM5145 Quickstart Calculator
• LM5145 Simulation Models
• For TI's reference design library, visit TI Designs
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
12.1.3 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5145 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support

12.2.1 Related Documentation
For related documentation see the following:
• LM5145 Synchronous Buck Controller High Density EVM (SNVU545)
• Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics (SLYT682)
• AN-2162 Simple Success with Conducted EMI from DC-DC Converters (SNVA489)
• White Papers:
– Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications
(SLYY104)
• Power House Blogs:
– Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility
12.2.1.1 PCB Layout Resources

• AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021)
• AN-1229 Simple Switcher PCB Layout Guidelines (SNVA054)
• Constructing Your Power Supply – Layout Considerations (SLUP230)
• Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x (SNVA721)
• High-Density PCB Layout of DC/DC Converters

LM5145
Documentation Support (continued)

12.2.1.2 Thermal Design Resources
• AN-2020 Thermal Design by Insight, Not Hindsight (SNVA419)
• AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages (SNVA183)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
• Thermal Design Made Simple with LM43603 and LM43602 (SNVA719)
• PowerPAD™Thermally Enhanced Package (SLMA002)
• PowerPAD Made Easy (SLMA004)
• Using New Thermal Metrics (SBVA025)
12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 14. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
LM5145 Click here Click here Click here Click here Click here
12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
NexFET, PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
LM5145
PACKAGE OUTLINE
RGY0020B SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.6 B
A
3.4
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SECTION
SCALE A-A
30.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.08 C
0.00
1.7 0.1
2X 1.5 (0.2) TYP
10 11 EXPOSED
14X 0.5 THERMAL PAD
9
12
SYMM 21
2X 2.7 0.1
3.5
A A
2
19
0.3
1 20 20X
0.2
PIN 1 ID SYMM
(OPTIONAL) 0.1 C A B
0.5 0.05
20X
0.3
4222860/B 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com

LM5145
EXAMPLE BOARD LAYOUT

RGY0020B VQFN - 1 mm max height
(1.7)
SYMM
1 20
20X (0.6)
2
19
20X (0.25)
(1.1)
(4.3)
SYMM 21
(2.7)
14X (0.5)
(0.6)
9 12
(R0.05) TYP
10 11
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4222860/B 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
LM5145
EXAMPLE STENCIL DESIGN

RGY0020B VQFN - 1 mm max height
4X (0.75)
(R0.05) TYP
1 20
20X (0.6)
2
19
21
20X (0.25)
4X
(1.21)
SYMM
(4.3)
(0.71)
TYP
14X (0.5)
9 12
METAL
TYP
10 11
4X (0.75) (0.475)
TYP
SYMM
(3.3)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222860/B 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com

PACKAGE OPTION ADDENDUM
www.ti.com 16-Jun-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM5145RGYR ACTIVE VQFN RGY 20 3000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 LM5145
& no Sb/Br)
LM5145RGYT ACTIVE VQFN RGY 20 250 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 LM5145
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 16-Jun-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5145RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.18 8.0 12.0 Q1
LM5145RGYT VQFN RGY 20 250 180.0 12.4 3.8 4.8 1.18 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5145RGYR VQFN RGY 20 3000 370.0 355.0 55.0
LM5145RGYT VQFN RGY 20 250 220.0 205.0 50.0
Pack Materials-Page 2
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Product Order Technical Tools & Support &

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Typical Application Circuit and Efficiency Performance, VOUT = 5 V

RC2 SYNC Out SYNCOUT

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6 Pin Configuration and Functions

Connect Exposed Pad on bottom to AGND and PGND on the PCB.

(1) P = Power, G = Ground, I = Input, O = Output.

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Pin Functions (continued)

6.1 Wettable Flanks

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7.2 ESD Ratings

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7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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7.6 Switching Characteristics

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7.7 Typical Characteristics

Figure 1. Efficiency vs Load, CCM Figure 2. Efficiency vs Load, DCM

Figure 3. Efficiency vs Load, CCM Figure 4. Efficiency vs Load, CCM

Figure 5. Efficiency vs Load, CCM Figure 6. FB Voltage vs Junction Temperature

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Typical Characteristics (continued)

VIN Shutdown Quiescent Current (PA)

VIN Operating Quiescent Current (mA)

40°C 25°C 125°C 40°C 25°C 125°C

VIN Operating Quiescent Current (mA)

40°C 25°C 125°C VCC = 8V

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Typical Characteristics (continued)

BST UVLO Threshold (V)

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Typical Characteristics (continued)

EN Standby Threshold (V)

Switching Frequency (kHz)

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Typical Characteristics (continued)

LO Gate Driver RDS(on) (:)

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8.2 Functional Block Diagram

RT OSCILLATOR & LEVEL DRIVER HO

kFF*VIN + 0.3 V ADAPTIVE SW

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8.3 Feature Description