NCP1397A/B, NCV1397A/B

High Performance Resonant

Mode Controller with
Integrated High-Voltage
Drivers
The NCP1397 is a high performance controller that can be utilized www.onsemi.com
in half bridge resonant topologies such as series resonant, parallel
resonant and LLC resonant converters. It integrates 600 V gate 16
drivers, simplifying layout and reducing external component count.
With its unique architecture, including a 500 kHz Voltage Controlled 1
Oscillator whose control mode permits flexibility when an ORing SO−16, LESS PIN 13
function is required, the NCP1397 delivers everything needed to build D SUFFIX
a reliable and rugged resonant mode power supply. CASE 751AM
The NCP1397 provides a suite of protection features with
MARKING DIAGRAMS
configurable settings to optimize any application. These include:
auto−recovery or fault latch−off, brown−out, open optocoupler, 16
soft−start and short−circuit protection. Deadtime is also adjustable to
NCx1397yG
overcome shoot through current. AWLYWW
Features 1
• High−Frequency Operation from 50 kHz up to 500 kHz
• 600 V High−Voltage Floating Driver x = P (standard) or V (automotive)
y = A or B
• Adjustable Minimum Switching Frequency with ±3% Accuracy A = Assembly Location
• Adjustable Deadtime from 100 ns to 2 ms. WL = Wafer Lot
Y = Year
• Startup Sequence Via an Externally Adjustable Soft−Start WW = Work Week
• Brown−Out Protection for a Simpler PFC Association G = Pb−Free Package
• Latched Input for Severe Fault Conditions, e.g. Over Temperature
or OVP
PIN CONNECTIONS
• Timer−Based Input with Auto−Recovery Operation for Delayed
Event Reaction CSS(dis) 1 16 Vboot
• Latched Overcurrent Protection Fmax 2 15 Mupper
• Disable Input for Immediate Event Reaction or Simple ON/OFF Ctimer 3 14 HB
Control
Rt 4
• VCC Operation up to 20 V
BO 5 12 VCC
• Low Startup Current of 300 mA
FB 6 11 Mlower
• 1 A/0.5 A Peak Current Sink/Source Drive Capability
DT 7 10 GND
• Common Collector Optocoupler Connection for Easier ORing
Skip/Disable 8 9 Fault
• Optional Common Emitter Optocoupler Connection
• Internal Temperature Shutdown (Top View)

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100 ORDERING INFORMATION
See detailed ordering and shipping information in the package
Qualified and PPAP Capable dimensions section on page 26 of this data sheet.
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Flat Panel Display Power Converters • Industrial and Medical Power Sources
• High Power ac−dc Adapters for Notebooks • Offline Battery Chargers
• Computing Power Supplies

© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

October, 2015 − Rev. 6 NCP1397/D
 NCP1397A/B, NCV1397A/B

R18

Figure 1. Typical Application Example

PIN FUNCTION DESCRIPTION

Pin # Pin Name Function Pin Description
1 CSS(dis) Soft−Start Discharge Soft−start capacitor discharge pin. Connect to the soft−start capacitor to reset it
before startup or during overload conditions.
2 Fmax Maximum frequency clamp A resistor sets the maximum frequency excursion
3 Ctimer Timer duration Sets the timer duration in presence of a fault
4 Rt Minimum frequency clamp Connecting a resistor to this pin, sets the minimum oscillator frequency reached
for VFB = 1 V.
5 BO Brown−Out Detects low input voltage conditions. When brought above Vlatch (4 V typically), it
fully latches off the controller.
6 FB Feedback Injecting current into this pin increases the oscillation frequency up to Fmax.
7 DT Deadtime A simple resistor adjusts the dead−time width
8 Skip/Disable Skip or Disable input Upon release, a clean startup sequence occurs if VFB < 0.3 V. During the skip
mode, when FB doesn’t drop below 0.3 V, the IC restarts without soft−start
sequence.
9 Fault Fault detection input When asserted, the external timer starts to countdown and shuts down the
controller at the end of its time duration. Simultaneously the Soft−Start discharge
switch is activated so the converter operating frequency goes up to protect
application power stage. This input features also second fault comparator with
higher threshold (1.5 V typically) that:
A) Speeds up the timer capacitor charging current 8 times – NCP1397A
B) latches off the IC permanently – NCP1397B
In both versions the second fault comparator helps to protect application in case
of short circuit on the output or transformer secondary winding.
10 GND Analog ground −
11 Mlower Low side output Drives the lower side MOSFET
12 VCC Supplies the controller The controller accepts up to 20 V
13 NC Not connected Increases the creepage distance
14 HB Half−bridge connection Connects to the half−bridge output
15 Mupper High side output Drives the higher side MOSFET
16 Vboot Bootstrap pin The floating VCC supply for the upper stage

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 NCP1397A/B, NCV1397A/B

VDD
Temperature
Shutdown

S VBOOT
Imin
VFB  VFB(o ) D Q

Vref + Vref
Clk Q
−−
Rt
+ R
IDT

Management
C FF
DT Adj. 50% DC Mupper

VCC
I = Imax for Vfb = 5.3 V
I = 0 for Vfb < Vfb(min)
BO
Reset
VDD
PON
Reset
Imax UVLO
VFB = 5 Fault
VDD Vdd Fast
Timeout
Fault
Fault HB
Vref
Itimer1 Itimer2
Fmax

Level
Timer + Shifter NC
−− Timeout
Fault
+
Vref

PON Reset
Vtimer OFF
Reset VCC

PON Reset
Fault
SS(dis) Fault

Enable
(if Vfb<0.3V)

G=1 Mlower
FB +
−− > 0 only VDD
V=V (FB) −− VFB(min)
RFB +
−−
GND
+ +
VFB(fault)
VFB(min)
Skip/
−−
Disable
+ 20 ns Noise
Vref
Filter
Deadtime +
IDT Vref Skip/Disable
DT Adjustment
VDD

20 ms Noise
IBO
Filter

Q Q
BO + +
S R PON Reset
−− −−
+ + 20 ms Noise
VBO Vlatch Filter

Fault +
−−
+ +
Vref(fault)
−−
+ 1 ms Noise
Vref(OCP) Filter

Figure 2. Internal Circuit Architecture (NCP1397A)

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 NCP1397A/B, NCV1397A/B

VDD
Temperature
Shutdown

S VBOOT
Imin
VFB  VFB(o ) D Q
Vref + Vref
Clk Q
−−
Rt
+ R
IDT

Management
C FF
DT Adj. 50% DC Mupper

VCC
I = Imax for Vfb = 5.3 V
I = 0 for Vfb < Vfb_min
BO
Reset
VDD

PON
Imax Reset
UVLO
Vfb = 5 Fault
VDD Fast
Timeout
Fault
Fault HB
Vref

Itimer1
Fmax

If FAULT Itimer else 0

Level
Timer + Shifter NC
−− Timeout
Fault

+
Vref

PON Reset
Vtimer OFF
Reset VCC

PON Reset
Fault
SS(dis) Fault

Enable
(if Vfb<0.3V)

G=1 Mlower
FB +
−− > 0 only VDD
V=V (FB) −− VFB(min)
RFB +
−−
GND
+ +
VFB(fault)
VFB(min)
Skip/
−− Disable
+ 20 ns Noise
Vref
Filter
Deadtime +
IDT Vref Skip
DT Adjustment
VDD

20 ms Noise
IBO Filter

Q Q
BO + +
R PON Reset
−− −− S
+ + 20 ms Noise
VBO Vlatch Filter

Fault +
−−
+ +
Vref(fault)
−−
+ 1 ms Noise
Vref(OCP) Filter

Figure 3. Internal Circuit Architecture (NCP1397B)

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 NCP1397A/B, NCV1397A/B

MAXIMUM RATINGS
Rating Symbol Value Unit
High Voltage bridge pin, pin 14 VBRIDGE −1 to 600 V

Floating supply voltage, ground referenced VBOOT − VBRIDGE 0 to 20 V

High side output voltage VDRV(HI) VBRIDGE−0.3 to V
VBOOT+0.3

Low side output voltage VDRV(LO) −0.3 to VCC+0.3 V

Allowable output slew rate dVBRIDGE/dt 50 V/ns
Power Supply voltage, pin 12 VCC 20 V
Maximum voltage, all pins (except pin 11 and 10) − −0.3 to 10 V
Thermal Resistance Junction−to−Air, SOIC version RqJA 130 °C/W
Storage Temperature Range − −60 to +150 °C
ESD Capability, Human Body Model (HBM) (All pins except HV pins) − 2 kV
ESD Capability, Machine Model (MM) − 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model 200 V per JEDEC Standard JESD22−A115−A
2. This device meets latchup tests defined by JEDEC Standard JESD78.

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 NCP1397A/B, NCV1397A/B

ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

SUPPLY SECTION

VCC(on) Turn−on threshold level, VCC going up 12 9.7 10.5 11.3 V

VCC(min) Minimum operating voltage after turn−on 12 8.7 9.5 10.3 V
Vboot(on) Startup voltage on the floating section 16−14 8 9 10 V
Vboot(min) Cutoff voltage on the floating section 16−14 7.4 8.4 9.4 V
Istartup Startup current, VCC < VCC(on) 12 − − 300 mA
VCC(reset) VCC level at which the internal logic gets reset 12 − 6.6 − V
ICC1 Internal IC consumption, no output load on pin 15/14 – 11/10, 12 − 4 − mA
FSW = 300 kHz

ICC2 Internal IC consumption, 1 nF output load on pin 15/14 – 11/10, 12 − 11 − mA

FSW = 300 kHz

ICC3 Consumption in fault or disable mode (All drivers disabled, 12 − 1.5 − mA

Rt = 34 kW, RDT = 10 kW)
VOLTAGE CONTROL OSCILLATOR (VCO)
FSW(min) Minimum switching frequency, Rt = 34 kW on pin 4, Vpin6 = 0.8 V, 4 58.2 60 61.8 kHz
DT = 300 ns
FSW(max) Maximum switching frequency, Rf(max) = 1.9 kW on pin 2, Vpin6 > 2 440 500 560 kHz
5.3 V, Rt = 34 kW, DT = 300 ns
FBSW Feedback pin swing above which Df = 0 6 − 5.3 − V
DC Operating duty−cycle symmetry 11−15 48 50 52 %
Tdel1 Delay before driver restart from fault or disable mode − − 700 − ns
Tdel2 Delay before driver restart after VCC(on) event (Note 4) − − 11 − ms
Vref(Rt) Reference voltage for Rt pin 4 2.18 2.3 2.42 V
FEEDBACK SECTION
RFB Internal pulldown resistor 6 − 20 − kW
VFB(min) Voltage on pin 6 below which the FB level has no VCO action 6 − 1.1 − V
VFB(off) Voltage on pin 6 below which the controller considers the FB fault 6 240 280 320 mV
VFBoff(hyste) Feedback fault comparator hysteresis 6 − 45 − mV
DRIVE OUTPUT
Tr Output voltage risetime @ CL = 1 nF, 10−90% of output signal 15−14/11−10 − 40 − ns
Tf Output voltage falltime @ CL = 1 nF, 10−90% of output signal 15−14/11−10 − 20 − ns
ROH Source resistance 15−14/11−10 − 13 − W
ROL Sink resistance 15−14/11−10 − 5.5 − W
Tdead Deadtime with RDT = 10 kW from pin 7 to GND 7 250 290 340 ns
Tdead(max) Maximum deadtime with RDT = 82 kW from pin 7 to GND 7 − 2 − ms
Tdead(min) Minimum deadtime, RDT = 3 kW from pin 7 to GND 7 − 100 − ns
IHV(LEAK) Leakage current on high voltage pins to GND 14, 15,16 − − 5 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip
cycle implementation.
4. Guaranteed by design.

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 NCP1397A/B, NCV1397A/B

ELECTRICAL CHARACTERISTICS (continued)

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

TIMERS
Itimer1 Timer capacitor charge current during feedback fault or when 3 150 175 190 mA
Vref(fault) < Vpin9 < Vref(OCP)

Itimer2 Timer capacitor charge current when Vpin9 > Vref(OCP) (Icharge1 + 3 1.1 1.3 1.5 mA
Icharge2) – A version only

Ttimer Timer duration with a 1 mF capacitor and a 1 MW resistor, Itimer1 3 − 24 − ms

current applied
TtimerR Timer recurrence in permanent fault, same values as above 3 − 1.4 − s
Vtimer(on) Voltage at which pin 3 stops output pulses 3 3.8 4 4.2 V
Vtimer(off) Voltage at which pin 3 restarts output pulses 3 0.95 1 1.05 V
RSS(dis) Soft−start discharge switch channel resistance 1 − 100 − W
PROTECTION
Vref(Skip) Reference voltage for Skip/Disable input (Note 4) 8 630 660 690 mV
Hyste(Skip) Hysteresis for Skip/Disable (Note 4) 8 − 45 − mV
Vref(Fault) Reference voltage for Fault comparator 9 0.99 1.04 1.09 V
Hyste(Fault) Hysteresis for fault comparator input 9 − 60 − mV
Vref(OCP) Reference voltage for OCP comparator 9 1.47 1.55 1.63 V
Hyste(OCP) Hysteresis for OCP comparator input 9 − 90 − mV
Tp(Disable) Propagation delay from disable input to the drive shutdown 8 − 60 100 ns
IBO(bias) Brown−Out input bias current 5 − 0.02 − mA
VBO Brown−Out level 5 0.99 1.04 1.09 V
IBO Hysteresis current, Vpin5 > VBO 5 25 28 31 mA
Vlatch Latching voltage 5 3.7 4 4.3 V
TSD Temperature shutdown − 140 − − °C
TSD(hyste) Hysteresis − − 30 − °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip
cycle implementation.
4. Guaranteed by design.

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 NCP1397A/B, NCV1397A/B

TYPICAL CHARACTERISTICS

10.55 9.52

9.50
10.50
9.48

VCC(min) (V)
VCC(on) (V)

9.46
10.45
9.44

9.42
10.40
9.40

10.35 9.38
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 4. VCC(on) Threshold Figure 5. VCC(min) Threshold

60.05 510

60 509

508
59.95
FSW(max) (kHz)
FSW(min) (kHz)

507
59.9
506
59.85
505

59.8 504

59.75 503
−40 −20 0 20 40 60 80 100 120 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 6. FSW(min) Frequency Clamp Figure 7. FSW(max) Frequency Clamp

23.0 0.661

22.5
0.660
22.0
21.5 0.659
Vref(skip) (V)
RFB (kW)

21.0
0.658
20.5

20.0 0.657

19.5
0.656
19.0
18.5 0.655
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 8. Pulldown Resistor (RFB) Figure 9. Skip/Disable Threshold (Vref(skip))

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TYPICAL CHARACTERISTICS

17.0 9.0

16.0 8.5

15.0 8.0
7.5
14.0
ROHA (W)

ROLA (W)
7.0
13.0
6.5
12.0
6.0
11.0
5.5
10.0 5.0
9.0 4.5
8.0 4.0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 10. Source Resistance (ROH) Figure 11. Sink Resistance (ROL)

114 297
113 296
112 295

111 294
Tdead(nom) (ns)
Tdead(min) (ns)

293
110
292
109
291
108
290
107
289
106 288
105 287
104 286
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 12. Tdead(min) Figure 13. Tdead(nom)

2.065 4.035

2.060 4.030

2.055 4.025
Tdead(max) (ms)

Vlatch (V)

2.050 4.020

2.045 4.015

2.040 4.010

2.035 4.005
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 14. Tdead(max) Figure 15. Latch Level (Vlatch)

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TYPICAL CHARACTERISTICS

1.038 28.8

1.036 28.6

1.034 28.4

28.2
1.032

IBO (mA)
VBO (V)

28.0
1.030
27.8
1.028
27.6
1.026
27.4
1.024 27.2
1.022 27.0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 16. Brown−Out Reference (VBO) Figure 17. Brown−Out Hysteresis Current
(IBO)

1.050 178

1.048
176
1.046

1.044 174
Vref(fault) (V)

Itimer1 (mA)

1.042
172
1.040

1.038 170

1.036
168
1.034
1.032 166
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 18. Fault Input Reference (Vref(fault)) Figure 19. Ctimer 1st Current (Itimer1)

1.565 1.34
1.33
1.560
1.32
1.555
1.31
Vref(OCP) (V)

Itimer2 (mA)

1.550 1.30

1.545 1.29
1.28
1.540
1.27
1.535
1.26

1.530 1.25
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 20. OCP reference (Vref(OCP)) Figure 21. Ctimer 2nd Current (Itimer2)

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TYPICAL CHARACTERISTICS

4.035 0.288

4.030 0.286

0.284
4.025
Vtimer(on) (V)

VFB(off) (V)
0.282
4.020
0.280
4.015
0.278

4.010 0.276

4.005 0.274
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 22. Fault Timer Ending Voltage Figure 23. FB Fault Detection Threshold
(Vtimer(on)) (VFB(fault))

1.000

0.999

0.998
Vtimer(off) (V)

0.997

0.996

0.995

0.994

0.993

0.992
−40 −25 −10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Figure 24. Fault Timer Reset Voltage (Vtimer(off))

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 NCP1397A/B, NCV1397A/B

APPLICATION INFORMATION

The NCP1397A/B includes all necessary features to help are stopped. The controller now waits for the discharge
building a rugged and safe switch−mode power supply via an external resistor on Pin 3 to issue a new clean
featuring an extremely low standby power. The below startup sequence via soft−start.
bullets detail the benefits brought by implementing the • Cumulative fault events: In the NCP1397A/B, the
NCP1397A/B controller: timer capacitor is not reset when the fault disappears. It
• Wide frequency range: A high−speed Voltage Control actually integrates the information and cumulates the
Oscillator allows an output frequency excursion from occurrences. A resistor placed in parallel with the
50 kHz up to 500 kHz on Mlower and Mupper outputs. capacitor will offer a simple way to adjust the discharge
• Adjustable dead−time: Due to a single resistor wired rate and thus the auto−recovery retry rate.
to ground, the user has the ability to include some • Overcurrent detection using Fault input: The fault
dead−time, helping to fight cross−conduction between input is specifically designed to protect LLC
the upper and the lower transistor. application in case of short circuit or overload. In case
• Adjustable soft−start: Every time the controller starts the voltage on this input grows above first threshold the
to operate (power on), the switching frequency is Itimer current source is activated and Fault timer
pushed to the programmed starting value by external capacitor starts charging. Simultaneously the Soft−Start
components (RFmin//RFstart) and slowly moves down discharge switch is activated to increase operating
toward the minimum frequency, until the feedback loop frequency of the converter. The IC stops operation in
closes. The soft−start discharge input (SS(dis)) case the Fault timer elapses. The Fault input includes
discharges the Soft−Start capacitor before any IC restart also second fault comparator that:
excluding the restart after Disable is released AND FB − Speeds up the fault timer capacitor charging by
voltage is higher than 0.3 V. The Soft−Start discharge increasing the Itimer1 current to Itimer2 – NCP1397A
switch also activates in case the Fault input detects the − Latches off the device – NCP1397B
overload conditions. The second fault comparator thus helps to protect the power
• Adjustable minimum and maximum frequency stage in case of hard short circuit (like shorted transformer
excursion: In resonant applications, it is important to winding etc.)
stay away from the resonating peak to keep operating • Skip cycle possibility: The absence of the soft−start on
the converter in the right region. Thanks to a single the Skip/Disable input (in case the VFB > 0.3 V) offers
external resistor, the designer can program its lowest an easy way to implement skip cycle when power
frequency point, obtained in lack of feedback voltage saving features are necessary. A simple resistive divider
(during the startup sequence or in short−circuit from the feedback pin to the Skip/Disable input, and
conditions). Internally trimmed capacitors offer a $3% skip can be implemented.
precision on the selection of the minimum switching • Broken feedback loop detection: Upon startup or any
frequency. The adjustable upper stop being less precise time during operation, if the FB signal is missing, the
to $12%. timer starts to charge timer capacitor. If the loop is
• Low startup current: When directly powered from the really broken, the FB level does not grow−up before the
high−voltage DC rail, the device only requires 300 mA timer ends charging. The controller then stops all pulses
to startup. and waits until the timer pin voltage collapses to 1 V
• Brown−Out detection: To avoid operation from a low typically before a new attempt to restart, via the
input voltage, it is interesting to prevent the controller soft−start. If the optocoupler is permanently broken, a
from switching if the high−voltage rail is not within the hiccup takes place.
right boundaries. Also, when teamed with a PFC • Common collector or common emitter optocoupler
front−end circuitry, the brown−out detection can ensure connection options: This IC allows the designer to
a clean startup sequence with soft−start, ensuring that select from two possible optocoupler configurations.
the PFC is stabilized before energizing the resonant
tank. The BO input features a 28 mA hysteresis current Voltage−Controlled Oscillator
for the lowest consumption. The VCO section features a high−speed circuitry allowing
operation from 100 kHz up to 1 MHz. However, as a division
• Adjustable fault timer duration: When a fault is
by two internally creates the two Q and /Q outputs, the final
detected on the Fault input or when the FB path is
effective signal on output Mlower and Mupper switches
broken, timer pin starts to charge an external capacitor.
between 50 kHz and 500 kHz. The VCO is configured in
If the fault is removed, the timer opens the charging
such a way that if the feedback pin voltage goes up, the
path and nothing happens. When the timer reaches its
switching frequency also goes up. Figure 25 shows the
selected duration (via a capacitor on Pin 3), all pulses
architecture of the VCO oscillator.

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FBinternal
VDD

max
+ FSW
-

max
Imin
0 to IFmax S
Vref
D Q
Rt +
Clk Q
-
Rt sets Cint
Fmin for V(FB) = 0 + R

VDD

IDT

Vref Imin
A B

DT
RDT sets
the deadtime
VDD
VCC
Fmax

Fmax sets
the maximum FSW

FB
+ VFB < VFB(off)
RFB - Start fault timer
20 k +
Vb(off)

Figure 25. The Simplified VCO Architecture

The designer needs to program the maximum switching VCC

frequency and the minimum switching frequency. In LLC
configurations, for circuits working above the resonant
frequency, a high precision is required on the minimum
frequency, hence the $3% specification. This minimum
FB
switching frequency is actually reached when no feedback +
R1
closes the loop. It can happen during the startup sequence, −
11.3 k
a strong output transient loading or in a short−circuit
+
condition. By installing a resistor from Pin 4 to GND, the R3 D1
minimum frequency is set. Using the same philosophy, 100 k 2.3 V
Vref
wiring a resistor from Pin 2 to GND will set the maximum 0.5 V Fmax
R2
frequency excursion. To improve the circuit protection 8.7 k
features, we have purposely created a dead zone, where the RFmax
feedback loop has no action. This is typically below 1.1 V.
Figure 26 details the arrangement where the internal voltage
(that drives the VCO) varies between 0 and 2.3 V. However,
Figure 26. The OPAMP Arrangement Limits the
to create this swing, the feedback pin (to which the VCO Modulation Signal between 0.5 and 2.3 V
optocoupler emitter connects), will need to swing typically
between 1.1 V and 5.3 V.

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This techniques allows us to detect a fault on the converter

in case the FB pin cannot rise above 0.3 V (to actually close
the loop) in less than a duration imposed by the
programmable timer. Please refer to the fault section for
detailed operation of this mode.
As shown on Figure 26, the internal dynamics of the VCO
control voltage will be constrained between 0.5 V and 2.3 V,
whereas the feedback loop will drive Pin 6 (FB) between
1.1 V and 5.3 V. If we take the default FB pin excursion
numbers, 1.1 V = 50 kHz, 5.3 V = 500 kHz, then the VCO
maximum slope will be:
500 k * 50 k
+ 107 kHz/V
4.2
Figures 27 and 28 portray the frequency evolution
depending on the feedback pin voltage level in a different Figure 28. Here a Different Minimum Frequency was
frequency clamp combination. Programmed as well as a Maximum Frequency
Excursion

Please note that the previous small−signal VCO slope has

now been reduced to 300k / 4.1 = 71 kHz / V on Mupper and
Mlower outputs. This offers a mean to magnify the feedback
excursion on systems where the load range does not generate
a wide switching frequency excursion. Due to this option,
we will see how it becomes possible to observe the feedback
level and implement skip cycle at light loads. It is important
to note that the frequency evolution does not have a real
linear relationship with the feedback voltage. This is due to
the deadtime presence which stays constant as the switching
period changes.
The selection of the three setting resistors (Fmax, Fmin and
deadtime) requires the usage of the selection charts
displayed below:
Figure 27. Maximal Default Excursion,
Rt = 41 kW on Pin 4 and RF(max) = 1.9 kW on Pin 2

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 NCP1397A/B, NCV1397A/B

1900
VCC = 15 V
550 VFB = 6.5 V 1700
DT = 300 ns
1500
450
1300
Fmax (kHz)

DT (ns)
350 1100
900
250 Fmin = 200 kHz
700
500
150
Fmin = 50 kHz 300
50 100
1.9 11.9 21.9 31.9 41.9 3.5 13.5 23.5 33.5 43.5 53.5 63.5 73.5 83.5
RFmax (kW) RDT (kW)
Figure 29. Maximum Switching Frequency Resistor Figure 32. Deadtime Resistor Selection
Selection Depending on the Adopted Minimum
Switching Frequency
ORing capability and optocoupler connection
configurations
500 If for any particular reason, there is a need for a frequency
VCC = 15 V
450 VFB = 1 V variation linked to an event appearance (instead of abruptly
DT = 300 ns stopping pulses), then the FB pin lends itself very well to the
400 addition of other sweeping loops. Several diodes can easily
350 be used perform the job in case of reaction to a fault event
Fmin (kHz)

or to regulate on the output current (CC operation).

300 Figure 33 shows how to do it.
250
VCC
200

150

100
2 4 6 8 10 12 14 16 18 20
In1 FB VCO
RFmin (kW)
Figure 30. Minimum Switching Frequency Resistor In2
20 k
Selection (Fmin = 100 kHz to 500 kHz)

100 Figure 33. Thanks to the FB Configuration, Loop

VCC = 15 V ORing is Easy to Implement
90
VFB = 1 V
80 DT = 300 ns The VCO configuration used in this IC also offers an easy
70
way to connect optocoupler (or pulldown bipolar) directly
Fmin (kHz)

to the Rt pin instead of FB pin (refer to Figures 34 and 35).

60 The optocoupler is then configured as “common emitter”
50
and the operating frequency is controlled by the current that
is taken out from the Rt pin – we have current controller
40 oscillator (CCO). If one uses this configuration it is needed
to maintain FB pin voltage between 0.3 V and 1 V otherwise
30
the FB fault will be detected. The FB pin can be still used for
20 open FB loop detection in some applications – to do so it is
20 30 40 50 60 70 80 90 100 110 needed to keep optcoupler emitter voltage higher then 0.3 V
RFmin (kW) for nominal load conditions. One needs to take RFB
Figure 31. Minimum Switching Frequency Resistor pulldown resistor into account when using this
Selection (Fmin = 20 kHz to 100 kHz) configuration. It is possible to implement skip mode using
Skip/disable input and emitter resistors Rskip1 and Rskip2.

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 NCP1397A/B, NCV1397A/B

Fstart(adj) − RFstart/RFmin
Fmin(adj) − RFmin
Fmax(adj) − Rc + Rskip1 + Rskip2
SS
Fmax
RFstart
Rt
Rc VCC
RFmin FB
GND
Skip/Disable
CSS NCP1397

OK1
Rskip1

Rskip2

Figure 34. Feedback Configuration Using Direct Connection to the Rt Pin

Rbias
Fstart(adj) − RFstart/RFmin
Fmin(adj) − RFmin
Fmax(adj) − Rc + Rskip1 + Rskip2
SS
Fmax
RFstart
Rt
Rc VCC
RFmin FB
GND
Skip/Disable
CSS NCP1397

OK1
Rskip1

Rskip2 1N4148

Figure 35. Feedback Configuration Using Direct Connection to the Rt Pin – No Open FB Loop Detection

Dead−Time Control
Deadtime control is an absolute necessity when the During the discharge time, the clock comparator is high and
half−bridge configuration comes to play. The deadtime invalidates the AND gates: both outputs are low. When the
technique consists in inserting a period during which both comparator goes back to the low level, during the timing
high and low side switches are off. Of course, the deadtime capacitor Ct recharge time, A and B outputs are validated.
amount differs depending on the switching frequency, hence By connecting a resistor RDT to ground, it creates a current
the ability to adjust it on this controller. The option ranges whose image serves to discharge the Ct capacitor: we control
between 100 ns and 2 ms. The deadtime is actually made by the dead−time. The typical range evolves between 100 ns
controlling the oscillator discharge current. Figure 36 (RDT = 3.5 kW) and 2 ms (RDT = 83.5 kW). Figure 39 shows
portrays a simplified VCO circuit based on Figure 25. the typical waveforms.

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 NCP1397A/B, NCV1397A/B

VDD

Icharge:
FSW(min) + FSW(max)
S
D Q
+
Clk Q
−
Idis R

Ct + 3 V−1 V

Vref

DT

RDT
A B

Figure 36. Dead−time Generation

Soft−Start Sequence
In resonant controllers, a soft−start is needed to avoid SS
suddenly applying the full current into the resonating circuit. Action
With this controller the soft−start duration is fully adjustable
using eternal components. The purpose of the Soft−Start pin
is to discharge Soft−Start capacitor before IC restart and in
case of fault conditions detected by Fault input.
Once the controller starts operation, the Soft−Start Target is
capacitor (refer to Figure 37) is fully discharged and thus it Reached
starts charging from the Rt pin. The charging current
increases operating frequency of the controller above Fmin.
As the soft−start capacitor charges, the frequency smoothly
decreases down to Fmin. Of course, practically, the feedback
loop is supposed to take over the VCO lead as soon as the Figure 38. A Typical Startup Sequence on a LLC
output voltage has reached the target. If not, then the Converter Using NCP1397
minimum switching frequency is reached and a fault is
detected on the feedback pin (typically below 300 mV).
Figure 38 depicts a typical LLC startup using NCP1397A/B Please note that the soft−start capacitor is discharged in the
controller. following conditions:
− A startup sequence
− During auto−recovery burst mode
SS
RF(start)
Fmax − A brown−out recovery
Rt − A temperature shutdown recovery
RFmin The skip/disable input undergoes a special treatment.
GND
RFmax Since we want to implement skip cycle using this input, we
CSS
NCP1397 cannot activate the soft−start every time the feedback pin
Fstart(adj) − RFstart/RFmin stops the operations in low power mode. Therefore, when
Fmin(adj) − RFmin
Fmax(adj) − RFmax the skip/enable pin is released, no soft−start occurs to offer
the best skip cycle behavior. However, it is very possible to
Figure 37. Soft−Start Components Arrangement
combine skip cycle and true disable, e.g. via ORing diodes
driving Pin 8. In that case, if a signal maintains the
skip/disable input high long enough to bring the feedback
level down (below 0.3 V) since the output voltage starts to
fall down, then the soft−start discharge switch is activated.

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 NCP1397A/B, NCV1397A/B

4.00

3.00
Vct in Volts
Plot1

2.00

1.00
Ct Voltage
0

16.0
Clock Pulses
DT
Clock in Volts

12.0
Plot2

8.00

4.00

8.00 DT
DT
Difference in Volts

4.00
Plot3

−4.00
A−B
−8.00

56.2 m 65.9 m 75.7 m 85.4 m 95.1 m

time in seconds
Figure 39. Typical Oscillator Waveforms

Brown−Out protection Vbulk VDD

The Brown−Out circuitry (BO) offers a way to protect the
ON/OFF
resonant converter from low DC input voltages. Below a Rupper IBO
given level, the controller blocks the output pulses, above it,
it authorizes them. The internal circuitry, depicted by BO +
Figure 40, offers a way to observe the high−voltage (HV) BO
−
rail. A resistive divider made of Rupper and Rlower, brings a
Rlower
portion of the HV rail on Pin 5. Below the turn−on level, the +
28 mA current source IBO is off. Therefore, the turn−on VBO
level solely depends on the division ratio brought by the
resistive divider.

Figure 40. The Internal Brown−out Configuration with

an Offset Current Source

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 NCP1397A/B, NCV1397A/B

450 16.0 351 V

350 12.0 250 V

Plot1 Vin in Volts

Vcmp in Volts
Vin
250 8.0

150 4.0

50 0
BO

20 m 60 m 100 m 140 m 180 m

time in seconds
Figure 41. Simulation Results for 350 / 250 ON / OFF Levels

To the contrary, when the internal BO signal is high V bulk1 * V bulk2

(Mlower and Mupper pulse), the IBO source is activated and R lowerer + VBO
IBO ǒV bulk1 * VBOǓ
creates a hysteresis. As a result, it becomes possible to select
the turn−on and turn−off levels via a few lines of algebra: If we decide to turn−on our converter for Vbulk1 equals
IBO is off 350 V and turn it off for Vbulk2 equals 250 V, then we obtain:
R lower Rupper = 3.57 MW
V()) + V bulk1 (eq. 1) Rlower = 10.64 kW
R lower ) R upper The bridge power dissipation is 4002 / 3.781 MW =
IBO is on 45 mW when front−end PFC stage delivers 400 V.
R lower Figure 41 simulation result confirms our calculations.
V()) + V bulk2
R lower ) R upper Latchoff Protection
(eq. 2)

ǒ Ǔ
There are some situations where the converter shall be
R lower R upper
) IBO fully turned−off and stay latched. This can happen in
R lower ) R upper presence of an overvoltage (the feedback loop is drifting) or
when an over temperature is detected. Thanks to the addition
We can now extract Rlower from Equation 1 and plug it into
of a comparator on the BO pin, a simple external circuit can
Equation 2, then solve for Rupper:
lift up this pin above Vlatch (4 V typical) and permanently
V bulk1 * VBO disable pulses. The VCC needs to be cycled down below
R upper + R lower
VBO 6.5 V typically to reset the controller.

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 NCP1397A/B, NCV1397A/B

VCC Vbulk
20 ms
+ RC To permanent
Q1 − latch
Vout +
Vlatch
Rupper
IBO
VDD

BO +
BO
−
NTC +
Rlower
VBO

Figure 42. Adding a Comparator on the BO Pin Offers a way to Latch−off the Controller

On Figure 42, Q1 is blocked and does not bother the BO discharges via an external parallel resistor. In case the
measurement as long as the NTC and the optocoupler are not overload lasts for more than timer duration (given by Itimer,
activated. As soon as the secondary optocoupler senses an Vtimer, Ctimer and Rtimer) the IC stops the operation and waits
OVP condition, or the NTC reacts to a high ambient until the Ctimer will discharge to 1 V. The application then
temperature, Q1 base is brought to ground and the BO pin restarts via Soft−Start.
goes up, permanently latching off the controller. In case of heavy overload, like transformer short circuit,
the primary current grows very fast and thus could reach
Protection Circuitry danger level prior the fault timer elapses. The NCP1397B
This resonant controller offers a dedicated input (Fault therefore features additional comparator (1.55 V) on the
input) to detect primary overcurrent conditions and protect Fault input to permanently latch the application and protect
power stage from damage. against destruction. Figure 44 depicts the architecture of the
Once the voltage on the Fault input exceeds 1.04 V fault circuitry for NCP1397B controller.
threshold the external timer capacitor starts charging by The NCP1397A features second fault comparator as well
Itimer1 current. Simultaneously the Soft−Start discharge but in this case it doesn’t latches off the IC but speeds up the
switch is activated to shift operating frequency up to keep Fault timer capacitor charging by turning on additional
primary current at acceptable level. In case the overload current source Itimer2 – refer to Figure 43. The NCP1397A
disappears fast enough the Soft−Start discharge switch is can thus be used in applications that have to recover
open, Itimer1 current turned−off and timer capacitor automatically from any fault conditions.

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 NCP1397A/B, NCV1397A/B

discharge at VCC(on)/
VDD
restart if VFB < 0.3 V
SS(dis) Css
VDD

Itimer2
Itimer1
Ctimer Ctimer

UVLO
Reset Average
Rtimer Input
Current
+
+ - Fault To Primary
+ Current Sensing
Vref(fault) Circuitry
+ -

+
-
VtimerON 1 = ok
+ VCC
VtimerOFF 0 = fault
- Vref(OCP)
+

+ FB
Vref(skip)
FB

1 = ok
0 = fault

Reset Skip/Disable Skip

DRIVING SS
LOGIC

A A

B B

Figure 43. Fault Input Logic for NCP1397A

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 NCP1397A/B, NCV1397A/B

discharge at VCC(on)/
restart if VFB < 0.3 V
SS(dis) Css
VDD

Itimer1
Ctimer Ctimer

UVLO
Reset Average
Rtimer Input
Current
+
+ - Fault To Primary
+ Current Sensing
Vref(fault) Circuitry
+ -

to latch
+
-
VtimerON 1 = ok
+ VCC
VtimerOFF 0 = fault
- Vref(OCP)
+

+ FB
Vref(skip) FB

1 = ok
0 = fault

Reset Skip/Disable Skip

DRIVING SS
LOGIC

A A

B B

Figure 44. Fault Input Logic for NCP1397B

On Figures 43 and 44 examples, a voltage proportional to overload stays there, after a few tens of milli −seconds,
primary current, once averaged, gives an image of the input switching pulses will disappear and a protective
power in case Vin is kept constant via a PFC circuit. If the auto−recovery cycle will take place. Adjusting the resistor
output loading increases above a certain level, the voltage on R in parallel with the timer capacitor will give the flexibility
this pin will pass the 1 V threshold and start the timer. If the to adjust the fault burst mode (refer to Figure 45).

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 NCP1397A/B, NCV1397A/B

SMPS Stops

4V

Fault is Gone
SMPS Re−starts

1V

Reset at Re−start

Figure 45. A Resistor Can Easily Program the Capacitor Discharge Time

VCC lose regulation in light load conditions, forcing the FB level

to increase. When it reaches the programmed level, it
triggers the skip input and stops pulses. Then Vout slowly
drops, the loop reacts by decreasing the feedback level
which, in turn, unlocks the pulses, Vout goes up again and so
FB on: we are in skip cycle mode. As the feedback voltage does
not drop below 0.3 V the Soft−Start discharge switch is not
activated in this case. Please refer also to Figure 35 for skip
Skip/Disable mode function implementation when optocoupler is
connected directly to Rt pin.

Startup Behavior
When the VCC voltage increases, the internal current
Figure 46. Skip Cycle Can Be Implemented Via Two consumption is kept below Istrup. When VCC reaches the
Resistors on the FB Pin to the Fast Fault Input VCC(on) level, output Mlower goes high first and then output
Mupper. This sequence will always be the same whatever
triggers the pulse delivery: fault, OFF to ON etc… Pulsing
Skip/Disable the output Mlower high first gives an immediate charge of the
The Skip/Disable input is not affected by a delayed action. bootstrap capacitor. Then, the rest of pulses follow,
As soon as its voltage exceeds 0.66 V typical, all pulses are delivered at the highest switching value, set by the RFstart
off and maintained off as long as the fault is present. When resistor in parallel with RFmin resistor on Pin 4. The
the pin is released, pulses come back and the soft−start is soft−start capacitor ensures a smooth frequency decrease to
activated (in case the VFB < 0.3 V). either the programmed minimum value (in case of fault) or
Thanks to the low activation level, this pin can observe the to a value corresponding to the operating point if the
feedback pin via a resistive divided and thus implement skip feedback loop closes first. Figure 47 shows typical signals
cycle operation. The resonant converter can be designed to evolution at power on.

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 NCP1397A/B, NCV1397A/B

Figure 47. At Power On, Output A is First Activated and the Frequency Slowly Decreases Based on the Soft−Start
Capacitor Voltage

Figure 47 depicts an auto−recovery situation, where the stops the output pulses whenever it is activated, that is to say,
timer has triggered the end of output pulses. In that case, the when VCC falls below 9.5 V typical. At this time, the VCC
VCC level was given by an auxiliary power supply, hence its pin still receives its bias current from the startup resistor and
stability during the hiccup. A similar situation can arise if the increases toward VCC(on). When the voltage reaches
user selects a more traditional startup method, with an VCC(on), a standard sequence takes place, involving a
auxiliary winding. In that case, the VCC(min) comparator soft−start. Figure 48 portrays this behavior.

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 NCP1397A/B, NCV1397A/B

Figure 48. When the VCC is to Low, All Pulses are Stopped Until VCC Goes Back to the Startup Voltage

The High−Voltage Driver

The driver features a traditional bootstrap circuitry, refueling path. Figure 49 shows the internal architecture of
requiring an external high−voltage diode for the capacitor the high−voltage section.

HV
Vboot
B Pulse Level
Trigger Shifter S Cboot
Q Mupper
Q
R
HB

UVLO Dboot
VCC aux
VCC
Fault
Mlower
A Delay
+
GND

Figure 49. The Internal High−voltage Section of the NCP1397

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 NCP1397A/B, NCV1397A/B

The device incorporates an upper UVLO circuitry that As stated in the maximum rating section, the floating
makes sure enough Vgs is available for the upper side portion can go up to 600 VDC and makes the IC perfectly
MOSFET. The B and A outputs are delivered by the internal suitable for offline applications featuring a 400 V PFC
logic, as Figure 43 testifies. A delay is inserted in the lower front−end stage.
rail to ensure good matching between these propagating
signals.

ORDERING INFORMATION
Device Package Shipping†
NCP1397ADR2G
NCV1397ADR2G* SOIC−16, Less Pin 13
2500 / Tape & Reel
NCP1397BDR2G (Pb−Free)
NCV1397BDR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 NCP1397A/B, NCV1397A/B

PACKAGE DIMENSIONS

SOIC−16 NB, LESS PIN 13

CASE 751AM
ISSUE O

D A B NOTES:
16 9 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 TOTAL IN EXCESS OF THE b DIMENSION AT
H E MAXIMUM MATERIAL CONDITION.
C 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

MILLIMETERS
0.25 M B M 1 8 L
e b 15X DIM MIN MAX
15X A 1.35 1.75
0.25 M T A S B S A1 0.10 0.25
b 0.35 0.49
C 0.19 0.25
D 9.80 10.00
SEATING A1 h x 45 _
C PLANE
E 3.80 4.00
e 1.27 BSC
A H 5.80 6.20
h 0.25 0.50
L 0.40 1.25
M M 0_ 7_

SOLDERING FOOTPRINT*
6.40
15X 1.12
1 16

15X
0.58

1.27
PITCH

8 9

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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27