Full custom design flow for a

transimpedance amplifier using Cadence

Virtuoso
Cite as: AIP Conference Proceedings 2222, 020004 (2020); https://doi.org/10.1063/5.0003971
Published Online: 16 April 2020

Sanjana Anna Lukose, and Anu Assis

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AIP Conference Proceedings 2222, 020004 (2020); https://doi.org/10.1063/5.0003971 2222, 020004

© 2020 Author(s).
 Full Custom Design Flow For A Transimpedance Amplifier
Using Cadence Virtuoso
Sanjana Anna Lukose1, a) and Anu Assis1, b)

1
Thangal Kunju Musaliar College Of Engineering, Kollam, Kerala, India
a)
sanjanaanna@gmail.com
b)
anushafi@gmail.com

Abstract. The paper deals with the design of a Transimpedance Amplifier (TIA) using Cadence Virtuoso and also
mentions the full custom IC design flow. The Transimpedance Amplifier is generally a current to voltage converter.
The design was done in 90nm CMOS technology and was able to simulate a large value for gain-bandwidth product.

INTRODUCTION
The full custom design flow of a VLSI design layout means the design includes from the beginning like from the
circuit level of design. It can be defined as a methodology in order to design an integrated circuit by specifically
mentioning the layout of each and every transistor and all the connections between them. This type of design can be
advantageous as it can maximize the performance of the chip by minimizing the area. This paper shows the full
custom design flow using the design of a TIA and all the simulations and design work was done in Cadence. The
TIA was designed using the 90nm technology. The TIA is widely used in visible light communication, photodiode
and sensor applications.

FULL CUSTOM DESIGN FLOW

The full custom design as mentioned in the introduction means the whole design procedure including the
beginning part like the schematic design. There are other types of design like semi design flow instead of the
schematic entry it has HDL entry. The following part explains every steps in the full custom design flow using the
design of a TIA with 90nm CMOS Technology.

Proceedings of the International Conference on Microelectronics, Signals and Systems 2019

AIP Conf. Proc. 2222, 020004-1–020004-5; https://doi.org/10.1063/5.0003971
Published by AIP Publishing. 978-0-7354-1981-0/$30.00

020004-1
 Full Custom IC Design Flowchart

The chart below shows the flowchart of a full custom IC design flow:
START

SCHEMATIC ENTRY

SIMULATION

LAYOUT
Schematic Entry
PHYSICAL VERIFICATION

RC-EXTRACTION

GDS II

The schematic entry is the first step in this design flow. It means the schematic design of the circuit where we
can specify the transistor values and make the required interconnections between them. In this step connections were
made according to the circuit by using Cadence Virtuoso Schematic Editor. The specifications of each transistor and
other components used in the circuit can be varied as per required using the editor specifications.

FIGURE 1: Schematic representation of TIA using Virtuoso Editor

Simulation
This step involves the testing part of the schematic circuit that is designed. The simulation is done so as to check
whether the circuit is working. Thus the functioning check is done during the simulation part. The simulation was
done using the multimode simulator- ADE L from Cadence Virtuoso. Thus during the simulation we can obtain
various outputs regarding the circuit. In the design of the TIA the input-output graph and the gain graph was plotted.
The plots are shown in figure 2 and 3 respectively.

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 FIGURE 2: Input-Output Plot

FIGURE 3: Gain Plot of the TIA

Layout
The layout of the schematic representation is the design of the IC on the basis of the actual size. This actually
helps in finding the actual area as well as power loss and so on. The layout design can be done using Layout XL in
Cadence. The figure 4 shows the layout of the TIA designed.

FIGURE 4: Layout of TIA using Layout XL

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 Physical Verification
The physical verification step involves three different steps included. They are DRC, LVS and QRS. The DRC
check in physical verification step means to check the dimensions of the layout. The LVS means Layout Versus
Schematic and is done to check whether the schematic and layout matches. The QRC in physical verification means
to extract the parasites from the design. These three verification steps are to be successfully done in physical
verification step once the layout has been over. These steps are done using Assura in Cadence.

RC Extraction
The RC extraction step is done as the next step after the physical verification. This can be considered as a
continuation step to QRC. In this RC extraction actually the parasites included in the design are extracted. That is
displays all the components including the parasites are displayed. The figure 5 shows the tree display in RC
Extraction step. This RC Extraction is also done using Assura in Cadence.

FIGURE 5: Tree mode display in RC Extaction

GDS II
This is the final step of a full custom design flow. The GDS II step is done in order to generate the stream out file.
This step is done using Virtuoso. The stream out file shows all the components and layout specifications and other
errors if any presented. Thus it can be considered as a consolidated data of the layout design. The figure 5 shows the
steam out file generated in the design of the TIA.

FIGURE 6: Stream out file generated during GDS II using Virtuoso

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 CONCLUSION
The paper thus explains a full custom design flow using the design of a Tranimpedance amplifier of 90nm CMOS
Technology. The whole work was done using Cadence Virtuoso. Therefore a 90nm Transimpedance Amplifier was
designed with a high value of gain-bandwidth product. The gain obtained was around 25dB and bandwidth obtained
was almost GHz range. Thus the TIA can be used in various applications where the output is current but the
required output is current like a photodiode.

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