YDA147

D- 515
STEREO 5W-15W DIGITAL AUDIO POWER AMPLIFIER

■Overview
YDA147 (D-515) is a high-efficiency digital audio power amplifier IC with the maximum output of 15W × 2ch.
YDA147 has a “Pure Pulse Direct Speaker Drive Circuit” that directly drives speakers while reducing distortion of
pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate
characteristics and low noise characteristics among digital amplifier ICs in the same class.
In addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use
conditions.
YDA147 features Power Limit Function, Non-clip Function, and DRC (Dynamic Range Control) Function that were
developed by Yamaha original digital amplifier technology.
YDA147 has overcurrent protection function for speaker output terminals, high temperature protection function, and
lowsupply voltage malfunction prevention function.

■Features
・Operating supply voltage range
PVDD: 8.0V to 16.5V
・Maximum momentary output
20 W×2ch (VDDP=14V, RL=4Ω, THD+N=10%)
15 W×2ch (VDDP=12V, RL=4Ω, THD+N=10%)
・Maximum continuous output
15 W*1×2ch (VDDP=15V, RL=8Ω, THD+N=10%, Ta=70°C)
10.5W*1×2ch (VDDP=15V, RL=4Ω, THD+N=10%, Ta=25°C)
・Distortion Rate (THD+N)
0.01 % (VDDP=12V, RL=8Ω, Po=0.1W, 1kHz)
・Residual Noise
48µVrms (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Efficiency
92 % (VDDP=12V, RL=8Ω)
・S/N Ratio
105 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Channel separation
-80 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・PSRR
60dB (VDDP=12V,Vripple=100mV, 1kHz, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Non-clip function/DRC function (switchable)
・Power limit function
・Clock External Synchronization Function
・Master/Slave Synchronization Function using clock outputs
・Over-current Protection Function, High Temperature Protection Function,
Low Voltage Malfunction Prevention Function, and DC Detection Function
・Sleep Function using SLEEPN terminal and Output Mute Function using MUTEN terminal
・Stereo/Monaural Switching Function
・Spread Clock Function
・Pop Noise Reduction Function
・Package
Lead-free 48-pin Plastic SQFP (Exposed stage)

Note) *1: A value based on Yamaha's board implementation conditions (See Note *2 of page 25)

YDA147 CATALOG
CATALOG No.:LSI-4DA147A41
2007.9
 YDA147
■Terminal Configuration

< 48-pin SQFP Top View >

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YDA147
■Terminal Function

No. Name *4) I/O *1), *2), *3) Function

1 NC − Normally, use this terminal in no-connection
2 NC − Normally, use this terminal in no-connection
3 PVDDREG PVDD Power supply terminal for regulators
4 AVDD OA 3.3V regulator output terminal
5 INLP IA Analog input terminal (Lch+)
6 INLM IA Analog input terminal (Lch-)
7 VREF OA Reference voltage output terminal
8 INRM IA Analog input terminal (Rch-)
9 INRP IA Analog input terminal (Rch+)
10 AVSS GND Analog ground terminal
11 PLIMIT IA Power limit setting terminal
12 NC − Normally, use this terminal in no-connection
13 PVDDPR PVDD Power supply terminal for digital amplifier output (Rch+)
14 PVDDPR PVDD Power supply terminal for digital amplifier output (Rch+)
15 OUTPR O Digital amplifier output terminal (Rch+)
16 OUTPR O Digital amplifier output terminal (Rch+)
17 OUTPR O Digital amplifier output terminal (Rch+)
18 PVSSR GND Ground terminal for digital amplifier output (Rch)
19 PVSSR GND Ground terminal for digital amplifier output (Rch)
20 OUTMR O Digital amplifier output terminal (Rch-)
21 OUTMR O Digital amplifier output terminal (Rch-)
22 OUTMR O Digital amplifier output terminal (Rch-)
23 PVDDMR PVDD Power supply terminal for digital amplifier output (Rch-)
24 PVDDMR PVDD Power supply terminal for digital amplifier output (Rch-)
25 NC − Normally, use this terminal in no-connection
26 SLEEPN I Sleep control terminal
27 PROTN O/D Error flag output terminal
28 MUTEN I MUTE control terminal
29 CKOUT O Clock output terminal for synchronization
30 CKIN I External clock input terminal
31 NCDRC0 I Non-clip/DRC1/DRC2 mode selection terminal 0
32 NCDRC1 I Non-clip/DRC1/DRC2 mode selection terminal 1
33 GAIN0 I GAIN setting terminal 0
34 GAIN1 I GAIN setting terminal 1
35 NC − Normally, use this terminal in no-connection
36 NC − Normally, use this terminal in no-connection
37 PVDDML PVDD Power supply terminal for digital amplifier output (Lch-)
38 PVDDML PVDD Power supply terminal for digital amplifier output (Lch-)
39 OUTML O Digital amplifier output terminal (Lch-)
40 OUTML O Digital amplifier output terminal (Lch-)
41 OUTML O Digital amplifier output terminal (Lch-)
42 PVSSL GND Ground terminal for digital amplifier output (Lch)
43 PVSSL GND Ground terminal for digital amplifier output (Lch)
44 OUTPL O Digital amplifier output terminal (Lch+)
45 OUTPL O Digital amplifier output terminal (Lch+)
46 OUTPL O Digital amplifier output terminal (Lch+)
47 PVDDPL PVDD Power supply terminal for digital amplifier output (Lch+)
48 PVDDPL PVDD Power supply terminal for digital amplifier output (Lch+)
(Note) *1 I: Input terminal, O: Output terminal, A: Analog terminal, O/D: Open/Drain output terminal
*2 PVDD should be connected each other on a board.
*3 GND should be connected each other on a board.
*4 Each output terminal with the same name (OUTPR, OUTMR, OUTPL, and OUTML) should be connected on a
board.

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 YDA147
■Block Diagram

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YDA147
■Functional Description

● Digital Amplifier Function

YDA147 has digital amplifiers with analog input, PWM pulse output, the maximum output of 20W × 2ch.
Adopting “Pure Pulse Direct Speaker Drive Circuit” reduces distortion and noise on PWM pulse output signal.
・Digital Amplifier Gain
The total gain of the digital amplifier varies depending on operation modes, as shown below.

NCDRC1 NCDRC0 GAIN1 GAIN0 Total Gain Operation Mode

L L +22dB
Normal mode
L H +28dB
L L Non-clip: OFF
H L +34dB
DRC: OFF
H H +16dB
L L +34dB
L H +40dB
L H Non-clip mode
H L +46dB
H H +28dB
L L +34dB
L H +40dB
H L DRC1 mode
H L +46dB
H H +28dB
L L +34dB
L H +40dB
H H DRC2 mode
H L +46dB
H H +28dB

・Audio Signal Input

For a differential input, the signal should be input to INLP and INLM terminals (Lch) and to INRP and INRM terminals
(Rch) through a DC-cut capacitor (CIN).

On the contrary, for a single-ended input, the signal should be input to INLP terminal (Lch) and to INRP terminal (Rch)
through a DC-cut capacitor (CIN). At this time, INLM and INRM terminals should be connected to AVSS through DC-cut
capacitors (CIN) with the same value.

In the differential input mode, use signal sources with the same impedance to reduce pop-noise. Its value should be 10kΩ or
less. Use a DC-cut capacitor (CIN) of 1µF. (The capacitance value should be less than 1.5µF throughout the operating
temperature range.)

(Cautions)
When inputting audio signals in Power-off state ( PVDD < VHUVLL ) or Sleep state, current may flow toward the former
device from YDA147's ground, through each protection circuit of analog pins (INLP, INLM, INRP, and INRM).
For this reason, audio signals should not be input in Power-off state ( PVDD < VHUVLL ) or Sleep state.

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 YDA147
・Input Impedance
The input impedance (ZIN) is 18.8kΩ regardless of a Gain setting.

・Reference Voltage Output Function

Half a voltage of AVDD terminal is output to the reference voltage terminal (VREF).
Connect a capacitor of 0.1µF for voltage stabilization.

・Maximum Output
The output varies depending on load impedance and a supply voltage, as shown below.

Maximum momentary Output 20W×2ch (PVDD=14V, RL=4Ω, THD+N=10%)

15W×2ch (PVDD=12V, RL=4Ω, THD+N=10%)
Maximum Continuous Output 15W×2ch (PVDD=15V, RL=8Ω, THD+N=10%, Ta=70℃)
10.5W×2ch (PVDD=15V, RL=4Ω, THD+N=10%, Ta=25℃)

The maximum momentary output means a possible maximum output by considering heat problems due to power
loss separately.
The maximum continuous output means a maximum output with Tjmax not exceeding 150°C at a given
temperature while outputting a sine wave continuously. In addition, this value is based on Yamaha's board
implementation conditions. (See Note *2 of Page 25)

A possible maximum continuous output in other settings can be converted by the following data:
1. Graph of Power Dissipation vs Output Power of Example of typical characteristics. (See Page 29)
2. Power Dissipation of Electrical Characteristics. (See Page 25)

●Control Function

・Output Power limit Function

This is the function to set a voltage at which the output is clipped. AVDD
At this time, a value at which the output is clipped is defined as a power limit value
(VPL).
Using this function prevents increase of temperature in a device as well as allowing Voltage
Dividing
the maximum output power to be limited. Resistor R1
The output power limit value is determined by a voltage (voltage dividing resistor 1, PLIMIT
2) applied to PLIMIT terminal.
In addition, changing the voltage at PLIMIT terminal during power-on is prohibited.
Voltage
Dividing
The relation between a resistor ratio (R2/(R1+R2)(between voltage dividing resistor Resistor R2
1 and 2) and an output power with a 10% distortion is shown below. AVSS
Since it may vary between MIN and MAX due to variation of internal AVDD, select
resistors in consideration of the variation.
The setting values shown here are common to stereo and monaural mode.
PLIMIT terminal setting circuit
PLIMIT resistor R1 and R2 should be set as follows.
R1+R2=500kΩ or less
R1//R2=50kΩ to 70kΩ (R1//R2 means a parallel resistance between R1 and R2)

Example 1: 4Ω max30W (8Ω max15W)

R1=220k+4.7k, 、R2=75k
Example 2: 8Ω min10W
R1=200k, R2=75k+1.5k

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YDA147
* Minimum value restriction on the output power limit.
The minimum value of the output-power limit values is restricted by the value determined with the resistance voltage
division ratio of 0.45.
Even though the resistance voltage division ratio is set beyond 0.45, the output-power limit value wouldn t be set
lower.

* Cancellation of the output power limit function.

It is possible to disable the power limit by setting 0 V (voltage division ratio 0 ) to the PLIMIT pin.

Enlarged Figures
PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （4Ω） PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （4Ω）

35 10

Typ Typ
9
30 MIN MIN
MAX MAX
8

Output Power at 10％ distortion [W]

Output Power at 10％ distortion [W]

25 7

6
20

5
15
4

10 3

2
5
1

0 0
0.300

0.350

0.400

0.450

0.500
0.200

0.250

0.300

0.350

0.400

0.450

0.500

PLIMIT Voltage Dividing Ratio PLIMIT Voltage Dividing Ratio

PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （8Ω） PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （8Ω）

18 10
Typ
16 Typ 9 MIN
MIN MAX
Output Power at 10％ distortion [W]

Output Power at 10％ distortion [W]

MAX 8
14

7
12
6
10
5
8
4
6
3

4
2

2 1

0 0
0.200

0.250

0.300

0.350

0.400

0.450

0.250

0.300

0.350

0.400

0.450

PLIMIT Voltage Dividing Ratio PLIMIT Voltage Dividing Ratio

PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （16Ω） PLIMIT Voltage Dividing Ratio vs Output Power at 10％ distortion （16Ω）

9 5

4.5 Typ
8 Typ
MIN
MIN
MAX
Output Power at 10％ distortion [W]

MAX 4
7
Output Power at 10％ distortion [W]

3.5
6
3
5
2.5
4
2
3
1.5

2
1

1 0.5

0 0
0.200

0.250

0.300

0.350

0.400

0.450

0.250

0.300

0.350

0.400

0.450

PLIMIT Voltage Dividing Ratio PLIMIT Voltage Dividing Ratio

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 YDA147
・Non-clip/DRC Function
This is the function to change the gain by detecting an input level to the PWM amplifier and to raise an average output
level while suppressing clipping.
A mode is determined by the combination of NCDRC[1:0] terminals, as shown below.

NCDRC1 NCDRC0 Mode

L L Non-clip & DRC mode OFF
L H Non-clip mode
H L DRC1 mode
H H DRC2 mode

In Non-clip mode, the gain increases by 12dB. The gain is automatically adjusted so that an output peak voltage becomes
a power limit value. The maximum attenuation is -12dB. Attack Time is 0 second. The release time from -12dB to 0dB is
7.7 s (typ.).

In DRC1 mode, the gain increases by 12dB. Dynamic Range Compression (a half of gain in dB) is performed within an
output range of -12dB (-24dB for input range) from the power limit value. Attack Time is 0 s. The release time from
-12dB to 0dB is 3.9 s (typ.).

In DRC2 mode, the gain increases by 12dB. As with DRC1, similar compression is performed, but power-limit operation
is not performed. PLIMIT terminal can be used to set a DRC operating point. Therefore, the setting of a gain curve is
possible regardless of the maximum output power, and this allows for DRC operation from a low output power.
NCDRC [1:0] terminal should be switched under either of the following conditions.
・Before PVDD power-on (lower than the PVDD start-up threshold voltage (VHUVLH))
・SLEEPN=L
Pop noise may occur when switching it under an operating condition other than the above.

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YDA147

A condition in which the

power limit is being applied.

Power Limit Value （VPL）

OFF
NCDRC[1:0]=00
Output Voltage [dB]

Output Voltage [dB]

Input Voltage [dB] 0

Non-clip/DRC Gain Curve (OFF)

A condition in which the

power limit is being applied.

Power Limit Value （VPL）

Non-clip
NCDRC[1:0]=01

OFF
NCDRC[1:0]=00
Output Voltage [dB]

Output Voltage [dB]

-12
Input Voltage [dB] 0

Non-clip/DRC Gain Curve (Non-clip)

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 YDA147
A Condition パワーリミットが掛
in which the
power limit is being applied.
かっている状態

パワーリミット値（V
Power Limit Value (VPL) PL）

DRC1
NCDRC[1:0]=10

OFF
VPL - 12dB
NCDRC[1:0]=00
出力電圧[dB]

Output Voltage [dB]

-24 入力電圧[dB] 0
Input Voltage [dB]

Non-clip/DRC Gain Curve (DRC1)

A condition in which it is not applied

even if exceeding the power limit.

Power Limit Value （VPL）

DRC2
NCDRC[1:0]=11

OFF
VPL - 12dB
NCDRC[1:0]=00
Output Voltage [dB]

Output Voltage [dB]

-24 Input Voltage [dB] 0

Non-clip/DRC Gain Curve (DRC2)

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YDA147
・Sleep Function
YDA147 shifts into sleep mode when SLEEPN terminal goes to “L” level.
In the sleep mode, all functions stop and consumption current is minimized (ＩSLEEP).
When shifting into sleep mode during any protection mode, the protection mode is cancelled and PROTN terminal output
becomes Hi-Z state.
The digital amplifier output becomes Weak Low (a state grounded through a high resistance).
AVDD and VREF outputs are pulled down.
When the level at SLEEPN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation, the sleep
mode is cancelled and the state shifts into the normal operation state after the period of sleep recovery time (tWU).

・Mute Function
YDA147 shifts into mute mode when MUTEN terminal goes to “L” level.
In the mute mode, the digital amplifier output becomes Weak Low (a state grounded through a high resistance).
When the level at MUTEN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation and state of
SLEEPN terminal=H, the mute mode is cancelled and the state shifts into the normal operation state after the period of
mute recovery time (tMRCV).

・Clock Control Function

The setting of CKIN terminal controls the clock mode as shown below.

CKIN terminal Setting Mode CKOUT

L fixed Internal Clock mode Internal Clock (frequency: fCK) output
H fixed Internal Clock (Spread clock) mode Internal Clock (Spread Clock) frequency: (fCK)
output
Clock input External Clock mode CKIN input buffer output (frequency: fCKIN)

When CKIN terminal is held L or H level, internal clock mode is selected to generate a clock internally.
And, when CKIN terminal is held H level, Spread Clock function operates to reduce EMI.
When an external clock is input to CKIN terminal, its frequency should be fCKIN.
Do not use with CKIN terminal left open.

・Stereo/Monaural Switching Function

When INRP and INRM terminals (Rch input) are connected to AVDD, monaural mode is selected.
In the monaural mode, input signals input to INLP and INLM terminals (Lch input) are output from Lch and Rch digital
amplifiers.
With the monaural mode, parallel operation can be realized by connecting OUTPL to OUTPR and connecting OUTML
to OUTMR.
For details of connections, see “Single operation in monaural mode” (See page 20) in the “Examples of Application
Circuits.”
The switching between stereo and monaural modes should be performed under the following conditions.
・Before PVDD power-on (lower than the PVDD shut-down threshold voltage)

・Digital Amplifier Pop Noise Reduction Function

Pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by
minimizing an output offset voltage.

・Multi-chip Synchronization Function

The external clock synchronization function and clock output function are prepared and the use of master/slave
configuration realizes carrier clock synchronization.
When using it with multi chips synchronized, one is used as a master chip and the other is used as a slave chip. At this
time, connect CKOUT terminal of a master chip to CKIN terminal of a slave chip.
When using 3 chips (master/slave1/slave2), connect CKOUT terminal of a slave1 chip to CKIN terminal of a slave2 chip.
For details of connections, see “MASTER-SLAVE operation” (See page 23 and 24) in the “Examples of Application
Circuits.”
PVDD pins should be connected each other on a board.

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 YDA147
・Startup Sequence, Shutdown Sequence

VDDP

PVDD VHUVLH

VDDA
AVDD

tWU

OUTPL/OUTPR

OUTML/OUTMR

Digital Amplifier Output

Power Supply Startup Sequence

VDDP

PVDD
VHUVLH

VDDA
AVDD

OUTPL
/OUTPR

OUTML
/OUTMR

Digital Amplifier Output Stopping Digital Amplifier Output

Power Supply Shutdown Sequence

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YDA147

VIH_SLPN
SLEEPN

AVDD
tWU

OUTPL
/OUTPR

OUTML
/OUTMR

Digital Amplifier Output

Startup Sequence from Sleep State

SLEEPN VIL_SLPN

AVDD

OUTPL
/OUTPR

OUTML
/OUTMR

Digital Amplifier Output Stopping Digital Amplifier Output

Transient Sequence to Sleep State

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 YDA147
● Regulator Output

When SLEEPN terminal is at H, YDA147 outputs VDDA to AVDD terminal. Connect a capacitor of 1µF to 4.7µF to
AVDD terminal for stabilization. (0.8µF or more should be secured including its variation and temperature change.)
AVDD output must be used only for YDA147. If this output is used in a peripheral circuit of YDA147, the maximum
current that can be driven will be IDDA.

●LC Filter

YDA147 adopts the modulation method that reduces speaker loss sufficiently at mute state by the use of only an inductance
the speaker has, and this allows for direct connection to a speaker without an LC filter.
When an LC filter is used, use the LC filter circuits shown below. At this time, the following constant should be used
according to an impedance of a speaker. Using these constants makes a low-pass filter with a cut-off frequency of 50kHz or
so, Q=0.7 or so.

LC filter constants:
RL L1 C1 C2
4Ω 10μH 0.33μF 0.22μF
8Ω 22μH 0.22μF 0.1μF

L1
L1 RL
C1
RL L1
C1
L1
C2 C2
C2 C2

LC Filter circuit (Stereo) LC Filter circuit (Monaural)

* With use of LC filters, if there is a possibility of not using a speaker, audio signals within 20kHz should be input.
And, if its band limitation is not possible, remove the speaker under the following conditions: SLEEPN terminal = L or
MUTEN terminal = L, or PVDD = Power Off.

●Speaker Inductance

In the following cases, use a speaker with an inductance of 20µH or more (at around the switching frequency (fCKIN or fCK)).
1. Direct connection of a speaker to an output pin of the digital amplifier without an LC filter.
2. Connection of a speaker to a position after components for EMI measures such as ferrite beads etc. (filterless).
With an inductance of less than 20µH, power loss in the speaker and this device may increase.

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YDA147
●Protection Function

YDA147 has the following four digital amplifier protection functions: overcurrent protection function, high temperature
protection function, low voltage malfunction prevention function, and DC detection function.

Protection Functions PROTN PROTN Digital Amplifier Protection Mode Cancel

terminal terminal Output State
Output Latch
Over current SLEEPN terminal=L or
Low Latched WL*1)
Protection Function PVDD shutdown
High Temperature SLEEPN terminal=L or
Power Limit
Protection Function − Not latched PVDD shutdown or
(-6dB)
(High Temp. power limiter state) lower temperature
High Temperature SLEEPN terminal=L or
Protection Function Low Not latched WL*1) PVDD shutdown or
(High Temp. shutdown state) lower temperature
Low Voltage Malfunction
(HighZ) − WL*1) −
Prevention Function
SLEEPN terminal=L or
DC Detection Function Low Latched WL*1)
PVDD shutdown
*1: WL=Weak Low (a state when grounded with a high resistance)

Use a circuit as shown below when pulling up PROTN terminal output externally.
1) Pull up the terminal to a voltage obtained by dividing the voltage between PVDD and GND with voltage-dividing
resistors.
Find values with reference to the following formula so that a voltage at the terminal becomes 3.3V or less when
PROTN terminal is in “H” output (Hi-Z).
2.0V ≦ (R2 / (R1 + R2)) × VDDP ≦ 3.3V ;however, R1 > 100kΩ, 10kΩ < R2 < 100kΩ

2) The pull-up should be performed to an external supply voltage lower than 3.3V. The pull-up resistor R3 should be a
value as follows. 40kΩ < R3 < 200kΩ (47kΩ is recommended.)

In each case, select these values so that 0.4mA or more current will not flow into the terminal while PROTN terminal is in
L state.

PROTN terminal Pull-Up Connection 1 (A pull-up to PVDD)

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 YDA147

VCC(3.3V)

R3

PROTN
Error
Flag

PROTN terminal Pull-Up Connection 2 (A pull-up to 3.3V)

* If automatic return setting is given by connecting PROTN terminal to SLEEPN terminal, use a separate power supply
as VCC, not the same power supply as AVDD.
* When VCC is used as AVDD, see Startup Sequence (page 12 and 13).

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YDA147
・Digital Amplifier Over current Protection Function
This is the function to protect the device by detecting short-circuiting (to the supply voltage, to the ground, and between
terminals) at digital amplifier output terminals.
In the protection mode, PROTN terminal becomes L level and output terminals become Weak Low state (a state
grounded through a high resistance).
The protection mode can be cancelled by turning off the power supply or inputting an L level signal to SLEEPN terminal
momentarily.
And, when PROTN terminal is externally connected to SLEEPN terminal, automatic return mode is selected. At this time,
the protection mode is cancelled even if the protection mode is established by detecting an overcurrent state, and PROTN
terminal output is turned from L level into Hi-Z state and a normal operation state is given after a given standby time
(tWU). (Automatic Return Function)
The current value to detect a short-circuiting between terminals is 8A (typ,VDDP=12V), 10A (typ,VDDP=15V).

・High Temperature Protection Function

This is the function to protect the device by detecting an unusual temperature in YDA147.
The protection mode operates in the following two modes according to the temperature.

1) High Temperature Power Limiter State

If the temperature rises and reaches 155°C (typ.), the high temperature power limiter state is given. This state
decreases the power limit level by 6dB in order to limit the digital amplifier output power, and attempts to lower the
temperature.
In this way, when the temperature falls and lowers than 130°C (typ.), the high temperature power limiter state is
automatically cancelled and the gain is restored to the original setting value.
In the power limiter state, this does not affect on PROTN terminal.

2) High Temperature Cutoff State

If the temperature rises and reaches 165°C (typ.) during the high temperature power limiter state, the high temperature
cutoff state is given. This state outputs an L level signal from PROTN terminal and digital amplifier output terminals
become Weak Low state (a state grounded through a high resistance).
In this way, when the temperature goes down and lowers than 130°C (typ.), the high temperature cutoff mode is
automatically cancelled.

And, even if the cutoff state is established by detecting an unusual temperature, when PROTN terminal is externally
connected to SLEEPN terminal, the cutoff state is cancelled and PROTN terminal output is turned from L into Hi-Z
state and a normal operation state is given if the temperature is sufficiently lowered after a given standby time (tWU).
(Automatic Return Function)
If the temperature is not sufficiently lowered, the high temperature protection mode will be established.

・Low Voltage Malfunction Prevention Function

This is the function to protect the device when the supply voltage at PVDDREG terminal is unusually lowered.
In this protection mode, the digital amplifier output terminals become Weak Low state (a state grounded through a high
resistance).
This protection mode is given if the supply voltage at PVDDREG terminal becomes a voltage lower than PVDD
shutdown threshold voltage (VHUVLL).
When the supply voltage at PVDDREG terminal exceeds PVDD startup threshold voltage (VHUVLH), the protection mode
is cancelled and a normal operation mode is given after a given standby time (tWU). (Automatic Return Function)

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 YDA147
・DC Detection Function
This is the function to protect the speaker connected to the digital amplifier output when a DC signal is continuously
output from the digital amplifier.
When MUTEN terminal=L, the DC detection function is disabled.
When a voltage in excess of a given time (tDCDET) and a given level (VDCDET) is output to the digital amplifier output, the
DC detection mode is given. This state outputs an L level signal from PROTN terminal and digital amplifier output
terminals become Weak Low state (a state grounded through a high resistance).
Once the DC detection mode is given, an L level signal keeps outputting from PROTN terminal even if the DC output
state is cancelled. The protection mode is cancelled by turning off the power supply or inputting an L level signal to
SLEEPN terminal momentarily.
And, even if DC protection mode is established by detecting a DC signal, when PROTN terminal is externally connected
to SLEEPN terminal, the protection mode is cancelled and PROTN terminal output is turned from L into Hi-Z state and a
normal operation state is given after a given standby time (tWU).

18
YDA147
■Examples of Application Circuits
(Caution)

・A ceramic capacitor of 1µF should be used as a bypass capacitor between the following terminals: PVDDPL-PVSSL, PVDDML-PVSSL,
PVDDPR-PVSSR, and PVDDMR-PVSSR. Please mount the capacitor as close as possible to each terminal.
・A former-stage impedance of input terminals should be 10kΩ or less.
・Select resistor values so that a voltage becomes 2.0V to 3.3V when PROTN terminal is at H level and current becomes 0.4mA or less
when PROTN terminal is at L.
・For PLIMIT terminal setting, see page 5 and 6.
・For a pull-up resistor for PROTN terminal, see page 14 and 15.

Single operation in stereo mode (differential-input, external clock operation)

VSSP
V DDP V DDP VDDP

1uF 1uF

220uF
PVDDPL

OUTPL

OUTPL

PVSSL

PVSSL

OUTML

OUTML
OUTPL

OUTML

PVDDML

PVDDML
PVDDPL

V DDP
NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN External Clock

Rch Input- INRM CKOUT (open)

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN V CC
Error Flag
PLIMIT SLEEPN Sleep Control

V SSA NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

V DDP V DDP
VSSP

19
 YDA147
:

Single operation in stereo mode (single-ended input, external clock operation)

V SSP
VDDP V DDP V DDP

1uF 1uF

220uF

PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
OUTPL

OUTPL

OUTML

OUTML
PVDDPL

PVDDML

PVDDML
V DDP NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
INLM NCDRC0

0.1uF
VREF CKIN External Clock

INRM CKOUT (open)

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN VCC
Error Flag
PLIMIT SLEEPN Sleep Control

V SSA NC NC

PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

V DDP V DDP
V SSP

Single operation in stereo mode (differential-input, input signal level (externally set), external clock operation)

VSSP
VDDP V DDP V DDP

1uF 1uF

220uF
PVDDPL

OUTPL

OUTPL

OUTPL

PVSSL

PVSSL

OUTML

OUTML
PVDDPL

OUTML

PVDDML

PVDDML

V DDP
NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN External Clock

Rch Input- INRM CKOUT (open)

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN V CC
Error Flag
PLIMIT SLEEPN Sleep Control

NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

V SSA

1uF 1uF

V DDP V DDP
VSSP

20
YDA147

Single operation in stereo mode (single-ended input, input signal level (externally set), external clock operation)

V SSP
VDDP V DDP V DDP

1uF 1uF

220uF

PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
OUTPL

OUTPL

OUTML

OUTML
PVDDPL

PVDDML

PVDDML
V DDP

NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF mode select
INLM NCDRC0

0.1uF
VREF CKIN External Clock

INRM CKOUT (open)

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN VCC
Error Flag
PLIMIT SLEEPN Sleep Control

NC NC

PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

V DDP VDDP
V SSP

Single operation in monaural mode (differential-input, external clock operation)

VDDP V DDP V DDP

1uF 1uF

220uF
OUTPL

OUTML
PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
PVDDPL

OUTPL

OUTML

PVDDML

PVDDML

V DDP
NC NC

NC NC

PVDDREG GAIN1
0.1uF Gain
Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN External Clock

INRM CKOUT (open)

INRP MUTEN Mute Control

AVSS PROTN V CC
Error Flag
PLIMIT SLEEPN Sleep Control

NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR

VSSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

V DDP V DDP
V SSP

21
 YDA147

Single operation in stereo mode (differential-input, internal clock operation)

VSSP
V DDP VDDP VDDP

1uF 1uF

220uF

PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
OUTPL

OUTPL

OUTML

OUTML
PVDDPL

PVDDML

PVDDML
V DDP
NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN AVSS

Rch Input- INRM CKOUT (open)

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN V CC
Error Flag
PLIMIT SLEEPN Sleep Control

NC NC

PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR
V SSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

VDDP V DDP
VSSP

Single operation in stereo mode (differential-input, external clock operation, automatic return setting)

V SSP
VDDP V DDP V DDP

1uF 1uF

220uF
PVDDPL

OUTPL

OUTPL

PVSSL

PVSSL

OUTML

OUTML
OUTPL

OUTML

PVDDML

PVDDML
PVDDPL

V DDP
NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN External Clock

V DDP
Rch Input- INRM CKOUT (open)
1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN

PLIMIT SLEEPN

NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR

V SSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

V SSP

1uF 1uF

V DDP VDDP
V SSP

22
YDA147
M A S TE R -S LA V E operation (differential-input, external clock operation)

V SSP
VDDP V DDP V DDP

1uF 1uF

220uF

M aster

PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
PVDDPL

OUTPL

OUTPL

OUTML

OUTML

PVDDML

PVDDML
V DDP
NC NC

NC NC

P VD D R E G G AIN 1
G ain
0.1u F Select
A VD D G A IN 0
1uF
1 uF
Lch Input+ IN LP N C D R C1
N on-C lip/D R C 1/D R C 2
1 uF
m ode select
Lch Input- IN LM N C D R C0

0.1uF
VR EF C KIN E xtern al C lock

R ch Input- IN R M CKOUT
1 uF
R ch Inpu t+ IN R P M U TEN M ute C ontrol
1 uF
AVS S P R O TN VCC
E rror F lag
P LIM IT S LE EPN Sleep C ontrol

NC NC

PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR
V SSA

1uF 1uF

V DDP V DDP
V SSP

V SSP
VDDP V DDP V DDP

1uF 1uF

220uF

Slave1
PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
PVDDPL

OUTPL

OUTPL

OUTML

OUTML

PVDDML

PVDDML

V DDP
NC NC

NC NC

P VD D R E G G AIN 1
G ain
0.1u F Select
A VD D G A IN 0
1uF
1 uF
Lch Input+ IN LP N C D R C1
N on-C lip/D R C 1/D R C 2
1 uF
m ode select
Lch Input- IN LM N C D R C0

0.1uF
VR EF C KIN

R ch Input- IN R M CKOUT
1 uF
R ch Inpu t+ IN R P M U TEN M ute C ontrol
1 uF
AVS S P R O TN VCC
E rror F lag
P LIM IT S LE EPN Sleep C ontrol

NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR

V SSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

V DDP V DDP
V SSP

V SSP
VDDP V DDP V DDP

1uF 1uF

220uF

Slave2
PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
PVDDPL

OUTPL

OUTPL

OUTML

OUTML

PVDDML

PVDDML

V DDP
NC NC

NC NC

P VD D R E G G AIN 1
G ain
0.1u F Select
A VD D G A IN 0
1uF
1 uF
Lch Input+ IN LP N C D R C1
N on-C lip/D R C 1/D R C 2
1 uF
m ode select
Lch Input- IN LM N C D R C0

0.1uF
VR EF C KIN

R ch Input- IN R M CKOUT (open)

1 uF
R ch Inpu t+ IN R P M U TEN M ute C ontrol
1 uF
AVS S P R O TN VCC
E rror F lag
P LIM IT S LE EPN Sleep C ontrol

NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR

V SSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

V DDP V DDP
V SSP

23
 YDA147

MASTER-SLAVE operation (differential-input, external clock operation, automatic return setting)

VSSP
VDDP VDDP VDDP

1uF 1uF

220uF

Master

PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
PVDDPL

OUTPL

OUTPL

OUTML

OUTML

PVDDML

PVDDML
VDDP
NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN External Clock

Rch Input- INRM CKOUT

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN

PLIMIT SLEEPN

NC NC

PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR
VSSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

VDDP VDDP
VSSP

VSSP
VDDP VDDP VDDP

1uF 1uF

220uF

Slave1
PVDDPL

OUTPL

PVSSL

PVSSL

OUTML
PVDDPL

OUTPL

OUTPL

OUTML

OUTML

PVDDML

PVDDML

VDDP
NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN

Rch Input- INRM CKOUT

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN

PLIMIT SLEEPN

NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR

VSSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

1uF 1uF

VDDP VDDP
VSSP

VSSP
VDDP VDDP VDDP

1uF 1uF

220uF

Slave2
PVDDPL

OUTPL

OUTPL

OUTPL

PVSSL

PVSSL

OUTML

OUTML

OUTML
PVDDPL

PVDDML

PVDDML

VDDP
NC NC

NC NC

PVDDREG GAIN1
Gain
0.1uF Select
AVDD GAIN0
1uF
1uF
Lch Input+ INLP NCDRC1
Non-Clip/DRC1/DRC2
1uF
mode select
Lch Input- INLM NCDRC0

0.1uF
VREF CKIN

Rch Input- INRM CKOUT (open) VDDP

1uF
Rch Input+ INRP MUTEN Mute Control
1uF
AVSS PROTN

PLIMIT SLEEPN

NC NC
PVDDMR

PVDDMR
PVDDPR

PVDDPR

OUTMR

OUTMR

OUTMR

VSSA
OUTPR
OUTPR

OUTPR

PVSSR

PVSSR

VSSP

1uF 1uF

VDDP VDDP
VSSP

24
YDA147
■Electrical Characteristics
●Absolute Maximum Ratings *1)
Parameter Symbol Min. Max. Unit
Power Supply terminal (PVDD) Voltage Range VDDP -0.3 20 V
Input Terminal Voltage Range VIN -0.3 4 V
PROTN Terminal Voltage Range VPROTN -0.3 4 V
Power Dissipation (Ta=25℃) PD25 6.5*2) W
Power Dissipation (Ta=70℃) PD70 4.21*2) W
Power Dissipation (Ta=85℃) PD85 3.4*2) W
Junction Temperature TJMAX 150 °C
Storage Temperature TSTG -40 150 °C
Note) *1: Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life,
and when using a device in excess even a moment, it may immediately cause damage to device or may
significantly deteriorate its reliability.
*2: A value based on the following implementation conditions:
LC Filter：L=22 [µH]/C=0.47[µH], Board Layer：4 layers(FR-4), Board Size：80 [mm] × 60 [mm],
Board Copper Foil Thickness：35 [µm], Wiring Density：379%, Device Heat Pad：soldering on the board
Through Hole for heat dissipation：25 (5×5) holes from a point just below the exposed stage to the inner layer (VSS)
and B layer.

●Recommended Operating Condition

Parameter Symbol Min. Typ. Max. Unit
Power Supply Voltage (PVDD) VDDP 8 - 16.5 V
Operating Ambient Temperature Ta -40 25 85 °C
Speaker Impedance (Stereo) RL 3.6 4 - Ω
Speaker Impedance (Monaural) *3 RL 3.6 4 - Ω
Note) *3: Connect terminals between OUTPL and OUTPR and between OUTML and OUTMR before use.

●DC Characteristics (VSS=0V, VDDP=8V to 16.5V, Ta=-40°C to 85°C, CKIN=1MHz, unless otherwise specified.)
Parameter Symbol Conditions Min. Typ. Max. Unit
PVDD Startup threshold voltage VHUVLH - - 6.5 - V
PVDD Shutdown threshold voltage VHUVLL - - 6.0 - V
DC Detection Voltage VDCDET PVDD=15V - 4 - V
DC Detection Time tDCDET - - 0.5 - s
Digital terminal*4) H level input voltage VIH - 2.52 - - V
Digital terminal*4) L level input voltage VIL - - - 0.9 V
*4)
Digital terminal Input Impedance RIN_D - 3.3 - - MΩ
SLEEPN terminal H level input voltage VIH_SLPN - 2.0 - - V
SLEEPN terminal L level input voltage VIL_SLPN - - - 0.8 V
SLEEPN terminal Input Impedance RIN_ SLPN - 3.3 - - MΩ
CKOUT Output Voltage VOL IOL=4mA - - 0.4 V
CKOUT Output Voltage VOH IOH=-4mA 2.4 - - V
PROTN Output Voltage VOL IOL=0.4mA - - 0.4 V
INLP, INLM, INRP, INRM terminals
RIN - - 18.8 - kΩ
Input impedance
AVDD Output Voltage VDDA 3.0 3.3 3.6 V
AVDD Output Current IDDA - - 1 mA
VREF Output Voltage VREF - VDDA /2 - V
PVDD Consumption Current IDDP VDDP=12V, no-load - 32 - mA
PVDD consumption current
ISLEEP VDDP=15V, Ta=25°C - 20 - µA
during power-down mode (SLEEPN=L)
PVDD consumption current
IMUTE VDDP=15V, Ta=25°C - 16 - mA
during Mute state (MUTEN=L)
PVDD consumption current
INOSIG VDDP=15V, Ta=25°C - 32 - mA
during no signal input
Note) *4: This value is applicable to MUTEN, CKIN, NCDRC0, NCDRC1, GAIN0, and GAIN1 (CMOS I/F) terminals.

25
 YDA147
●AC characteristics (VSS=0V, VDDP=8V to 16.5V, Ta=-40°C to 85°C, CKIN=1MHz, unless otherwise specified.)
Parameter Symbol Min. Typ. Max. Unit
CKIN Input Frequency fCKIN 0.9 1,0 1.1 MHz
CKIN Input Duty DTCKEXT 40 - 60 %
Self-excited Clock Frequency fCK - 1.0 - MHz
Sleep Recovery Time tWU - 1 1.5 s
Mute Recovery Time tMRCV - - 1 ms

●Analog Characteristics
(VSS=0V, VDDP=12V, Ta=25°C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN= CKIN= L*6), unless otherwise specified.)
Parameter Symbol Conditions Min. Typ. Max. Unit
RL=4Ω, VDDP=12V, THD+N=10% 15 W
Maximum momentary Output
Po RL=8Ω, VDDP=15V, THD+N=10% 15 W
(stereo)
RL=4Ω, VDDP=14V, THD+N=10%, 20 W
Maximum momentary Output RL=4Ω, VDDP=12V, THD+N=10% 20 W
Po
(monaural) RL=4Ω, VDDP=15V, THD+N=10% 30 W
GAIN[1:0]=L,L 22 dB
GAIN[1:0]=L,H 28 dB
Voltage Gain AV
GAIN[1:0]=H,L 34 dB
GAIN[1:0]=H,H 16 dB
Total Harmonic Distortion Rate
THD+N RL=4Ω,PO=0.1W 0.01 %
(stereo) (BW::20kHz)
Total Harmonic Distortion Rate
THD+N RL=4Ω,PO=0.2 W 0.02 %
(monaural) (BW::20kHz)
Signal /Noise Ratio (stereo)
SNR RL=4Ω,GAIN[1:0]=H,H 105 dB
(BW::20kHz A-Filter)
Signal /Noise Ratio monaural)
SNR RL=4Ω,GAIN[1:0]=H,H 105 dB
(BW::20kHz A-Filter)
Residual Noise (stereo)
Vn RL=4Ω,GAIN[1:0]=H,H 48 µVrms
(BW::20kHz A-Filter)
Residual Noise (monaural)
Vn RL=4Ω,GAIN[1:0]=H,H 48 µVrms
(BW::20kHz A-Filter)
Channel Separation Ratio CS 1kHz 80 dB
Power Supply Rejection Ratio (stereo)
PSRR Vripple=200mV, f=1kHz 60 dB
(PVDD applied)
Power Supply Rejection Ratio
PSRR Vripple=200mV, f=1kHz 60 dB
(monaural) (PVDD applied)
Common Mode Rejection Ratio
CMRR f=1kHz 41 dB
(stereo)
Common Mode Rejection Ratio
CMRR f=1kHz 41 dB
(monaural)
RL=4Ω 88 %
Maximum Efficiency (stereo) η
RL=8Ω 92 %
RL=4Ω, 20W output 93 %
Maximum Efficiency (monaural) η
RL=8Ω, 10W output 93 %
*5)
Output Offset Voltage (stereo) |Vo| 5 15 mV
Output Offset Voltage (monaural) *5) |Vo| 5 15 mV
f=20Hz -1 0 1 dB
Frequency characteristics fRES
f=20kHz -1 0 1 dB

26
YDA147
Note) *5: The offset voltage is denoted by considering a typical value and the maximum value as σ and 3σ, respectively.
*6: The same specification is applied to the external clock mode and internal clock (spread clock mode).
All the values of analog characteristics were obtained in our evaluation circumstance.
Depending upon pattern layout etc., characteristics may vary.
The measurement is performed with an 8Ω or 4Ω resistor connected in series with a 30µH coil as an output load.

27
 YDA147
● Example of typical characteristics
(VSS=0V, VDDP=12V, Ta=25°C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN=1MHz, unless otherwise specified)

28
YDA147

Power Dissipation vs Output Power Power Dissipation vs Output Power

(YDA147 stereo) (YDA147 stereo)
4 10
Power Dissipation [W]
Power Dissipation [W]

8
3
6
2 12V 8Ω 25℃ 12V 4Ω 25℃
15V 8Ω 25℃ 4 15V 4Ω 25℃
12V 8Ω 70℃ 12V 4Ω 70℃
1 15V 8Ω 70℃ 2 15V 4Ω 70℃

0 0
0 5 10 15 20 0 5 10 15 20
Output Power [W] Output Power [W]

Power Dissipation vs Output Power Power Dissipation vs Output Power

(YDA147 mono) (YDA147 mono)
4 6
12V 8Ω 25℃ 12V 4Ω 25℃
Power Dissipation [W]
Power Dissipation [W]

15V 8Ω 25℃ 5 15V 4Ω 25℃

3 12V 4Ω 70℃
12V 8Ω 70℃ 4
15V 4Ω 70℃
15V 8Ω 70℃
2 3
2
1
1
0 0
0 5 10 15 20 0 5 10 15 20 25
Output Power [W] Output Power [W]

29
 YDA147
■Package Outline

30
YDA147

31
 YDA147

Notice The specifications of this product are subject to improvement changes without prior notice.