Nju9101 e

NJU9101
Low Power Analog Front End
■FEATURES ■GENERAL DESCRIPTION
●Supply Voltage +2.4V to +3.6V NJU9101 is a Low Power Analog Front End IC for use
●Low Current Consumption 4µA (OPA, OPB), in micro-power sensing applications,
150µA (ADC) especially electrochemical sensors. It provides a
●Low Noise Amplifier 1.3µVpp typ. (0.1 to 10Hz) complete signal processing solution between sensor
●Low Offset Voltage Amplifier 300µV max. and micro-processor as smart-sensor module.
●RF immunity Amplifier NJU9101 has 2 channel low power operational
●Programmable Cell Bias Voltage amplifiers. These amplifiers provide potentiostat and
OPA: 0.3V to 1.7V (7 steps) trans-impedance-amplifiers to constitute gas sensor
OPB: 0.25V to 1.75V (50mV step) systems. The NJU9101 has calibration circuit by using
●Programmable Gain Pre-Amplifier 1V/V to 8V/V output data of built-in high precision ADC. It is suitable
●High resolution Programmable Gain ADC for temperature variation of sensor.
1V/V to 8V/V, 16-Bit (NFB), 32sps to 2k sps NJU9101 operates over voltage range of 2.4V to 3.6V.
●System Calibration for offset & gain drift Total average current consumption can be less than
●Control external EEPROM as a Master device 5µA.
●Ambient Operating Temperature -40°C to +85°C
●Interface I2C (3-Bit selectable slave address)
●Package EQFN-24-LE (4mm x 4mm)
■APPLICATION
●Gas Monitor ●Blood Glucose Meter
●Current Sensing Systems ●Low Power Systems
●Photodiode Sensing Systems ●Portable equipment
■EQUIVALENT CIRCUIT BLOCK DIAGRAM
Ver.3 -1-
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NJU9101
■PIN CONFIGURATION
EQFN-24-LE
PIN NO. SYMBOL DESCRIPTION Pin Type

1 SCL I2C serial clock input Digital Input
I2C serial data input / output
2 SDA Digital Input / Output
(which requires an pull-up resistor)
I2C serial clock output for external EEPROM
3 EXSCL Digital Output
(which requires an pull-up register)
I2C serial data input / output for external EEPROM
4 EXSDA Digital Input / Output
(which requires an pull-up resister)
5 AD0 Chip address selection input 0 Select from 7 chip addresses “000” Digital Input
6 AD1 Chip address selection input 1 to “110”. Do not select address Digital Input
“111”, which address is for
7 AD2 Chip address selection input 2 Digital Input
production test purpose
8 TEST TEST terminal (This terminal is used for production test. Connect to VDD) Analog Input
9 VDD Voltage Supply Power Supply
10 VREFA+ Positive voltage reference input for ADC Analog Input
11 VREFIN Voltage reference input for Bias Resistor Analog Input
12 BOUT Voltage output for Bch. OpAmp Analog Output
13 BIN- Negative voltage input for Bch. OpAmp Analog Input
14 BIN+ Positive voltage input for Bch. OpAmp Analog Input
15 SWS Switch Source input / output Switch Input / Output
16 SWD Switch Drain input / output Switch Input / Output
17 AIN+ Positive voltage input for Ach. OpAmp Analog Input
18 AIN- Negative voltage input for Ach. OpAmp Analog Input
19 AOUT Voltage output for Ach. OpAmp Analog Output
20 AUXIN- Auxiliary negative input Analog Input
21 AUXIN+ Auxiliary positive input Analog Input
Negative voltage reference input for ADC
22 VREFA- Analog Input
(connect to GND, is recommended)
23 GND GND GND
24 RDYB RDYB output / GPIO Digital Input / Output
PAD EXPPAD Exposed PAD on backside (connect to GND) GND
Ver.3 -2-
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NJU9101
■MARK INFORMATION
NJU9101 MLE (TE1)
Part Number Package Taping Form
■ORDERING INFORMATION
PACKAGE HALOGEN- TERMINAL WEIGHT
PART NUMBER RoHS MARKING MOQ(pcs)
OUTLINE FREE FINISH (mg)
NJU9101MLE EQFN-24-LE O O Sn-2Bi 9101 31 1,000
■ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATINGS UNIT
Power Supply Voltage VDDabso 5 V
Analog Input Voltage(1) VIA -0.3 to VDD+0.3 not exceeding 5 V
Digital Input Voltage VID -0.3 to 6 V
Switch Input Voltage(1) VIS -0.3 to VDD+0.3 not exceeding 5 V
On State Switch Current ISO -40 to +40(3) mA
Power Dissipation(Ta=25°C)(2) PD 830(4) 2-layer) mW
Storage Temperature Range Tstg -40 to +150 °C
(1): The input pins have clamp diodes to the power supply pins. Limit the input current to 10mA or less whenever input signals
exceed the power supply rail by 0.3V.
(2): Power dissipation is the power that can be consumed by the IC at Ta=25°C, and is the typical measured value based on
JEDEC condition. When using the IC over Ta=25°C subtract the value [mW/°C] = PD / Tstg max. - 25) per temperature.
(3: Continuous maximum switch current (DC current) value at Ta = 25°C. For Ta = 25°C or higher, refer to “3. Shorting FET
function (analog switch)” in the “Application Manual”.
(4): Mounted on glass epoxy board.
(101.5×114.5×1.6mm: based on EIA/JEDEC standard, 2Layers FR-4.)
■RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL RATINGS UNIT
Power Supply Voltage VDD +2.4 to +3.6 V
Operating Temperature Range Topr -40 to +85 °C
Ver.3 -3-
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NJU9101
■ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all limits ensured for Ta = 25°C, VDD = VREFIN = VREFA+ = 3V
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
OPA, OPB
Input Offset Voltage VIO VICM = VDD/2, Rs = 50Ω - - ±300 µV
Input Offset Voltage Drift ∆VIO / ∆T - ±1 - µV/°C
Input Bias Current IB - 10 - pA
Open Loop Gain AV - 100 - dB
Common Mode Rejection Ratio CMR VICM = GND to 2V 65 80 - dB
Common Mode Input Voltage Range VICM CMR ≥ 65dB GND - 2 V
VOH ISOURCE = 1mA 2.8 2.85 - V
Maximum Output Voltage
VOL ISINK = 1mA - 0.15 0.2 V
Gain Band Width GBW - 30 - kHz
Slew Rate SR - 0.01 - V/µs
f = 100Hz, RS = 50Ω - 50 - nV/√Hz
Equivalent Input Noise Voltage en
f = 0.1Hz to 10Hz - 1.3 - µVpp
Unless otherwise specified, all limits ensured for Ta = 25°C, VDD = VREFIN = VREFA+ = 3V, ADC reference Voltage = External
OPA, OPB with BIASRES (Potentiostat)
OPA referred to OPB Input Offset OPA BIAS = 1V
VIO1A-B - - ±0.6 mV
Voltage 1 OPB BIAS = 1V
OPA referred to OPB Input Offset ∆VIO1A-B OPA BIAS = 1V
- ±2 - µV/°C
Drift 1 / ∆T OPB BIAS = 1V
VIO2A-B 295 300 305 mV
Voltage 2 OPB BIAS = 0.7V
- ±5 - µV/°C
Drift 2 / ∆T OPB BIAS = 0.7V
VIO3A-B -605 -600 -595 mV
Voltage 3 OPB BIAS = 1.6V
- ±8 - µV/°C
Drift 3 / ∆T OPB BIAS = 1.6V
Analog Switch (ANASW)
Analog Switch = ON
On State Resistance RON 10 30 Ω
IDS = -10mA
Analog Switch = OFF
Off Leakage Current ILOFFD VSWS=2V/1V, - ±1 - nA
VSWD=1V/2V
Ver.3 -4-
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NJU9101
Unless otherwise specified, all limits ensured for Ta = 25°C, VDD = VREFIN = VREFA+ = 3V, Temperature Input Mode
Temperature Sensor
Temperature Accuracy (Error) 1 TACC1 Ta = 25°C - ±1 ±5 °C
Temperature Accuracy (Error) 2 TACC2 Ta = -40°C to +85°C - ±3 - °C
Temperature Resolution TRES - 0.25 - °C
Unless otherwise specified, all limits ensured for Ta = 25°C, VDD = 3V

Internal Reference
Internal Reference Voltage VIREF ±1% 2.028 2.048 2.068 V
∆VIREF
Internal Reference Drift Ta = -40°C to +85°C - 30 - ppm/°C
/ ∆T
Unless otherwise specified, all limits ensured for Ta = 25°C, VDD = VREFIN = VREFA+ = 3V, Auxiliary Differential Input Mode
PREAMP
PREAMP Gain =
PREAMP Gain Error GACCP - ±0.1 - %
1V/V to 8V/V
PREAMP Gain = 1V/V
PREAMP Common Mode Rejection CMRPRE AUXIN+ = AUXIN- = 70 90 - dB
GND+0.05 to VDD-1
PREAMP Common Mode PREAMP Gain = 1V/V GND
VICMP - VCC-1 V
Input Voltage CMRPRE ≥ 70dB +0.05
Ver.3 -5-
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NJU9101
Unless otherwise specified, all limits ensured for Ta = 25°C, VDD = VREFIN = VREFA+ = 3V, Auxiliary Input Mode
ADC Chopping = ON, ADC Reference Voltage = External, ADC Gain = 1V/V, ADC Decimation Ratio = “320”
ADC
Resolution N No missing code(5) 16 - - Bit
Noise Free Bit NFB - 16 - Bit
See p.22
Conversion Time DR - - - SPS
“ADC Conversion Time”
Output Noise VnADC VREFA+ = 3V - 13.9 - µVrms
Integral Non Linearity INL - ±1 - LSB
ADC Gain =
Gain Error - ±0.1 - %
1V/V to 8V/V
AUXIN+ = AUXIN- =
Offset Error - ±1 - LSB
VDD/2
VREF =
Differential Input Voltage Range VIDADC - ±VREF - V
|(VREFA+)-(VREFA-)|
AUXIN+ = AUXIN- =
ADC Common Mode Rejection CMRADC 80 90 - dB
GND to VDD
ADC Common Mode Input Voltage
VICADC CMRADC ≥ 80dB GND - VDD V
Range
(5) This Parameter has not production tested, please refer to Typical Characteristics.
Power Supply / OSC
Voltage Range VDD 2.4 - 3.6 V
Bias Resistance RBIAS - 1.5 - MΩ
Supply Current 1 IDD1 All Circuit Block Off - 0.5 1 µA
Supply Current 2 IDD2 OPA OPB - 4 5.5 µA
Internal Reference
Supply Current 3 IDD3 - 31 40 µA
Voltage (2.048V)
Supply Current 4 IDD4 PREAMP - 55 75 µA
Supply Current 5 IDD5 ADC - 150 200 µA
OSC Frequency fOSC ±10% 276 307 338 kHz
Ver.3 -6-
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NJU9101
■CHARACTERISTICS OF I/O STAGES FOR I2C BUS Compatible (SDA, SCL)

I2C BUS Load Conditions
STANDARD MODE: Pull up resistance 4kΩ (Connected to VDD), Load capacitance 200pF (Connected to GND)
FAST MODE: Pull up resistance 4kΩ (Connected to VDD), Load capacitance 50pF (Connected to GND)
SYM Standard Mode Fast Mode
PARAMETER UNIT
BOL MIN. TYP. MAX. MIN. TYP. MAX.
Low Level Input Voltage VIL 0.0 - 0.3VDD 0.0 - 1.5 V
High Level Input Voltage VIH 0.7VDD - 5.5 2.7 - 5.5 V
Low Level Output Voltage
VOL 0 - 0.4 0 - 0.4 V
(3mA at SDA pin)
Input current each I/O pin with an input voltage
Ii -10 - 10 -10 - 10 µA
between 0.1VDD and 0.9VDD max.
■CHARACTERISTICS OF BUS LINES (SDA, SCL) FOR I2C BUS Compatible Devices
STANDARD MODE: Pull up resistance 4kΩ (Connected to VDD), Load capacitance 200pF (Connected to GND)
FAST MODE: Pull up resistance 4kΩ (Connected to VDD), Load capacitance 50pF (Connected to GND)
SYM Standard Mode Fast Mode
PARAMETER UNIT
BOL MIN. TYP. MAX. MIN. TYP. MAX.
SCL clock frequency fSCL 10 - 100 10 - 400 kHz
Hold time (repeated) START condition tHD:STA 4.0 - - 0.6 - - µs
Low period of the SCL clock tLOW 4.7 - - 1.3 - - µs
High period of the SCL clock tHIGH 4.0 - - 0.6 - - µs
Set-up time for a repeated START condition tSU:STA 4.7 - - 0.6 - - µs
Data hold time tHD:DAT 0 - - 0 - - µs
Data set-up time tSU:DAT 250 - - 100 - - ns
Rise time of both SDA and SCL signals tr - - 1000 - - 300 ns
Fall time of both SDA and SCL signals tf - - 300 - - 300 ns
Set-up time for STOP condition tSU:STO 4.0 - - 0.6 - - µs
Bus free time between a STOP
tBUF 4.7 - - 1.3 - - µs
and START condition
Capacitive load for each bus line Cb - - 400 - - 400 pF
Noise margin at the Low Level VnL 0.5 - - 0.5 - - V
Noise margin at the High Level VnH 1 - - 1 - - V
Cb: Total capacitance of one bus line in pF.
■TIMING ON THE I C BUS (SDA, SCL) 2
SDA
tf tr tf tHD:STA tf
tBUF
tSU:DAT
SCL
tHD:STA tSU:STA tSU:STO

tLOW tHD:DAT tHIGH
S Sr P S
Ver.3 -7-
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NJU9101
■CHARACTERISTICS OF I/O STAGES FOR EEPROM I2C BUS (EXSDA, EXSCL)

Pull up resistance 4kΩ (Connected to VDD), Load capacitance 50pF (Connected to GND)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Low Level Input Voltage VIL 0.0 - 0.3VDD V
High Level Input Voltage VIH 0.7VDD - - V
Low Level Output Voltage
VOL 0 - 0.4 V
(3mA at SDA pin)
Input current each I/O pin with an input voltage
Ii -10 - 10 µA
between 0.1VDD and 0.9VDD max.
■CHARACTERISTICS OF BUS LINES (EXSDA, EXSCL)

Pull up resistance 4kΩ (Connected to VDD), Load capacitance 50pF (Connected to GND)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
EXSCL clock frequency fSCL 92 102.3 112.7 kHz
Hold time (repeat) START condition tHD:STA 7.2 6.5 5.9 µs
Low period of the EXSCL clock tLOW 7.2 6.5 5.9 µs
High period of the EXSCL clock tHIGH 3.6 3.3 3.0 µs
Set-up time for a repeated START condition tSU:STA 7.2 6.5 5.9 µs
Data hold time (EXSDA input) tHD:DAT 0 - - µs
Data hold time (EXSDA output) tHD:DAT 7.2 6.5 5.9 µs
Data Set-up time (EXSDA input) tSU:DAT 0 - - µs
Data Set-up time (EXSDA output) tSU:DAT 7.2 6.5 5.9 µs
Rise time of both EXSDA and EXSCL signals tr - - 300 ns
Fall time of EXSDA and EXSCL signals tf - - 300 ns
Set-up time for STOP condition tSU:STO 7.2 6.5 5.9 µs
Bus free time between a STOP and START
tBUF 7.2 6.5 5.9 µs
condition
Capacitive load for each bus line Cb - - 400 pF
Noise margin at the Low level VnL 0.5 - - V
Noise margin at the High level VnH 1 - - V
Cb: total capacitance of one bus line in pF.
■TIMING ON THE EEPROM I2C BUS (EXSDA, EXSCL)
EXSDA
tf tr tf tHD:STA tf
tBUF
tSU:DAT
EXSCL
tHD:STA tSU:STA tSU:STO

tLOW tHD:DAT tHIGH
S Sr P S
Ver.3 -8-
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NJU9101
■REGISTER DESCRIPTION
NJU9101 has register (list shown below) which can access it through I2C bus.
It can control the external EEPROM address corresponding to each register address from NJU9101.
REGISTER EEPROM REGISTER BIT
ADDRESS ADDRESS NAME D7 D6 D5 D4 D3 D2 D1 D0
0x00 - CTRL - RST SENSCK [1:0] MEAS MEAS_SEL [1:0] MEAS_SC
0x01 - STATUS - - BOOT CLKRUN RDYB OV CERR OFOV
0x02 - AMPDATA0 AMPDATA [15:8]
0x03 - AMPDATA1 AMPDATA [7:0]
0x04 - AUXDATA0 AUXDATA [15:8]
0x05 - AUXDATA1 AUXDATA [7:0]
0x06 - TMPDATA0 TMPDATA [9:2]
0x07 - TMPDATA1 TMPDATA [1:0] - - - - - -
0x08 - ID ID [7:0]
0x09 - ROMADR0 - - - - - ROMADR [10:8]
0x0A - ROMADR1 ROMADR [7:0]
0x0B - ROMDATA ROMDATA [7:0]
0x0C - ROMCTRL - - ROMERR ROMBUSY ROMSTOP ROMACT ROMMODE [1:0]
0x0D - TEST TEST [7:0]
0x0E 0x000 ANAGAIN - - - - PRE_GAIN [1:0] ADC_GAIN [1:0]
0x0F 0x001 BLKCONN0 - - BIASSWA BIASSWB PRE_BIAS [3:0]
0x10 0x002 BLKCONN1 OPA_BIAS [2:0] OPB_BIAS [4:0]
0x11 0x003 BLKCONN2 PREMODE INPSWA INPSWB ANASW BIASSWN PAMPSEL BIASSEL VREFSEL
0x12 0x004 BLKCTRL BLKCTRL [7:0]
0x13 0x005 ADCCONV - ADCCHOP CLKDIV [1:0] REJ [1:0] OSR [1:0]
0x14 0x006 SYSPRESET RDYBOE RDYBDAT RDYBMODE [1:0] - - - AMPAUX
0x15 0x007 SCAL1A0 - - - - - - - SCAL1A [8]
0x16 0x008 SCAL1A1 SCAL1A [7:0]
0x17 0x009 SCAL2A0 - - - - - - - SCAL2A [8]
0x18 0x00A SCAL2A1 SCAL2A [7:0]
0x19 0x00B SCAL3A0 - - - - - - - SCAL3A [8]
0x1A 0x00C SCAL3A1 SCAL3A [7:0]
0x1B 0x00D SCAL4A0 - - - - - - - SCAL4A [8]
0x1C 0x00E SCAL4A1 SCAL4A [7:0]
0x1D 0x00F SCAL1B0 SCAL1B [15:8]
0x1E 0x010 SCAL1B1 SCAL1B [7:0]
0x1F 0x011 SCAL2B0 SCAL2B [15:8]
0x20 0x012 SCAL2B1 SCAL2B [7:0]
0x21 0x013 SCAL3B0 SCAL3B [15:8]
0x22 0x014 SCAL3B1 SCAL3B [7:0]
0x23 0x015 SCAL4B0 SCAL4B [15:8]
0x24 0x016 SCAL4B1 SCAL4B [7:0]
0x25 0x017 OCAL1A0 - - - - - - OCAL1A [9:8]
0x26 0x018 OCAL1A1 OCAL1A [7:0]
Ver.3 -9-
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NJU9101
0x27 0x019 OCAL2A0 - - - - - - OCAL2A [9:8]
0x28 0x01A OCAL2A1 OCAL2A [7:0]
0x29 0x01B OCAL3A0 - - - - - - OCAL3A [9:8]
0x2A 0x01C OCAL3A1 OCAL3A [7:0]
0x2B 0x01D OCAL4A0 - - - - - - OCAL4A [9:8]
0x2C 0x01E OCAL4A1 OCAL4A [7:0]
0x2D 0x01F OCAL1B0 - OCAL1B [14:8]
0x2E 0x020 OCAL1B1 OCAL1B [7:0]
0x2F 0x021 OCAL2B0 - OCAL2B [14:8]
0x30 0x022 OCAL2B1 OCAL2B [7:0]
0x31 0x023 OCAL3B0 - OCAL3B [14:8]
0x32 0x024 OCAL3B1 OCAL3B [7:0]
0x33 0x025 OCAL4B0 - OCAL4B [14:8]
0x34 0x026 OCAL4B1 OCAL4B [7:0]
0x35 0x027 SCAL1 SCAL1 [7:0]
0x36 0x028 SCAL2 SCAL2 [7:0]
0x37 0x029 SCAL3 SCAL3 [7:0]
0x38 0x02A OCAL1 OCAL1 [7:0]
0x39 0x02B OCAL2 OCAL2 [7:0]
0x3A 0x02C OCAL3 OCAL3 [7:0]
0x3B 0x02D AUXSCAL0 AUX_SCAL [15:8]
0x3C 0x02E AUXSCAL1 AUX_SCAL [7:0]
0x3D 0x02F AUXOCAL0 AUX_OCAL [15:8]
0x3E 0x030 AUXOCAL1 AUX_OCAL [7:0]
0x3F - CHKSUM CHKSUM [7:0]
Ver.3 - 10 -
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NJU9101
■EVERY REGISTER DESCRIPTION
CTRL Register Register Address: 0x00, EEPROM Address: -

CTRL
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - RST SENSCK [1:0] MEAS MEAS_SEL [1:0] MEAS_SC
R /W - WS RW RW RW RW
RESET - - 0x0 0 0x0 0
BIT BIT NAME FUNCTION

Write Software Reset.
When read this bit, always return “0”.
[6] RST
0: No effect
1: Reset
Change offset voltage of OPB to check sensor diagnostic.
00: OFF (No change)

[5:4] SENSCK
01: Plus Offset (Change Offset Voltage ≈ +5.0mV)
10: Minus Offset (Change Offset Voltage ≈ -5.0mV)
11: Reserve
Measurement Switch
When write “1”, ADC conversion starts.
When read this bit, returns “1” in case of under conversion, “0” in case of idle condition.
When select “Single Conversion” mode, this bit is set to “0” automatically after conversion
completion. When select “Continuous Conversion” mode and write “0”, ADC conversion
[3] MEAS
stop and return to an idol state.
0: Measurement OFF
(Operating condition of this chip follows “BLKCTRL” condition)
1: Measurement ON
Measurement Mode Selection.
00: Temperature sensor input mode

[2:1] MEAS_SEL
01: Amplifier input mode
10: Auxiliary input mode
11: Reserve
Measurement Mode for ADC
[0] MEAS_SC
0: Single Conversion
1: Continuous Conversion
Ver.3 - 11 -
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NJU9101
STATUS Register Register Address: 0x01, EEPROM Address: -

STATUS
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - - BOOT CLKRUN RDYB OV CERR OFOV
R /W - - R R R R R R
RESET - - 1 - 1 0 0 0

Booting flag for IC.
NJU9101 reads initial register value from external EEPROM as booting.
This bit returns “1” until the reading of the initial register value is completed from start.
[5] BOOT
0: Completion of booting
1: Under booting
System Clock Condition.
[4] CLKRUN
0: System Clock is sleeping
1: System Clock is operating
Data Ready Flag. When conversion data is updated, this bit is cleared to “0”.
When either “AMPDATA0”, “AUXDATA0”, or “TMPDATA0” is read, this bit is set to “1”.
[3] RDYB
0: New ADC data is ready
1: New ADC data is not ready
Overflow flag in sensitivity calibration of ADC output data.
When over flow is occurred in sensitivity calibration of ADC conversion data, this bit is set to
“1”. When this bit is “1”, ADC output data (“AMPDATA” or “AUXDATA”) is set to 0x7FFF
(positive over flow) or 0x8000 (negative over flow). When either “AMPDATA0”,
[2] OV
“AUXDATA0”, or “TMPDATA0” is read, this bit is cleared to “0”.
0: ADC conversion data is valid

1: ADC conversion data is over flow (set 0x7FFF or 0x8000)
Overflow flag in calibration coefficient data.
When over flow is occurred in setting of calibration coefficient data, this bit is set to “1”. In
case of “1”, ADC output data is invalid value.
[1] CERR When either “AMPDATA0”, “AUXDATA0” or “TMPDATA0” is read, this bit is cleared to “0”.
0: No overflow in calibration coefficient calculation

1: Overflow in calibration coefficient calculation (Output data is invalid)
Overflow flag in offset calibration of ADC output data.
When over flow is occurred in offset calibration of ADC conversion data, this bit is set to “1”.
In case of “1”, ADC output data is invalid value.
[0] OFOV When either “AMPDATA0”, “AUXDATA0” or “TMPDATA0” is read, this bit is cleared to “0”.
0: No overflow in offset calibration data

1: Overflow in offset calibration data (Output data is invalid)
Ver.3 - 12 -
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NJU9101
AMPDATA0 / AMPDATA1 Register Register Address: 0x02 / 0x03, EEPROM Address: -

AMPDATA0 AMPDATA1
Register Address: 0x02 Register Address: 0x03
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME AMPDATA [15:0]
R /W R
RESET -

AMPDATA0 [7:0]
ADC output data register for amplifier input mode.
+ AMPDATA[15:0]
Signed 16-Bit data.
AMPDATA1 [7:0]
AUXDATA0 / AUXDATA1 Register Register Address: 0x04 / 0x05, EEPROM Address: -

AUXDATA0 AUXDATA1
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME AUXDATA [15:0]
R /W R
RESET -

AUXDATA0 [7:0]
ADC output data register for Auxiliary input mode.
+ AUXDATA[15:0]
Signed 16-Bit data.
AUXDATA1 [7:0]
TMPDATA0 / TMPDATA1 Register Register Address: 0x06 / 0x07, EEPROM Address: -

TMPDATA0 TMPDATA1
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME TMPDATA [9:0] - - - - - -
R /W R/W - - - - - -
RESET - - - - - - -

ADC output data register for Temperature sensor input mode.
TMPDATA0 [7:0] Signed 8.2 fixed point format. (-45°C to +127.75°C)
+ TMPDATA[9:0] Temperature calibration calculation is executed by value of TMPDATA.
TMPDATA1 [7:6] When calibration is executed by using external temperature sensor, write data
which getting from external temperature sensor to this register.
Ver.3 - 13 -
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NJU9101
ID Register Register Address: 0x08, EEPROM Address: -

ID
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME ID [7:0]
R /W R
RESET 0x55

[7:0] ID [7:0] Fixed value “0x55” is stored as a chip identification code in this register.
ROMADR0 / ROMADR1 Register Register Address: 0x09 / 0x0A, EEPROM Address: -

ROMADR0 ROMADR1
Register Address: 0x09 Register Address: 0x0A
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - - - - - ROMADR [10:0]
R /W - - - - - RW
RESET - - - - - 0x0

ROMADR0 [2:0]
+ ROMADR[10:0] This is EEPROM address selection register that read/write from/to EEPROM.
ROMADR1 [7:0]
*Be sure to set ROMADR0[4:3] = “00” to control EEPROM.
ROMDATA Register Register Address: 0x0B, EEPROM Address: -

ROMDATA
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME ROMDATA [7:0]
R /W RW
RESET 0x00

In read mode, return a reading data from EEPROM.
[7:0] ROMDATA [7:0]
In write mode, set a writing data to EEPROM.
Ver.3 - 14 -
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NJU9101
ROMCTRL Register Register Address: 0x0C, EEPROM Address: -

ROMCTRL
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - - ROMERR ROMBUSY ROMSTOP ROMACT ROMMODE [1:0]
R /W - - RC R WS WS W
RESET - - - - 0x0 0x0 0x0

When I2C bus communication error occurs during accessing to external EEPROM, this bit
is set to “1”. It is communication error in the following cases,
1) When NJU9101 outputs address, data, acknowledge data, it receives the EXSDA data
different from the EXSDA data which outputs.
2) NJU9101 receives NACK response in the timing which it is expected to receive ACK
[5] ROMERR
response.
And, It is cleared to “0” when this bit is written in “1”.
0: I2C communication is not error

1: I2C communication is error
This bit shows accessing status to external EEOPROM.
[4] ROMBUSY
0: Completion of the access
1: Under accessing
When write “1” to “ROMSTOP” bit, stop accessing to external EEPROM. “ROMBUSY” bit
is cleared to “0” immediately. When it stops accessing during writing to external EEPROM,
[3] ROMSTOP ROM data is not guaranteed. In the read mode, this bit always returns “0”.
1: stop accessing to external EEPROM

When write “1” to ROMACT bit, start accessing to external EEPROM with following
“ROMMODE[1:0]” data. In write “0” case, it is not started accessing.
And, to start accessing to external EEPROM, it is necessary that it is not accessing timing
[2] ROMACT to external EEPROM (“ROMBUSY” bit = “0”), and system clock is during operation
(“CLKRUN” bit = “1”). In the read mode, this bit always returns “0”.
1: start accessing to external EEPROM

Write operation for external EEPROM. In the read mode, this bit returns “0”.
00: Read one byte data from external EEPROM (address ROMADR[10:0]),
and, store this one byte data to ROMDATA[7:0] bit register in NJU9101.
[1:0] ROMMODE
01: Write ROMDATA[7:0] bit data to register in external EEPROM which is assigned by
ROMADR[10:0] address.
10: Load external EEPROM data to Host-register (ex. MPU)
11: Store Host-register setting (ex. MPU) into external EEPROM data.
Ver.3 - 15 -
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NJU9101
TEST Register Register Address: 0x0D, EEPROM Address:

TEST
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME TEST [7:0]
R /W RW
RESET 0x00
*This register is for production test purpose. Do not write data to this register.
ANAGAIN Register Register Address: 0x0E, EEPROM Address: 0x000

ANAGAIN
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - - - - PRE_GAIN [1:0] ADC_GAIN [1:0]
R /W - - - - RW RW
RESET - - - - 0x0 0x0

Pre-amplifier gain selection
00: 1 V/V
[3:2] PRE_GAIN
01: 2 V/V
10: 4 V/V
11: 8 V/V
Programmable-gain-amplifier in ADC selection
00: 1 V/V
[1:0] ADC_GAIN
01: 2 V/V
10: 4 V/V
11: 8 V/V
Ver.3 - 16 -
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NJU9101
BLKCONN0 Register Register Address: 0x0F, EEPROM Address: 0x001

BLKCONN0
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - - BIASSWA BIASSWB PRE_BIAS [3:0]
R /W - - RW RW RW
RESET - - 0x0 0x0 0x0

This is Switch for connecting “BIASRES” and “OPA positive input”
[5] BIASSWA
0: Open “BIASRES” and “OPA positive input”
1: Connect “BIASRES” and “OPA positive input”
This is Switch for connecting “BIASRES” and “OPB positive input”
[4] BIASSWB
0: Open “BIASRES” and “OPB positive input”
1: Connect “BIASRES” and “OPB positive input”
Negative input bias level for PREAMP (From 0.3V to 1.7V are 100mV steps)
This bias level is set by “BIASRES” Circuit Block.
VREFIN = 3V or at INTVREF(2.048V) as follows

0000: GND
0001: 0.3V
[3:0] PRE_BIAS 0010: 0.4V
0011: 0.5V
:
:
1101: 1.5V
1110: 1.6V
1111: 1.7V
Ver.3 - 17 -
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NJU9101
BLKCONN1 Register Register Address: 0x10, EEPROM Address: 0x002

BLKCONN1
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME OPA_BIAS [2:0] OPB_BIAS [4:0]
R /W RW RW
RESET 0x0 0x0

Bias Level for OPA, This bias level is set by “BIASRES” Block.

000: GND
001: 0.3V
[7:5] OPA_BIAS 010: 0.5V
011: 0.7V
100: 1.0V
101: 1.3V
110: 1.5V
111: 1.7V
Bias Level for OPB (From 0.25V to 1.75V are 50mV steps).

00000: GND
00001: 0.25V
[4:0] OPB_BIAS 00010: 0.3V
00011: 0.35V
:
11101: 1.65V
11110: 1.7V
11111: 1.75V
Ver.3 - 18 -
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NJU9101
BLKCONN2 Register Register Address: 0x11, EEPROM Address: 0x003

BLKCONN2
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT
PREMODE INPSWA INPSWB ANASW BIASSWN PAMPSEL BIASSEL VREFSEL
NAME
R /W RW RW RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Select PREAMP mode
[7] PREMODE
0: Non-Inverted Amplifier mode
1: Instrumentation Amplifier mode
OPA positive input connection
[6] INPSWA
0: GND Positive input is connected to GND.
1: AIN+ Positive input is connected to AIN+ Pin.
OPB positive input connection
[5] INPSWB
0: GND Positive input is connected to GND.
1: BIN+ Positive input is connected to BIN+ Pin.
Build in Analog Switch Status
[4] ANASW 0: Switch OFF

1: Switch ON On Resistance is 10Ω typ.
Absolute Maximum Input Current is ±50mA.
Select switch for PREAMP / ADC Negative Input at AMP / AUX input mode.
[3] BIASSWN
0: OPB Output / AUXIN-
1: BIASRES This is selectable bias level set by “PRE_BIAS”.
Enable / Disable PREAMP for signal path.
[2] PAMPSEL
0: Disable (Bypass PREAMP)
1: Enable
Reference Voltage selection for Bias Register
[1] BIASSEL
0: Internal Reference (2.048V)
1: External Reference
Reference Voltage selection for ADC
[0] VREFSEL
0: Internal Reference (2.048V)
1: External Reference
Ver.3 - 19 -
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NJU9101
BLKCTRL Register Register Address: 0x12, EEPROM Address: 0x004

BLKCTRL
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME BLKCTRL [7:0]
R /W RW
RESET 0x00

Circuit Block Powered down selection.
When ADC is in the idle state, circuit block which this bit is set to “0” is automatically
powered down.
The circuit block which this bit is set to “1” is kept powered on state even in case of ADC
idle state. When all bits are “0”, NJU9101 goes “power down mode” except for Digital
block.
[7] BIASRES block

[7:0] BLKCTRL
[6] OPB block
[5] OPA block
[4] OSC block
[3] PREAMP block
[2] INTVREF(2.048V block
[1] ADC block
[0] Temperature Sensor block
Refer to “● Power-Down Control” for details.
Ver.3 - 20 -
http://www.njr.com/
NJU9101
ADCCONV Register Register Address: 0x13, EEPROM Address: 0x005

ADCCONV
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - ADCCHOP CLKDIV [1:0] REJ [1:0] OSR [1:0]
R /W - RW RW RW RW
RESET - 0x0 0x0 0x0 0x0

ADC CHOP Switch. It is effective in reducing offset Voltage of PREAMP and ADC.
Reduce offset voltage by chopping input signal.
When this bit is “1”, conversion time becomes long.
[6] ADCCHOP (ex. 16.2ms(ADCCHOP=”0”) -> 31.1ms(ADCCHOP=”1”))
0: CHOP OFF
1: CHOP ON
Select operation clock frequency for sigma-delta modulator. fOSC=307.2kHz typ.
00: fmod=(1/2) x fOSC

[5:4] CLKDIV
Select rejection mode for Sinc3 filter
00: 50/60Hz Rejection

[3:2] REJ
01: 50Hz Rejection
10: 60Hz Rejection
11: Reserved
Select Decimation ratio for Sinc3 filter.
[1:0] OSR
Total Decimation Ratio is decided by OSR / REJ bits combination.
Ver.3 - 21 -
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NJU9101
ADC Decimation Ratio

REJ [1:0]
OSR [1:0] 00 01 10 11
00 768 768 640 -
01 384 384 320 -
10 192 192 160 -
11 96 96 80 -
ADC Conversion Time [ms]

OSR REJ [1:0]
[1:0] 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
00 16.2 16.2 13.7 - 31.3 31.3 26.3 - 5 5 4.2 - 15.3 15.3 12.8 -
01 8.7 8.7 7.5 - 16.3 16.3 13.8 - 2.5 2.5 2.1 - 7.8 7.8 6.5 -
10 5.0 5.0 4.3 - 8.8 8.8 7.6 - 1.3 1.3 1.0 - 4.0 4.0 3.4 -
11 3.1 3.1 2.8 - 5.1 5.1 4.5 - 0.6 0.6 0.5 - 2.1 2.1 1.8 -
Single Conversion Continuous Conversion
State
CHOP: OFF CHOP: ON CHOP: OFF CHOP: ON
Conversion Time vs Resolution (ADC)

ADC CHOP: ON CHOP: OFF
Conversion ADC Gain ADC Gain
Time 1V/V 2V/V 4 V/V 8 V/V 1 V/V 2 V/V 4 V/V 8 V/V
26.3ms 16 / (16) 16 / (16) 16 / (16) 16 / (16) 16 / (16) 16 / (16) 15.6 / (16) 15.3 / (16)
13.8ms 16 / (16) 16 / (16) 15.2 / (16) 16 / (16) 16 / (16) 16 / (16) 15 / (16) 14.8 / (16)
7.6ms 15 / (16) 14.7 / (16) 14.5 / (16) 14 / (16) 15 / (16) 14.7 / (16) 14.1 / (16) 13.5 / (16)
4.5ms 14 / (16) 14 / (16) 13.5 / (16) 12 / (14.7) 14 / (16) 14 / (16) 13.6 / (16) 12 / (14.7)
Noise Free Bit / (Effective Number of Bits), Unit: bit
Ver.3 - 22 -
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NJU9101
SYSPRESET Register Register Address: 0x14, EEPROM Address: 0x006

SYSPRESET
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME RDYBOE RDYBDAT RDYBMODE [1:0] - - - AMPAUX
R /W RW RW RW - - - RW
RESET 0x0 - 0x1 - - - 0x0

RDYB terminal direction of GPIO mode
[7] RDYBOE
0: RDYB terminal is input mode
1: RDYB terminal is Output mode
Return RDYB terminal level in input mode.
[6] RDYBDAT
Store RDYB terminal level in Output mode.
Select function of RDYB terminal
00: RDYB terminal outputs “RDYB” bit in STATUS register.

01: RDYB terminal outputs “RDYB” bit in STATUS register.
[5:4] RDYBMODE
with open-drain circuit style.
10: RDYB terminal is used as GPIO.
Output condition is set by “RDYBDAT” and “RDYBOE”.
11: Reserved
Select Calibration channel coefficient assignment.
0: AMPDATA uses SCAL/OCAL calibration coefficient.

[0] AMPAUX
AUXDATA uses AUX_SCAL / AUX_OCAL calibration coefficient.
1: AMPDATA uses AUX_SCAL / AUX_OCAL calibration coefficient.
AUXDATA uses SCAL/OCAL calibration coefficient.
Ver.3 - 23 -
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NJU9101
SCALxA0 / SCALxA1 Register Register Address: 0x15 to 0x1C, EEPROM Address: 0x007 to 0x00E
SCALxA0 (x=1 to 4) SCALxA1 (x=1 to 4)
Register Address: 0x15, 0x17, 0x19, 0x1B Register Address: 0x16, 0x18, 0x1A, 0x1C
EEPROM Address: 0x007, 0x009, 0x00B, 0x00D EEPROM Address: 0x008, 0x00A, 0x00C, 0x00E
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - - - - - - - SCALxA [8:0]
R /W - - - - - - - RW
RESET - - - - - - - -

SCALxA0 [0]
SCALxA [8:0] 1st order Gain Calibration parameter for AMPDATA.
+
(x=1 to 4) This parameter is signed 9-Bit data.
SCALxA1 [7:0]
SCALxB0 / SCALxB1 Register Register Address: 0x1D to 0x24, EEPROM Address: 0x00F to 0x016
SCALxB0 (x=1 to 4) SCALxB1 (x=1 to 4)
Register Address: 0x1D, 0x1F, 0x21, 0x23 Register Address: 0x1E, 0x20, 0x22, 0x24
EEPROM Address: 0x00F, 0x011, 0x013, 0x15 EEPROM Address: 0x010, 0x012, 0x014, 0x016
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME SCALxB [15:0]
R /W RW
RESET -

SCALxB0 [7:0]
SCALxB [15:0] Zero-order Gain Calibration parameter for AMPDATA.
+
(x=1 to 4) This parameter is unsigned 16-Bit data.
SCALxB1 [7:0]
Ver.3 - 24 -
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NJU9101
OCALxA0 / OCALxA1 Register Register Address: 0x25 to 0x2C, EEPROM Address: 0x017 to 0x01E
OCALxA0 (x=1 to 4) OCALxA1 (x=1 to 4)
Register Address: 0x25 to 0x28 Register Address: 0x29 to 0x2C
EEPROM Address: 0x017 to 0x01A EEPROM Address: 0x01B to 0x01E
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - - - - - - OCALxA [9:0]
R /W - - - - - - RW
RESET - - - - - - -

OCALxA0 [1:0]
OCALxA [9:0] 1st order Offset Calibration parameter for AMPDATA.
+
OCALxA1 [7:0]
OCALxB0 / OCALxB1 Register Register Address: 0x2D to 0x34, EEPROM Address: 0x01F to 0x026
OCALxB0 (x=1 to 4) OCALxB1 (x=1 to 4)
Register Address: 0x2D, 0x2F, 0x31, 0x33 Register Address: 0x2E, 0x30, 0x32, 0x34
EEPROM Address: 0x01F, 0x021, 0x023, 0x025 EEPROM Address: 0x020, 0x022, 0x024, 0x026
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME - OCALxB [14:0]
R /W - RW
RESET - -

OCALxB0 [6:0]
OCALxB [14:0] Zero-order Offset Calibration parameter for AMPDATA.
+
OCALxB1 [7:0]
SCALx Register Register Address: 0x35 to 0x37, EEPROM Address: 0x027 to 0x029
SCALx (x=1 to 3)
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME SCALx [7:0]
R /W RW
RESET -

Threshold Temperature for AMPDATA Sensitivity Calibration.
SCALx
[7:0] Signed 8.0 fixed point format. (-45°C to +127°C)
(x=1 to 3)
-45°C ≤ SCAL1 < SCAL2 < SCAL3 ≤ +127°C
Ver.3 - 25 -
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NJU9101
OCALx Register Register Address: 0x38 to 0x3A, EEPROM Address: 0x02A to 0x02C
OCALx (x=1 to 3)
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME OCALx [7:0]
R /W RW
RESET -

Threshold Temperature for AMPDATA Offset Calibration.
OCALx
[7:0] Signed 8.0 fixed point format. (-45°C to +127°C)
(x=1 to 3)
-45°C ≤ OCAL1 < OCAL2 < OCAL3 ≤ +127°C
AUX_SCAL0 / AUX_SCAL1 Register Register Address: 0x3B / 0x3C, EEPROM Address: 0x02D / 0x02E
AUX_SCAL0 AUX_SCAL1
Register Address: 0x3B Register Address: 0x3C
EEPROM Address: 0x02D EEPROM Address: 0x02E
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME AUXSCAL [15:0]
R /W RW
RESET -

AUX_SCAL0 [7:0]
AUXSCAL Sensitivity Calibration for AUXDATA.
+
[15:0] (Auxiliary calibration does not have temperature coefficient).
AUX_SCAL1 [7:0]
AUX_OCAL0 / AUX_OCAL1 Register Register Address: 0x3D / 0x3E, EEPROM Address: 0x02F / 0x030
AUX_OCAL0 AUX_OCAL1
Register Address: 0x3D Register Address: 0x3E
EEPROM Address: 0x02F EEPROM Address: 0x030
BIT [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME AUXOCAL [15:0]
R /W RW
RESET -

AUX_OCAL0 [7:0]
AUXOCAL Offset Calibration for AUXDATA.
+
[15:0] (Auxiliary calibration does not have temperature coefficient.)
AUX_OCAL1 [7:0]
Ver.3 - 26 -
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NJU9101
CHKSUM Register Register Address: 0x3F, EEPROM Address: -

CHKSUM
BIT [7] [6] [5] [4] [3] [2] [1] [0]
BIT NAME CHKSUM [7:0]
R /W R
RESET -

Check Sum value of register set value is showed which is read from external EEPROM.
Check Sum value is updated in following cases, when start up, when finish reading saved
data from in external EEPROM, and when finish to road setting data to host-register from
[7:0] CHKSUM
external EEPROM. Check Sum result value is finally showed as 1’s complement. This
result is summed unsigned data of each address byte (0x000 to 0x030) in external
EEPROM.
Ver.3 - 27 -
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NJU9101
■TYPICAL CHARACTERISTICS
Ver.3 - 28 -
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NJU9101
Ver.3 - 29 -
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NJU9101
Ver.3 - 30 -
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NJU9101
Ver.3 - 31 -
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NJU9101
Ver.3 - 32 -
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NJU9101
Ver.3 - 33 -
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■ Application Manual
NJU9101
■APPLICATION NOTE / GLOSSARY

NJU9101 consists of the following circuit block.
CIRCUIT BLOCK NAME SYMBOL

2 Low Current Operational Amplifiers “OPA”, “OPB”
Bias Level Setting Register “BIASRES”
10Ω Analog Switch “ANASW”
Variable Gain Pre-Amplifier “PREAMP”
Temperature Sensor “TempSensor”
Internal Reference “INTVREF (2.048V)”
16-Bit sigma delta ADC “16-Bit ADC”
Digital Control & Calibration “Control&Calibration”
I2C Bus Compatible Control “I2C”
NJU9101 is suitable for many kinds of low power analog signal applications by using these circuit blocks.
1. Setting example following conditions

1.1 Temperature Sensor Measurement
Write below code to measure Temperature.
REGISTER REGISTER
No. CONTENTS BIT NAME BIT VALUE
ADDRESS NAME
1 Select Temperature Input Mode MEAS_SEL [2:1] 00
Select ADC Conversion Mode
2 MEAS_SC [0] 0
(Exp. Single Conversion)
0x00 CTRL
3 Start AD Conversion 1
Check completion of the AD conversion MEAS [3]
4 -
( “MEAS” bit = “0”)
0x06 TMPDATA0
5 Acquire AD conversion data. (TMPDATA) TMPDATA [9:0] -
0x07 TMPDATA1
Ver.3 - 34 -
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NJU9101
1.2 System Example 1 (Potentiostat Measurement)

Write below code to constitute “potentiostat” and “trans-impedance-amplifier”
REGISTER REGISTER
No. CONTENS BIT NAME BIT VALUE
ADDRESS NAME
1 Connect the switch “BIASRES” and “OPA” BIASSWA [5] 1
0x0F BLKCONN0
2 Connect the switch “BIASRES” and “OPB” BIASSWB [4] 1
3 Select output of BIASRES 0x11 BLKCONN2 BIASSWN [3] 1
Bias level for “trance-impedance-amplifier”
4 OPA_BIAS [7:5]
(GND to 1.7V)
0x10 BLKCONN1 any
Bias level for “potentiostat”
5 OPB_BIAS [4:0]
(GND to 1.75V
6 Powered on BIASRES, OPA, OPB, OSC 0x12 BLKCTRL BLKCTRL [7:0] 0xF0
7 Enable PREAMP 0x11 BLKCONN2 PAMPSEL [2] 1
8 Select Amp Input Mode MEAS_SEL [2:1] 01
Set Measurement Mode for ADC
9 MEAS_SC [0] 0
(ex.: Single conversion)
0x00 CTRL
10 Start measurement 1
11 -
( “MEAS” bit = “0”)
Acquire AD conversion data 0x02 AMPDATA0
12 AMPDATA [15:0] -
(AMPDATA) 0x03 AMPDATA1
Ver.3 - 35 -
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■ Application Manual NJU9101
1.3 System Example 2 (Differential Input)

Write below code to constitute “Differential Amplifier Input” by using OPA/OPB.
REGISTER REGISTER
ADDRESS NAME
1 Open OPA input switch BIASSWA [5] 0
0x0F BLKCONN0
2 Open OPB input switch BIASSWB [4] 0
3 Select OPA sensor signal input INPSWA [6] 1
4 Select OPB sensor signal input 0x11 BLKCONN2 INPSWB [5] 1
5 Select OPB output BIASSWN [3] 0
6 Powered on OPA, OPB, OSC 0x12 BLKCTRL BLKCTRL [7:0] 0x70
9 MEAS_SC [0] 0
0x00 CTRL
11 -
( “MEAS” bit = “0”)
12 AMPDATA [15:0] -
Ver.3 - 36 -
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1.4 System Example 3 (Single Input (Non-Inverting))

Write below code to constitute “Single Amplifier Input” by using OPA/OPB.
REGISTER REGISTER
ADDRESS NAME
1 Open OPA input switch BIASSWA [5] 0
0x0F BLKCONN0
2 Close OPB input switch BIASSWB [4] 1
3 Select OPA sensor signal input INPSWA [6] 1
4 Connect OPB positive input to GND 0x11 BLKCONN2 INPSWB [5] 0
5 Select BIASRES output BIASSWN [3] 1
6 Powered on BIASRES, OPA, OPB, OSC 0x12 BLKCTRL BLKCTRL [7:0] 0xF0
9 MEAS_SC [0] 0
0x00 CTRL
11 -
( “MEAS” bit = “0”)
12 AMPDATA [15:0] -
Ver.3 - 37 -
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1.5 Auxiliary (external Input) Measurement

Write below code to constitute “Differential Amplifier Input” by using PREAMP.
REGISTER REGISTER
ADDRESS NAME
1 Select AUXIN input BIASSWN [3] 1
0x11 BLKCONN2
2 Enable PREAMP PAMPSEL [2] 1
3 Select Auxiliary input mode MEAS_SEL [2:1] 10
4 MEAS_SC [0] 0
0x00 CTRL
6 -
( “MEAS” bit = “0”)
Acquire AD conversion data 0x04 AUXDATA0
7 AUXDATA [15:0] -
(AUXDATA) 0x05 AUXDATA1
Ver.3 - 38 -
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NJU9101
2. Potentiostat & Trans-impedance-amp circuit block

Potentiostat consists of “OPB”, “Variable Bias Resister (BIASRES)”. “Reference Electrode (RE)” bias voltage is set by “Variable
Bias Resister (BIASRES)” using command in “OPB_BIAS” bits. “Trans-impedance-amp(OPA)” connected to the “Working
Electrode (WE)” is used to provide an output voltage that is proportional to the cell current. Bias Voltage of OPA is also set by
BIASRES using command in “OPA_BIAS” bits.
OPA gain is set by external resister (RTIA). and, please connect RL between WE and negative input of OPA.
3. Shorting FET Function

NJU9101 has Internal Analog Switch (ANASW). This switch can
Maximum Allowed Current (mA)

connect between WE and RE of Chemical Sensor Cell. This Switch
is switched on/off by “ANASW” bit.
In discrete system, depletion FET (ex. J177) is usually used as
shorting FET. But, this switch “ANASW” in NJU9101 is
enhancement FET (not depletion FET).
Therefore, this switch “ANASW” is effective only during powered on.
This means that “ANASW” can’t turn on during powered off.
ON resistance of this switch “ANASW” is 10Ω typ. This is to get a
quick stabilized time after powered on.
Junction Temperature (°C)
4. Regarding Sensor Diagnostic Function

NJU9101 has Sensor Diagnostic Function using “SENSCK” bits.
When “SENSCK” mode turns ON (“1”), Offset Voltage of “OPA” changes around ±5mV. To switch “SENSCK” bits to
“0””1””0”, you can get as below waveforms.
* This is one of way to Sensor Diagnostic that we propose only.
AOUT Voltage
Sensor BOUT
SENSCK SENSCK
Condition Condition
OFF ON
ALL connected 1V 0.6V Waveform1
WE opened 1V 1V
Waveform2
CE opened 1V 1V
RE opened 0V 0V Waveform3
ONOFFON
Waveform1 Waveform2 Waveform3
All connected WE or CE opened RE opened
Ver.3 - 39 -
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NJU9101
5. Variable Bias Register (BIASRES)

“Variable Bias Resister (BIASRES)” for “OPA”, “OPB”, and “PREAMP” are shown in below.
The Bias Voltage for these amplifiers are given by resister ladder ratio (total resister = 1.5MΩ). These resister ladder ratio are
set by “OPA_BIAS”, “OPB_BIAS”, “PRE_BIAS” registers. Setting Name of these register (ex. 0.5V @ VREFIN=3V) is in
VREFIN=3V condition.
If VREFIN is not 3V (ex. VREFIN=2.5V), the selected Voltage is shifted as follow.

If register setting is “1.5V @ VREFIN=3V”  Actual Voltage is 1.5V * (2.5V/3.0V) = 1.25V
And, when “BIASSEL = 0”, BIASSEL_SW is turned on and fixed voltage “INTVREF (2.048V)” is given to the resister ladder
shown in figure below.
VREFIN=3V
TOTAL 1.5MΩ
475k
24k
INTVREF
BIASSEL_SW
2.048V
150k
1.75
25k
1.7
200k
1.55
25k
1.5
25k
1.45
25k
1.4
1.1
BIN+ 25k
1.05
OPB 25k
BOUT 1.0 100mVsteps

25k
0.95
25k
BIN- PREAMP
0.9
500k
OUTN
0.6 INN
25k
50mVsteps
0.55
25k
0.5
25k
0.45
OUTP
0.3
25k
INP
0.25
125k
GND/0.3/0.5/1.0/1.5/1.7V
OPA
AIN+ AIN- RTIA AOUT
RL
Ver.3 - 40 -
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NJU9101
6. PREAMP Gain Calculation

“Non-Inverted Amplifier” or “Instrumentation Amplifier” is selected by “PREMODE” bit.
“Pre-Amplifier-Gain” is selected by “PRE_GAIN” bits.
Input Voltage range of INP&INN is “0V” to “VDD-1V”.

Output Voltage range of OUTP&OUTN is “0.05V” to “VDD-0.05V”.
* Please design not to exceed Input & Output Voltage range.
6.1. PREMODE = 0 (Non-Inverted Amplifier)
INP
V OUTP  V INP  V INP  INN 

OUTP
R2
R1
R2
R1 V OUTN   V INN 
V OUTP  OUTN  R2
GAIN  1
OUTN
V INP  INN  R1
INN
Gain PRE_GAIN R1 R2
1 V/V 00 320kΩ 0Ω
2 V/V 01 160kΩ 160kΩ
4 V/V 10 80kΩ 240kΩ
8 V/V 11 40kΩ 280kΩ
6.2. PREMODE = 1 (Instrumentation Amplifier)
INP
V OUTP  V INP  V INP  INN 

OUTP
R2
R1
R2
V OUTN   V INN    V INN  INP

R1 R2
R2 R1
V OUTP  OUTN  R2
GAIN   1 2 
V INP  INN 
OUTN
INN
R1
Gain PRE_GAIN R1 R2
1 V/V 00 320kΩ 0Ω
2 V/V 01 160kΩ 80kΩ
4 V/V 10 80kΩ 120kΩ
8 V/V 11 40kΩ 140kΩ
Ver.3 - 41 -
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NJU9101
7. Low Power Management

NJU9101 is intended for use in portable devices, so the power consumption is as low as possible in order to ensure a long
battery life. Following usage assumption of NJU9101 is in a portable gas detector. And its power consumption is summarized
in below. The total power consumption for NJU9101 is below @3V average over time, this excludes any current drawn from
any pin, please consider another device’s consumption.
< Condition >

- The system is used about 8 hours a day, and 16 hours a day it is in Standby mode.
- Basically, Only “OPB” and “BIASRES” block are turned On in Standby mode.
- Potentiostat Measurement is once per second.
- Aux Data Measurement is one per minutes.
- Temperature Measurement is one per minutes.
- ADC conversion time uses approximately 16.6ms. (OSR=”01”, REJ=”10”, ADCCHOP=”1”)
3-Lead Potentiostat Aux Data Temperature Total Current

Standby
Potentiostat Measurement Measurement Measurement Consumption
Current Consumption 0.5µA 10.5µA 215.5µA 160.5µA 250.5µA
16 (h) 8 (h) 480 (s) 8 (s) 8 (s)
Time On a Day
66.6% 33.3% 0.556% 0.009% 0.009%
Average Current 0.33µA 3.5µA 1.2µA 0.01µA 0.02µA 5.06µA
ANASW ON OFF OFF OFF OFF
BIASRES OFF ON ON ON ON
OPA OFF ON ON ON ON
OPB OFF ON ON ON ON
PREAMP OFF OFF ON OFF ON
ADC OFF OFF ON ON ON
Temp. sensor OFF OFF OFF OFF ON
I2C & Logic ON ON ON ON ON
Ver.3 - 42 -
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NJU9101
8. I2C-BUS Interface
NJU9101 has 2 types of I2C bus, one bus communicates to host device such as MCU, the other bus communicates to external
EEPROM which is to retain the IC configurations, calibration parameters, .etc. These 2 types of I2C bus operate independently.
NJU9101 operates for host interface as I2C slave device, and operates for EEPROM interface as I2C Master Device.
One I2C-bus which connects to host device is SCL/SDA, and the other I2C-bus which connects to external EEPROM is
EXSCL/EXSDA.
Communicate I2C bus I/O Master / Slave

Host Device SCL Input
NJU9101:Slave
(e.g.: MCU) SDA Input / Open-Drain Output
EXSCL Open-Drain Output
External EEPROM NJU9101:Master
EXSDA Input / Open-Drain Output
uP Serial EEPROM 16kbits

(I2C Master) (I2C Slave)
SCL SDA EXSCL EXSDA
AD0
I2C Master Interface
AD1 I2C Slave Interface
(EEPROM Bridge)
AD2
10 8
(address) (data)
Host Register
ADC
8.1. I2C Slave Interface

This interface is used for the Host that accesses to registers in NJU9101. NJU9101 is a I2C Slave device for the host MCU.
The operation of which conversion trigger, conversion data reading, access external EEPROM, .etc. are executed through
reading and writing of registers in NJU9101. Registers in NJU9101 are register address 0x00 to 0x3F and each address has
8 bits width register.
Ver.3 - 43 -
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● I2C Protocol
7bit-I2C Slave address consists of a fixed four-bit ‘0x9(b1001)’ and chip address pin ‘AD2’, ‘AD1’, ‘AD1’.
In case of write operation, transmit the writing data in following,

‘Slave address’ + ‘Write bit (0)’ + ‘Write Register address’ + ‘Write data’.
When more than 2 bites of write data are transmitted, register address are increment automatically, and write the date into
corresponding registers. When register address is over 0x3F, return to address 0x00 and lap around.
In case of read operation, transmit the data in following,

‘Slave address’ + ‘Write bit (0)’ + ‘Read Register address’ and then transmit ‘repeat start’ command.
When more than 2 bites of read data are read, register address are increment automatically, and read the date into
corresponding address. When register address is over 0x3F, return to address 0x00 and lap around.
4 3 1 2 6 8
S I2C Slave Addr[3:0] AD2 AD1 AD0 W A 0 0 Register Addr[5:0] A Write Data Byte A P
4 3 1 2 6 8 8 8
S I2C Slave Addr[3:0] AD2 AD1 AD0 W A 0 0 Register Addr[5:0] A Write Data Byte A Write Data Byte A Write Data Byte A P
Register Addr Register Addr+1 Register Addr+N
4 3 1 2 6 4 3 8
S I2C Slave Addr[3:0] AD2 AD1 AD0 W A 0 0 Register Addr[5:0] A Sr I2C Slave Addr[3:0] AD2 AD1 AD0 R A Read Data Byte A P
4 3 1 2 6 4 3 8 8
S I2C Slave Addr[3:0] AD2 AD1 AD0 W A 0 0 Register Addr[5:0] A Sr I2C Slave Addr[3:0] AD2 AD1 AD0 R A Read Data Byte A Read Data Byte A Read Data Byte A P
Register Addr Register Addr+1 Register Addr+N
S: Start Condition
Sr: Repeat Start Condition
P: Stop Condition
A: Ack
A: Nack
R: Read
W: Write
● I2C external EEPROM Interface

I2C external EEPROM of 16k-Bit (2kByte) can be connected as a external storage device for NJU9101. ‘Microchip 24LC16B’
is used as a standard External EEPROM. Other I2C Serial EEPROM with communication compatible can be used. Some
areas in external EEPROM are used as preset area for configuration data of NJU9101. The remaining areas in external
EEPROM can be used for any uses.
NJU9101 supports 4-operations for external EEPROM from host-interface (MCU).

· Read data from arbitrary address area in external EEPROM.
· Write data to arbitrary address area in external EEPROM.
· Load the all data from external EEPROM to host register (MCU).
· Store register data in host register (MCU) to external EEPROM.
See also, “EVERY REGISTER DESCRIPTION : ROMCTRL” to control the external EEPROM.
Ver.3 - 44 -
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■ Application manual NJU9101
● External EEPROM operating flow & External EEPROM I2C bus timing
Flow chart of access to external EEPROM is shown in below. When access to external EEPROM, system clock has to be
operating and ‘ROMBUSY’ bit has to be ‘0’. And it can also access to external EEPROM under ADC conversion (Except for
reading the initial register value just after reset release.).
no
yes
no no
yes yes
no no
yes yes
External EEPROM requires about 5ms of write time internally after write operation. During this period, NJU9101 cannot
read/write from/to external EEPROM and external EEPROM returns ‘NACK’ for address byte. When NJU9101 starts to
access to external EEPROM, NJU9101 does polling until receive ‘ACK’, and wait for completion of writing time in external
EEPROM.
When NJU9101 is not connected with external EEPROM, address byte of NJU9101 always receives ‘NACK’. Therefore,
External EEPROM Control block in NJU9101 cannot stop polling. In such case, stop accessing to external EEPROM quickly
by writing “1” to “ROMSTOP” bit, or it can break out of the polling by generating communication error (“ROMERR”=”1”) with
fixed “0” for EXSDA terminal.
I2C-bus of external EEPROM uses 3-system clock every 1 bit transfer, therefore maximum translate is fin/3[bps].
Ver.3 - 45 -
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● ∆Σ ADC control
∆Σ ADC conversion flow is shown in below.
RESET
Wait Clock start

CLKRUN=0
MEAS=0
ROMBUSY=0
BOOT=1
Load data from OTPROM

CLKRUN=1
MEAS=0
ROMBUSY=0
BOOT=1
Load data from EEPROM

CLKRUN=1
MEAS=0
ROMBUSY=1
BOOT=1
BLKCNT[4] = 0 BLKCNT[4] BLKCNT[4] = 1

(OSC Power)
BLKCNT[4] = 0
Idle with clock stop Idle
CLKRUN=0 CLKRUN=1
MEAS=0 MEAS=0
ROMBUSY=0 BLKCNT[4] = 1 ROMBUSY=0
BOOT=0 Wait Clock start BOOT=0
Write MEAS = 1 Write MEAS = 1
Wait Clock start

CLKRUN=0
MEAS=1
MEAS_SC = 1 MEAS_SC = 0 MEAS_SC = 1 MEAS_SC = 0

MEAS_SC MEAS_SC
Complete Conversion
(RDYB =0)
Continuous Single
Conversion Conversion
CLKRUN=1 CLKRUN=1
MEAS=1 MEAS=1
Complete Conversion
Write MEAS = 0 MEAS = 0
RDYB =0
BLKCNT[4] = 0 BLKCNT[4] BLKCNT[4] BLKCNT[4] = 1

(OSC Power) (OSC Power)
BLKCNT[4] = 0 BLKCNT[4] = 1
Ver.3 - 46 -
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● Start-Up
After power-on reset or release I2C reset, start internal clock (OSC) and load data from external EEPROM to NJU9101’s
register. During loading, ‘ROMBUSY’ shows ‘1’. After finish loading to NJU9101’s register, NJU9101 becomes idle state or
idle state with clock stop which are following BLKCNT [4] setting.
● Idle State
“Idle state” means in the state which is not conversion state. In the idle state, ‘BLKCNT [4](OSC power down)’bit changes the
powered-on/off of system clock. During stopping the system clock, NJU9101 is idle state with clock stop, and it cannot write
the data of NJU9101 register except ‘CTRL’ and ‘BLKCNT’ register. This means that “Please write ‘BLKCNT[4]’=’1’, when
change the data of NJU9101 register”.
● Conversion
When write ‘MEAS’ bit = ‘1’, conversion starts with following NJU9101 register setting.
First, Wake up time of modulator Twu is required after conversion started.
TWU = 20 / fmod [sec]
Tadc is the time which is divided ‘decimation rate (set in OSR / REJ bit) by fmod (normal modulation clock frequency of ΔΣ
modulator ≈ 153.6 kHz).
Tadc = Decimation rate / fmod [sec]
Standard timing of ADC conversion is defined as Tadc.

And, after completion of conversion, it requires around 70 cycle of system clock (70 / fOSC) to do data corrective calculation.
This calculation time is defined as Tcal.
Tcal = 70 / fOSC ≈ 230µ [sec]
● Single Conversion
Conversion time of ‘Single conversion’ is ‘ Twu + 3 * Tadc + ‘Tcal ’. The settling time of ADC requires ‘ 3 * Tadc ’.
After complete data correction, data register is updated, and RDYB bit is asserted.
Tadc Tadc Tadc
Tcal
Ver.3 - 47 -
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● Single Conversion + Chopping Operation

Conversion time of ‘Single Conversion + Chopping Operation’ is ‘ Twu + 6 * Tadc + Tcal ’. The settling time of ADC requires ‘ 6 *
Tadc ’. After complete data correction, data register is updated, and ‘RDYB’ bit is asserted. And then, ‘MEAS’ bit turns to ‘0’,
become idle state again. Chopping operation can cancel offset voltage into ADC by swapping differential positive - negative
input.
Tadc Tadc Tadc Tadc Tadc Tadc
Tcal
● Continuous Conversion
The first conversion time of ‘Continuous Conversion’ is ‘ Twu + 3 * Tadc + Tcal ’. The settling time of ADC requires ‘ 3 * Tadc ’.
After complete the first conversion data correction, data register is updated, and RDYB bit is asserted. And after that, data
register is updated and RDYB bit is asserted every Tadc. Conversion rate after the first conversion is 1/Tadc [sps]. This
conversion is continued until written ‘MEAS = 0’.
Tadc Tadc Tadc Tadc Tadc Tadc
Tcal Tcal Tcal
● Continuous Conversion + Chopping Operation

The first conversion time of ‘Continuous Conversion + Chopping Operation’ is ‘Twu + 6 * Tadc + Tcal’. The settling time of ADC
requires ‘6 * Tadc’. After complete data correction, data register is updated, and RDYB bit is asserted. And after that, data register
is updated and RDYB bit is asserted every ‘3 * Tadc’. Conversion rate after the first conversion is ‘1/(3 * Tadc)’ [sps]. This
conversion is continued until written ‘MEAS = 0’.
Tadc Tadc Tadc Tadc Tadc Tadc Tadc Tadc Tadc Tadc Tadc
Tcal Tcal
Ver.3 - 48 -
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NJU9101
● Conversion at ‘Idle state with Clock Stop’

In case of ‘Idle state with Clock Stop (BLKCNT[4]=0)’, it is necessary an additional time (≈830µs) to wake up the clock circuit
after start conversion trigger. When ‘Single Conversion’ is set, it turns ‘Idle state with Clock Stop (BLKCNT [4] = 0)’ automatically
after complete the conversion.
Tadc Tadc Tadc
Tcal
● Power-Down Control
Power down control signal of each circuit block in NJU9101 is controlled by following registers value ‘MEAS’, ‘MEAS_SEL’,
‘VREFSEL’, ‘PAMPSEL’, and ‘BLKCNT[7:0]’.
BIASRES circuit block power down

BLKCNT Power
Block
[7] Condition
0 PWR DOWN
BIASRES
1 OPERATE
OPA circuit block power down

MEAS_SEL BLKCNT Power
Block MEAS
[1:0] [5] Condition
0 - 0
PWR DOWN
1 00 / 10 0
OPA
1 01 0
OPERATE
- - 1
OPB circuit block power down

Block MEAS
[1:0] [6] Condition
0 - 0
PWR DOWN
1 00 / 10 0
OPB
1 01 0
OPERATE
- - 1
Ver.3 - 49 -
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OSC circuit block power down

BLKCNT [4] BLKCNT [1] Power
Block MEAS
OSC ADC Condition
0 0 0 PWR DOWN
1 0 0
OSC
- 1 - OPERATE
- - 1
PREAMP circuit block power down

Block MEAS PAMPSEL
[1:0] [3] Condition
0 - - 0 PWR DOWN
1 00 - - OPERATE
PREAMP 1 01 / 10 0 0 PWR DOWN
1 01 / 10 1 0
OPERATE
- - - 1
2.048V INTVREF circuit block power down

Block MEAS BIASSEL VREFSEL
[1:0] [2] Condition
0 - 1 - 0 PWR DOWN
1 00 1 - 0
OPERATE
1 01 / 10 1 0 0
INTVREF
1 01 / 10 1 1 0 PWR DOWN
- - 1 - 1
OPERATE
- - 0 - -
ADC circuit block power down

BLKCNT Power
Block MEAS
[1] Condition
0 0 PWR DOWN
ADC 1 0
OPERATE
- 1
Temperature Sensor circuit power down

Block MEAS
[1:0] [0] Condition
0 - 0 PWR DOWN
Temp. 1 00 0 OPERATE
Sensor 1 01 / 10 0 PWR DOWN
- - 1 OPERATE
Ver.3 - 50 -
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● Data Processing
Analog Input is modulated to PDM signal by 2nd Order ΔΣ modulator. And then, this PDM signal changes to PCM signal by
Sinc3 Digital Filter. Sinc3 Digital Output data is stored to AMPDATA / AUXDATA / TMPDATA register after data calibration.
● ∆Σ Modulator
Normal modulation clock frequency of ΔΣ (Sigma Delta) modulator (fmod) is 153.6 kHz. This frequency (fmod) is the over-
sampling clock of the ADC which is divided OSC system clock (fOSC) with setting of ‘CLKDIV’ bit. Modulated ratio of this
modulator is 66.7%. When +1.5Vpp of differential signal is input, modulated output goes to +1Vpp.
● Sinc3 Digital Filter

Digital Filter in NJU9101 is 3rd Order Sinc-Filter that has 768 of maximum decimation ratio. This decimation ratio can be set by
‘OSR’ and ‘REJ’ bit.
■ Sinc3 filter frequency example 1

(CHOPPING OFF setting example)
Conversion Time = 7.5ms (Single conversion)
Decimation Ratio=320
(OSR=01, REJ=10, CLKDIV=00, ADCCHOP=0)

(CHOPPING ON setting example)
Conversion Time = 13.8ms (Single conversion)
Decimation Ratio = 320

Ver.3 - 51 -
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NJU9101

(50 / 60Hz Reduction setting example)
Conversion Time = 61.6ms (Single Conversion)


(Fastest Conversion Time setting example)
Conversion Time = 2.8ms (Single Conversion)
Ver.3 - 52 -
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● Data Calibration
Analog Input is modulated to PDM signal by 2nd Order ΔΣ modulator. And then, this PDM signal is changed to signed 19 bit
PCM signal (ADCDATA) by Sinc3 Digital Filter. The full-scale range of ADCDATA is -262144 to +262143 (0x40000 to 0x3FFFF).
ADCDATA is stored to AMPDATA / AUXDATA / TMPDATA register after data calibration.
PRE Delta-Sigma Digital 19 ADCDATA AMPDATA 16

Vin AMPDATA
AMP Modulator Filter Calibration Circuit
PRE_GAIN ADC_GAIN
AUXDATA 16
AUXDATA
Calibration Circuit
TMPDATA 10
TMPDATA
Calibration Circuit
Regarding calculation of ADCDATA, Voltage GAIN of PREAMP (Gpre) and Conversion GAIN of ADC (Gadc) are defined as
below,
Gain of PREAMP Gain of ADC

PAMPSEL PRE_GAIN Gpre ADC_GAIN Gadc
0 XX 1 00 1
1 00 1 01 2
1 01 2 10 4
1 10 4 11 8
1 11 8
When it is assumed that

“Vref” :Reference Voltage selected by “VREFSEL”bit.
“Vin” :Differential Input Voltage of PREAMP
Digital Filter Output (ADCDATA) is output as below, when ADCDATA range is limited as signed 19 bit range (min:-
262144(0x40000), max:+262143(0x3FFFF).
2 𝑉௜௡
ADCDATA = 262144 × 𝐺௣௥௘ × 𝐺௔ௗ௖ × ×
3 𝑉௥௘௙
Ver.3 - 53 -
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● AMPDATA Calibration
AMPDATA Calibration has temperature calibration of offset and Sensitivity for ADCDATA. And then, calibrated data is stored
to AMPDATA[15:0] register. AMPDATA calibration path is shown in below.
OFOV
PRE Delta-Sigma Digital 19 ADCDATA OV

+
AMP Modulator Filter 19 D0 A
OC Divide 19 16
+
(Offset Coefficient) Limit AMPDATA
8 A/B
SCAL
- 17 SC B
(SCALx/-45) 10
(Sensitivity Coefficient)
10
+ 18
OCAL 8 CERR CERR

-
(OCALx/-45) 10
10 20 19
TMPDATA +
X + X +
10 9
10 16
+ +
OCALA OCALB SCALA SCALB

(OCALxA) (OCALxB) (SCALxA) (SCALxB)
8
Sensor Coefficients Table
Calibration coefficients for offset are set for four temperature areas. For these temperature areas, 0-order coefficient (offset
value: OCALxB at OCALx[C]) and 1st-order coefficient (temperature slope: OCALxA) are set. These temperature area are set
by OCALx[C] (-45C ≤ OCAL1 < OCAL2 < OCAL3 ≤ 127C). These coefficients are automatically selected by TEMPDATA
value. Offset Calibration coefficient “OC” is signed 17-bits factor and calculated as below
Condition Calculation
-45 ≤ TEMPDATA [9:2] ˂ OCAL1 OC = [ {TEMPDATA – (-45 x 4) } x OCAL1A ] + (OCAL1B x 4)
OCAL1 ≤ TEMPDATA [9:2] ˂ OCAL2 OC = [ {TEMPDATA – (OCAL1 x 4) } x OCAL2A ] + (OCAL2B x 4)
OCAL2 ≤ TEMPDATA [9:2] ˂ OCAL3 OC = [ {TEMPDATA – (OCAL2 x 4) } x OCAL3A ] + (OCAL3B x 4)
OCAL3 ≤ TEMPDATA [9:2] OC = [ {TEMPDATA – (OCAL3 x 4) } x OCAL4A ] + (OCAL4B x 4)
* When ”OC” value exceeds signed 17-bits range (-65536 to +65535 (0x10000 to 0x0FFFF)), “CERR” bit is set as error flag
of offset calibration coefficient. In this situation, AMPDATA is not correct value.
And then, ADCDATA and offset coefficient “OC” are summed. Converted DATA “D0” is calculated as below,
D0 = ADCDATA + (OC x 4)
* When ”D0” value exceeds signed 19-bits range (-262144 to +262143 (0x40000 to 0x3FFFF)), “OFOV” bit is set as error
flag. In this situation, AMPDATA is not correct value.
Calibration coefficients for sensitivity are set for four temperature areas. For these temperature areas, 0-order coefficient
(sensitivity value: SCALxB at SCALx[C]) and 1st-order coefficient (temperature slope: SCALxA) are set. These temperature
area are set by SCALx[C] (-45C ≤ SCAL1 < SCAL2 < SCAL3 ≤ 127C). These coefficients are automatically selected by
TEMPDATA value. Sensitivity Calibration coefficient “SC” is unsigned 18-bits factor and calculated as below.
Ver.3 - 54 -
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NJU9101
Condition Caluculation
-45 ≤ TEMPDATA [9:2] ˂ SCAL1 SC = [ {TEMPDATA – (-45 x 4) } x SCAL1A ] + (SCAL1B x 4)
SCAL1 ≤ TEMPDATA [9:2] ˂ SCAL2 SC = [ {TEMPDATA – (SCAL1 x 4) } x SCAL2A ] + (SCAL2B x 4)
SCAL2 ≤ TEMPDATA [9:2] ˂ SCAL3 SC = [ {TEMPDATA – (SCAL2 x 4) } x SCAL3A ] + (SCAL3B x 4)
SCAL3 ≤ TEMPDATA [9:2] SC = [ {TEMPDATA – (SCAL3 x 4) } + (SCAL4B x 4)
* When ”SC” value exceeds the range of 8192 to 262143 (0x2000 to 0x3FFFF), “CERR” bit is set as error flag of sensitivity
calibration coefficient. In this situation, AMPDATA is not correct value. And when “SC” value is regarded as signed 2.16 fixed
point, this data range is equivalent to 4.0 to 0.125.
For Sensitivity calculation, offset conversion data “D0” is divided by “SC”. This result (quotient) is rounded to integer, and
then, AMPDATA is decided.
𝐷0 × 2ଵସ
AMPDATA = Round ቆ ቇ
𝑆𝐶
* When AMPDATA value exceeds signed 16-bits range (-32768 to +32767 (0x8000 to 0x7FFF)), “OV” bit is set as error flag.
In this situation, ADCDATA value is limited to min: -32768(0x8000) or max: +32767(0x7FFF), and then stored to AMPDATA
register.
Calibration Range Set Resolution

Register
±1.0 conv. 14-Bit conv. ±1.0 conv. 14-Bit conv.
Offset coef.
0th OCALxB ±1.0 ±8192 1 / (2^14) 0.5LSB
1st OCALxA ±0.03125 / °C ±256LSB / °C 1 / (2 to 14) / °C 0.5LSB / °C
Sens coef.
0th SCALxB x0.125 to x4.0 - 61ppm -
1st SCALxA ±15625ppm / °C - 61ppm / °C -
Offset Offset Offset Offset Offset

Area 1 Area 2 Area 3 Area 4
1.0
OCAL4B
OCAL4A
OCAL1B
OCAL1A
OCAL3B
OCAL3A
0.0 TMPDATA[degree]
-45 OCAL1 OCAL2 OCAL3 127
OCAL2A
OCAL2B
-1.0
1/Gain=Sensitivity Gain Gain Gain Gain

Area 1 Area 2 Area 3 Area 4
4.0
SCAL4B SCAL4A
SCAL2B
SCAL2A
SCAL1A SCAL3B SCAL3A

SCAL1B
1.0 TMPDATA[degree]
-45 SCAL1 SCAL2 SCAL3 127
0.125
Ver.3 - 55 -
http://www.njr.com/
● AUXDATA Calibration
AUXDATA Calibration has offset and Sensitivity calibration for ADCDATA. And then, calibrated data is stored to
AUXDATA[15:0] register. AUXDATA calibration path is shown in below.
16
AUX_SCAL
PRE Delta-Sigma Digital 19 ADCDATA 17

AMP /4
Modulator Filter OV
OFOV
33 17 16
16
+
X /2 Limit AUXDATA
17 D1
16
AUX_OCAL -
Conversion Data “D1” after offset calibration is calculated as below. (Low order 2-bit of ADCDATA are rounded down)
𝐴𝐷𝐶𝐷𝐴𝑇𝐴
D1 = Truncate( ) − AUX_OCAL
4
* When “D1” value exceeds signed 17-bits range (-65536 to +65535 (0x10000 to 0x0FFFF)), “OFOV” bit is set as error flag. In
this situation, AUXDATA value is not correct value.
For sensitivity calibration, it is multiplied conversion data “D1” by “AUX_SCAL” coefficient. This result (product) is divided by
2^16, and is rounded to integer. And then, AUXDATA is decided.
𝐷1 × 𝐴𝑈𝑋_𝑆𝐶𝐴𝐿
AUXDATA = Round( )
2ଵ଺
* When AUXDATA value exceeds signed 16-bits range (-32768 to +32767 (0x8000 to 0x7FFF)), “OV” bit is set as error flag.
In this situation, ADCDATA value is limited to min: -32768(0x8000) or max: +32767(0x7FFF), and then stored to AUXDATA
register.
Calibration Range Set Resolution

Register
±1.0 conv. 14-Bit conv. ±1.0 conv. 14-Bit conv.
Offset calibration coef. AUX_OCAL ±0.5 ±4096 1 / (2^17) 0.125LSB
Sensitivity calibration coef. AUX_SCAL x0.0 to x2.0 - 30.5ppm / °C -
TMPDATA Calibration
TMPDATA data conversion are converted ADCDATA to temperature code. In TMPDATA conversion, fixed setting of these
bits “VREFSEL”, “ADC_GAIN”, PRE_GAIN” are used. TMPDATA is converted to signed 10-bits data shown as 0.25C/LSB.
The data range of TMPDATA is -45.00C to +127.75C (0x34C to 0x1FF). When converted value exceeds this range, “OV” bit
is set as error flag. In this situation, ADCDATA value is limited to min: -45.00C (0x34C) or max: +127.75C (0x1FF), and then
stored to TMPDATA register.
Ver.3 - 56 -
http://www.njr.com/
NJU9101
■EVALUATION BOARD PCB LAYOUT
(Note) Install the decoupling capacitor in the proximity of the NJU9101.
Ver.3 - 57 -
http://www.njr.com/
NJU9101
EQFN24-LE
Unit: mm
■PACKAGE DIMENSIONS ■EXAMPLE OF SOLDER PADS DIMENSIONS
Ver.3 - 58 -
http://www.njr.com/
NJU9101
EQFN24-LE
■PACKING SPEC Unit: mm
TAPING DIMENSIONS
REEL DIMENSIONS
TAPING STATE
PACKING STATE
Ver.3 - 59 -
http://www.njr.com/
NJU9101
INFRARED REFLOW SOLDERING METHOD EAE-D1006-000-02
Recommended reflow soldering procedure
f
260 e
230
d
220
180
150
Room Temp.
a b c g
a Temperature ramping rate : 1 to 4 /s

b Pre-heating temperature : 150 to 180
time : 60 to 120s
c Temperature ramp rate : 1 to 4 /s
d 220 or higher time : Shorter than 60s
e 230 or higher time : Shorter than 40s
f Peak temperature : Lower than 260
g Temperature ramping rate : 1 to 6 /s
The temperature indicates at the surface of mold package.
Ver.3 - 60 -
http://www.njr.com/
NJU9101
[ CAUTION ]
1. NJR strives to produce reliable and high quality semiconductors. NJR’s semiconductors are intended for specific applications and
require proper maintenance and handling. To enhance the performance and service of NJR's semiconductors, the devices,
machinery or equipment into which they are integrated should undergo preventative maintenance and inspection at regularly
scheduled intervals. Failure to properly maintain equipment and machinery incorporating these products can result in catastrophic
system failures
2. The specifications on this datasheet are only given for information without any guarantee as regards either mistakes or omissions.
The application circuits in this datasheet are described only to show representative usages of the product and not intended for the
guarantee or permission of any right including the industrial property rights.
All other trademarks mentioned herein are the property of their respective companies.
3. To ensure the highest levels of reliability, NJR products must always be properly handled.
The introduction of external contaminants (e.g. dust, oil or cosmetics) can result in failures of semiconductor products.
4. NJR offers a variety of semiconductor products intended for particular applications. It is important that you select the proper
component for your intended application. You may contact NJR's Sale's Office if you are uncertain about the products listed in this
datasheet.
5. Special care is required in designing devices, machinery or equipment which demand high levels of reliability. This is particularly
important when designing critical components or systems whose failure can foreseeably result in situations that could adversely
affect health or safety. In designing such critical devices, equipment or machinery, careful consideration should be given to
amongst other things, their safety design, fail-safe design, back-up and redundancy systems, and diffusion design.
6. The products listed in this datasheet may not be appropriate for use in certain equipment where reliability is critical or where the
products may be subjected to extreme conditions. You should consult our sales office before using the products in any of the
following types of equipment.
 Aerospace Equipment
 Equipment Used in the Deep Sea
 Power Generator Control Equipment (Nuclear, steam, hydraulic, etc.)
 Life Maintenance Medical Equipment
 Fire Alarms / Intruder Detectors
 Vehicle Control Equipment (Automobile, airplane, railroad, ship, etc.)
 Various Safety Devices
7. NJR's products have been designed and tested to function within controlled environmental conditions. Do not use products under
conditions that deviate from methods or applications specified in this datasheet. Failure to employ the products in the proper
applications can lead to deterioration, destruction or failure of the products. NJR shall not be responsible for any bodily injury, fires
or accident, property damage or any consequential damages resulting from misuse or misapplication of the products. The
products are sold without warranty of any kind, either express or implied, including but not limited to any implied warranty of
merchantability or fitness for a particular purpose.
8. Warning for handling Gallium and Arsenic (GaAs) Products (Applying to GaAs MMIC, Photo Reflector). These products use Gallium
(Ga) and Arsenic (As) which are specified as poisonous chemicals by law. For the prevention of a hazard, do not burn, destroy, or
process chemically to make them as gas or power. When the product is disposed of, please follow the related regulation and do
not mix this with general industrial waste or household waste.
9. The product specifications and descriptions listed in this datasheet are subject to change at any time, without notice.
Ver.3 - 61 -
http://www.njr.com/

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NJU9101

Low Power Analog Front End

■FEATURES ■GENERAL DESCRIPTION

■EQUIVALENT CIRCUIT BLOCK DIAGRAM

PIN NO. SYMBOL DESCRIPTION Pin Type

NJU9101 MLE (TE1)

Part Number Package Taping Form

■ABSOLUTE MAXIMUM RATINGS

■RECOMMENDED OPERATING CONDITIONS

Unless otherwise specified, all limits ensured for Ta = 25°C, VDD = 3V

■CHARACTERISTICS OF I/O STAGES FOR I2C BUS Compatible (SDA, SCL)

tHD:STA tSU:STA tSU:STO

■CHARACTERISTICS OF I/O STAGES FOR EEPROM I2C BUS (EXSDA, EXSCL)

■CHARACTERISTICS OF BUS LINES (EXSDA, EXSCL)

■TIMING ON THE EEPROM I2C BUS (EXSDA, EXSCL)

tHD:STA tSU:STA tSU:STO

REGISTER EEPROM REGISTER BIT

ADDRESS ADDRESS NAME D7 D6 D5 D4 D3 D2 D1 D0

0x00 - CTRL - RST SENSCK [1:0] MEAS MEAS_SEL [1:0] MEAS_SC

0x01 - STATUS - - BOOT CLKRUN RDYB OV CERR OFOV

0x02 - AMPDATA0 AMPDATA [15:8]

0x03 - AMPDATA1 AMPDATA [7:0]

0x04 - AUXDATA0 AUXDATA [15:8]

0x05 - AUXDATA1 AUXDATA [7:0]

0x06 - TMPDATA0 TMPDATA [9:2]

0x07 - TMPDATA1 TMPDATA [1:0] - - - - - -

0x09 - ROMADR0 - - - - - ROMADR [10:8]

0x0A - ROMADR1 ROMADR [7:0]

0x0B - ROMDATA ROMDATA [7:0]

0x0C - ROMCTRL - - ROMERR ROMBUSY ROMSTOP ROMACT ROMMODE [1:0]

0x0D - TEST TEST [7:0]

0x0E 0x000 ANAGAIN - - - - PRE_GAIN [1:0] ADC_GAIN [1:0]

0x0F 0x001 BLKCONN0 - - BIASSWA BIASSWB PRE_BIAS [3:0]

0x10 0x002 BLKCONN1 OPA_BIAS [2:0] OPB_BIAS [4:0]

0x12 0x004 BLKCTRL BLKCTRL [7:0]

0x14 0x006 SYSPRESET RDYBOE RDYBDAT RDYBMODE [1:0] - - - AMPAUX

0x15 0x007 SCAL1A0 - - - - - - - SCAL1A [8]

0x16 0x008 SCAL1A1 SCAL1A [7:0]

0x17 0x009 SCAL2A0 - - - - - - - SCAL2A [8]

0x18 0x00A SCAL2A1 SCAL2A [7:0]

0x19 0x00B SCAL3A0 - - - - - - - SCAL3A [8]

0x1A 0x00C SCAL3A1 SCAL3A [7:0]

0x1B 0x00D SCAL4A0 - - - - - - - SCAL4A [8]

0x1C 0x00E SCAL4A1 SCAL4A [7:0]

0x1D 0x00F SCAL1B0 SCAL1B [15:8]

0x1E 0x010 SCAL1B1 SCAL1B [7:0]

0x1F 0x011 SCAL2B0 SCAL2B [15:8]

0x20 0x012 SCAL2B1 SCAL2B [7:0]

0x21 0x013 SCAL3B0 SCAL3B [15:8]

0x22 0x014 SCAL3B1 SCAL3B [7:0]

0x23 0x015 SCAL4B0 SCAL4B [15:8]

0x24 0x016 SCAL4B1 SCAL4B [7:0]

0x25 0x017 OCAL1A0 - - - - - - OCAL1A [9:8]

0x26 0x018 OCAL1A1 OCAL1A [7:0]

0x27 0x019 OCAL2A0 - - - - - - OCAL2A [9:8]

0x28 0x01A OCAL2A1 OCAL2A [7:0]

0x29 0x01B OCAL3A0 - - - - - - OCAL3A [9:8]

0x2A 0x01C OCAL3A1 OCAL3A [7:0]

0x2B 0x01D OCAL4A0 - - - - - - OCAL4A [9:8]