NCP1589D

Low Voltage Synchronous

Buck Controller with Light
Load Efficiency and
Transient Enhancement
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The NCP1589D is a low cost PWM controller designed to operate
from a 5 V or 12 V supply. This device is capable of producing an MARKING
output voltage as low as 0.8 V and converting voltage from as low as DIAGRAM
2.5 V. It is easy to operate and provides an optimal level of integration
to reduce size and cost of the power supply. It operates in Ramp Pulse 1589D
Modulation mode for superior load step and release response. In DFN10 ALYWG
addition to fast transient response, it also includes a 1.5 A gate driver CASE 485C G
design and light load efficiency features such as adaptive non−overlap
circuitry and diode emulation. It normally operates at a range of 1589D = Specific Device Code
200−500 kHz in continuous current conduction mode, which reduces A = Assembly Location
L = Wafer Lot
with current at light load for further power saving. Protection features
Y = Year
include programmable overcurrent protection, output overvoltage and W = Work Week
undervoltage protection and input undervoltage lockout (UVLO). G = Pb−Free Device
(Note: Microdot may be in either location)
Features
• VCC Range from 4.5 V to 13.2 V
• Adjustable Operating frequency
• Boost Pin Operates to 35 V PIN CONNECTIONS
• Ramp Pulse Modulation Control
• Precision 0.8 V Internal Reference BOOT 1 10 PGOOD

• Adjustable Output Voltage LX 2 9 VORPM

• Internal 1.5 A Gate Drivers UG 3 8 FB

• 80% Max Duty Cycle LG 4 7 COMP/DISB

Flag
• Input Under Voltage Lockout GND 5 6 VCC
• Programmable Current Limit
• Adaptive Diode Mode Emulation in Light Load (Top View)

• This is a Pb−Free Device

Applications ORDERING INFORMATION

• Graphics Cards Device Package Shipping†
• Desktop Computers NCP1589DMNTWG DFN10 3000 /
• Servers / Networking (Pb−Free) Tape & Reel
• DSP & FPGA Power Supply †For information on tape and reel specifications,
• DC−DC Regulator Modules including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

January, 2017 − Rev. 2 NCP1589D/D
 NCP1589D

VCC = 4.5 V − 13.2 V VBST = 4.5 V − 15 V VIN = 2.5 V − 19 V

VCC
PGOOD BOOT

COMP/DISB UG
C1 R2

LX VOUT
C2

FB LG

ROCSET
FLAG GND VORPM
C3
R4
R1
R3 R9 R10
GND

Figure 1. Typical Application Diagram

PGOOD
10

VORPM 9 PGOOD
±10% of Vref
MONITOR
OV and UV ±25% of Vref
0.8 V
(Vref)
POR 6 VCC
UVLO

+
FAULT LATCH VOCP
−

FB 8 − 1 BOOT
− FAULT
+ R
+
PWM Q 3 UG
0.8 V OUT
S
(Vref)
2 LX
+
−
RPMSET
2V
RAMP +
LX
−
COMP VPRM VCC
VORPM
COMP/DISB 7 4 LG

FAULT 5 GND
LX AZCD logic

Figure 2. Detailed Block Diagram

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 NCP1589D

PIN FUNCTION DESCRIPTION

Pin No. Symbol Description
1 BOOT Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired
input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (CBOOT) between this pin
and the LX pin. Typical values for CBOOT range from 0.1 mF to 1 mF. Ensure that CBOOT is placed near the
IC.
2 LX Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the
top MOSFET. Also used for low side MOSFET RDS(on) current detection and diode emulation.

3 UG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−channel MOSFET.
4 LG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−channel MOSFET. Also used
to set the overcurrent limit.

5 GND IC ground reference. All control circuits are referenced to this pin. Connect to FLAG.
6 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capaci-
tor to GND. Ensure that this decoupling capacitor is placed near the IC. Also low−side MOSFET drive volt-
age.
7 COMP/DISB Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM
comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop.
Pull this pin low for disable.
8 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to com-
pensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly
to Vout.
9 VORPM Output voltage information for RPM threshold
10 PGOOD Power Good output. Pulled Low if VFB is outside ±10% of 0.8 V Vref.

ABSOLUTE MAXIMUM RATINGS

Pin Name Symbol VMAX VMIN
Main Supply Voltage Input VCC 15 V −0.3 V
Bootstrap Supply Voltage Input BOOT 35 V wrt/GND −0.3 V
40 V < 100 ns −0.3 V
15 V wrt/LX −0.3 V
Switching Node (Bootstrap Supply Return) LX 35 V −5 V
40 V for < 100 ns −10 V for < 200 ns

High−Side Driver Output (Top Gate) UG 30 V wrt/GND −0.3 V wrt/LX

15 V wrt/LX −5 V for < 200 ns
40 V for < 100 ns
Low−Side Driver Output (Bottom Gate) LG 15 V −0.3 V
−5 V for < 200 ns

Feedback, VORPM FB, VORPM 6.0 V −0.3 V

COMP/DISB COMP/DISB 5.5 V −0.3 V
PGOOD PGOOD 7V −0.3 V

MAXIMUM RATINGS
Rating Symbol Value Unit
Thermal Resistance, Junction−to−Ambient RqJA 165 °C/W
Thermal Resistance, Junction−to−Case RqJC 45 °C/W
Operating Junction Temperature Range TJ 0 to 150 °C
Operating Ambient Temperature Range TA 0 to 95 °C
Storage Temperature Range Tstg −55 to +150 °C
Moisture Sensitivity Level MSL 1 −
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

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 NCP1589D

ELECTRICAL CHARACTERISTICS (0°C < TA < 95°C; 4.5 V < [BOOT−LX] < 13.2 V, 4.5 V < BOOT < 30 V, 0 V < LX < 21 V,
CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.)

Characteristic Conditions Min Typ Max Unit

VCC Input Voltage Range 4.5 13.2 V
BOOT Voltage Range 13.2 V wrt LX 4.5 30 V
dV/dt on VCC −10 10 V/ms
VREF AND ERROR AMPLIFIER
Reference Voltage Vref 0.8 V
Output Voltage Accuracy Reference and Error Amplifier Excluding −1.0 1.0 %
External Resistive Divider Tolerance
SUPPLY CURRENT
VCC Quiescent Supply Current No Switching, VCC = 13.2 V 2.5 3.8 mA
BOOT Quiescent Current No Switching 0.1 100 mA
UNDERVOLTAGE LOCKOUT
VCC UVLO Threshold VCC Rising 4.4 V
VCC UVLO Threshold VCC Falling 4.0 V
VCC UVLO Hysteresis VCC Rising or VCC Falling 400 mV
SWITCHING REGULATOR
Ramp Slope 0.5 V/ms
Ramp−Amplitude Voltage 1.50 V
Minimum Duty Cycle 0 %
Maximum Duty Cycle 70 83 92 %
LG Minimum on Time 200 350 ns
ERROR AMPLIFIER
Open Loop DC Gain (Note 1) 80 120 dB
Output Source Current Vfb < 0.8 V 2.0 mA
Output Sink Current Vfb > 0.8 V 2.0
Unity Gain Bandwidth (Note 1) 15 MHz
Disable Threshold 0.7 0.8 0.9 V
Output Source Current During Disable 10 40 mA
GATE DRIVERS
Upper Gate Source BOOT − LX = 5 V 1.5 A
Upper Gate Sink BOOT − LX = 5 V 1.8 W
Lower Gate Source VCC = 5 V 1.5 A
Lower Gate Sink VCC = 5 V 1.2 W
UG Falling to LG Rising Delay Tdead1 VCC = 12 V, UG−LX < 1.0 V, LG > 1.0 V 20 30 ns
(Note 1) Only Valid for CCM Operating Mode
LG Falling to UG Rising Delay Tdead2 VCC = 12 V, LG < 1.0 V, UG > 1.0 V 20 30 ns
(Note 1) Only Valid for CCM Operating Mode
UG Internal Resistor to LX Unbiased, BOOT − LX = 0 45 kW
LX Internal Resistor to GND 45 kW
SOFT−START
Soft−Start Time VCC > 4.5 V, COMP w Disable Threshold 2.0 2.6 ms
Enable to Soft−Start Delay (Note 1) VCC > 4.5 V, COMP Rises and Crosses 500 ms
Disable Threshold
1. Guaranteed by design but not tested in production.

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 NCP1589D

ELECTRICAL CHARACTERISTICS (0°C < TA < 95°C; 4.5 V < [BOOT−LX] < 13.2 V, 4.5 V < BOOT < 30 V, 0 V < LX < 21 V,
CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.)

Characteristic Conditions Min Typ Max Unit

POWER GOOD INCLUDING OVP AND UVP THRESHOLD
Output Voltage Logic Low, Sinking 4 mA 0.4 V
Overvoltage until PGOOD goes low 880 902 mV
Undervoltage until PGOOD goes low 698 720 mV
PGOOD High Upper Limit Hysteresis 16 mV
PGOOD High Lower Limit Hysteresis 16 mV
OVP Threshold to Part Disable 950 1000 1030 mV
UVP Threshold to Part Disable 570 600 630 mV
Power Good Delay (Note 1) 1.0 ms
ZERO CURRENT DETECTION (LX Pin)
Zero Current Detection Blank Timer after LX > 50 mV, LG on time 200 250 350 ns
TG < 1.0 V
Capture Time for LX Voltage (Note 1) Time to Capture LX Voltage Once LG is < 40 ns
1.0 V
ZERO CURRENT Vth ADJUSTMENT DETECTION (LX Pin)
Negative LX Detection Voltage Vbdls 200 300 400 mV
Positive LX Detection Voltage Vbdhs 0.2 0.5 1.0 V
Time for Vth Adjustment and Settling Time 300 kHz 3.0 3.7 ms
Zero Current Detection Blank Timer after Blanking Time After LG is < 1.0 V 40 ns
LG < 1.0 V (Note 1)
Initial Negative Current Detection Thresh- LX−GND, Includes $2 mV Offset Range −5.0 −3.0 −1.0 mV
old Voltage Setpoint (Note 1)
Vth Adjustable Range (Note 1) −16 0 15 mV
OVERCURRENT PROTECTION
OC Current Source Sourced from LG pin, before SS 9.5 10 10.5 mA
OCP Programming Time VCC > 4.5 V, Roscset = 60 kW 1.0 5.0 ms
1. Guaranteed by design but not tested in production.

Phase

Ugate to Phase

1V
Lgate

Tdead1 Tdead2

Figure 3. Dead Time Definition

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 NCP1589D

APPLICATIONS INFORMATION

Overcurrent Protection (OCP) from 0 to 2.5 V in 4.2 ms; however if the output capacitors
The NCP1589D monitors the voltage across the low side already has 1.2 V voltage, the NCP1589D will not discharge
MOSFET and used this information to determine if there is the capacitors, instead the soft−start sequence will begin at
excessive output current. The voltage across the low side 1.2 V and then ramp the output up to 2.5 V.
MOSFET is measured from the LX pin when it is conducted,
and is referenced to ground. The overcurrent measurement Power Good
is timed to occur at the end of the low side MOSFET The PGOOD pin is an open drain connection, with an
conduction period. active high output to signal the condition of the converter.
If the voltage drop across the bottom MOSFET exceeds PGOOD is pulled low during soft−start cycle, and if there is
the overcurrent protection threshold, then an internal overvoltage or undervoltage fault. If the voltage on the FB
counter is triggered and incremented. If the voltage drop pin is within ±10% of Vref (800 mV) then the PGOOD pin
does not exceed the threshold for the next cycle, the internal will not be pulled low. The PGOOD pin does not have an
counter will be reset. The NCP1589D will latch the over internal pull-up resistor.
current protection fault condition after 4 consecutive cycles
Overvoltage Protection (OVP)
of overcurrent events. If the voltage on the FB pin exceeds the overvoltage
When the NCP1589D latches an overcurrent protection threshold (1000 mV, 125% of Vref), the NCP1589D will
fault, both the high side and low side MOSFETs are turned latch an overvoltage fault. During an overvoltage fault event
off. To reset the overcurrent protection fault, the power to the the UG pin will be pulled low, and the LG pin will stay high
VCC pin must be cycled. until the voltage on the FB pin goes below Vref/2 (400 mV).
The overcurrent threshold can be set externally, by If the overvoltage fault condition stays, the NCP1589D will
varying the ROCSET resistor shunted from low side gate pin continue drive the LG pin, LG will go high if FB exceeds
to ground. During power on reset, after the VCC and BOOT 1000 mV, then go low when FB is below 400 mV. The power
pins both pass the undervoltage lockout threshold, the of the NCP1589D needs to be cycled up to clear the
NCP1589D will source a 10 mA current from LG pin through overvoltage fault.
the ROCSET resistor and produce a voltage. This voltage will
be sampled and locked by the device as the overcurrent Undervoltage Protection (UVP)
protection threshold. For example, if ROCSET is set to 10 kW, If the voltage on the FB pin falls below the undervoltage
the 10 mA of current will yield a 100 mV threshold, and if threshold after the soft−start cycle completes, then the
the voltage across the low side MOSFET exceeds 100 mV NCP1589D will latch an undervoltage fault. During an
at the end of the its conduction period, an overcurrent event undervoltage fault, both the UG and LG pins will be pulled
will be detected. The OCP threshold is only associated with low. Toggling power or COMP pin will reset the
power on reset, and won’t be wiped out by pulling COMP undervoltage protection unit.
pin down (disabling the part).
If the ROCSET resistor is not present, the overcurrent VORPM (RPM threshold)
protection threshold will max out at 640 mV. The The NCP1589D runs in RPM mode, its switching
recommended range for ROCSET is 5 kW to 60 kW which frequency is controlled by COMP ripple voltage and RPM
yields a threshold voltage range of 50 mV to 600 mV. threshold. The VORPM pin is connected to the output
voltage through an external divider. This voltage value is
Internal Soft−Start proportional to the output voltage and sets the RPM
To prevent excess inrush current during startup, the threshold voltage internally with input voltage information
NCP1589D uses a calibrated current source with an internal obtained through the switch node. The internal RPM
soft−start capacitor to ramp the reference voltage from 0 V threshold voltage (DTH) is a function of both Vout and Vin.
to 800 mV over a period of around 4 ms. The soft−start ramp R9
V out
generator will reset if the input power supply voltages reach DTH + R10)R9
V ramp ) V offset (eq. 1)
V in
the undervoltage lockout threshold, or if the NCP1589D is
disabled by having the COMP pin pulled low. Where R9/R10 (Figure 1) is the input voltage divider of
VORPM pin Vramp is the internal ramp amplitude, Voffset is
Startup into a Precharged Load the offset voltage of the threshold.
During a startup, the NCP1589D will detect the residual Each time when COMP voltage exceeds RPM threshold
charge on the output capacitors. Instead of fully discharging voltage, an internal ramp signal is started and UG is driven
the capacitors, the soft−start will begin from the precharged high. When the internal ramp intercepts with COMP
output voltage level. For example, if the NCP1589D is voltage, the UG pin is reset low. The NCP1589D system
configured to provide a regulated output voltage of 2.5 V, the operates at pseudo-fixed frequency in continuous current
normal soft−start sequence will ramp the output voltage

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 NCP1589D

conduction mode. The output frequency can be determined adaptively to ensure the minimum amount of diode
by the following equation: conduction period to further reduce the converter power
k1 Ramp_slope V out consumption in the light load condition.
F SW + 1

ǒ V
R9
out R10)R9
V
in
Ǔ
V ramp ) V offset
1 ) k2 V in

(eq. 2)
Feedback Voltage
The NCP1589D allows the output voltage to be adjusted
from 0.8 V to 5 V via an external resistor divider network
Where k1, k2 is an internal trimmed value; by default, (R1, R4 in Figure 1). The controller will try to maintain
k1 = 1, k2 = 0, Ramp_slope = 0.5 V/ms, Vramp = 1.5 V, 0.8 V at the FB pin. Thus, if a resistor divider circuit was
Voffset = 20 mV. placed across the feedback pin to Vout, the controller will
regulate the output voltage in proportion to the resistor
Light Load Operation
divider ratio in order to maintain 0.8 V at the FB pin. The
In continuous current conduction mode, the operating relation between the resistor divider network and the output
frequency of the NCP1589D is almost constant. In light voltage is show in the following equation:
load, it runs in a discontinuous current mode with a
scaled-down frequency as a function of the load current. R4 + R1 ǒ V ref
Ǔ
V out * V ref
+ R1 ǒ 0.8 V
V out * 0.8 V
Ǔ (eq. 3)

Internal zero current detection threshold will change

4.4 V
4.0 V

VCC

Internal
UVLO
Fault

1.3 V
COMP

LG

UG

VOUT

0.8 V

FB

PGOOD
POR NORMAL
OCP Soft−Start Time
Programming Time
Figure 4. Typical Startup Sequence

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 NCP1589D

PACKAGE DIMENSIONS

DFN10, 3x3, 0.5P

CASE 485C
ISSUE E
D A NOTES:
L L 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
B 2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL.
L1 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
ALTERNATE A−1 ALTERNATE A−2 THE TERMINALS.

ÇÇÇ
5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG
DETAIL A SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS
E

ÇÇÇ
PIN ONE ALTERNATE TERMINAL ONTO BOTTOM SURFACE OF TERMINAL b.
REFERENCE CONSTRUCTIONS 6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B
ALTERNATE CONSTRUCTION ARE NOT APPLICABLE. WET-

ÇÇÇ
TABLE FLANK CONSTRUCTION IS DETAIL B AS SHOWN ON
2X 0.15 C SIDE VIEW OF PACKAGE.

ÉÉ
ÇÇ ÉÉ
A3 EXPOSED Cu MOLD CMPD MILLIMETERS

ÇÇ ÇÇ
2X 0.15 C DIM MIN MAX
TOP VIEW A 0.80 1.00
A1 0.00 0.05
A1 A3 0.20 REF
DETAIL B (A3) ALTERNATE B−1 ALTERNATE B−2 b 0.18 0.30
0.10 C D 3.00 BSC
DETAIL B D2 2.40 2.60
A ALTERNATE E 3.00 BSC
CONSTRUCTIONS E2 1.70 1.90
10X 0.08 C e 0.50 BSC
SEATING
SIDE VIEW A1 C PLANE A3 K 0.19 TYP
L 0.35 0.45
L1 0.00 0.03
DETAIL A D2
10X L A1
1 5
DETAIL B SOLDERING FOOTPRINT*
WETTABLE FLANK OPTION
CONSTRUCTION
2.64 10X
0.55
PACKAGE
E2 OUTLINE

K 10 6 1.90 3.30
10X b
e
0.10 C A B
0.05 C NOTE 3
BOTTOM VIEW
10X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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