1

Dynamic Logic

Dynamic CMOS Logic

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13
Dynamic Logic  Enhancement-load dynamic shift register (ratioed logic)
Multi-stage pass transistor logic driven by two non-overlapping clocks I1 and I2
level transitions of two clocks
A
Comb. Comb. Comb. do not occur simultaneously
B logic logic logic
I1
I1 I2 I1 I2
C
D
Enhancement-load dynamic shift register (ratioed logic)
I1 I
0Æ0Æ1Æ0 2 1Æ0Æ0Æ0 I1 I2 Issues: weak 0 & weak 1
1Æ0Æ0Æ0 off/on on/off 0Æ0Æ1Æ0
load off/on
NMOS switch Æ ࢝ࢋࢇ࢑૚
Pass on/off 0 weak
1
Vin Tr. 1 driver 0 ࢃ
ሺ ሻ࢒࢕ࢇࢊ
smaller ࡸ
ࢃ Æ ࢂࡻࡸ lower
ሺ ሻ࢙࢏࢔࢑
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3 ࡸ

• ĭ1 active : Vin Ö Cin1, nMOS load off

• ĭ2 active : Pass transistor of 2nd stage on, Cout1 Ö Cin2
Ö nMOS load on, the output of 1st inverter attains its valid logic(Cin1 preserved)
• ĭ1 active : Cout2 is determined and transferred into Cin3
Ö Also, a new input level can be accepted into Cin1
• VOL of each stage is strictly determined by the driver to load ratio (ratioed-dynamic logic)
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 14
Dynamic Logic  Enhancement-load dynamic shift register (ratioless logic)
ratioless logic : I11Æ0Æ0Æ0
1Æ0Æ0Æ0
I20Æ0Æ1Æ0 I11Æ0Æ0Æ0
0Æ0Æ1Æ0
(strong VOL) on weak 1 weak 1
on/off weak 0 off/on on/off
Issues: weak 1 0 0 VDD-VTn
Æstrong 0 weak 1
1 1 0
Vin off

Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

• In each stage, the input pass transistor and the load transistor are driven by the same clock phase
• I1 active : Vin transfer to Cin Ö 1st inverter is active Ö Vout1 attains its valid logic level
• I2 active : 2nd pass transistor on Ö the logic level is transferred onto the next stage
Considering two cases
ˆ Case 1 :
• If VCout1 is high at the end of the active I1 phase
– By mean of VCin1 low input Ö nMOS driver off Ö Vout1=VDD-VTn
• I2 active : The voltage level is transfer to Cin2 via charge sharing over the pass transistor
– Cout/CinĹto correctly transfer a logic-high level ‫ܥ‬௢௨௧ଵ ܸ஼೚ೠ೟భ ൌ ܸ஼೔೙మ (‫ܥ‬௜௡ଶ ൅ ‫ܥ‬௢௨௧ଵ )
஼೚ೠ೟భ
ˆ Case 2 Iˆܸ஼೔೙భ ‹•Š‹‰Š†—”‹‰–Š‡active I1 phaseǡ ‫ݏ݄݊݁ݐ‬I2݅‫݁ݒ݅ݐܿܽݏ‬ǡ ܸ஼೔೙మ ൌ ܸ
஼೔೙మ ା஼೚ೠ೟భ ஼೚ೠ೟భ
• If Vout1 is logic-low at the end of the active I1 phase must make sure ܸ஼೔೙మ ൐ ்ܸ೙
– VCin1 high, nMOS driver on֜Vout1=0V (weak 0)
• As I2 active : Transfer by pass transistor
• Ratioless dynamic logic : VOL=0 (strong 0), independent of driver-to-load ratio
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15
Dynamic Logic General Circuit Structure of Synchronous Dynamic Logic
Ratioed
I1 I2 I1

nMOS nMOS
Logic Logic
Stage 1 Stage 2

Ratioless
I1 I2

nMOS nMOS
Logic Logic
Stage 1 Stage 2

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 16
Dynamic Logic  Single-phase CMOS transmission gate dynamic shift register

CK=1 Æ 0 Æ 1
One-stage shift register

D0
D1

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17
Pseudo n-MOS Logic (ratioed logic) — Basic Circuit Structure
Principle: Example with fan-in equal 5
‹ Use only the pull-down network.

‹ Choose pull-up strength of p-MOS

smaller than pull-down strength of

network is important to ensure
correct operation. ABC  D  E

A
Fd (A, B,....., N) B

A C
Pull-Down
B Network D
x x
x x
x x E
N
Fd (A, B,....., N)

Advantage: Less transistors and lower input capacitance (only one gate cap.).
Disadvantage: High power dissipation(static power for low output) , weak ‘0’
and probably low pull-up speed (for small VOL).
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 18
Dynamic Logic  Pre-charged Logic
‰pseudo-nMOS logic’s main disadvantage was the static current that it consumes.
‹ One way to get rid of it is to build a dual pMOS stack to cut this static

current path (CMOS).

‹ Another approach to eliminate this static current is pre-charging.

‰ What do you mean by pre-charging?

‹ Before each evaluation phase, pre-charge the output high

‹ Execution of Boolean expression either discharges output or leaves it high

• A single low-to-high transition on the input allowed, but NOT a high-to-

low transition during evaluation
The load capacitor has been discharged at the Hi input kevel, and hence the load
capacitor can not be charged back to an Hi level when the input is switched from
Hi to Lo owing to no on-state PMOS path. Non-overlapping
)Precharge (good, but not always poosible)

static Dual pMOS

Network )Precharge precharge
current

)evalute
)evalute
evalute
ISC probably
Pseudo-nMOS CMOS Pre-charge occurs if PDN is on
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19
Dynamic Logic  Pre-charged Logic / NAND2

Dynamic NAND2
VDD
evaluation

evaluation

evaluation
precharge

precharge

precharge
evaluation
precharge

)Precharge ck
out
b
x
a
y a
ck
)evalute

pMOS off b
Æ Positive charges in
pMOS off
the MOSFET channel Æ Charge sharing
run to floating out node
nMOS
out a & b On
ÆOut is
nMOS b on nMOS b discharged
to gnd
Æ Charges on the On Æ
Charge
output node are shared sharing
to the nodes x and y

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 20
Dynamic Logic  Dynamic CMOS vs. Static CMOS
‰ In static circuits at every point in time (except when switching) the
output is connected to either GND or VDD via a low resistance path.
‹ fan-in of N requires 2N devices

‰ Dynamic circuits rely on the temporary storage of signal values on

the capacitance of high impedance nodes.
‹ requires only N + 2 transistors

‹ takes a sequence of precharge and conditional evaluation phases

to realize logic functions

‰ Dynamic circuits operate faster than Conventional static CMOS circuits
(owing to smaller fan-out capacitance)
‹ Conventional static CMOS circuits are intrinsically slow because

each gate must drive both NMOS and PMOS transistors.

‹ Dynamic logic circuits, however, drive only NMOS transistors and

thus have the advantage of faster operation and smaller area

compared to conventional CMOS circuits.
‹ Dynamic logic circuits have been widely used for high-performance

microprocessors and other logic chips.

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21
Dynamic Logic  Properties of Dynamic Gates
‰ Logic function is implemented by the PDN only
‹ number of transistors is N + 2 (versus 2N for static complementary CMOS)
)Precharge
‹ should be smaller in area than static complementary CMOS off
‰ Full swing outputs (VOL = GND and VOH = VDD)
‰ Ratioless ʊ sizing of the devices is not important for proper functioning
(only for performance) )evalute
no Isc

‰ Faster switching speeds VTn<Vin<VDD|VTp|

‹ reduced load capacitance due to lower number of transistors per gate

Dual pMOS
(Cint) so a reduced logical effort (i.e. Cg,gate /Cg,inv) Network
Isc
‹ reduced load capacitance due to smaller fan-out (Cext)
‹ no Isc, so all the current provided by PDN goes into discharging CL
‹ Ignoring the influence of precharge time on the switching speed of the gate,
tpLH = 0 but the presence of the evaluation transistor slows down the tpHL
(because the transistor number n of PDN increases by 1 and the equivalent
RC increases). WpHL v n2
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 22
Dynamic Logic  Properties of Dynamic Gates (Cont’d)

‰ Power dissipation should be better

‹ consumes only dynamic power – no short circuit power consumption
since the pull-up path is not on when evaluating
‹ lower CL- both Cint (since there are fewer transistors connected to the
drain output) and Cext (since the output load is one per connected gate,
not two)
‹ by construction can have at most one transition per cycle – no glitching
‰ But power dissipation can be significantly higher due to
‹ higher transition probabilities (if the output remains at low logic state)
Recurring action : Precharged to high level then evaluated into low level
‹ extra load on CLK
‰ PDN starts to work as soon as the input signals exceed VTn, so set VTH, VIH
and VIL all equal to VTn
‹ low noise margin (NML)
‰ Needs a precharge clock
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23
Dynamic Logic  Precharged Logic (Cont’d)
‰ Implement the logic function with nMOS pull-down stack as in pseudo-nMOS
‰ Can use a single clock signal ) = )pre-charge=)evaluate
0 Æ1 0 Æ1 1Æweak 1 clk
clk1 out1clk2 out2 clk
1 1Æ0
0 0
1 1

‰Once the output of a dynamic gate is discharged, it cannot be charged again

until the next precharge operation.
‰Output can be in the high impedance state during and after evaluation (i.e. PDN
off), the high logic state is stored on CL.
‰These gates cannot be cascaded, even if complementary clocks are used
for alternating stages/clk2=!clk1:
clk1=clk2: out1=Lo during evaluation Æ out2 wrongly discharges owing to a race condition
out1=Hi during precharge Æ out2 always discharges during evaluation if all
 Inputs to the gate can make at most one transition during evaluation. inputs are precharged.
 Constrained by low-to-high transition requirement at the input during evaluation
 A high-to-low transition on the input during evaluation will result in abnormal discharge
of the pre-charged output node. (because the output can not be charged during evaluation)
 Need to put an inverting stage between them o Domino Logic
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 25
Dynamic Logic — Cascading Dynamic Gates

Precharge Evaluate Precharge Evaluate

0 Æ1
V
0 Æ1
) ) 1Æweak 1 )
out1 out2 or even weak 0
in 1Æ0 in

out1 VTn
) ) 'V
out2
t

1o0 Transition at the node out1 results in incorrect discharge at

the node out2 at the onset of evalution

Only 0o1 Transitions allowed at inputs!

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26
Dynamic Logic  Domino Logic
precharged Rise
node monotonically

clk clk
x

This can be any

static CMOS gate
(NAND, NOR, etc.)

‰ During pre-charge:
‹ Output of dynamic stage (X) “pre-charged” high when clk is low

‹ Domino gate output driving input of another always low during pre-charge

‰ During evaluate:
‹ X is conditionally discharged during evaluation
‹ Output of static buffer rises monotonically (remains low or goes from low
to high transition)
‹ Inverting gate can be any inverting static CMOS gate

‹ It is impossible for buffer output to go from H-to-L during evaluation

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 27
Dynamic Domino Logic — Optimizing for Single Edge Circuits
‰ In domino logic circuits, only one edge is significant – the rising edge (i.e. NMOS path
for pre-charged logics)
‰ Can optimize the speed of this edge
" Make nMOS transistor in the inverter much smaller than the pMOS
Æ Lowers the loading on the precharge gate
" If the following gate is not a precharge gate, make the pMOS transistors
in this gate much smaller than the nMOS

larger Smaller
Hi or Lo or
VTH VTH
HiÆLo LoÆHi

" Gate delay can be cut almost in half! (If large >> small)
" But the other edge becomes very slow, so must allow time somewhere
(the delay of the other edge < half a period of the clock)
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28
Dynamic Logic  Domino Chains

)
(clk)

nMOS nMOS nMOS

)
(clk)

‰ Cascaded gates can be switched from PRECHARGE to EVALUATE on the same

clock edge
‹ Logic decisions propagate through the cascade (or chain) like a row of

falling dominos
‰ Length of domino chains is limited by EVALUATE time
‹ Logic must propagate to the output before ) falls

(longest delay : goes from Lo to High transition for every stage)

‰ Inputs to domino stage must be held stable during EVALUATE
(any input changeÆincrease propagation time to the output of the last stage)
‰ Domino gates are ratioless
‰ All domino gates are NONINVERTING (no XOR function)
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 29
Dynamic CMOSņ୏ᄊᡄᒠ႔ϐୢᚒ(I)
1/ႝ಻ख़ཥϩթୢᚒ ; ᒡΕߞဦ‫࣬ॶ؃ܭ‬ՏਔᗋԖᡂ୏Ǵ
ஒёૈ཮Ԗႝ಻ख़ཥϩթୢᚒǴᏤठ‫่݀ॶ؃‬ᒱᇤǶ mix025_1.l
2/ၗ਑ᝡ‫و‬ୢᚒ ; ‫ٿ‬ӕࠠ୏ᄊCMOSႝၡՍௗ ᒡǴஒวғ len_25=0.24u
ᡄᒠ႔໔ၗ਑ᝡ‫و‬ୢᚒǴԶ೷ ԋᒡрႝՏྗՏᒱᇤǶ *first stage
mpclk1 : w=2u l=len_25
¾Nࠠ୏ᄊᡄᒠ႔Ǻ‫࣬ॶ؃‬ՏਔǴᒡрҗႣкϐȶ1’फ़ࣁȶ0’ mna : w=2u l=len_25
ĺΠ΋ભNMOSᒱᇤ‫ܫ‬ႝ mnb : w=1u l=len_25
¾Pࠠ୏ᄊᡄᒠ႔Ǻ‫࣬ॶ؃‬ՏਔǴᒡрҗႣ‫ܫ‬ϐȶ0’ϲࣁȶ1’ mnc : w=1u l=len_25
ĺΠ΋ભPMOSᒱᇤкႝ mnclk1 : w=1u l=len_25
ၗ਑ᝡ‫و‬ୢᚒǴ Y=0 : wrong state! Y1=VDD : weak level! *second stage
A=B=C=1ÆY1=0ÆY=1 ႝ಻ख़ཥϩթୢᚒ mpclk2 : w=2u l=len_25
y mny1 : w=2u l=len_25
mnclk2 : w=1u l=len_25
y1

Y1ᙯᄊ‫ۯ‬
clk ᒨ೷ԋY
I I ᒱᇤ‫ܫ‬ႝ
྽Y1ᒡрࣁc0c Y1 ‘1’ĺ‘0’ Y
C
ਔǴҗ‫ܭ‬வႣ
кࣁc1c‫ܫ‬ႝԿ A ႝ಻
B ‫܌‬ाᡄᒠྗՏ ‘0’ĺ‘1’ ϩ٦
c0cሡਔ໔‫ۯ‬ᒨ
Ǵ೭ஒ٬ࡕ΋ B C
A ભ‫ڙ‬Ԝኩਔc1c ‘0’ ‘0’
ቹៜǴԶр౜
ᒱᇤᡄᒠᒡр
I I

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30
Dynamic Logic — Noise in Domino Logic: Charge Sharing

‰ Domino designs often fail due to charge sharing if internal nodes are not
considered
ƒ Occurs when internal node was low; capacitance divider with output formed
ƒ Reduce charge sharing by reducing capacitance of internal nodes
relative to capacitance of load Cout >> Cx
– High fan-out gates suffer least from charge sharing
ƒ Pre-charge internal nodes where necessary with “secondary pre-charge
devices” (generally, every other node suffices)
CoutVH=(Cout+Cx)Vout
Vout=[Cout/(Cout+Cx)]VH
clk
clk
out
goes to high skew gate (large Vth)
Cout in
in Î erroneous state transition at
x
the high skew gate (next gate)
0 Cx out

Let Cout= Cx x

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 31
Dynamic CMOSņ୏ᄊᡄᒠ႔ϐୢᚒ(II)
3.ᅅႝࢬୢᚒ : Nࠠ୏ᄊCMOS‫࣬ॶ؃ܭ‬Տਔ
ऩᒡрࣁȶ1’Ǵ߾Ԝਔᒡр࿯ᗺࣁੌௗ‫ރ‬ᄊ Leakage Current Problem
ǴԜ࿯ᗺϐ஌ғႝ৒΢‫ޑ‬ႝ಻ஒ཮೸ၸཱུؕ MM0355V.L
len_35=0.35u cval=0.002pf
ᆶ୷݈ϐ஌ғ଍ӛୃᓸΒཱུᡏ‫ޑ‬ᅅႝࢬ‫ܫ‬ႝ mpclk2 : w=2u l=len_35
Ǵ‫ࢂ܈‬࿶җVG=0‫ޑ‬ԛᖏज़ኳԄNMOSFETϐ mny1 : w=2u l=len_35
ᅅႝࢬ‫ܫ‬ႝǶӢԜǴஒёૈ೷ԋᡄᒠᒱᇤǶ mnclk2 : w=1u l=len_35
* ccouple lext y cval
4.ጠӝᚇૻୢᚒ :ΞᆀՍॣ(crosstalk)ୢᚒ * vext lext gnd dc 1 pwl 0 0 7m 0 7.01m 5 7.03m 5 7.04m 0
'VY
CC
'VL ext $ sweep cval poi 3 0.002pf 0.02pf 0.2pf
‫ځ‬ѬᏤጕ Lext CC  C L .end ᅅႝࢬ

ጠӝႝ৒ n+ y
CC p+ n
I ‘1’ well clk
ੌௗᗺ p+
Y ‘1’
CL
n+ a
A ‘0’
n+ ጠӝᚇૻ

n+ y
I ‘1’
n+
Lext
p+

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32
Dynamic CMOSņ୏ᄊᡄᒠ႔ϐୢᚒ(III)

5. ᚇૻխࣝΚ෧Ͽୢᚒ : Nࠠ୏ᄊCMOS‫؃ܭ‬ Input Noise Problem

MM0355V.L
ॶ࣬ՏਔǴऩᒡΕൂӢᚇૻᜢ߯Զҗȶ0’ len_35=0.24u cval=0.002pf
ό҅த‫ޑ‬΢ϲԿVTNа΢Ǵ߾NMOSஒᏤ೯ mpclk2 : w=2u l=len_35
Ԝਔᒡр࿯ᗺϐ஌ғႝ৒΢‫ޑ‬ႝ಻཮‫ܫ‬ႝ mny1 : w=2u l=len_35
mny2 : w=2u l=len_35
Ǵஒёૈ೷ԋᡄᒠᒱᇤǶ mnclk2 : w=1u l=len_35
.end

leakage

I
Y y
ᚇૻ
a
clk

b
‘0’ a

b
I

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 33
Dynamic CMOSņ୏ᄊᡄᒠ႔ϐୢᚒ(IV)
6. ङय़႔ཱུጠӝ(Backgate Coupling) : җ‫୏ܭ‬ᄊᡄᒠ႔ᒡрᆄ‫ੌޑ‬ௗଯߔ‫ރל‬ᄊǴङ
य़႔ཱུႝ৒ጠӝஒᏤठੌௗ࿯ᗺ‫ޑ‬ႝՏफ़եǶ
` Out2 ࿶җM4ႝ඲ᡏ‫ޑ‬CgdᆶCgsႝ৒‫܄‬ጠӝԿOut1Ƕ(see the next page)
Cgs6 Cgd4 VDD
+Q5
Mp Vout1=VCL1 M6 M5 VDD
CLK Cgd6 +Q4
Out1 =1
Cgd4 Out2 =0 +Q + VDD
+Q1 +Q3 Vout2=VCL2
A=0 M1 M4  CL1 Cgs4
CL1 Cgs4 +Q2 CL2

B=0 M2 M3 In charge sharing

+Qout=+Q1+Q2+Q3+Q4+Q5 0
+Q1= CL1VCL1 Vout1=Vout2=VDD M3 offÆonÎVout1=VCL1=VXzVDD
VX +Q2
CLK Me +Q 2 = C (V
gs4 CL1VCL2) +Q 2 =C gs4(0) +Q2=Cgs4(VCL10)
+Q3= Cgd4(VCL1VCL2) M3 off +Q3= Cgd4(0) M3 on +Q3= Cgd4(VCL10) +Q 0
+Q4= Cgd6(VCL1VCL2) +Q4= Cgd6(0) +Q4= Cgd6(VCL10) 1 + +Q3
+Q5= Cgs6(VCL1VDD) +Q5= Cgs6(0) +Q5= Cgs6(VCL10)  CL1
Dynamic NAND Static NAND
୷‫ܭ‬ႝ಻όྐǴ +Q =+Q1+Q2+Q3+Q4+Q5
Domino Architecture Q Q  Q  Q  Q out
M3 off : VCL2 = VCL1 = VDD ; 1 2 3 4  Q5
VCgs4 = VCgd4 = VCgd6 = VCgs6 = 0
C L1VDD (CL1  C gs 4  C gd 4  C gd 6 )V X  C gs6 (V X  VDD )
M3 offÆon : VCL2 = 0; (C L1  C gs6 )VDD (C L1  C gs 4  C gd 4  C gd 6  C gs6 )V X
VCL1 = VCgs4 = VCgd4 = VCgd6 = VX ; C L1 C gs6
VCgs6 = VX  VDD VX VDD C L1>> Cgs4+Cgd4+Cgd6+CCgs6
C L1 C gs 4  C gd 4  C gd 6 C gs6 Î VX | VDD
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34
Dynamic CMOSņ Backgate Coupling Effect

Mp off Æ charge sharing

2
Out1
1 CLK

0 Out2
In

-1
0 2 Time, ns 4 6

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 36
Dynamic Logic — Noise in Domino: Coupling and Gnd Bounce
Supply Coupling Bounce
High-skew gate means
Coupling the gate has a high Vth

high skew gate Smaller VTH

larger
Hi or VTH Lo or
clk clk HiÆLo LoÆHi clk
1 0

0 1 1
1
0

Vt I

ௗூ
Vgndൌ ‫ܮ‬ ൅ ‫ܴܫ‬
ௗ௧
Clocked nMOS and pMOS Clocked nMOS and pMOS
Ground Bounce
are ON simultaneously are ON simultaneously

‰ The output of a domino gate is a dynamic node

‰ Coupling on the dynamic node can cause the static gate to glitch
‰ Input glitches can discharge dynamic node
ƒ Portion of glitch > Vt is important
‰ Ground bounce can cause a glitch or turn on the nMOS pull down
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37
Domino Dynamic CMOSņମจԄ୏ᄊᡄᒠ႔
ှ،നեπբᓎ౗ज़‫ڋ‬Ϸႝ಻ख़ཥϩթୢᚒϐႝၡ

I I W/Lλ W/Lλ
I I \
I1 W/Lλ

A NN A NN
ᒡ A A A
ࠠࠠ ࠠࠠ ᒡ NN ᒡ NN NN
Ε ᒡ
ࠠࠠ ࠠࠠ ࠠࠠ
B
୵ C ᆛ
ᆛ B C ᆛ
ᆛ Ε Ε Ε
ၡၡ ၡၡ B
୵ C ᆛ
ᆛ B
୵ C ᆛ
ᆛ B
୵ C ᆛ
ᆛ
ၡၡ ၡၡ ၡၡ
I I
I I I
ዴߥҗႣк຾Ε‫࣬ॶ؃‬ՏਔǴᒡрό཮ ှ،ႝ಻ख़ཥ
Ԗȶ1’ᙯȶ0’ϐኩᄊ౜ຝǴԶ٬Π΋ભౢғϩթୢᚒϐႝၡ ෧ϿਔેߞဦॄၩϐБ‫ݤ‬
ႝ಻ख़ཥϩթ‫ޔ܈‬ௗ‫ܫ‬ႝǴ຾ԶᏤठᒱ
ᇤᡄᒠǶ I I I I I I
ମจԄ୏ᄊᡄᒠ႔ϐલᗺǺ
1.‫؂‬΋ঁମจԄ୏ᄊᡄᒠ႔ભ֡ࣁ҅ӛ
ᡄᒠǴ຾ՉᡄᒠӝԋਔǴѝૈஒϸӛ A ӭ A NN A NN A NN A NN
ٰମ ٰମ
ᡄᒠ‫ܫ‬࿼ӧ᏾ᡏႝၡϐᒡΕᆄ‫܈‬ᒡр ख़ ࠠࠠ Ծจ ࠠࠠ ࠠࠠ Ծจ ࠠࠠ
ᆄǴ೭཮ቹៜႝၡᡄᒠϐന٫ϯ௃‫ ׎‬B C Ⴃ B Cᆛᆛ ‫ځ‬ԄB Cᆛᆛ B Cᆛᆛ ‫ځ‬ԄB Cᆛᆛ
Ƕ к ၡၡ Ѭ႔ ၡၡ ၡၡ Ѭ႔ ၡၡ
2.୏ᄊᡄᒠ႔ભϐനեπբᓎ౗ज़‫(ڋ‬ᒡ
I I I
р࿯ᗺੌௗਔϐᒱᇤ୏բ)Ϸႝ಻ख़ཥ
ϩթୢᚒϝฅӸӧǶ
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 38
Dynamic Logic — NORA (Zipper) Domino
‰ NORA (NO-RAce) or Zipper Domino – fast b/c all dynamic
‰ Extremely noise sensitive: trips if output drops by a threshold
ƒ This includes power supply bounce between gates
ƒ Problem is that you have a noisy output connected to a noise sensitive input
‰ Tried on DEC J11 and AT&T’s “CRISP” microprocessor, but both chips failed
on first silicon
N-BlockᆶP-BlockҬᒱ‫୏ޑ‬ᄊᡄᒠՍௗࢎᄬǴӧྗഢ໘ࢤǴN-BlockᆶP-Blockᒡрϩձ೏Ⴃкႝ‫ډ‬VDDᆶႣ‫ܫ‬ႝ‫ډ‬GNDǶӧ຾Εຑ՗໘ࢤ‫߃ޑ‬
යǴN-Block‫ޑ‬ᒡΕࣁ߻΋ભP-BlockᒡрႣ‫ܫ‬ႝ‫ޑ‬GNDЪP-Block‫ޑ‬ᒡΕࣁ߻΋ભN-BlockᒡрႣкႝ‫ޑ‬VDDǶ‫܌‬аǴଷ೛ಃ΋ભࣁN-Block‫ޑ‬
୏ᄊᡄᒠǴ‫ځ‬ᒡΕߞဦऩஒ٬N-BlockᏤ೯Ǵ٬ளᒡр‫ܫ‬ႝᙯᄊࣁ0VǶԜեྗՏௗ‫ډ‬Π΋ભ‫ޑ‬P-Block୏ᄊᡄᒠ‫ޑ‬ᒡΕǴஒёૈ٬ளP-BlockᏤ
೯Ǵᒡр೏кႝ‫ډ‬VDDǶаԜᜪ௢ǴಃΒભ໒‫؂ޑۈ‬΋ભӧຑ՗໘ࢤਔǴѸ໪฻߻΋ભᒡрԖౢғᙯᄊǴѬԾρ‫ޑ‬ᒡрωૈԖᙯᄊᐒ཮ǶӢ
ԜǴᜪ՟߻य़ග‫ޑډ‬ȃ-BlockᆶϸӛᏔᄬԋ‫ޑ‬domino logicϐՍௗࢎᄬ΋ኬǴ‫؂‬΋ભ‫ޑ‬ᒡрᙯᄊѸ໪฻߻΋ભ‫ޑ‬ᒡрวғᙯᄊǴωԖᙯᄊᐒ཮Ƕ
(ᜪ՟வଆ‫ۈ‬ମจ໒‫ۈ‬٩‫ׇ‬௢ॹΠ΋ঁମจ)
NORA (NO-RAce) Replace static gate with P-Block of pre-discharged logic
clk clk clk
ёаགྷႽԋǴNORA
Dominoࢂஒচٰ‫ޑ‬ Evaluation: A high-to-low transition
Domino logicϐᓉᄊ on the input during
Hi or HiÆLo evaluation will result in
ϸӛᏔඤԋP-Block abnormal discharge of the
୏ᄊᡄᒠǶ pre-discharged output node.
A high-to-low transition A Lo-to-high transition
on the input during on the input during
evaluation will result in evaluation will result in
Evaluation:
abnormal discharge of the abnormal discharge of the Lo or LoÆHi
pre-discharged output node. pre-discharged output
node.
N-Block P-Block N-Block
Clk=0: pre-charge output to Hi pre-discharge output to Lo pre-charge output to Hi
Clk=1: evaluation; Hi or HiÆLo evaluation; Lo or LoÆHi evaluation; Hi or HiÆLo
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Dynamic Logic — NORA (NO-Race) Domino / Pipeline
I storage I inverter
NORA CMOS I-section I  inverter NORA CMOS I-section I storage
I preparation I evaluation
I evaluation I preparation
I I I I

A N A N I A N A N I
nMOS pMOS nMOS pMOS
Input

Input

ࠠ ࠠ ࠠ ࠠ
logic logic logic logic
B Cᆛ B Cᆛ I B Cᆛ B Cᆛ I
ၡ ၡ ၡ ၡ

I I I I

C2MOS Latch C2MOS Latch

Pipeline NORA CMOS
I I

I-section I-section I-section

OR I I

I-section CMOS
Latch
I-section CMOS
Latch
I-section
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 40
Dynamic Logic — NORA (NO-Race) Domino / Pipeline NORA CMOS
I preparation; I evaluation; I evaluation; I preparation;
M1A off, M1B on M(N+1)B on MNA off,
I evaluation I preparation I preparation I evaluation
M1A on, M1B off M(N+1)B off MNA on,
I I I I
IN I I I I I OUT
M1B yyy
section M1A section section section M(N1)B section MNA
OR I I I I
IN I CMOS I CMOS I I CMOS I CMOS OUT
yyy
section Latch section Latch section section Latch section Latch

ჹ‫ܭ‬வINᒡΕ‫ޑ‬Սӈၗ਑(‫ٯ‬ӵ: a1 , a2 , a3 , a4 , a5 , a6 , …)Զ‫ق‬Ǵ
(1)clkે‫ݢ‬Ս‫ޑ‬ಃ΋ঁຼයે‫ݢ‬җ0ᡂ1 (I=0Æ1)ਔǴI-sectionࣁຑ՗໘ࢤǴa1 ໺ᒡ‫ډ‬M1A ໒ᜢ‫ޑ‬ᒡрǶ
(2)clkે‫ݢ‬Ս‫ޑ‬ಃΒঁຼයϐॄъ‫(ڬ‬I=0)ǴIത -sectionࣁຑ՗໘ࢤǴ a1 ໺ᒡ‫ډ‬M1B໒ᜢ‫ޑ‬ᒡрǶ྽Iҗ0ᡂ1ਔǴI-
sectionࣁຑ՗໘ࢤǴa2໺ᒡ‫ډ‬M1A ໒ᜢ‫ޑ‬ᒡрǴӕਔ a1໺ᒡ‫ډ‬M2A ໒ᜢ‫ޑ‬ᒡрǶ
(3)clkે‫ݢ‬Ս‫ޑ‬ಃΟঁຼයϐॄъ‫(ڬ‬I=0)ǴIത -sectionࣁຑ՗໘ࢤǴ a2 ໺ᒡ‫ډ‬M1B໒ᜢ‫ޑ‬ᒡрǴӕਔ a1໺ᒡ‫ډ‬M2B໒
ᜢ‫ޑ‬ᒡрǶ྽Iҗ0ᡂ1ਔǴI-sectionࣁຑ՗໘ࢤǴa3໺ᒡ‫ډ‬M1A ໒ᜢ‫ޑ‬ᒡрǴӕਔ a2໺ᒡ‫ډ‬M2A ໒ᜢ‫ޑ‬ᒡрЪa1
ჹ‫ܭ‬΋ঁӭભ୏ᄊᡄᒠ‫س‬಍ӧ຾ՉՍӈၗ਑‫ޑ‬໺ᒡԶ‫ق‬Ǵऩ‫ޔ‬ௗ೸ၸൂ΋ঁOPSBՍௗࢎᄬ໺ᒡǴҗ‫ܭ‬ӧຑ՗໘ࢤਔǴऩ୏
໺ᒡ‫ډ‬M3A ໒ᜢ‫ޑ‬ᒡрǶᄊᡄᒠ‫ޑ‬ᒡр཮Ԗᙯᄊ‫ޑ‬௃‫ݩ‬Ǵஒёૈ཮ࢂᜪ՟ମจ௢ॹ౜ຝǴவ߻य़ભ໒‫ۈ‬۳ࡕ೴ભ຾Չᒡрᙯᄊ‫୏ޑ‬բǴᏤठࡕय़‫ޑ‬
…………………………………………………………………………………………………………..
΋٤ભ‫ޑ‬ᙯᄊ୏բค‫ݤ‬ӧຑ՗໘ࢤ຾Չ҅த‫ޑ‬ᙯᄊǴ൩೏ॐ຾Εྗഢ໘ࢤǶᙖҗ೭ᅿqjqfmjofࢎᄬǴ‫؂‬΋ঁၗ਑Ǵ‫؂ܭ‬΋
ঁਔેъ‫ڬ‬යѝ཮໺ᒡ΋ঁtfdujpoϷ‫ځ‬ᒡр໒ᜢǴѝाtd,section+td,sw<tevaluationǴၗ਑൩ё҅ዴ۳‫س‬಍ᒡрᆄ໺ᒡǶ
(N)clkે‫ݢ‬Ս‫ޑ‬ಃNঁຼයϐॄъ‫(ڬ‬I=0)ǴIത -sectionࣁຑ՗໘ࢤǴ aN1໺ᒡ‫ډ‬M1B໒ᜢ‫ޑ‬ᒡрǴЪak໺ᒡ‫ډ‬M(Nk)B
໒ᜢ‫ޑ‬ᒡрǴk=1~N1Ǵa1ς໺ᒡ‫ډ‬M(N1)B໒ᜢ‫ޑ‬ᒡрǶ྽Iҗ0ᡂ1ਔǴI-sectionࣁຑ՗໘ࢤǴaN໺ᒡ‫ډ‬M1A ໒
ᜢ‫ޑ‬ᒡрǴЪak໺ᒡ‫ډ‬M(N+1k)A ໒ᜢ‫ޑ‬ᒡрǴ k=1~N1Ǵa1ς໺ᒡ‫ډ‬MNA ໒ᜢ‫ޑ‬ᒡрǴΨ൩ࢂOUTǶ
ஒ᏾ᡏႝၡϩԋNࢤǴ೸ၸ໒ᜢ‫ޑ‬௓‫ڋ‬Ϸ୏ᄊੌௗ࿯ᗺ‫ޑ‬ኩӸᐒ‫ڋ‬Ǵ٬‫؂‬΋ঁၗ਑࿶җN-1ঁਔેຼය‫ޑ‬໺ᒡǴӧ
ಃNঁຼය‫ډ‬ၲOUTǴΨ൩ࢂᇥǴவଆ‫ۈ‬ਔ໔‫ډ‬NঁຼයࡕǴ‫ঁ؂‬ਔેຼය൩཮Ԗ΋ঁՍӈၗ਑٩‫ׇ‬வOUT໺рǶ
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Dynamic Logic — Zipper Domino

\1 I \1 I

A N A N A N A N
ᒡ
nMOS
ࠠ pMOS
ࠠ nMOS
ࠠ pMOS
ࠠ
Ε
logic logic logic logic
B
୵ Cᆛ B Cᆛ B Cᆛ B Cᆛ
ၡ ၡ ၡ ၡ

I \2 I \2

VDD I
VDD-|VT,p| To improve
\1 • Charge leakage
• Charge sharing

\2
VT, n
0
I
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 42
Dynamic Logic — Dual-Rail Logic

‰ The reason the maximum overhead is 2x for monotonic gates is, in the worst case, you
need to compute the true and complement for each logic function, since some future
function might need both the true and complement outputs of this function.
‰ Rather than building two separate gates for generating x and x you can use one merged
gate. This gate is similar to a switch network that routes gnd to either out or !out.

a ˜b  a ˜b
a ˜b  a ˜b

XNOR XOR

X a ˜b  a ˜b
X a ˜b  a ˜b

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Dynamic Logic — Dual Rail Constraint
a AND b
‰ In a dual-rail gate you need to implement the function F and !F
a
" You have as inputs ai and !ai b 0 1
" So you end up building !F, using !ai, and it is the dual of F 0 0 0
• Dual implies parallel devices becomes series
1 0 1
• Implies all dual rail gates have series structures
• Can’t build large fan-in dual rail gate!
a
b 1 0
1 1 1
0 1 0
a ˜b
{

AND: X
OR: Y a ˜b ab a OR b
a
NAND: X a ˜b b 0 1
NOR: Y a ˜b ab 0 0 1
b b 1 1 1

‰ Most gates don’t share as many transistors as the EXOR gate.

AND / OR gates don’t really share any transistors.
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 44
Dynamic Logic — Using Parallel Logic
‰ Could make the logic pre-discharge the output to zero, and then selectively pull
the output up too. In this case, the logic transistors would be pMOS devices:
‰ In this case, the pMOS stack is evaluated
on )2, and predischarge the output on )1.
‰ Since pMOS devices are slower than
nMOS, the nMOS style precharged logic
block is usually preferred instead of this
style, but both will work.

‰ The good precharge gates to build (with parallel transistors) are:

‰ These functions use parallel transistors

instead of series stacks.
‰ For NAND gates using nMOS
evaluation transistors you must
unfortunately still use series
evaluation transistors:
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Dynamic Logic — 0/1 Detection Circuit
Detect whether the values of all bits are equal to the value of the ref signal.
For example, ref=0, A=1, B=C=D=0
VDD
n out
ref A B C D

clk

[D C B A]=S[3:0]
In pre-charge phase,
The node n is precharged to have a high voltage level.
In evaluation phase,
y i[0:3], S[i] = ref Î there exists no path from node n to ground
Î n=1, and out=0
y i[0:3], S[i] z ref Î there exists at least a path from node n to ground
Î n=0, and out=1
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