Resistor Transistor Logic
Resistor Transistor Logic
Resistor Transistor Logic
Operation
1. When the transistor operates in saturation region, maximum current
flows through the resistor R3. The output voltage VQ is logic 0 level
voltage.
2. When the transistor operates in cut-off, no current flows through resistor
R3 and the output voltage VQ = +5V; it is logic 1 level voltage.
3. When both the inputs are in logic 0, transistors T 1 and T2 operates in cut-
off region and the output is VQ = +5V (logic 1).
4. When any one of the inputs is at logic 1 level, the corresponding
transistor operates in saturation, and the output is VY = 0.2V (logic 0).
5. When both the inputs are at logic 1 level, both the transistors operate in
saturation and the output is VY = 0.2V (logic 0).
VA VB Transistor T1 Transistor T2 VQ
0 0 Cut-off Cut-off 1
0 1 Cut-off Saturation 0
1 0 Saturation Cut-off 0
1 1 Saturation Saturation 0
Operation of RTL NOR Gate
VA VB VQ
0 0 1
0 1 0
1 0 0
1 1 0
Operation of NoR Gate
Drawbacks
1. Low noise margin
2. Fan out is poor
3. Propagation delay is high and the speed of operation is low
4. High power dissipation
It works like this. The diodes marked D1 and D2, together with resistor
R1, form a two-input AND function. At the input to D3, logic 0 is represented
by approximately 0.7 V, while logic 1 is in the range 4 to 5 V. D3 increases the
voltage required to turn on the transistor. This gives a better separation between
the voltage levels recognized as a logic 0 and logic 1.
For the transistor to conduct, D3 must be turned on. This happens when
the anode voltage reaches 1.4 V. If the voltage at the anode is much higher than
this, the base will be driven to a high voltage. The transistor will be strongly
turned on, with low resistance, and thus F will be discharged toward 0 V. If the
anode is at a low voltage, the base will also be low. This keeps the transistor
off (essentially infinite resistance), allowing the output node to reach a logic 1
voltage level.
Gates constructed in this circuit have a limit to the number of gate inputs
to which their output can be connected. This is called fan-out. The pull-up
resistor R2 is what limits the fan-out. The output F is at +Vcc as long as no
current is being drawn from the power supply to charge electrical nodes to
which F is connected. However, if F is connected to the A or B input of a
similar gate, current is drawn through R2. The voltage at F is reduced according
to Ohm's law. If there are too many connections drawing current, the voltage
at F may be so reduced that it can no longer be recognized as logic 1. Thus, the
number of fan-outs must be carefully limited in this kind of logic.
A B F
0 0 1
0 1 1
1 0 1
1 1 0
Operation of NAND Gate
Advantages
1. Fan out is high
2. Power dissipation is 8 – 12 mW
3. Noise immunity is good
Disadvantages
1. More elements are required
2. Propagation delay is more.
3. Speed of operation is less