SEMICONDUCTOR TECHNICAL DATA

 
 
  

  

  

 
  

High–Performance Silicon–Gate CMOS

The MC54/74HC4051A, MC74HC4052A and MC54/74HC4053A utilize
silicon–gate CMOS technology to achieve fast propagation delays, low ON
resistances, and low OFF leakage currents. These analog multiplexers/ J SUFFIX
demultiplexers control analog voltages that may vary across the complete CERAMIC PACKAGE
16 CASE 620–10
power supply range (from VCC to VEE).
The HC4051A, HC4052A and HC4053A are identical in pinout to the 1
metal–gate MC14051AB, MC14052AB and MC14053AB. The Channel–Se- N SUFFIX
lect inputs determine which one of the Analog Inputs/Outputs is to be 16 PLASTIC PACKAGE
connected, by means of an analog switch, to the Common Output/Input. CASE 648–08
1
When the Enable pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard D SUFFIX
CMOS outputs; with pullup resistors they are compatible with LSTTL 16 SOIC PACKAGE
outputs. 1 CASE 751B–05
These devices have been designed so that the ON resistance (Ron) is
DW SUFFIX
more linear over input voltage than R on of metal–gate CMOS analog 16 SOIC WIDE PACKAGE
switches.
1 CASE 751G–02
For a multiplexer/demultiplexer with channel–select latches, see
HC4351A. DT SUFFIX
16
• Fast Switching and Propagation Speeds TSSOP PACKAGE
1
• Low Crosstalk Between Switches CASE 948F–01
• Diode Protection on All Inputs/Outputs ORDERING INFORMATION
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V MC54HCXXXXAJ Ceramic
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V MC74HCXXXXAN Plastic
• Improved Linearity and Lower ON Resistance Than Metal–Gate MC74HCXXXXAD SOIC
Counterparts MC74HCXXXXADW SOIC Wide
• Low Noise MC74HCXXXXADT TSSOP
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates FUNCTION TABLE – MC54/74HC4051A
HC4052A — 168 FETs or 42 Equivalent Gates Control Inputs
HC4053A — 156 FETs or 39 Equivalent Gates
Select
LOGIC DIAGRAM Enable C B A ON Channels
MC54/74HC4051A L L L L X0
Single–Pole, 8–Position Plus Common Off L L L H X1
L L H L X2
13 L L H H X3
X0
14 L H L L X4
X1 L H L H X5
15 3 COMMON
X2 X L H H L X6
ANALOG 12 OUTPUT/
INPUTS/ X3 MULTIPLEXER/ INPUT L H H H X7
OUTPUTS X4 1 DEMULTIPLEXER H X X X NONE
5 X = Don’t Care
X5
2 Pinout: MC54/74HC4051A (Top View)
X6
4 VCC X2 X1 X0 X3 A B C
X7
11 16 15 14 13 12 11 10 9
A
CHANNEL 10
SELECT B
INPUTS 9
C
6
ENABLE
PIN 16 = VCC
PIN 7 = VEE 1 2 3 4 5 6 7 8
PIN 8 = GND
X4 X6 X X7 X5 Enable VEE GND
This document contains information on a new product. Specifications and information herein are subject to
change without notice.

10/97

 Motorola, Inc. 1997 1 REV 0

Free Datasheet http://www.Datasheet4U.com

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

FUNCTION TABLE – MC74HC4052A

LOGIC DIAGRAM Control Inputs
MC74HC4052A
Double–Pole, 4–Position Plus Common Off Select
Enable B A ON Channels
12
X0 L L L Y0 X0
14
X1 13 L L H Y1 X1
15 X SWITCH X
X2 L H L Y2 X2
11 L H H Y3 X3
X3
ANALOG COMMON H X X NONE
INPUTS/OUTPUTS 1 OUTPUTS/INPUTS
Y0 X = Don’t Care
5 3
Y1 Y SWITCH Y
2
Y2
4
Y3 Pinout: MC74HC4052A (Top View)
10
CHANNEL-SELECT A VCC X2 X1 X X0 X3 A B
9 PIN 16 = VCC
INPUTS B
PIN 7 = VEE 16 15 14 13 12 11 10 9
PIN 8 = GND
6
ENABLE

1 2 3 4 5 6 7 8
Y0 Y2 Y Y3 Y1 Enable VEE GND

FUNCTION TABLE – MC54/74HC4053A

Control Inputs
LOGIC DIAGRAM
MC54/74HC4053A Select
Triple Single–Pole, Double–Position Plus Common Off Enable C B A ON Channels
L L L L Z0 Y0 X0
12 L L L H Z0 Y0 X1
X0 14
13 X SWITCH X L L H L Z0 Y1 X0
X1 L L H H Z0 Y1 X1
L H L L Z1 Y0 X0
2 L H L H Z1 Y0 X1
Y0 15 COMMON
ANALOG 1 Y SWITCH Y L H H L Z1 Y1 X0
INPUTS/OUTPUTS Y1 OUTPUTS/INPUTS
L H H H Z1 Y1 X1
H X X X NONE
5
Z0 4
3 Z SWITCH Z X = Don’t Care
Z1
11
A
CHANNEL-SELECT 10 PIN 16 = VCC
INPUTS B
9 PIN 7 = VEE Pinout: MC54/74HC4053A (Top View)
C PIN 8 = GND
6 VCC Y X X1 X0 A B C
ENABLE
16 15 14 13 12 11 10 9
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch

1 2 3 4 5 6 7 8
Y1 Y0 Z1 Z Z0 Enable VEE GND

MOTOROLA 2 High–Speed CMOS Logic Data

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
 MC54/74HC4051A MC74HC4052A MC54/74HC4053A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit This device contains protection

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
VCC
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Positive DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
(Referenced to GND)
(Referenced to VEE)
– 0.5 to + 7.0
– 0.5 to + 14.0
V circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
VEE
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIS ÎÎÎ
Negative DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ
ÎÎÎ
Analog Input Voltage
– 7.0 to + 5.0
VEE – 0.5 to
V
V
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VCC + 0.5
cuit. For proper operation, Vin and

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout should be constrained to the
v
range GND (Vin or Vout) VCC. v

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
I DC Current, Into or Out of Any Pin ± 25 mA Unused inputs must always be

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW tied to an appropriate logic voltage
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TSSOP Package† 450 Unused outputs must be left open.

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature Range – 65 to + 150 _C

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP
260
300
_C

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_ C from 65_ to 125_ C
Ceramic DIP: – 10 mW/_ C from 100_ to 125_ C
SOIC Package: – 7 mW/_ C from 65_ to 125_ C
TSSOP Package: – 6.1 mW/_ C from 65_ to 125_ C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Referenced to VEE) 2.0 12.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage, Output (Referenced to – 6.0 GND V
GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin ÎÎÎ
ÎÎÎ ÎÎÎ
Analog Input Voltage

ÎÎÎ
ÎÎÎ
Digital Input Voltage (Referenced to GND)
VEE
GND
VCC
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIO*

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA ÎÎÎ
ÎÎÎ ÎÎÎ
Static or Dynamic Voltage Across Switch

ÎÎÎ
ÎÎÎ
Operating Temperature Range, All Package Types – 55
1.2
+ 125
V
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Input Rise/Fall Time

ÎÎÎ
ÎÎÎ
(Channel Select or Enable Inputs)
VCC = 2.0 V
VCC = 3.0 V
0
0
1000
600
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
* For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

High–Speed CMOS Logic Data 3 MOTOROLA

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
MC54/74HC4051A MC74HC4052A MC54/74HC4053A

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Guaranteed Limit
VCC
S b l
Symbol P
Parameter C di i
Condition V –55 to 25°C ≤85°C ≤125°C U i
Unit
VIH Minimum High–Level Input Voltage, Ron = Per Spec 2.0 1.50 1.50 1.50 V
Channel–Select or Enable Inputs 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Voltage, Ron = Per Spec 2.0 0.5 0.5 0.5 V
Channel–Select or Enable Inputs 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
Iin Maximum Input Leakage Current, Vin = VCC or GND, 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Channel–Select or Enable Inputs VEE = – 6.0 V
ICC Maximum Quiescent Supply Channel Select, Enable and µA
Current (per Package) VIS = VCC or GND; VEE = GND 6.0 1 10 20
VIO = 0 V VEE = – 6.0 6.0 4 40 80
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

DC CHARACTERISTICS — Analog Section

Guaranteed Limit
S b l
Symbol P
Parameter C di i
Condition VCC VEE –55 to 25°C ≤85°C ≤125°C U i
Unit
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to 4.5 0.0 190 240 280 Ω
VEE; IS ≤ 2.0 mA 4.5 – 4.5 120 150 170
(Figures 1, 2) 6.0 – 6.0 100 125 140
Vin = VIL or VIH; VIS = VCC or 4.5 0.0 150 190 230
VEE (Endpoints); IS ≤ 2.0 mA 4.5 – 4.5 100 125 140
(Figures 1, 2) 6.0 – 6.0 80 100 115
∆Ron Maximum Difference in “ON” Vin = VIL or VIH; 4.5 0.0 30 35 40 Ω
Resistance Between Any Two VIS = 1/2 (VCC – VEE); 4.5 – 4.5 12 15 18
Channels in the Same Package IS ≤ 2.0 mA 6.0 – 6.0 10 12 14
Ioff Maximum Off–Channel Leakage Vin = VIL or VIH; µA
Current, Any One Channel VIO = VCC – VEE; 6.0 – 6.0 0.1 0.5 1.0
Switch Off (Figure 3)
Maximum Off–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0
Leakage Current, HC4052A VIO = VCC – VEE; 6.0 – 6.0 0.1 1.0 2.0
Common Channel HC4053A Switch Off (Figure 4) 6.0 – 6.0 0.1 1.0 2.0
Ion Maximum On–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0 µA
Leakage Current, HC4052A Switch–to–Switch = 6.0 – 6.0 0.1 1.0 2.0
Channel–to–Channel HC4053A VCC – VEE; (Figure 5) 6.0 – 6.0 0.1 1.0 2.0

MOTOROLA 4 High–Speed CMOS Logic Data

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
 MC54/74HC4051A MC74HC4052A MC54/74HC4053A

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
S b l
Symbol P
Parameter V –55 to 25°C ≤85°C ≤125°C U i
Unit
tPLH, Maximum Propagation Delay, Channel–Select to Analog Output 2.0 370 465 550 ns
tPHL (Figure 9) 4.5 74 93 110
6.0 63 79 94
tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 60 75 90 ns
tPHL (Figure 10) 4.5 12 15 18
6.0 10 13 15
tPLZ, Maximum Propagation Delay, Enable to Analog Output 2.0 290 364 430 ns
tPHZ (Figure 11) 4.5 58 73 86
6.0 49 62 73
tPZL, Maximum Propagation Delay, Enable to Analog Output 2.0 345 435 515 ns
tPZH (Figure 11) 4.5 69 87 103
6.0 59 74 87
Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: HC4051A 130 130 130
HC4052A 80 80 80
HC4053A 50 50 50
Feedthrough 1.0 1.0 1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD P
Power Di
Dissipation
i i C Capacitance
i (Fi
(Figure 13)* HC4051A 45 pF
F
HC4052A 80
HC4053A 45
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 5 MOTOROLA

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
MC54/74HC4051A MC74HC4052A MC54/74HC4053A

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Limit*
VCC VEE
S b l
Symbol P
Parameter C di i
Condition V V 25°C U i
Unit
BW Maximum On–Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage to ‘51 ‘52 ‘53 MHz
or Minimum Frequency Response Obtain 0dBm at VOS; Increase fini Frequency 2.25
2 25 –2.25 80 95 120
(Figure 6) Until dB Meter Reads –3dB;
4.50 –4.50 80 95 120
RL = 50Ω, CL = 10pF
6.00 –6.00 80 95 120
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to Obtain 2.25 –2.25 –50 dB
(Figure 7) 0dBm at VIS 4.50 –4.50 –50
fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –40
4.50 –4.50 –40
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –40
— Feedthrough Noise. Vin ≤ 1MHz Square Wave (tr = tf = 6ns); 2.25 –2.25 25 mVPP
Channel–Select Input to Common Adjust RL at Setup so that IS = 0A; 4.50 –4.50 105
I/O (Figure 8) Enable = GND RL = 600Ω, CL = 50pF 6.00 –6.00 135
2.25 –2.25 35
4.50 –4.50 145
RL = 10kΩ, CL = 10pF 6.00 –6.00 190
— Crosstalk Between Any Two fin = Sine Wave; Adjust fin Voltage to Obtain 2.25 –2.25 –50 dB
Switches (Figure 12) 0dBm at VIS 4.50 –4.50 –50
(Test does not apply to HC4051A) fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –60
4.50 –4.50 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –60
THD Total Harmonic Distortion fin = 1kHz, RL = 10kΩ, CL = 50pF %
(Figure 14) THD = THDmeasured – THDsource
VIS = 4.0VPP sine wave 2.25 –2.25 0.10
VIS = 8.0VPP sine wave 4.50 –4.50 0.08
VIS = 11.0VPP sine wave 6.00 –6.00 0.05
* Limits not tested. Determined by design and verified by qualification.

MOTOROLA 6 High–Speed CMOS Logic Data

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
 MC54/74HC4051A MC74HC4052A MC54/74HC4053A

250 100 125°C

Ron , ON RESISTANCE (OHMS)

Ron , ON RESISTANCE (OHMS)

200 80
25°C
125°C
150 25°C 60
TBD TBD
100 40 – 55°C

– 55°C
50 20

0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 4.5 V

105
75
Ron , ON RESISTANCE (OHMS)

125°C Ron , ON RESISTANCE (OHMS) 125°C

90
60
75 25°C 25°C

60 45
TBD TBD
45 – 55°C – 55°C
30
30
15
15

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1c. Typical On Resistance, VCC – VEE = 6.0 V Figure 1d. Typical On Resistance, VCC – VEE = 9.0 V

PLOTTER
70
Ron , ON RESISTANCE (OHMS)

60 125°C
PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER
50 25°C SUPPLY
40 TBD – + VCC
30 – 55°C
DEVICE
UNDER TEST
20

10 ANALOG IN COMMON OUT

0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
GND VEE
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1e. Typical On Resistance, VCC – VEE = 12.0 V Figure 2. On Resistance Test Set–Up

High–Speed CMOS Logic Data 7 MOTOROLA

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
MC54/74HC4051A MC74HC4052A MC54/74HC4053A

VCC VCC

VCC VCC
VEE 16 VEE 16
ANALOG I/O
OFF OFF
VCC A VCC
NC OFF COMMON O/I OFF COMMON O/I

VIH 6 VIH 6
7 7
8 8
VEE VEE

Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up Common Channel, Test Set–Up

VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
VEE N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O

VIL 6 6
7 7
8 8
VEE VEE
*Includes all probe and jig capacitance

Figure 5. Maximum On Channel Leakage Current, Figure 6. Maximum On Channel Bandwidth,

Channel to Channel, Test Set–Up Test Set–Up

VIS VCC VOS VCC

0.1µF 16 dB 16
RL
fin OFF METER ON/OFF COMMON O/I
TEST
RL CL* RL ANALOG I/O
POINT
OFF/ON RL CL*
RL

6 6
7 7 VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 6 ns
VEE VCC VEE
CHANNEL SELECT CHANNEL SELECT
VIL or VIH GND
*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 7. Off Channel Feedthrough Isolation, Figure 8. Feedthrough Noise, Channel Select to
Test Set–Up Common Out, Test Set–Up

MOTOROLA 8 High–Speed CMOS Logic Data

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
 MC54/74HC4051A MC74HC4052A MC54/74HC4053A

VCC
VCC
16
VCC
CHANNEL ON/OFF COMMON O/I
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL

6
ANALOG 7
OUT 50%
8

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 9a. Propagation Delays, Channel Select Figure 9b. Propagation Delay, Test Set–Up Channel
to Analog Out Select to Analog Out

VCC
16
ANALOG I/O COMMON O/I
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
7
ANALOG 8
OUT 50%

*Includes all probe and jig capacitance

Figure 10a. Propagation Delays, Analog In Figure 10b. Propagation Delay, Test Set–Up
to Analog Out Analog In to Analog Out

tf tr POSITION 1 WHEN TESTING tPHZ AND tPZH

VCC 1 POSITION 2 WHEN TESTING tPLZ AND tPZL
90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG 7
OUT 50% 8
HIGH
IMPEDANCE

Figure 11a. Propagation Delays, Enable to Figure 11b. Propagation Delay, Test Set–Up
Analog Out Enable to Analog Out

High–Speed CMOS Logic Data 9 MOTOROLA

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
MC54/74HC4051A MC74HC4052A MC54/74HC4053A

VCC
VIS A
VCC
16 16
RL VOS
fin ON ON/OFF COMMON O/I
ANALOG I/O NC
0.1µF OFF/ON

OFF
VEE RL CL* RL CL* VCC
RL 6
7
6 VEE 8 11
7
8 CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 12. Crosstalk Between Any Two Figure 13. Power Dissipation Capacitance,
Switches, Test Set–Up Test Set–Up

0
VIS
VCC VOS – 10 FUNDAMENTAL FREQUENCY
0.1µF 16 – 20
TO
fin ON DISTORTION – 30
RL METER
CL* – 40
dB

– 50
DEVICE
– 60
6 SOURCE
– 70
7
8 – 80
VEE – 90
*Includes all probe and jig capacitance
– 100
1.0 2.0 3.125
FREQUENCY (kHz)

Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at VCC or GND through a low value resistor helps minimize
VCC or GND logic levels. VCC being recognized as a logic crosstalk and feedthrough noise that may be picked up by an
high and GND being recognized as a logic low. In this exam- unused switch.
ple: Although used here, balanced supplies are not a require-
VCC = +5V = logic high ment. The only constraints on the power supplies are that:
GND = 0V = logic low
VCC – GND = 2 to 6 volts
The maximum analog voltage swings are determined by VEE – GND = 0 to –6 volts
the supply voltages VCC and VEE. The positive peak analog VCC – VEE = 2 to 12 volts
voltage should not exceed VCC. Similarly, the negative peak and VEE ≤ GND
analog voltage should not go below VEE. In this example, the
difference between VCC and VEE is ten volts. Therefore, When voltage transients above VCC and/or below VEE are
using the configuration of Figure 15, a maximum analog sig- anticipated on the analog channels, external Germanium or
nal of ten volts peak–to–peak can be controlled. Unused Schottky diodes (Dx) are recommended as shown in Figure
analog inputs/outputs may be left floating (i.e., not con- 16. These diodes should be able to absorb the maximum
nected). However, tying unused analog inputs and outputs to anticipated current surges during clipping.

MOTOROLA 10 High–Speed CMOS Logic Data

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
 MC54/74HC4051A MC74HC4052A MC54/74HC4053A

VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
–5V SIGNAL SIGNAL –5V
Dx Dx

VEE VEE

6 11 TO EXTERNAL CMOS
7 10 CIRCUITRY 0 to 5V 7
8 9 DIGITAL SIGNALS 8
–5V VEE

Figure 15. Application Example Figure 16. External Germanium or

Schottky Clipping Diodes

+5V +5V

+5V 16 +5V +5V 16 +5V

ANALOG ANALOG ANALOG ANALOG
ON/OFF ON/OFF
VEE SIGNAL SIGNAL VEE VEE SIGNAL SIGNAL VEE
+5V
*
R R R +5V
6 11 6 11
LSTTL/NMOS LSTTL/NMOS
7 10 7 10
CIRCUITRY CIRCUITRY
8 9 8 9
VEE VEE
* 2K ≤ R ≤ 10K HCT
BUFFER
a. Using Pull–Up Resistors b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs

11 LEVEL 13
A X0
SHIFTER

14
X1

10 LEVEL 15
B X2
SHIFTER

12
X3

9 LEVEL 1
C X4
SHIFTER

5
X5

6 LEVEL 2
ENABLE X6
SHIFTER

4
X7

3
X
Figure 18. Function Diagram, HC4051A

High–Speed CMOS Logic Data 11 MOTOROLA

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
MC54/74HC4051A MC74HC4052A MC54/74HC4053A

10 LEVEL 12
A X0
SHIFTER

14
X1

9 LEVEL 15
B X2
SHIFTER

11
X3
13
X
6 LEVEL 1
ENABLE Y0
SHIFTER

5
Y1

2
Y2

4
Y3

3
Y

Figure 19. Function Diagram, HC4052A

11 LEVEL 13
A X1
SHIFTER

12
X0
14
X
10 LEVEL 1
B Y1
SHIFTER

2
Y0
15
Y
9 LEVEL 3
C Z1
SHIFTER

5
Z0
4
Z
6 LEVEL
ENABLE
SHIFTER

Figure 20. Function Diagram, HC4053A

MOTOROLA 12 High–Speed CMOS Logic Data

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
 MC54/74HC4051A MC74HC4052A MC54/74HC4053A

OUTLINE DIMENSIONS

J SUFFIX
–A CERAMIC PACKAGE
– CASE 620–10
NOTES:
16 9 ISSUE V 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
–B 2. CONTROLLING DIMENSION: INCH.
– 3. DIMENSION L TO CENTER OF LEAD WHEN
1 8 FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
C L THE LEAD ENTERS THE CERAMIC BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
–T B 0.240 0.295 6.10 7.49
–
SEATING N K C — 0.200 — 5.08
PLANE D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
E M G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
F G J 16 PL K 0.125 0.170 3.18 4.31
D 16 PL 0.25 (0.010) M T B S L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
0.25 (0.010) M T A S N 0.020 0.040 0.51 1.01

N SUFFIX
–A PLASTIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
– CASE 648–08 Y14.5M, 1982.
ISSUE R 2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
F DIM MIN MAX MIN MAX
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.070 1.02 1.77
–T PLANE G 0.100 BSC 2.54 BSC
– H 0.050 BSC 1.27 BSC
K M J
H J 0.008 0.015 0.21 0.38
G K 0.110 0.130 2.80 3.30
D 16 PL L 0.295 0.305 7.50 7.74
M 0° 10° 0° 10°
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

D SUFFIX
PLASTIC SOIC PACKAGE
–A CASE 751B–05
– ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B MOLD PROTRUSION.
P 8 PL 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–
1 8 0.25 (0.010) M B M PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
G MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45° B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
–T
–
SEATING M J J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
D 16 PL M 0° 7° 0° 7°
0.25 (0.010) M T B S A S P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

High–Speed CMOS Logic Data 13 MOTOROLA

DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com
MC54/74HC4051A MC74HC4052A MC54/74HC4053A

OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
–A–
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING
16 9 PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B– 8X P 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
0.010 (0.25) M B M
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 8 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
J MATERIAL CONDITION.
16X D
MILLIMETERS INCHES
0.010 (0.25) M T A S B S DIM MIN MAX MIN MAX
A 10.15 10.45 0.400 0.411
F B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
R X 45 _ F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
C K 0.10 0.25 0.004 0.009
–T– M 0_ 7_ 0_ 7_
SEATING M P 10.05 10.55 0.395 0.415
14X G K PLANE R 0.25 0.75 0.010 0.029

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF

0.10 (0.004) M T U S V S
NOTES:
0.15 (0.006) T U S

ÉÉ
ÇÇ
K 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K1 2. CONTROLLING DIMENSION: MILLIMETER.

ÇÇ
ÉÉ
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
16 9 PROTRUSIONS OR GATE BURRS. MOLD FLASH OR

ÇÇ
ÉÉ
2X L/2 J1 GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
B SECTION N–N FLASH OR PROTRUSION. INTERLEAD FLASH OR
L PROTRUSION SHALL NOT EXCEED
–U– 0.25 (0.010) PER SIDE.
J
PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT. PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
1 8 DIMENSION AT MAXIMUM MATERIAL CONDITION.
N 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.25 (0.010) 7. DIMENSION A AND B ARE TO BE DETERMINED AT
0.15 (0.006) T U S DATUM PLANE –W–.
A M
MILLIMETERS INCHES
–V–
DIM MIN MAX MIN MAX
N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
F C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
DETAIL E F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
0.10 (0.004) M 0_ 8_ 0_ 8_
–T– SEATING H DETAIL E
PLANE D G

MOTOROLA 14 High–Speed CMOS Logic Data

DL129 — Rev 6
F r e e D a t a s h e e t
 MC54/74HC4051A MC74HC4052A MC54/74HC4053A

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◊ MC74HC4051A/D
High–Speed CMOS Logic Data 15 MOTOROLA
DL129 — Rev 6
Free Datasheet http://www.Datasheet4U.com