V e r s i o n 2 .

0 , 1 1 S e p 2 00 8

®
CoolSET -F3R

ICE3BR2565JF

Off-Line SMPS Current Mode

Controller with integrated 650V
CoolMOS® and Startup cell
(frequency jitter Mode) in FullPak

Power Management & Supply

N e v e r s t o p t h i n k i n g .
CoolSET®-F3R
ICE3BR2565JF
Revision History: 2008-09-11 Datasheet
Previous Version: 0.2
Page Subjects (major changes since last revision)
15 Add max. limitation for CBK capacitance
17,18 Revise description of protection mode. Add constrains of 25.5V Vcc OVP
19 Revise max. voltage for VFB, VCS and VBA
19 Revise ID_Puls to Tj=125°C and add the avalanche rating
23 Add Drain Source Avalanche Breakdown Voltage
24~28 Add typical controller performance characteristics
29,30 Add typical CoolMOS® performance characteristics
31 Add input power curve
32 Revise outline dimension

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com

CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.

Edition 2008-09-11
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2008 Infineon Technologies AG.
All Rights Reserved.

Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
 CoolSET®-F3R
ICE3BR2565JF
Off-Line SMPS Current Mode Controller with
integrated 650V CoolMOS® and Startup cell
(frequency jitter Mode) in FullPak
Product Highlights
• TO220 FullPak with low Rdson MOSFET for high power application
• Active Burst Mode to reach the lowest Standby Power Requirements
< 100mW PG-TO220FS-6
• Auto Restart protection for overload, overtemperature, overvoltage
• External auto-restart enable function PG-TO220-6-247
• Built-in soft start and blanking window
• Extendable blanking Window for high load jumps
• Built-in frequency jitter and soft driving for low EMI
• Green Mould Compound
• Pb-free lead plating; RoHS compliant
Features Description
• 650V avalanche rugged CoolMOS® with built-in The CoolSET®-F3R FullPak is the enhanced version of
Startup Cell CoolSET®-F3 and targets for the Off-Line Adapters and
• Active Burst Mode for lowest Standby Power high power range SMPS in DVD R/W, DVD Combi, set top
• Fast load jump response in Active Burst Mode box, etc. It has a wide Vcc range to 25V by adopting the
• 67kHz internally fixed switching frequency BiCMOS technology. With the merit of Active Burst Mode, it
• Auto Restart Protection Mode for Overload, can achieve the lowest Standby Power Requirements
Open Loop, VCC Undervoltage, (<100mW) at no load and Vin = 270VAC. Since the
Overtemperature & Overvoltage controller is always active during the Active Burst Mode, it
• Built-in Soft Start is an immediate response on load jumps and leads to <1%
• Built-in blanking window with extendable voltage ripple voltage at output. In case of protection for
blanking time for short duration high current Overtemperature, Overvoltage, Open loop and Overload
• External auto-restart enable pin conditions, it would enter Auto Restart Mode. Thanks for the
• Max Duty Cycle 75% internal precise peak current limitation, it can provide
• Overall tolerance of Current Limiting < ±5% accurate information to optimize the dimension of the
• Internal PWM Leading Edge Blanking transformer and the output diode. The built-in blanking
• BiCMOS technology provide wide VCC range window can provide sufficient buffer time before entering
• Built-in Frequency jitter and soft driving for low the Auto Restart Mode. In case of longer blanking time, a
EMI simply addition of capacitor to BA pin can serve the
purpose. Furthermore, the built-in frequency jitter function
can effectively reduce the EMI noise and further reduce the
scale of input filter. The component counts can further be
reduced with the various built-in functions such as soft start,
blanking time and frequency jitter.

Typical Application
+

Snubber
Converter
CBulk DC Output
85 ... 270 VAC
-

CVCC
VCC Drain
Startup Cell
Power Management

PWM Controller
Current Mode
CS
Precise Low Tolerance Peak CoolMOS®
Current Limitation
RSense

FB
Active Burst Mode
GND Control
Unit BA
Auto Restart Mode
CoolSET®-F3R
( Jitter )

Type Package VDS FOSC RDSon1) 230VAC ±15% 85-265 VAC

2)
ICE3BR2565JF PG-TO220-6-247 650V 67kHz 2.56 106W 81W2)
1)
typ @ Tj=25°C
2)
Calculated maximum input power in an open frame design at Ta=50°C, Tj=125°C and RthSA (external heatsink) = 2.7K/W. Refer to input power curve for
other Ta.

Version 2.0 3 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF

Table of Contents Page

1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1 Pin Configuration with PG-TO220-6-247 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3.1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.7.3.1 Auto Restart mode with extended blanking time . . . . . . . . . . . . . . . . .17
3.7.3.2 Auto Restart without extended blanking time . . . . . . . . . . . . . . . . . . .18
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.4 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3.7 CoolMOS® Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5 Typical Controller Performance Characteristics . . . . . . . . . . . . . . . . . .24

Version 2.0 4 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF

Table of Contents Page

6 Typical CoolMOS® Performance Characteristics . . . . . . . . . . . . . . . . . .29
7 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .34

Version 2.0 5 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Pin Configuration and Functionality

1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-TO220-6- 1.2 Pin Functionality
247 Drain (Drain of integrated CoolMOS®)
Pin Drain is the connection to the Drain of the internal
CoolMOS® and the HV of the startup cell.
Pin Symbol Function
CS (Current Sense)
1 Drain 650V1) CoolMos® Drain
The Current Sense pin senses the voltage developed
2 CS Current Sense/ on the series resistor inserted in the source of the
650V1) CoolMOS® Source integrated CoolMOS®. If CS voltage reaches the
internal threshold of the Current Limit Comparator, the
3 BA extended Blanking & external Driver output is immediately switched off. Furthermore
Auto Restart enable the current information is provided for the PWM-
4 VCC Controller Supply Voltage Comparator to realize the Current Mode.

5 GND Controller Ground

BA (extended Blanking & Auto-restart enable)
6 FB Feedback The BA pin combines the functions of extendable
1)
at Tj=110°C blanking time for over load protection and the external
auto-restart enable. The extendable blanking time
function is to extend the built-in 20 ms blanking time by
adding an external capacitor at BA to ground. The
external auto-restart enable function is an external
access to stop the gate switching and force the IC to
Package PG-TO220-6-247 enter auto-restart mode. It is triggered by pulling down
the BA pin to less than 0.33V.

VCC (Power Supply)

The VCC pin is the positive supply of the IC. The
operating range is between 10.5V and 25V.

GND (Ground)
The GND pin is the ground of the controller.
1 2 3 4 5 6

FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FB-
Signal is the only control signal in case of light load at
the Active Burst Mode.
Drain

GND
VCC
CS

BA

FB

Figure 1 Pin Configuration PG-TO220-6-247

(front view)

Version 2.0 6 11 Sep 2008

 2

Figure 2

Version 2.0
+
Converter
CBulk Snubber DC Output
85 ... 270 VAC VOUT
-

CVCC

VCC Drain
5.0V Power Management CoolMOS®
3.25kΩ
Startup Cell
Internal Bias Voltage 5.0V
Reference
IBK T2
Auto-restart
Enable BA T3 0.6V
GND
Signal Power-Down
#1 CBK Undervoltage Lockout
T1 Reset 18V
0.75 PWM
#2 10.5V
TAE VCC Oscillator Section
&

Representative Blockdiagram
C1 G1
Duty Cycle
20.7V max
0.9V 1 ms
VCC counter
C2 120us Blanking Time Soft Start Soft-Start Clock

25.5V Comparator
Thermal Shutdown Freq. jitter
Soft
Tj >130°C & Gate
Start FF1
0.33V C7 G7 Driver
C9 Block
1 S
&

7
S1 G8 R Q
1 G9
C3 G2
4.0V PWM
5.0V Comparator

& C8
4.5V Spike Auto
Representative Blockdiagram

RFB C4 20ms G5 Blanking Restart

Blanking 30us Mode Propagation-Delay
Time Compensation
25kΩ
Active Burst Vcsth Leading 10kΩ CS
C5 20ms Blanking & 0.68V
FB Mode C10 Edge
1.22V Time
2pF G6 Blanking 1pF D1
x3.3 220ns RSense
C6a PWM OP &
3.6V G10 C12
& 0.26V
Current Limiting
C6b G11 Current Mode
3.1V
Control Unit
ICE3BRxx65JF / CoolSET®-F3R ( Jitter Mode & FullPak)

# : optional external components;

#1 : CBK is used to extend the Blanking Time
#2 : TAE is used to enable the external Auto-restart feature
CoolSET®-F3R
ICE3BR2565JF

11 Sep 2008
Representative Blockdiagram
 CoolSET®-F3R
ICE3BR2565JF
Functional Description

3 Functional Description
All values which are used in the functional description condition which could otherwise lead to a destruction of
are typical values. For calculating the worst cases the the SMPS over time. Once the malfunction is removed,
min/max values which can be found in section 4 normal operation is automatically recovered after the
Electrical Characteristics have to be considered. next Start Up Phase.
The internal precise peak current limitation reduces the
3.1 Introduction costs for the transformer and the secondary diode. The
influence of the change in the input voltage on the
®
CoolSET -F3R FullPak is the further development of power limitation can be avoided together with the
the CoolSET®-F3 for high power application. The integrated Propagation Delay Compensation.
particular enhanced features are built-in features for Therefore the maximum power is nearly independent
soft start, blanking window and frequency jitter. It also on the input voltage which is required for wide range
provides the flexibility to increase the blanking window SMPS. There is no need for an extra over-sizing of the
by simply adding capacitance in BA pin. However, the SMPS, e.g. the transformer or the secondary diode.
proven outstanding features in CoolSET®-F3 are Furthermore, this full package version implements the
remained. frequency jitter mode to the switching clock such that
The intelligent Active Burst Mode at Standby Mode can the EMI noise will be effectively reduced.
effectively obtain the lowest Standby Power at
minimum load and no load condition. After entering the
burst mode, there is still a full control of the power
3.2 Power Management
conversion by the secondary side via the same D rain VC C
optocoupler that is used for the normal PWM control.
The response on load jumps is optimized. The voltage Startup C ell
ripple on Vout is minimized. Vout is on well controlled in
this mode.
The usually external connected RC-filter in the C oolM O S ®
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Furthermore a high voltage Startup Cell is integrated Power M anagem ent
into the IC which is switched off once the Undervoltage
U ndervoltage Lockout
Lockout on-threshold of 18V is exceeded. This Startup Internal Bias
18V
Cell is part of the integrated CoolMOS®. The external 10.5V
startup resistor is no longer necessary as this Startup
Cell is connected to the Drain. Power losses are
therefore reduced. This increases the efficiency under Pow er-Down Reset Voltage 5.0V
light load conditions drastically. Reference

This version is adopting the BiCMOS technology and it

can increase design flexibility as the Vcc voltage range Auto R estart
is increased to 25V. M ode

For this full package version, the soft start is a built-in Soft Start block Active Burst
M ode
function. It is set at 20ms. Then it can save external
component counts.
There are 2 modes of blanking time for high load
jumps; the basic mode and the extendable mode. The
blanking time for the basic mode is pre-set at 20ms
while the extendable mode will increase the blanking Figure 3 Power Management
time at basic mode by adding external capacitor at the
BA pin. During this time window the overload detection The Undervoltage Lockout monitors the external
is disabled. With this concept no further external supply voltage VVCC. When the SMPS is plugged to the
components are necessary to adjust the blanking main line the internal Startup Cell is biased and starts
window. to charge the external capacitor CVCC which is
connected to the VCC pin. This VCC charge current is
In order to increase the robustness and safety of the
controlled to 0.9mA by the Startup Cell. When the VVCC
system, the IC provides Auto Restart protection mode.
exceeds the on-threshold VCCon=18V the bias circuit
The Auto Restart Mode reduces the average power
are switched on. Then the Startup Cell is switched off
conversion to a minimum under unsafe operating
by the Undervoltage Lockout and therefore no power
conditions. This is necessary for a prolonged fault

Version 2.0 8 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Functional Description

losses present due to the connection of the Startup Cell

to the Drain voltage. To avoid uncontrolled ringing at
switch-on a hysteresis start up voltage is implemented. Amplified Current Signal
The switch-off of the controller can only take place after
Active Mode was entered and VVCC falls below 10.5V.
The maximum current consumption before the FB
controller is activated is about 150µA.
When VVCC falls below the off-threshold VCCoff=10.5V,
the bias circuit is switched off and the soft start counter 0.68V
is reset. Thus it is ensured that at every startup cycle
the soft start starts at zero. Driver t
The internal bias circuit is switched off if Auto Restart
Mode is entered. The current consumption is then
reduced to 250µA.
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart ton
Mode does not require re-cycling the AC line.
When Active Burst Mode is entered, the internal Bias is
switched off most of the time in order to reduce the t
current consumption below 500µA.
Figure 5 Pulse Width Modulation
3.3 Improved Current Mode In case the amplified current sense signal exceeds the
FB signal the on-time ton of the driver is finished by
Soft-Start Comparator resetting the PWM-Latch (see Figure 5).
The primary current is sensed by the external series
resistor RSense inserted in the source of the integrated
PWM-Latch CoolMOS®. By means of Current Mode regulation, the
FB secondary output voltage is insensitive to the line
C8 R Q variations. The current waveform slope will change with
Driver the line variation, which controls the duty cycle.
The external RSense allows an individual adjustment of
the maximum source current of the integrated
S Q
CoolMOS®.
To improve the Current Mode during light load
0.68V conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
PWM OP the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
x3.3 CS by VOSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
Improved In case of light load the amplified current ramp is too
Current Mode small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
Figure 4 Current Mode comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
Current Mode means the duty cycle is controlled by the By means of the time delay circuit which is triggered by
slope of the primary current. This is done by comparing the inverted VOSC signal, the Gate Driver is switched-off
the FB signal with the amplified current sense signal. until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing VFB below that
threshold.

Version 2.0 9 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Functional Description

3.3.1 PWM-OP
Soft-Start Comparator The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
PWM Comparator RSense connected to pin CS. RSense converts the source
FB current into a sense voltage. The sense voltage is
C8 amplified with a gain of 3.3 by PWM OP. The output of
the PWM-OP is connected to the voltage source V1.
Oscillator PWM-Latch The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
VOSC Comparator C8 and the Soft-Start-Comparator (see
time delay Figure 6).
circuit (156ns)
Gate Driver
3.3.2 PWM-Comparator
0.68V
The PWM-Comparator compares the sensed current
10kΩ signal of the integrated CoolMOS® with the feedback
X3.3 signal VFB (see Figure 8). VFB is created by an external
T2 R1 optocoupler or external transistor in combination with
V1 the internal pull-up resistor RFB and provides the load
PWM OP
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS®
exceeds the signal VFB the PWM-Comparator switches
Voltage Ramp off the Gate Driver.

Figure 6 Improved Current Mode

5V
RFB Soft-Start Comparator
VOSC
FB
max. PWM-Latch
Duty Cycle C8

PWM Comparator

Voltage Ramp t
0.68V

Optocoupler
0.68V PWM OP
FB CS
X3.3

Gate Driver t
Improved
156ns time delay
Current Mode

Figure 8 PWM Controlling

t

Figure 7 Light Load Conditions

Version 2.0 10 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Functional Description

3.4 Startup Phase When the VVCC exceeds the on-threshold voltage, the
IC starts the Soft Start mode (see Figure 10).
The function is realized by an internal Soft Start
S o ft S ta rt c o u n te r
resistor, an current sink and a counter. And the
amplitude of the current sink is controlled by the
counter (see Figure 11).
S o ftS
Soft Start finish

S o ft S ta rt

5V
S o ft S ta rt
R SoftS
S o ft-S ta rt
C o m p a ra to r SoftS
G a te D riv e r
C7 &

G7

0 .6 8 V
Soft Start 32I 8I 4I 2I I
Counter
x 3 .3 CS
PW M OP

Figure 9 Soft Start

In the Startup Phase, the IC provides a Soft Start Figure 11 Soft Start Circuit
period to control the primary current by means of a duty After the IC is switched on, the VSOFTS voltage is
cycle limitation. The Soft Start function is a built-in controlled such that the voltage is increased step-
function and it is controlled by an internal counter. wisely (32 steps) with the increase of the counts. The
. Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
decrease gradually and the duty ratio of the gate drive
increases gradually. The Soft Start will be finished in
20ms (tSoft-Start) after the IC is switched on. At the end of
the Soft Start period, the current sink is switched off.

VSoftS
tSoft-Start
VSOFTS32

V SoftS

VSoftS2 t
VSoftS1
Gate
Driver

Figure 10 Soft Start Phase t

Figure 12 Gate drive signal under Soft-Start Phase

Version 2.0 11 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Functional Description

Within the soft start period, the duty cycle is increasing 3.5 PWM Section
from zero to maximum gradually (see Figure 12).
In addition to Start-Up, Soft-Start is also activated at
0.75
each restart attempt during Auto Restart. PWM Section
Oscillator
VSoftS
Duty Cycle
tSoft-Start max
VSOFTS32
Clock

Frequency
Jitter

VFB t

Soft Start
4.5V Block FF1
S Gate Driver
Soft Start 1
Comparator R &
G8 Q
VOUT PWM G9
t Comparator

Current
VOUT Limiting
CoolMOS®
tStart-Up Gate

t
Figure 14 PWM Section Block
Figure 13 Start Up Phase
3.5.1 Oscillator
The Start-Up time tStart-Up before the converter output The oscillator generates a fixed frequency of 67KHz
voltage VOUT is settled, must be shorter than the Soft- with frequency jittering of ±4% (which is ±2.7KHz) at a
Start Phase tSoft-Start (see Figure 13). jittering period of 4ms.
By means of Soft-Start there is an effective A capacitor, a current source and current sink which
minimization of current and voltage stresses on the determine the frequency are integrated. The charging
integrated CoolMOS®, the clamp circuit and the output and discharging current of the implemented oscillator
overshoot and it helps to prevent saturation of the capacitor are internally trimmed, in order to achieve a
transformer during Start-Up. very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 67KHz ± 2.7KHz at period of 4ms.

3.5.2 PWM-Latch FF1

The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the internal
CoolMOS®. After the PWM-Latch is set, it is reset by
the PWM comparator, the Soft Start comparator or the
Current -Limit comparator. When it is in reset mode, the
output of the driver is shut down immediately.

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Functional Description

3.5.3 Gate Driver 3.6 Current Limiting

PWM Latch
FF1
VCC Current Limiting

PWM-Latch
1

Propagation-Delay
Compensation
Gate

CoolMOS® Vcsth
C10 Leading
Edge
Blanking
PWM-OP 220ns
Gate Driver
&
G10 C12
Figure 15 Gate Driver 0.26V
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
1pF
the switch on slope when exceeding the internal Active Burst 10k
CoolMOS® threshold. This is achieved by a slope Mode D1
control of the rising edge at the driver’s output (see
Figure 9).

CS
(internal)
Figure 17 Current Limiting Block
VGate
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS® is sensed
ca. t = 130ns via an external sense resistor RSense. By means of
RSense the source current is transformed to a sense
voltage VSense which is fed into the pin CS. If the voltage
5V VSense exceeds the internal threshold voltage Vcsth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
t A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
Figure 16 Gate Rising Slope CoolMOS® with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
Thus the leading switch on spike is minimized.
output power can be reduced to minimal.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage. In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
During power up, when VCC is below the undervoltage
Blanking is integrated in the current sense path for the
lockout threshold VVCCoff, the output of the Gate Driver
comparators C10, C12 and the PWM-OP.
is set to low in order to disable power transfer to the
secondary side. The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. When it is
activated, the current limiting is reduced to 0.26V. This
voltage level determines the maximum power level in
Active Burst Mode.

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Functional Description

3.6.1 Leading Edge Blanking For example, Ipeak = 0.5A with RSense = 2. The current
sense threshold is set to a static voltage level Vcsth=1V
VSense without Propagation Delay Compensation. A current
ramp of dI/dt = 0.4A/µs, or dVSense/dt = 0.8V/µs, and a
propagation delay time of tPropagation Delay =180ns leads
Vcsth to an Ipeak overshoot of 14.4%. With the propagation
tLEB = 220ns
delay compensation, the overshoot is only around 2%
(see Figure 20).

with compensation without compensation

V
1,3

t 1,25

1,2
Figure 18 Leading Edge Blanking

VSense
1,15

Whenever the internal CoolMOS® is switched on, a 1,1

leading edge spike is generated due to the primary- 1,05

side capacitances and reverse recovery time of the 1

secondary-side rectifier. This spike can cause the gate 0,95

drive to switch off unintentionally. In order to avoid a 0,9

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 V
premature termination of the switching pulse, this spike
dVSense µs
is blanked out with a time constant of tLEB = 220ns.
dt

3.6.2 Propagation Delay Compensation Figure 20 Overcurrent Shutdown

In case of overcurrent detection, there is always The Propagation Delay Compensation is realized by
propagation delay to switch off the internal CoolMOS®.
means of a dynamic threshold voltage Vcsth (see Figure
An overshoot of the peak current Ipeak is induced to the
21). In case of a steeper slope the switch off of the
delay, which depends on the ratio of dI/dt of the peak driver is earlier to compensate the delay.
current (see Figure 19).
VOSC max. Duty Cycle

Signal2 Signal1
ISense tPropagation Delay
Ipeak2 IOvershoot2
off time
Ipeak1
ILimit
VSense Propagation Delay t
IOvershoot1
Vcsth

t
Figure 19 Current Limiting
The overshoot of Signal2 is larger than of Signal1 due Signal1 Signal2
to the steeper rising waveform. This change in the t
slope is depending on the AC input voltage. Figure 21 Dynamic Voltage Threshold Vcsth
Propagation Delay Compensation is integrated to
reduce the overshoot due to dI/dt of the rising primary
current. Thus the propagation delay time between 3.7 Control Unit
exceeding the current sense threshold Vcsth and the
switching off of the integrated CoolMOS® is The Control Unit contains the functions for Active Burst
compensated over temperature within a wide range. Mode and Auto Restart Mode. The Active Burst Mode
Current Limiting is then very accurate. and the Auto Restart Mode both have 20ms internal
Blanking Time. For the Auto Restart Mode, a further
extendable Blanking Time is achieved by adding

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 CoolSET®-F3R
ICE3BR2565JF
Functional Description

external capacitor at BA pin. By means of this Blanking In order to make the startup properly, the maximum CBK
Time, the IC avoids entering into these two modes capacitor is restricted to less than 0.65uF.
accidentally. Furthermore those buffer time for the The Active Burst Mode has basic blanking mode only
overload detection is very useful for the application that while the Auto Restart Mode has both the basic and the
works in low current but requires a short duration of extendable blanking mode.
high current occasionally.
3.7.2 Active Burst Mode
3.7.1 Basic and Extendable Blanking Mode
The IC enters Active Burst Mode under low load
conditions. With the Active Burst Mode, the efficiency
increases significantly at light load conditions while still
BA maintaining a low ripple on VOUT and a fast response on
5.0V
load jumps. During Active Burst Mode, the IC is
# CBK IBK controlled by the FB signal. Since the IC is always
active, it can be a very fast response to the quick
change at the FB signal. The Start up Cell is kept OFF
0.9V
in order to minimize the power loss.
1
S1
G2

Internal Bias
C3
Spike
4.0V
Blanking
30us Current
20 ms Blanking Limiting
& Time &
G10
4.5V 20ms G5 Auto
C4 Blanking Restart
Time Mode 4.5V
C4

FB Active
20ms
&
Active FB Burst
C5 G6 Burst C5 &
Blanking Mode
1.22V Time Mode
1.22V G6
Control Unit

C6a
Figure 22 Basic and Extendable Blanking Mode 3.6V

There are 2 kinds of Blanking mode; basic mode and &

the extendable mode. The basic mode is just an C6b G11
internal pre-set 20ms blanking time while the 3.1V
extendable mode has extra blanking time by Control Unit
connecting an external capacitor to the BA pin in
Figure 23 Active Burst Mode
addition to the pre-set 20ms blanking time. For the
extendable mode, the gate G5 is blocked even though
the 20ms blanking time is reached if an external The Active Burst Mode is located in the Control Unit.
capacitor CBK is added to BA pin. While the 20ms Figure 23 shows the related components.
blanking time is passed, the switch S1 is opened by
G2. Then the 0.9V clamped voltage at BA pin is 3.7.2.1 Entering Active Burst Mode
charged to 4.0V through the internal IBK constant
The FB signal is kept monitoring by the comparator C5.
current. Then G5 is enabled by comparator C3. After
During normal operation, the internal blanking time
the 30us spike blanking time, the Auto Restart Mode is
counter is reset to 0. When FB signal falls below 1.22V,
activated.
it starts to count. When the counter reach 20ms and FB
For example, if CBK = 0.22uF, IBK = 13.5uA signal is still below 1.22V, the system enters the Active
Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 70ms Burst Mode. This time window prevents a sudden
entering into the Active Burst Mode due to large load
jumps.

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Functional Description

After entering Active Burst Mode, a burst flag is set and

the internal bias is switched off in order to reduce the
current consumption of the IC to approx. 500uA. VFB Entering Leaving
It needs the application to enforce the VCC voltage Active Burst Active Burst
above the Undervoltage Lockout level of 10.5V such Mode Mode
4.5V
that the Startup Cell will not be switched on 3.6V
accidentally. Or otherwise the power loss will increase 3.1V
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the 1.22V
application. The lowest VCC level is reached at no load
condition.
Blanking Timer t
3.7.2.2 Working in Active Burst Mode 20ms Blanking Time
After entering the Active Burst Mode, the FB voltage
rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors
the FB signal. If the voltage level is larger than 3.6V, the
internal circuit will be activated; the Internal Bias circuit
resumes and starts to provide switching pulse. In
Active Burst Mode the gate G10 is released and the VCS t
current limit is reduced to 0.26V. In one hand, it can
reduce the conduction loss and the other hand, it can
reduce the audible noise. If the load at VOUT is still kept
Current limit level
unchanged, the FB signal will drop to 3.1V. At this level 1.0V
during Active Burst
the C6b deactivates the internal circuit again by
Mode
switching off the internal Bias. The gate G11 is active
again as the burst flag is set after entering Active Burst 0.26V
Mode. In Active Burst Mode, the FB voltage is changing
like a saw tooth between 3.1V and 3.6V (see figure 17). VVCC t

3.7.2.3 Leaving Active Burst Mode

The FB voltage will increase immediately if there is a
high load jump. This is observed by the comparator C4.
As the current limit is appr. 26% during Active Burst
Mode, a certain load jump is needed so that the FB 10.0V
signal can exceed 4.5V. At that time the comparator C4
resets the Active Burst Mode control which in turn
blocks the comparator C12 by the gate G10. The IVCC t
maximum current can then be resumed to stabilize
VOUT. 2.4mA

500uA

VOUT t
Max. Ripple < 1%

Figure 24 Signals in Active Burst Mode

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Functional Description

3.7.3 Protection Modes 3.7.3.1 Auto Restart mode with extended

The IC provides Auto Restart Mode as the protection blanking time
feature. Auto Restart mode can prevent the SMPS from
destructive states. The following table shows the
relationship between possible system failures and the BA
5.0V
chosen protection modes. # CBK IBK
VCC Overvoltage Auto Restart Mode
Overtemperature Auto Restart Mode 0.9V

Overload Auto Restart Mode 1

S1
G2
Open Loop Auto Restart Mode
VCC Undervoltage Auto Restart Mode
Short Optocoupler Auto Restart Mode C3
Spike
4.0V
Blanking
External auto restart Auto Restart Mode 30us
enable
&

Before entering the Auto Restart protection mode, 4.5V 20ms G5 Auto
some of the protections can have extended blanking C4 Blanking Restart
FB Time Mode
time to delay the protection and some needs to fast
react and will go straight to the protection. Overload
Control Unit
and open loop protection are the one can have
extended blanking time while Vcc Overvoltage, Over
temperature, Vcc Undervoltage, short opto-coupler Figure 25 Auto Restart Mode
and external auto restart enable will go to protection In case of Overload or Open Loop, the FB exceeds
right away. 4.5V which will be observed by comparator C4. Then
After the system enters the Auto-restart mode, the IC the internal blanking counter starts to count. When it
will be off. Since there is no more switching, the Vcc reaches 20ms, the switch S1 is released. Then the
voltage will drop. When it hits the Vcc turn off threshold, clamped voltage 0.9V at VBA can increase. When there
the start up cell will turn on and the Vcc is charged by is no external capacitor CBK connected, the VBA will
the startup cell current to Vcc turn on threshold. The IC reach 4.0V immediately. When both the input signals at
is on and the startup cell will turn off. At this stage, it will AND gate G5 is positive, the Auto Restart Mode will be
enter the startup phase (soft start) with switching activated after the extra spike blanking time of 30us is
cycles. After the Start Up Phase, the fault condition is elapsed. However, when an extra blanking time is
checked. If the fault condition persists, the IC will go to needed, it can be achieved by adding an external
auto restart mode again. If, otherwise, the fault is capacitor, CBK. A constant current source of IBK will start
removed, normal operation is resumed. to charge the capacitor CBK from 0.9V to 4.0V after the
switch S1 is released. The charging time from 0.9V to
4.0V are the extendable blanking time. If CBK is 0.22uF
and IBK is 13.5uA, the extendable blanking time is
around 50ms and the total blanking time is 70ms. In
combining the FB and blanking time, there is a blanking
window generated which prevents the system to enter
Auto Restart Mode due to large load jumps.

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Functional Description

3.7.3.2 Auto Restart without extended blanking a trigger signal to the base of the externally added
time transistor, TAE at the BA pin. When the function is
enabled, the gate drive switching will be stopped and
then the IC will enter auto-restart mode if the signal
persists. To ensure this auto-restart function will not be
Auto Restart
Mode Reset
mis-triggered during start up, a 1ms delay time is
VVCC < 10.5V implemented to blank the unstable signal.
1ms
counter
UVLO VCC undervoltage is the Vcc voltage drop below Vcc
turn off threshold. Then the IC will turn off and the start
Auto-restart BA
Enable Stop up cell will turn on automatically. And this leads to Auto
Signal
0.33V C9 gate Restart Mode.
drive Auto Restart
mode Short Optocoupler also leads to VCC undervoltage.
When the FB pin is pulled low, there is no switching
TAE 25.5V
pulse. Then the Vcc will drop to Vcc turn off threshold.
120us
C2
And it leads to Auto Restart Mode.
Blanking
VCC
Time

VCC Spike
& Blanking
C1
20.7V 30us
G1
softs_period

4.5V
C4
Voltage
FB Thermal Shutdown Reference

Tj >130°C

Control Unit

Figure 26 Auto Restart mode

There are 2 modes of VCC overvoltage protection; one
is during soft start and the other is at all conditions.
The first one is VVCC voltage is > 20.7V and FB is > 4.5V
and during soft_start period and the IC enters Auto
Restart Mode. The VCC voltage is observed by
comparator C1. The fault conditions are to detect the
abnormal operating during start up such as open loop
during light load start up, etc. The logic can eliminate
the possible of entering Auto Restart mode if there is a
small voltage overshoots of VVCC during normal
operating.
The 2nd one is VVCC >25.5V and last for 120us and the
IC enters Auto Restart Mode. This 25.5V Vcc OVP
protection is inactivated during burst mode.
The Thermal Shutdown block monitors the junction
temperature of the IC. After detecting a junction
temperature higher than 130°C, the Auto Restart Mode
is entered.
In case the pre-defined auto-restart features are not
sufficient, there is a customer defined external Auto-
restart Enable feature. This function can be triggered
by pulling down the BA pin to < 0.33V. It can simply add

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Electrical Characteristics

4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 5). The voltage levels are valid if other ratings are
not violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 4
(VCC) is discharged before assembling the application circuit.Ta=25°C unless otherwise specified.

Parameter Symbol Limit Values Unit Remarks

min. max.
Switching drain current, pulse width tp Is - 2.68 A
limited by max. Tj=150°C

Pulse drain current, pulse width tp ID_Puls - 5.3 A

limited by max. Tj=150°C
Avalanche energy, repetitive tAR limited EAR - 0.07 mJ ID=1.8A
by max. Tj=150°C1)
Avalanche current, repetitive tAR limited IAR - 1.8 A
by max. Tj=150°C1)
VCC Supply Voltage VVCC -0.3 27 V
FB Voltage VFB -0.3 5.5 V
BA Voltage VBA -0.3 5.5 V
CS Voltage VCS -0.3 5.5 V
Junction Temperature Tj -40 150 °C Controller & CoolMOS®
Storage Temperature TS -55 150 °C
Thermal Resistance RthJA - 82 K/W
Junction -Ambient
Thermal Resistance RthJC - 5.2 K/W
Junction -case
Soldering temperature, wavesoldering Tsold - 260 °C 1.6mm (0.063 in.) from
only allowed at leads case for 10s
Power dissipation, Tc=25°C Ptot - 24 W Refer to Figure 57

ESD Capability (incl. Drain Pin) VESD - 2 kV Human body model2)

Mounting torque 60 Ncm M2.5 screws
1)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)

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Electrical Characteristics

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter Symbol Limit Values Unit Remarks

min. max.
VCC Supply Voltage VVCC VVCCoff 25 V Max. value limited due to Vcc
OVP
Junction Temperature of TjCon -25 130 °C Max value limited due to thermal
Controller shut down of controller
Junction Temperature of TjCoolMOS -25 150 °C
CoolMOS®

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from – 25 °C to 125 °C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Start Up Current IVCCstart - 150 250 µA VVCC =17V

VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V

IVCCcharge2 0.55 0.9 1.60 mA VVCC = 1V
IVCCcharge3 - 0.7 - mA VVCC =17V
Leakage Current of IStartLeak - 0.2 50 µA VDrain = 600V
Start Up Cell and CoolMOS® at Tj=100°C 1)

Supply Current with IVCCsup1 - 1.5 2.5 mA

Inactive Gate
Supply Current with Active Gate IVCCsup2 - 2.4 3.7 mA IFB = 0A
Supply Current in IVCCrestart - 250 - µA IFB = 0A
Auto Restart Mode with Inactive
Gate
Supply Current in Active Burst IVCCburst1 - 500 950 µA VFB = 2.5V
Mode with Inactive Gate
IVCCburst2 - 500 950 µA VVCC = 11.5V,VFB = 2.5V
VCC Turn-On Threshold VVCCon 17.0 18.0 19.0 V
VCC Turn-Off Threshold VVCCoff 9.8 10.5 11.2 V
VCC Turn-On/Off Hysteresis VVCChys - 7.5 - V
1)
The parameter is not subjected to production test - verified by design/characterization

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ICE3BR2565JF
Electrical Characteristics

4.3.2 Internal Voltage Reference

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FB
IFB = 0

4.3.3 PWM Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Fixed Oscillator Frequency fOSC1 58 67 75 kHz
fOSC2 62 67 74.5 kHz Tj = 25°C
Frequency Jittering Range fjitter - ±2.7 - kHz Tj = 25°C
Frequency Jittering period Tjitter - 4.0 - ms Tj = 25°C
Max. Duty Cycle Dmax 0.70 0.75 0.80

Min. Duty Cycle Dmin 0 - - VFB < 0.3V

PWM-OP Gain AV 3.1 3.3 3.5

Voltage Ramp Offset VOffset-Ramp - 0.68 - V

VFB Operating Range Min Level VFBmin - 0.5 - V

VFB Operating Range Max level VFBmax - - 4.3 V CS=1V, limited by

Comparator C41)
FB Pull-Up Resistor RFB 9 15.4 22 kΩ

1)
The parameter is not subjected to production test - verified by design/characterization

4.3.4 Soft Start time

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Soft Start time tSS - 20.0 - ms VFB > 4.0V

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ICE3BR2565JF
Electrical Characteristics

4.3.5 Control Unit

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Clamped VBA voltage during VBAclmp 0.85 0.9 0.95 V VFB = 4V
Normal Operating Mode
Blanking time voltage limit for VBKC3 3.85 4.00 4.15 V
Comparator C3
Over Load & Open Loop Detection VFBC4 4.28 4.50 4.72 V
Limit for Comparator C4
Active Burst Mode Level for VFBC5 1.13 1.22 1.31 V
Comparator C5
Active Burst Mode Level for VFBC6a 3.45 3.60 3.74 V After Active Burst
Comparator C6a Mode is entered
Active Burst Mode Level for VFBC6b 2.97 3.10 3.22 V After Active Burst
Comparator C6b Mode is entered
Overvoltage Detection Limit for VVCCOVP1 19.6 20.7 21.7 V VFB = 5V
Comparator C1

Overvoltage Detection Limit for VVCCOVP2 25.0 25.5 26.3 V

Comparator C2

Auto-restart Enable level at BA pin VAE 0.25 0.33 0.42 V

for Comparator C9

Charging current at BA pin IBK 10.1 13.5 16.1 µA Charge starts after the
built-in 20ms blanking
time elapsed
Thermal Shutdown1) TjSD 130 140 150 °C Controller

Built-in Blanking Time for tBK - 20 - ms without external

Overload Protection or enter capacitor at BA pin
Active Burst Mode
Inhibit Time for Auto-Restart tIHAE - 1.0 - ms Count when VCC>18V
enable function during start up
Spike Blanking Time before Auto tSpike - 30 - µs
Restart Protection

1)
The parameter is not subjected to production test - verified by design/characterization

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
and VVCCPD

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Electrical Characteristics

4.3.6 Current Limiting

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Peak Current Limitation Vcsth 0.88 1.06 1.13 V dVsense / dt = 0.6V/µs
(incl. Propagation Delay) (see Figure 13)
Peak Current Limitation during VCS2 0.22 0.26 0.29 V
Active Burst Mode
Leading Edge Blanking tLEB - 220 - ns

CS Input Bias Current ICSbias -1.5 -0.2 - µA VCS =0V

4.3.7 CoolMOS® Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Drain Source Breakdown Voltage V(BR)DSS 650 - - V Tj = 110°C1) (Refer to
Figure 65 for other
V(BR)DSS in different Tj)
VGS=0V, ID=0.25mA
Drain Source Avalanche V(BR)DS - 700 - V VGS=0V, ID=1.8A
Breakdown Voltage
Drain Source On-Resistance RDSon - 2.56 2.83 Ω Tj = 25°C
- 5.67 6.26 Ω Tj=125°C1)
- 6.91 7.64 Ω Tj=150°C1)
at ID = 1A
Effective output capacitance, Co(er) - 11 - pF VDS = 0V to 480V1)
energy related
Rise Time trise - 302) - ns
2)
Fall Time tfall - 30 - ns
1)
The parameter is not subjected to production test - verified by design/characterization
2)
Measured in a Typical Flyback Converter Application

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Typical Controller Performance Characteristics

5 Typical Controller Performance Characteristics

200 0.85

Vcc Charge Current IVCCcharge3 [mA]

192 0.81
Start Up Current I VCCstart [µA]

184 0.77

0.73
176
0.69
168

PI-004-8889A23
PI-001-8889A23
0.65
160
0.61
152
0.57
144
0.53
136
0.49
128
0.45
120 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]

Figure 27 Start Up Current IVCCstart Figure 30 VCC Charge Current IVCCcharge3

1.00 1.80
Vcc Charge Current IVCCcharge1 [mA]

0.96 1.75
Vcc Supply Current IVCCsup1 [mA]

0.92 1.70

0.88 1.65

0.84 1.60
PI-002-8889A23

PI-005-8889A23
0.80 1.55
0.76 1.50
0.72 1.45
0.68 1.40
0.64
1.35
0.60
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 1.30
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 28 VCC Charge Current IVCCcharge1 Figure 31 VCC Supply Current IVCCsup1

1.00
2.9
Vcc Charge Current I VCCcharge2 [mA]

0.96
2.8
Vcc Supply Current IVCCsup2 [mA]

0.92
2.7
0.88
2.6
0.84
PI-006-8888A12 ICE3BR2565JF

2.5
PI-003-8889A23

0.80
2.4
0.76
2.3
0.72
2.2
0.68
2.1
0.64
2.0
0.60
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 1.9
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 29 VCC Charge Current IVCCcharge2 Figure 32 VCC Supply Current IVCCsup2

Version 2.0 24 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Typical Controller Performance Characteristics

310 11.0

Vcc Turn-Off Threshold VVCCoff [V]

Vcc Supply Current IVCCrestart [uA]

300 10.9

290 10.8

280 10.7

270 10.6

PI-010-8889A23
PI-007-8889A23
260 10.5

250 10.4

240 10.3

230 10.2

220 10.1

210 10.0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125

Junction Temperature [°C] Junction Temperature [°C]

Figure 33 VCC Supply Current IVCCrestart Figure 36 VCC Turn-Off Threshold VVCCoff

5.20
600
5.16
580
Vcc Supply Current IVCCburst [uA]

Reference Voltage VREF [V]

5.12
560
5.08
540
5.04
520

PI-011-8889A23
PI-008-8889A23

5.00
500
4.96
480
4.92
460
4.88
440
4.84
420
4.80
400 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]

Figure 34 VCC Supply Current IVCCburst Figure 37 Reference Voltage VREF

70
18.5
69
Oscillator Frequency fosc1 [kHz]
Vcc Turn-On threshold VVCCon [V]

18.4
68
18.3
67
18.2
66
18.1
PI-012-8889A23

65
PI-010-8889A23

18.0
64
17.9
63
17.8
62
17.7
61
17.6
60
17.5 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 38 Oscillator Frequency fOSC1
Figure 35 VCC Turn-On Threshold VVCCon

Version 2.0 25 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Typical Controller Performance Characteristics

3.1 0.73
Frequency Jitter Range fjitter [+/-kHz]

Voltage Ramp Offset V Offset-Ramp [V]

3.0 0.72

2.9 0.71

2.8 0.70

2.7 0.69

PI-001-8889A23

PI-016-8889A23
2.6 0.68

2.5 0.67

2.4 0.66

2.3 0.65

2.2 0.64

2.1 0.63
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]

Figure 39 Frequency Jittering Range fjitter Figure 42 Voltage Ramp Offset VOffset-Ramp

20
Feedback Pull-Up resistor RFB [kOhm]

0.780
19
0.774
18
0.768
Max. Duty Cycle Dmax

17
0.762
16
0.756

PI-019-8889A23
PI-014-8889A23

15
0.750
14
0.744
13
0.738
12
0.732
11
0.726
10
0.720 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]

Figure 40 Max. Duty Cycle Dmax Figure 43 Feedback Pull-Up resistor RFB

0.95
3.50
Clamped VBA Voltage VBAclmp [V]

0.94
3.45
0.93
3.40
0.92
3.35
PWM OP Gain AV

0.91
3.30
PI-020-8889A23

0.90
PI-015-8889A23

3.25
0.89
3.20
0.88
3.15
0.87
3.10
0.86
3.05
0.85
3.00 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 44 Clamped VBA voltage VBAclmp
Figure 41 PWM-OP Gain AV

Version 2.0 26 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Typical Controller Performance Characteristics

4.10 3.70
Blanking time voltage limit VBKC3 [V]

Active Burst Model Leve VFBC6a [V]

4.08 3.68

4.06 3.66

4.04 3.64

4.02 3.62

PI-024-8889A23
PI-021-8889A23
4.00 3.60

3.98 3.58

3.96 3.56

3.94 3.54

3.92 3.52

3.90 3.50
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125

Junction Temperature [°C] Junction Temperature [°C]

Figure 45 Blanking time voltage limit VBKC3 Figure 48 Active Burst Mode Level VFBC6a

3.30
4.70
Active Burst Mode Level VFBC6b [V]

3.25
Over Load detection limit VFBC4 [V]

4.65
3.20

4.60 3.15

3.10
4.55

PI-025-8889A23
3.05
PI-022-8889A23

4.50
3.00
4.45
2.95

4.40 2.90

2.85
4.35
2.80
4.30 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 49 Active Burst Mode Level VFBC6b
Figure 46 Over Load Detection Limit VFBC4

1.40
21.0
Overvoltage Detection Limit VVCCovp1 [V]
Active Burst mode Level VFBC5 [V]

1.36
20.9
1.32
20.8
1.28
20.7
1.24
20.6
PI-023-8889A23

PI-026-8889A23

1.20
20.5
1.16
20.4
1.12
20.3
1.08
20.2
1.04
20.1
1.00
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 20.0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 47 Active Burst Mode Level VFBC5
Figure 50 Overvoltage Detection Limit VVCCOVP1

Version 2.0 27 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Typical Controller Performance Characteristics

1.20
Overvoltage Detection Level VVCCOVP2 [V]

26.0
1.16

Peak Current Limitation VCSth [V]

25.9

25.8 1.12

25.7 1.08

25.6 1.04

PI-031-8889A23
PI-027-8889A23
25.5 1.00

25.4 0.96

25.3 0.92

0.88
25.2
0.84
25.1
0.80
25.0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]

Figure 51 Over Load Detection Limit VVCCOVP2 Figure 54 Peak Current Limitation Vcsth

0.30
0.38
0.29
Peak Current Limitation VCS2 [V]

0.37
Auto-restart Enable Level V AE [V]

0.28
0.36
0.27
0.35
0.26
0.34

PI-032-8889A23
0.25
PI-028-8889A23

0.33
0.24
0.32
0.23
0.31
0.22
0.30
0.21
0.29
0.20
0.28 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]

Figure 52 Auto-restart Enable Level VAE Figure 55 Peak Current Limitation VCS2

290
15.0
280
Charging Current at BA pin IBK [µA]

Leading Edge Blanking tLEB [ns]

14.5
270
14.0
260
13.5
250
13.0
PI-033-8889A23
PI-029-8889A23

240
12.5
230
12.0
220
11.5
210
11.0
200
10.5
190
10.0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 53 Charging Current at BA pin IBK Figure 56 Leading Edge Blanking tLEB

Version 2.0 28 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Typical CoolMOS® Performance Characteristics

6 Typical CoolMOS® Performance Characteristics

30 5

25
4 Vcc > 10.5V

20
3
P tot [W]

ID [A]
15
2
10

1
5

0 0
0 40 80 120 160 0 5 10 15 20
T C [°C] VDS [V]

Figure 57 Power dissipation; Ptot=f(TC) Figure 60 Typ. output characteristics;

ID=f(VDS),Tj=25°C, parameter : VCC

Ugs 8 V, T 150 C

2.5
1
10 limited by on-state resistance
Vcc>10.5V

2
1 µs

1.5
10 µs
I D [A]
I D [A]

100 µs
0
10
1 ms 1

10 ms
0.5
DC

0
10
-1 0 5 10 15 20
0 1 2 3
10 10 10 10 V DS [V]
V DS [V]

Figure 58 Safe operation area; ID=f(VDS), parameter : Figure 61 Typ. output characteristics;
D=0, TC=25°C ID=f(VDS),Tj=150°C, parameter : VCC

15
101
14
13 vcc > 10.5 V
0.5
12
11
R DS(on) [:]
ZthJC [K/W]

0.2
0
10
10 0.1
9
0.05
0.02 8
0.01 7
single pulse
6
5
-1
10 0 1 2 3 4
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10 I D [A]
tp [s]

Figure 59 Transient thermal impedance; Figure 62 Typ. drain-source on-state resistance;

ZthJC=f(tp),parameter: D=tp/T RDS(on)=f(ID); Tj=150°C, parameter : VCC

Version 2.0 29 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Typical CoolMOS® Performance Characteristics

8 103

7
Ciss
6
2
10
R DS(on) [:]

C [pF]
98 %
4
Coss
1
3 typ 10
Crss

1
0
-60 -20 20 60 100 140 180 10
0 100 200 300 400 500
T j [°C]
V DS [V]

Figure 63 Drain-source on-state resistance; Figure 66 Typ. capacitances;

RDS(on)=f(Tj); ID=1A;, Vcc>10.5V C=f(VDS),VGS=0V,f=1MHz

2
50

1.6
40

1.2
Eoss [µF]

30
E AS [mJ]

0.8
20

0.4
10

0 0
20 60 100 140 180 0 100 200 300 400 500 600
T j [°C] VDS [V]

Figure 64 Avalanche energy; Figure 67 Typ. Coss stored energy; Eoss=f(VDS)

EAS=f(Tj),ID=0.7A,VDD=50V

700

660
V BR(DSS) [V]

620

580

540
-60 -20 20 60 100 140 180
T j [°C]

Figure 65 Drain-source breakdown voltage;

VBR(DSS)=f(Tj), ID=0.25mA

Version 2.0 30 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Input Power Curve

7 Input Power Curve

Two input power curves giving the typical input power versus ambient temperature are showed below;
Vin=85Vac~265Vac (Figure 68) and Vin=230Vac+/-15% (Figure 69). The curves are derived based on a typical
discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondary
to primary reflected voltage (higher priority). The calculation is based on RthSA=2.7K/W as heatsink and
RthCS=1.1K/W as thermal grease thermal resistance. The input power already includes the power loss at input
common mode choke, bridge rectifier and the CoolMOS. The device saturation current (ID_Puls @ Tj=125°C) is also
considered.
To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient
temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 68),
operating temperature is 50°C, estimated efficiency is 80%, then the estimated output power is 64.8W (81W *
80%).
90

80
Input power (85~265Vac) [W]

70

60

PI-005-ICE3BR2565JF_85Vac
50

40

30

20

10

0
0 10 20 30 40 50 60 70 80 90 100 110 120 130
Ambient Temperature [°C]

Figure 68 Input power curve Vin=85~265Vac; Pin=f(Ta)

110

100

90
Input power (230Vac) [W]

80

70
PI-006-ICE3BR2565JF_230Vac

60

50

40

30

20

10

0
0 10 20 30 40 50 60 70 80 90 100 110 120 130
Ambient Temperature [°C]

Figure 69 Input power curve Vin=230Vac+/-15%; Pin=f(Ta)

Version 2.0 31 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Outline Dimension

8 Outline Dimension

PG-TO220-6-247
(PB-free Plating FullPak
Package Outline)

Figure 70 PG-TO220-6-247 (PB-free Plating FullPak Package)

Dimensions in mm

Version 2.0 32 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Marking

9 Marking
Marking

Figure 71 Marking for ICE3BR2565JF

Version 2.0 33 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Schematic for recommended PCB layout

10 Schematic for recommended PCB layout

TR1

BR1 R11 C12

Spark Gap 3 D21
FUSE1 C11
X-CAP Vo
L bulk cap
L1 D11
Spark Gap 1 C1
C21
GND
Spark Gap 2 D11
Spark Gap 4 Z11
GND
N IC11
C2 C3 R12
C16
R21
CS DRAIN R13
Y-CAP Y-CAP C4 D13
R14
Y-CAP
F3
BA
CoolSET VCC
R23 R22
GND FB NC
C22

C13 C15

C23
* C14 R24

IC12 IC21

R25
F3 CoolSET schematic for recommended PCB layout

Figure 72 Schematic for recommended PCB layout

General guideline for PCB layout design using F3/F3R CoolSET (refer to Figure 72):
1. “Star Ground “at bulk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device
effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of
IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 72):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5mm (no safety concern)

Version 2.0 34 11 Sep 2008

 CoolSET®-F3R
ICE3BR2565JF
Schematic for recommended PCB layout

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and
reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through
the sensitive components such as the primary controller, IC11.

Version 2.0 35 11 Sep 2008

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