University of Tripoli

Faculty of Engineering
Department of Electrical and Electronic Engineering

EE219 Basic Electronic Circuits

Fall 2022
Eng. Taissir Y. Elganimi

Design of Bipolar Junction Transistor (BJT) Amplifiers

1. BJT Amplifier Biasing Design:
For the amplifier circuit shown in Figure (A) as an example, the DC equivalent circuit as shown in Figure
(B) can be simplified by Thevenin theorem as shown in Figure (C).

Figure (A)

Figure (B) Figure (C)

By applying Thevenin theorem,

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EE219 - Basic Electronic Circuits Design of BJT Amplifiers Prepared by Eng. Taissir Y. Elganimi

𝑅1 𝑅2 𝑅2 𝑅1 𝑅2
𝑅𝐵 = 𝑅1 //𝑅2 = & 𝑉𝐵𝐵 = 𝑉𝐶𝐶 = 𝑉𝐶𝐶
𝑅1 + 𝑅2 𝑅1 + 𝑅2 𝑅1 𝑅1 + 𝑅2
𝑅𝐵
∴ 𝑉𝐵𝐵 = 𝑉𝐶𝐶 (𝑅1 𝐷𝑒𝑠𝑖𝑔𝑛 𝐸𝑞𝑢𝑎𝑡𝑖𝑜𝑛)
𝑅1
And it can be rewritten as follows:
𝑅2 𝑉𝐶𝐶 𝑅1 𝑅1 𝑅𝐵 (𝑉𝐶𝐶 ⁄𝑉𝐵𝐵 )
𝑉𝐵𝐵 = 𝑉𝐶𝐶 → = 1+ → 𝑅2 = =
𝑅1 + 𝑅2 𝑉𝐵𝐵 𝑅2 (𝑉𝐶𝐶 ⁄𝑉𝐵𝐵 ) − 1 (𝑉𝐶𝐶 ⁄𝑉𝐵𝐵 ) − 1
𝑅𝐵
∴ 𝑅2 = (𝑅2 𝐷𝑒𝑠𝑖𝑔𝑛 𝐸𝑞𝑢𝑎𝑡𝑖𝑜𝑛)
1 − (𝑉𝐵𝐵 ⁄𝑉𝐶𝐶 )
And for stability, choose:
𝑅𝐵 ≤ 0.1𝛽𝑅𝐸 (𝑅𝐵 𝐷𝑒𝑠𝑖𝑔𝑛 𝐶𝑜𝑛𝑑𝑖𝑡𝑖𝑜𝑛)
---------------------------------------------------------------------------------------------------

2. DC and ac Load Lines:

To find the DC operating point (𝑉𝐶𝐸𝑄 , 𝐼𝐶𝑄 ) of this circuit, KVL can be applied with considering each
capacitor acts as an open circuit, and the ac voltage source is a short circuit:
𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 = 0
• In order to draw the DC load line, find two points on this DC load line equation:
The first point is when 𝐼𝐶 = 0 → 𝑉𝐶𝐸 = 𝑉𝐶𝐶 .
𝑉𝐶𝐶
The second point is when 𝑉𝐶𝐸 = 0 → 𝐼𝐶 = 𝑅
𝑅𝐶 + 𝐸
𝛼

• In order to draw the ac load line, find the ac load line equation with considering each capacitor acts as
a short circuit, and the DC and ac voltage sources are short circuit.
By writing the KVL expression as:
0 − 𝑖𝑐 (𝑅𝐶 //𝑅𝐿 ) − 𝑣𝑐𝑒 = 0
where 𝑖𝑐 is the ac collector current, and 𝑣𝑐𝑒 is the ac collector-to-emitter voltage.
Since the total instantaneous collector current can be expressed as:
𝑖𝐶 = 𝐼𝐶𝑄 + 𝑖𝑐

And the total instantaneous collector-to-emitter voltage can be expressed as:

𝑣𝐶𝐸 = 𝑉𝐶𝐸𝑄 + 𝑣𝑐𝑒

The last KVL expression can be rewritten as follows:

0 − (𝑖𝐶 − 𝐼𝐶𝑄 )(𝑅𝐶 //𝑅𝐿 ) − (𝑣𝐶𝐸 − 𝑉𝐶𝐸𝑄 ) = 0

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EE219 - Basic Electronic Circuits Design of BJT Amplifiers Prepared by Eng. Taissir Y. Elganimi

Or:
𝑉𝐶𝐸𝑄 𝑣𝐶𝐸
𝑖𝐶 = 𝐼𝐶𝑄 + −
𝑅𝐶 //𝑅𝐿 𝑅𝐶 //𝑅𝐿
This is the ac load line equation.
We need to find two points on the ac load line equation to draw it with the DC load line equation as follows:
The first point is when 𝑖𝐶 = 0 → 𝑣𝐶𝐸 = 𝑉𝐶𝐸𝑄 + 𝐼𝐶𝑄 𝑅𝑎𝑐 .

where 𝑅𝑎𝑐 = 𝑅𝐶 //𝑅𝐿 .

𝑉𝐶𝐸𝑄
The second point is when 𝑣𝐶𝐸 = 0 → 𝑖𝐶 = 𝐼𝐶𝑄 + 𝑅 .
𝐶 //𝑅𝐿

Note that at the Q-point with 𝑣𝐶𝐸 = 𝑉𝐶𝐸𝑄 , the currents 𝑖𝐶 and 𝐼𝐶𝑄 will be equal. Therefore, the ac load line
passes through the Q-point of the DC load line as shown below.
Then, the DC and ac load lines can be plotted as follows:
𝑖𝐶 (𝑚𝐴)
𝑉𝐶𝐸𝑄
𝐼𝐶𝑄 + 𝑅
𝐶 //𝑅𝐿
ac Load Line

𝐼𝐶𝑄 Q-point

DC Load Line

0 𝑉𝐶𝐸𝑄 𝑉𝐶𝐶 𝑣𝐶𝐸 (𝑉)

𝑉𝐶𝐸𝑄 𝐼𝐶𝑄 𝑅𝑎𝑐

As it is shown, the ac load line limits the voltage swing to the minimum 𝑉𝐶𝐸𝑄 and 𝐼𝐶𝑄 𝑅𝑎𝑐 . Thus, the
maximum voltage variation from the Q-point is the minimum of 𝑉𝐶𝐸𝑄 and 𝐼𝐶𝑄 𝑅𝑎𝑐 , without clipping at the
output voltage waveform.
When a sinusoidal wave signal is applied to the base of a BJT amplifier, it will vary the base current 𝑖𝐵
which will produce 𝑖𝐵 (𝑝𝑝) and therefore 𝑖𝐶 (𝑝𝑝) and 𝑣𝐶𝐸 (𝑝𝑝). Then, 𝑣𝐶𝐸 (𝑝𝑝) will become the output
voltage at the collector of this circuit (Common Emitter Amplifier without 𝑅𝐸 ).
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EE219 - Basic Electronic Circuits Design of BJT Amplifiers Prepared by Eng. Taissir Y. Elganimi

If the Q-point is at a high collector current 𝐼𝐶𝑄 , the lower half cycle of the output voltage wave will be
clipped due to the saturate 𝐼𝐶 as shown above.
Similarly, if the Q-point is at a low collector current 𝐼𝐶𝑄 , the upper half cycle of the output voltage wave
will be clipped due to the cutoff 𝐼𝐶 as shown below:
𝑖𝐶 (𝑚𝐴)
𝑉𝐶𝐸𝑄
𝐼𝐶𝑄 + 𝑅
𝐶 //𝑅𝐿

ac Load Line

𝐼𝐶𝑄 Q-point
DC Load Line

0 𝑉𝐶𝐸𝑄 𝑉𝐶𝐶 𝑣𝐶𝐸 (𝑉)

𝑉𝐶𝐸𝑄 𝐼𝐶𝑄 𝑅𝑎𝑐

---------------------------------------------------------------------------------------------------

3. BJT Optimum Q-point Design:

For maximum output voltage swing, we need 𝑖𝐶 = 2𝐼𝐶𝑄 when 𝑣𝐶𝐸 = 0. In other words, we need 𝑉𝐶𝐸𝑄 to be
equal to 𝐼𝐶𝑄 𝑅𝑎𝑐 .

∴ 𝑉𝐶𝐸𝑄 = 𝑉𝐶𝐶 − 𝐼𝐶𝑄 𝑅𝐷𝐶 = 𝐼𝐶𝑄 𝑅𝑎𝑐

𝑅𝐸
where 𝑅𝐷𝐶 = 𝑅𝐶 + in this example.
𝛼

𝑉𝐶𝐶
∴ 𝐼𝐶𝑄 = (𝑂𝑝𝑡𝑖𝑚𝑢𝑚 𝐼𝐶𝑄 𝐷𝑒𝑠𝑖𝑔𝑛 𝐸𝑞𝑢𝑎𝑡𝑖𝑜𝑛)
𝑅𝐷𝐶 + 𝑅𝑎𝑐
If the input wave increases the base current wave 𝑖𝐵 , then both 𝑖𝐶 and 𝑣𝐶𝐸 will be increased where both half
cycles of the output voltage waveform will be clipped simultaneously due to cutoff and saturation in the
case of the optimum collector current, and the peak-to-peak output voltage swing (before clipping) will be
equal to 2𝐼𝐶𝑄 𝑅𝑎𝑐 as shown below:

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EE219 - Basic Electronic Circuits Design of BJT Amplifiers Prepared by Eng. Taissir Y. Elganimi

𝑖𝐶 (𝑚𝐴)
𝑉𝐶𝐸𝑄
𝐼𝐶𝑄 + 𝑅
𝐶 //𝑅𝐿

ac Load Line

𝐼𝐶𝑄 Q-point
DC Load Line

0 𝑉𝐶𝐸𝑄 𝑉𝐶𝐶 𝑣𝐶𝐸 (𝑉)

𝑉𝐶𝐸𝑄 𝐼𝐶𝑄 𝑅𝑎𝑐

Good luck…