The document describes the Simple As Possible Computer (SAP-2), a simple 8-bit microprocessor. It includes tables listing the mnemonics and opcodes used by the SAP-2 instruction set. An example program is shown using SAP-2 instructions like MVI, ADD, STA, INR and HLT. The execution of the LDA (Load Accumulator) instruction is explained over 9 clock cycles, showing how it uses the Program Counter, Memory Address Register and other components to retrieve the data from memory.
The document describes the Simple As Possible Computer (SAP-2), a simple 8-bit microprocessor. It includes tables listing the mnemonics and opcodes used by the SAP-2 instruction set. An example program is shown using SAP-2 instructions like MVI, ADD, STA, INR and HLT. The execution of the LDA (Load Accumulator) instruction is explained over 9 clock cycles, showing how it uses the Program Counter, Memory Address Register and other components to retrieve the data from memory.
The document describes the Simple As Possible Computer (SAP-2), a simple 8-bit microprocessor. It includes tables listing the mnemonics and opcodes used by the SAP-2 instruction set. An example program is shown using SAP-2 instructions like MVI, ADD, STA, INR and HLT. The execution of the LDA (Load Accumulator) instruction is explained over 9 clock cycles, showing how it uses the Program Counter, Memory Address Register and other components to retrieve the data from memory.
The document describes the Simple As Possible Computer (SAP-2), a simple 8-bit microprocessor. It includes tables listing the mnemonics and opcodes used by the SAP-2 instruction set. An example program is shown using SAP-2 instructions like MVI, ADD, STA, INR and HLT. The execution of the LDA (Load Accumulator) instruction is explained over 9 clock cycles, showing how it uses the Program Counter, Memory Address Register and other components to retrieve the data from memory.
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET Mnemonics and Op-code Mnemonics Op code Mnemonics Op code ADD B 80H HLT 76H ADD C 81H IN byte DBH ANA B A0H INR A 3CH ANA C A1H INR B 04H ANI byte E6H INR C 0CH CALL address CDH JM address FAH CMA 2FH JMP address C3H DCR A 3DH JNZ address C2H DCR B 05H JZ address CAH DCR C 0DH LDA address 3AH
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET Mnemonics and Op-code Mnemonics Op code Mnemonics Op code MOV A,B 78H ORA C B1H MOV A,C 79H ORI byte F6H MOV B,A 47H OUT byte D3H MOV B,C 41H RAL 17H MOV C,A 4FH RAR 1FH MOV C,B 48H RET C9H MOV A,byte 3EH STA address 32H MOV B,byte 06H SUB B 90H MOV C,byte 0EH SUB C 91H NOP 00H XRA B A8H ORA B B0H XRA C A9H S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET Example Mnemonics Opcode MVI A,17H MVI A,byte 3E H MVI B,2DH MVI B,byte 06 H ADD B ADD B 80 H STA address 32 H STA 5600H INR A 3C H INR A MOV C,A 4F H
MOV C,A HLT 76 H
HLT
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA address LDA 8000H : Load the accumulator with the content of address 8000H
RAM address Content
2000H 3A H 2001H 00 H 2002H 80 H
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H T1 State: Address State Ø Output of PC is 2000H Ø 2000H is sent to the W bus Ø MAR loads 2000H Ø The content of address 2000H of RAM is available S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H T2 state: Increment State Ø PC has increased its value to 2001H Ø 2001H is now available at PC’s output
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H T3 State: Memory State Ø MDR enables the content of RAM address to W bus Ø IR loads the content
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H Execution Cycle: T4
Ø PC’s output 2001H is
enabled to W bus Ø Content of W bus is loaded to MAR
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H Execution Cycle: T5 Ø PC increases its output to 2002H Ø Content of address 2001H is enabled to W bus and loaded to B register
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H Execution Cycle: T6 Ø PC’s output 2002H is enabled to W bus Ø Content of W bus is loaded to MAR
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H Execution Cycle: T7 Ø PC increases its value to 2003H Ø Content of 2002H is enabled to W bus and loaded to C register
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H Execution Cycle: T8 Ø Contents of B & C registers are enabled to W bus to create the 16 bit address 8000H Ø 16 bit address is then loaded to MAR
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET LDA 8000H Execution Cycle: T9 Ø Content of memory address 8000H is enabled to W bus Ø Content of W bus is loaded to the Accumulator
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET JUMP Instruction Ø Instead of fetching the next instruction in the usual way, jumps to another part of program, e.g. JMP 3000H Ø Unconditional Jump
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET JUMP Instruction Ø JM 3000H : Jump to address 3000H if the sign flag is 1 (content of accumulator is -ve) Ø Otherwise fetch the next instruction at 2006H Ø Conditional Jump
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET CALL and RET Ø CALL 5000H : Call the subroutine starting from 5000H Ø RET : return, Have to return to the address next to the address where CALL 5000H was stored Ø CALL is unconditional
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET CALL and RET Ø When CALL is executed, the content of PC is automatically saved in memory locations FFFEH and FFFFH Ø Infinite Loop?
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET Thank You
S. M. Raiyan Chowdhury June 10, 2023 CSE 442: Microprocessor and Interfacing Lecturer, EEE, EWU Grad Student, EEE, BUET
