Isow7741 q1

ISOW7741-Q1, ISOW7742-Q1
SLLSFK3 – NOVEMBER 2022
ISOW774x-Q1 Quad-Channel Digital Isolator with Integrated Low-Emissions, Low-

Noise DC-DC Converter
1 Features 2 Applications
• Qualified for automotive applications • Hybrid, electric and power train system (EV/HEV)
• AEC-Q100 qualified with the following results: – Battery management system (BMS)
– Device temperature Grade 1: –40°C to +125°C – On-board charger (OBC)
ambient temperature range – Traction inverter
• 100 Mbps data rate – DC/DC converter
• Integrated DC-DC converter with low-emissions,
low-noise
3 Description
– Emission optimized to meet CISPR25 The ISOW7741-Q1 and ISOW7742-Q1 devices are
– Low frequency power converter at 25 MHz galvanically-isolated quad-channel digital isolator with
enabling low noise performance an integrated high-efficiency power converter with low
– Low output ripple: 24 mV emissions. The integrated DC-DC converter provides
• High efficiency output power up to 550 mW of isolated power, eliminating the
– Efficiency at max load: 46% need for a separate isolated power supply in space-
– Up to 0.55-W output power constrained isolated designs.
– VISOOUT accuracy of 5% Device Information
– 5 V to 5 V: Max available load current = 110 mA ISOW774x-Q1
– 5 V to 3.3 V: Max available load current = 140 FEATURE
ISOW774xF-Q1
mA
Surge Test Voltage 10 kVPK
– 3.3 V to 3.3 V: Max available load current = 60
mA Isolation Rating 5000 VRMS
• Independent power supply for channel isolator & Working Voltage 1000 VRMS/1500VPK
power converter Package DFM (20)
– Logic supply (VIO): 1.71-V to 5.5-V Body Size (Nom) 12.83 mm × 7.5 mm
– Power converter supply (VDD): 3-V to 5.5-V
• Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity VIO VISOIN
– ±8 kV IEC 61000-4-2 contact discharge EN_IO2

protection across isolation barrier INA Tx Rx OUTA
• Reinforced and Basic isolation options INB Tx Rx OUTB

• High CMTI: 100-kV/µs (typical)
Rx OUTC
• Safety Related Certifications: INC Tx
– VDE reinforced and basic insulation per DIN OUTD Rx Tx IND

EN_IO1
EN IEC 60747-17 (VDE 0884-17) GNDIO GISOIN
– UL 1577 component recognition program GND1 GN
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and D2
GB 4943.1-2011 certifications VDD VSEL
– ISOW774xB devices are planned DC-DC

Primary
DC-DC
Secondary
EN/FLT VISOOUT
• Extended temperature range: –40°C to +125°C
• 20-pin wide body SOIC package GND1 GND2
ISOW7741-Q1 Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLLSFK3 – NOVEMBER 2022 www.ti.com
Table of Contents
1 Features............................................................................1 7.18 Supply Current Characteristics Channel
2 Applications..................................................................... 1 Isolator - VIO, VISOIN = 1.8-V........................................19
3 Description.......................................................................1 7.19 Switching Characteristics - 5-V Supply................... 21
4 Revision History.............................................................. 2 7.20 Switching Characteristics - 3.3-V Supply................ 22
5 Description (continued).................................................. 3 7.21 Switching Characteristics - 2.5-V Supply................ 23
6 Pin Configuration and Functions...................................4 7.22 Switching Characteristics - 1.8-V Supply................ 24
7 Specifications.................................................................. 6 7.23 Insulation Characteristics Curves........................... 25
7.1 Absolute Maximum Ratings........................................ 6 7.24 Typical Characteristics............................................ 26
7.2 ESD Ratings............................................................... 6 8 Parameter Measurement Information.......................... 31
7.3 Recommended Operating Conditions.........................7 9 Detailed Description......................................................33
7.4 Thermal Information....................................................8 9.1 Overview................................................................... 33
7.5 Power Ratings.............................................................8 9.2 Functional Block Diagram......................................... 34
7.6 Insulation Specifications............................................. 9 9.3 Feature Description...................................................35
7.7 Safety-Related Certifications.................................... 10 9.4 Device Functional Modes..........................................38
7.8 Safety Limiting Values...............................................10 10 Application and Implementation................................ 40
7.9 Electrical Characteristics - Power Converter.............11 10.1 Application Information........................................... 40
7.10 Supply Current Characteristics - Power 10.2 Typical Application.................................................. 40
Converter.....................................................................12 11 Power Supply Recommendations..............................44
7.11 Electrical Characteristics Channel Isolator - 12 Layout...........................................................................45
VIO, VISOIN = 5-V..........................................................13 12.1 Layout Guidelines................................................... 45
7.12 Supply Current Characteristics Channel 12.2 Layout Example...................................................... 46
Isolator - VIO, VISOIN = 5-V...........................................13 13 Device and Documentation Support..........................47
7.13 Electrical Characteristics Channel Isolator - 13.1 Device Support....................................................... 47
VIO, VISOIN = 3.3-V.......................................................15 13.2 Documentation Support.......................................... 47
7.14 Supply Current Characteristics Channel 13.3 Receiving Notification of Documentation Updates..47
Isolator - VIO, VISOIN = 3.3-V........................................15 13.4 Support Resources................................................. 47
7.15 Electrical Characteristics Channel Isolator - 13.5 Trademarks............................................................. 47
VIO, VISOIN = 2.5-V.......................................................17 13.6 Electrostatic Discharge Caution..............................47
7.16 Supply Current Characteristics Channel 13.7 Glossary..................................................................47
Isolator - VIO, VISOIN = 2.5-V........................................17 14 Mechanical, Packaging, and Orderable
7.17 Electrical Characteristics Channel Isolator - Information.................................................................... 48
VIO, VISOIN = 1.8-V.......................................................19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
November 2022 * Initial release.
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: ISOW7741-Q1 ISOW7742-Q1

www.ti.com SLLSFK3 – NOVEMBER 2022
5 Description (continued)
The high-efficiency of the power converter allows for operation at a wide operating ambient temperature range
of –40°C to +125°C. This device provides improved emissions performance, allowing for simplified board design
and has provisions for ferrite beads to further attenuate emissions. The ISOW7741-Q1 and ISOW7742-Q1 has
been designed with enhanced protection features in mind, including soft-start to limit inrush current, over-voltage
and under-voltage lock out, fault detection on the EN/FLT pin, overload and short-circuit protection, and thermal
shutdown.
The ISOW7741-Q1 and ISOW7742-Q1 devices provide high electromagnetic immunity while isolating CMOS or
LVCMOS digital I/Os. The signal-isolation channel has a logic input and output buffer separated by a double
capacitive silicon dioxide (SiO2) insulation barrier, whereas, power isolation uses on-chip transformers separated
by thin film polymer as insulating material. If the input signal is lost, the default output is high for the ISOW7741-
Q1 and ISOW7742-Q1 devices without the F suffix and low for the ISOW7741F-Q1 and ISOW7742-Q1 devices
with the F suffix. The ISOW774x-Q1 can operate from a single supply voltage of 3 V to 5.5 V by connecting VIO
and VDD together on PCB. If lower logic levels are required, these devices support 1.71 V to 5.5 V logic supply
(VIO) that can be independent from the power converter supply (VDD) of 3 V to 5.5 V. VISOIN and VISOOUT needs
to be connected on board with either a ferrite bead or fed through a LDO.
These devices help prevent noise currents on data buses, such as CAN and LIN, or other circuits from entering
the local ground and interfering with or damaging sensitive circuitry. Through innovative chip design and layout
techniques, electromagnetic compatibility of the device has been significantly enhanced to ease system-level
ESD, EFT, surge and emissions compliance. The device is available in a 20-pin SOIC wide-body (SOIC-WB)
DFM package.
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

6 Pin Configuration and Functions
VIO 1 20 VISOIN
INA 2 19 OUTA
INB 3 18 OUTB
INC 4 17 OUTC
I S O LAT I O N
OUTD 5 16 IND
GNDIO 6 15 GISOIN
EN_IO1 7 14 EN_IO2
EN/FLT 8 13 VSEL
VDD 9 12 VISOOUT
GND1 10 11 GND2
Figure 6-1. ISOW7741-Q1 DFM Package 20-Pin SOIC-WB Top View
VIO 1 20 VISOIN
INA 2 19 OUTA
INB 3 18 OUTB
OUTC 4 17 INC
I S O LAT I O N
OUTD 5 16 IND
GNDIO 6 15 GISOIN
EN_IO1 7 14 EN_IO2
EN/FLT 8 13 VSEL
VDD 9 12 VISOOUT
GND1 10 11 GND2
Figure 6-2. ISOW7742-Q1 DFM Package 20-Pin SOIC-WB Top View
PIN
NO. I/O DESCRIPTION
NAME
ISOW7741-Q1 ISOW7742-Q1
GNDIO 6 6 — Ground connection for VIO. GND1 and GNDIO needs to be shorted on board.
GND1 10 10 — Ground connection for VDD. GND1 and GNDIO needs to be shorted on board.
Ground connection for VISOOUT. GND2 and GISOIN pins can be shorted on board or
GND2 11 11 —
connected through a ferrite bead. See the Layout Section for more information.
Ground connection for VISOIN. GND2 and GISOIN pins can be shorted on board or
GISOIN 15 15 —
connected through a ferrite bead. See the Layout Section for more information.
INA 2 2 I Input channel A

PIN
NO. I/O DESCRIPTION
NAME
ISOW7741-Q1 ISOW7742-Q1
INB 3 3 I Input channel B
INC 4 17 I Input channel C
IND 16 16 I Input channel D
OUTA 19 19 O Output channel A
OUTB 18 18 O Output channel B
OUTC 17 4 O Output channel C
OUTD 5 5 O Output channel D

Output Enable 1: When EN_IO1 is high or open then the channel output pins on side
1 are enabled. When EN_IO1 is low then the channel output pins on side 1 are in
EN_IO1 7 7 I
a high impedance state and the transmitter of the channel input pins on side 1 are
disabled.
Output Enable 2: When EN_IO2 is high or open then the channel output pins on side
2 are enabled. When EN_IO2 is low then the channel output pins on side 2 are in
EN_IO2 14 14 I
a high impedance state and the transmitter of the channel input pins on side 2 are
disabled.
Multi-function power converter enable input pin or fault output pin. Can only be used
as either an input pin or an output pin.
Power converter enable input pin: enables and disables the integrated DC-DC power
converter. Connect directly to microcontroller or through a series current limiting
resistor to use as an enable input pin. DC-DC power converted is enabled when
EN/FLT 8 8 I/O EN/FLT is high to the VIO voltage level and disabled when low at GND1 voltage level.
Fault output pin: Alert signal if power converter is not operating properly. This pin is
active low. Connect to microcontroller through a 5 kΩ or greater pull-up resistor in
order to use as a fault outpin pin.
See Section 9.3.3 for more information
VISOOUT selection pin. VISOOUT = 5 V when VSEL shorted to VISOOUT. VISOOUT = 3.3
VSEL 13 13 I V, when VSEL shorted to GND2. For more information see the Device Functional
Modes.
VIO 1 1 — Side 1 logic supply.
VDD 9 9 — Side 1 DC-DC converter power supply.
Side 2 supply voltage for isolation channels. VISOIN and VISOOUT pins can be shorted
VISOIN 20 20 — on board or connected through a ferrite bead. See Application and Implementation
for more information.
Isolated power converter output voltage. VISOIN and VISOOUT pins can be shorted on
VISOOUT 12 12 — board or connected through a ferrite bead. See Application and Implementation for
more information.

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDD Power converter supply voltage –0.5 6 V
VISOIN Isolated supply voltage, input supply for secondary side isolation channels –0.5 6 V
Isolated supply voltage, Power converter output
VISOOUT –0.5 4 V
VSEL shorted to GND2
Isolated supply voltage, Power converter output
VISOOUT –0.5 6 V
VSEL shorted to VISOOUT
VIO Primary side logic supply voltage –0.5 6 V
Voltage at INx, OUTx, EN_IOx(3) –0.5 VSI + 0.5 V
V Voltage at EN/FLT –0.5 VSI + 0.5 V
Voltage at VSEL –0.5 VISOOUT + 0.5 V
IO Maximum output current through data channels –15 15 mA
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD, VISOIN VISOOUT, and VIO are with respect to the local ground pin (GND1 or GND2). All voltage values except differential I/O bus
voltages are peak voltage values.
(3) VSI = input side supply; Cannot exceed 6 V.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1)
±3000
HBM ESD Classification Level 2
Electrostatic Charged-device model (CDM), per AEC Q100-011
V(ESD) ±1500 V
discharge CDM ESD Classification Level C6
Contact discharge per IEC 61000-4-2(2)
±8000
Isolation barrier withstand test
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.

7.3 Recommended Operating Conditions

Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 =
GISOIN (unless otherwise noted)
MIN NOM MAX UNIT
Power Converter
Power converter supply 3.3 V operation 2.97 3.3 3.63 V

VDD
voltage 5 V operation 4.5 5 5.5 V
Positive threshold when
Positive threshold when power
VDD(UVLO+) power converter supply is 2.7 2.95 V
converter supply is rising
rising
Positive threshold when
Positive threshold when power
VDD(UVLO-) power converter supply is 2.40 2.55 V
converter supply is falling
falling
Power converter supply Power converter supply voltage
VDD(HYS) 0.15 V
voltage hysteresis hysteresis
Channel Isolation
1.8 V operation 1.71 1.89 V
VIO, VISOIN (3) Channel logic supply voltage
2.5 V, 3.3 V, and 5 V operation 2.25 5.5 V
VIO(UVLO+) Rising threshold of logic supply voltage 1.55 1.7 V
VIO(UVLO-) Falling threshold of logic supply voltage 1.0 1.41 V
VIO(HYS) Logic supply voltage hysteresis 75 mV
VISOIN = 5 V –4 mA
VISOIN = 3.3 V –2 mA
IOH High level output current(1)
VISOIN = 5 V 4 mA
VISOIN = 3.3 V 2 mA
IOL Low level output current(1)
VISOIN = 2.5 V 1 mA
VISOIN = 1.8 V 1 mA
VIH High-level input voltage(2) 0.7 × VSI VSI V
VIL Low-level input voltage 0 0.3 × VSI V
DR Data rate 100 Mbps
Channel isolator ready after
tPWRUP VISOIN > VIO(UVLO+) 5 ms
power up or EN/FLT high
TA Ambient temperature –40 125 °C
(1) This current is for data output channel.

(2) VSI = input side supply; VSO = output side supply
(3) The channel outputs are in undetermined state when 1.89 V < VSI < 2.25 V and 1.05 V < VSI < 1.71 V

7.4 Thermal Information

ISOW774x-Q1
THERMAL METRIC(1) DFM (SOIC) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 68.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.6 °C/W
RθJB Junction-to-board thermal resistance 53.7 °C/W
ΨJT Junction-to-top characterization parameter 17.1 °C/W
ΨJB Junction-to-board characterization parameter 50.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings

VDD = VIO = 5.5 V, IISO = 110 mA, TJ = 150°C, TA ≤ 80°C, CL = 15 pF, input a 50-MHz 50% duty-cycle square wave
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation (both sides) VDD = 5.5 V, VIO = 5.5 V, VISOOUT = 1.48 W
VISOIN, IISOOUT = 100 mA, TJ = 150°C,
PD1 Maximum power dissipation (side-1) 0.74 W
TA ≤ 80°C, CL = 15 pF, input a 50-MHz
PD2 Maximum power dissipation (side-2) 50% duty-cycle square wave 0.74 W

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm
Shortest terminal-to-terminal distance across the
CPG External creepage(1) >8 mm
package surface
Minimum internal gap (internal clearance – capacitive
> 17
signal isolation)
DTI Distance through the insulation µm
Minimum internal gap (internal clearance –
>120
transformer power isolation)
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material group According to IEC 60664-1 I
Rated mains voltage ≤ 300 VRMS I-IV
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN VDE V 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM AC voltage (bipolar) 1500 VPK
voltage
AC voltage; Time dependent dielectric breakdown
1000 VRMS
VIOWM Maximum working isolation voltage (TDDB) Test
DC voltage 1500 VDC
VTEST = VIOTM; t = 60 s (qualification);
VIOTM Maximum transient isolation voltage 7071 VPK
VTEST = 1.2 × VIOTM; t = 1 s (100% production)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VIOSM Maximum surge isolation voltage(3) 6250 VPK
VTEST = 1.6 × VIOSM = 10000 VPK(qualification)
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; ≤5
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
≤5
qpd Apparent charge(4) Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s pC
Method b1, at routine test (100% production) and
preconditioning (type test),
≤5
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz ~3.5 pF
VIO = 500 V, TA = 25°C > 1012
RIO Insulation resistance(5) VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500 V, TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VISO(UL) Withstand isolation voltage VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100% 5000 VRMS
production)
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) ISOW77xx is suitable for safe electrical insulation and ISOW77xxB is suitable for basic electrical insulation only within the safety
ratings.. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.
7.7 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to DIN Recognized under Certified according to
Certified according to IEC Certified according to
EN IEC 60747-17 (VDE UL 1577 Component EN 61010-1:2010/A1:2019
62368-1, and IEC 60601-1 GB 4943.1-2011
0884-17) Recognition Program and EN 62368-1:2014
CSA 62368-1-19 and IEC
62368-1:2018 Ed. 3 and EN
62368-1:2020. (pollution degree
Reinforced insulation; 5000 VRMS Reinforced
2, material group I) 600
Maximum transient insulation per EN 61010-
VRMS (Reinforced) maximum
isolation voltage, 7071 Reinforced Insulation, 1:2010 up to working
working voltage;
VPK; Altitude ≤ 5000 m, voltage of 600 VRMS;
2 MOPP (Means of Patient Single protection, 5000
Maximum repetitive peak Tropical Climate, 700 5000 VRMS Reinforced
Protection) per CSA 60601-1:14 VRMS
isolation voltage, 1500 VRMS maximum working insulation per EN
and IEC 60601-1 Ed. 3+A1,
VPK; voltage; 62368-1:2014 up to
250 VRMS maximum working
Maximum surge isolation working voltage of 600
voltage. Temperature rating is
voltage, 6250 VPK VRMS (Reinforced)
90°C for reinforced insulation
and 125°C for basic insulation;
see certificate for details.
Certificate #: Pending Master Contract#: Pending File #: Pending Certificate #: Pending Client ID: Pending
7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
RθJA = 68.5°C/W, VI = 5.5 V, TJ = 150°C,
332
TA = 25°C
IS Safety input, output, or supply current(1) mA
RθJA = 68.5°C/W, VI = 3.6 V, TJ = 150°C,
507
TA = 25°C
PS Safety input, output, or total power(1) RθJA = 68.5°C/W, TJ = 150°C, TA = 25°C 1825 mW
TS Maximum safety temperature(1) 150 °C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use the following equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.

7.9 Electrical Characteristics - Power Converter

VDD = 5 V ±10% or 3.3 V ±10% and VISOIN power externally, GND1 = GNDIO, GND2 = GISOIN (over recommended
operating conditions, unless otherwise specified)
VDD = 5 V, VISOOUT = 5 V, VSEL = VISOOUT
VISOOUT Isolated supply voltage External IISOOUT = 0 to 55 mA 4.75 5 5.25 V
VISOOUT Isolated supply voltage External IISOOUT = 0 to 110 mA 4.5 5 5.25 V
VISOOUT(LINE
DC line regulation IISOOUT = 55 mA, VDD = 4.5 V to 5.5 V 2 mV/V
)
VISOOUT(LOA
DC load regulation IISOOUT = 0 to 110 mA 1%
D)
IISOOUT = 110 mA, CLOAD = 0.01 µF || 10 µF;

Efficiency at maximum load
EFF VI = VDD (ISOW774x-Q1); VI =0 V 46%
current (3)
(ISOW774x-Q1 with F suffix).
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP) 24 mV
(pk-pk) IISOOUT = 110 mA
DC current from VDD supply
IISOOUT_SC VISOOUT shorted to GND2 250 mA
under short circuit on VISOOUT
VDD = 5 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT Isolated supply voltage External IISOOUT = 0 to 70 mA 3.135 3.3 3.465 V
VISOOUT(LINE
)
VISOOUT(LOA
D)

current (3)
Output ripple on isolated supply 20-MHz bandwidth , CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP) 30 mV
VDD = 3.3 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT(LINE
)
VISOOUT(LOA
D)

current (3)
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP) 14 mV
(1) Power converter ILOAD = current required to power the secondary side. ILOAD does not take into account the channel isolator current.
See Supply Current Characteristics Channel Isolator section for details.

7.10 Supply Current Characteristics - Power Converter

VDD = 5 V ±10% or 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless otherwise
noted).
SUPPLY
CURRENT
Power Converter Disabled
Power converter supply
EN/FLT = GND1, VISOOUT = No ILOAD IDD 0.28 0.45 mA
current
Logic supply current EN/FLT = GND1 IIO 0.27 0.57 mA
Power Converter Enabled
VDD = 5 V, VSEL = VISOOUT ILOAD = 55 mA 115 171 mA
VDD = 5 V, VSEL = VISOOUT ILOAD = 110 mA 225 316 mA
Power converter supply VDD = 5 V, VSEL = GND2 ILOAD = 70 mA 127 169 mA
current input IDD
VDD = 5 V, VSEL = GND2 ILOAD = 140 mA 250 310 mA
VDD = 3.3 V, VSEL = GND2 ILOAD = 30 mA 74 112 mA
VDD = 3.3 V, VSEL = GND2 ILOAD = 60 mA 143 216 mA
VDD = 5 V VSEL = VISOOUT 110 mA
Power converter output
VDD = 5 V VSEL = GND2 IISOOUT 140 mA
current (1)
VDD = 3.3 V VSEL = GND2 60 mA
(1) ILOAD does not take into account the channel isolator current. See Supply Current Characteristics Channel Isolator section for details.

7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V

VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
Channel Isolation
VITH Input pin rising threshold 0.7 x VSI V
VITL Input pin falling threshold 0.3 x VSI V
Input pin threshold hysteresis
VI(HYS) 0.1 x VSI V
(INx)
IIL Low level input current VIL = 0 at INx –25 µA
IIH High level input current VIH = VSI (1) at INx 25 µA
IO = –4 mA, see Switching Characteristics VSO (1) –
VOH High level output voltage V
Test Circuit and Voltage Waveforms 0.4
IO = 4 mA, see Switching Characteristics Test
VOL Low level output voltage 0.4 V
Circuit and Voltage Waveforms
Common mode transient VI = VSI or 0 V, VCM = 1000 V; see Common-
CMTI 85 100 kV/us
immunity Mode Transient Immunity Test Circuit
7.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V

specified)
SUPPLY
CURRENT
ISOW7741-Q1 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741- IDD_IO 2.8 4.1 mA
Q1);
VI = 0 V (ISOW7741-Q1 with F suffix) IISOIN 4.3 6.3 mA
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741-Q1); IDD_IO 2.8 4.1 mA
VI = VCCI (ISOW7741-Q1 with F suffix) IISOIN 4.3 6.3 mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741-Q1); IDD_IO 2.8 4.1 mA

Channel Supply current -
DC signal IDD_IO 6.1 8.4 mA
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741-Q1);
IDD_IO 4.4 6.3 mA
1 Mbps
IISOIN 4.9 7.1 mA
Channel Supply current - All channels switching with square IDD_IO 5 7 mA

10 Mbps
AC signal wave clock input; CL = 15 pF IISOIN 6.3 8.9 mA
IDD_IO 12.2 14.2 mA
100 Mbps
IISOIN 25 32 mA
Q1);


specified)
SUPPLY
CURRENT
IDD_IO 4.2 6.3 mA
1 Mbps
IISOIN 5.1 7.2 mA
Channel Supply current - All channels switching with square IDD_IO 5.5 7.6 mA
10 Mbps
IDD_IO 16.7 20 mA
100 Mbps
IISOIN 17.33 22 mA
(1) VCCI = VIO or VISOIN

7.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V

VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
Channel Isolation
VI(HYS) 0.1 x VSI V
(INx)
IIL Low level input current VIL = 0 at INx -25 µA
CMTI 85 100 kV/us
7.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V

specified)
SUPPLY
CURRENT
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741- IDD_IO 2.8 4 mA
Q1);
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741-Q1); IDD_IO 2.8 4 mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741-Q1); IDD_IO 2.8 4 mA

IDD_IO 4.4 6.3 mA
1 Mbps
IISOIN 4.9 7.1 mA
10 Mbps
IDD_IO 9.4 12 mA
100 Mbps
IISOIN 17.5 25 mA
Q1);


specified)
SUPPLY
CURRENT
IDD_IO 4.2 6.3 mA
1 Mbps
IISOIN 5.1 7.2 mA
Channel Supply current - All channels switching with square IDD_IO 4.9 7 mA
10 Mbps
IDD_IO 13 16.6 mA
100 Mbps
IISOIN 13.7 17.5 mA


specified)
Channel Isolation
VI(HYS) 0.1 x VSI V
(INx)
CMTI 85 100 kV/us

specified)
SUPPLY
CURRENT
Q1);

IDD_IO 4.4 6.3 mA
1 Mbps
IISOIN 4.9 7.1 mA
10 Mbps
IDD_IO 8.2 11.2 mA
100 Mbps
IISOIN 14.6 18.8 mA
Q1);


specified)
SUPPLY
CURRENT
IDD_IO 4.2 6.3 mA
1 Mbps
IISOIN 5.1 7.2 mA
10 Mbps
IDD_IO 10.9 14.5 mA
100 Mbps
IISOIN 11.7 15.5 mA


specified)
Channel Isolation
VI(HYS) 0.1 x VSI V
(INx)
CMTI 85 100 kV/us

specified)
SUPPLY
CURRENT
Q1);

IDD_IO 4 5.7 mA
1 Mbps
IISOIN 4.4 6.5 mA
Channel Supply current - All channels switching with square IDD_IO 4.2 6 mA
10 Mbps
IDD_IO 6.9 9.6 mA
100 Mbps
IISOIN 12 15.8 mA
Q1);

DC signal IDD_IO 5 7.4 mA

specified)
SUPPLY
CURRENT
IDD_IO 4.2 6.3 mA
1 Mbps
IISOIN 4.5 7.2 mA
10 Mbps
IDD_IO 9.1 12.5 mA
100 Mbps
IISOIN 9.7 13.3 mA

7.19 Switching Characteristics - 5-V Supply

VISOIN = 5 V ±10%, VIO = 5 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
tPLH, tPHL Propagation delay time See Switching Characteristics Test 7.6 10.7 15.7 ns
PWD Pulse width distortion(1) |tPHL – tPLH| Circuit and Voltage Waveforms 0.9 5 ns
ENIO_tPLH, See Enable/Disable Propagation Delay
ENIO propagation delay time (opposite side) 210 473.8 ns
ENIO_tPHL Time Test Circuit and Waveform
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 4 ns
tsk(pp) Part-to-part skew time(3) 5.5 ns
tr Output signal rise time See Switching Characteristics Test 2.5 3.6 ns
tf Output signal fall time Circuit and Voltage Waveforms 2.4 3.5 ns
Channel disable propagation delay, high-to-high impedance
tPHZ 217 286 ns
output
Channel disable propagation delay, low-to-high impedance
tPLZ 217 286 ns
output
Channel enable propagation delay, high impedance-to-high
237 333 ns
output for ISOW774x-Q1 See Enable/Disable Propagation Delay
tPZH
Channel enable propagation delay, high impedance-to-high Time Test Circuit and Waveform
237 333 ns
output for ISOW774x-Q1 with F suffix
Channel enable propagation delay, high impedance-to-low
237 333 ns
output for ISOW774x-Q1
tPZL
237 333 ns
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
tDO Default output delay time from input power loss 0.1 0.3 μs
See Default Output Delay Time Test
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.7 ns
(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

7.20 Switching Characteristics - 3.3-V Supply

VISOIN = 3.3 V ±10%, VIO = 3.3 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
tPLH, tPHL Propagation delay time See Switching Characteristics Test 6 11 16.2 ns
PWD Pulse width distortion(1) |tPHL – tPLH| Circuit and Voltage Waveforms 0.6 4.7 ns
ENIO propagation delay time (opposite side) 220 474 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 4.1 ns
tr Output signal rise time See Switching Characteristics Test 1.8 2.7 ns
tPHZ 230 300.4 ns
output
tPLZ 230 299.6 ns
output
226 318.9 ns
tPZH
226 319.1 ns
225 317.9 ns
tPZL
225 317.6 ns



otherwise noted)
tPLH, tPHL Propagation delay time See Switching Characteristics Test 7.5 12 18 ns
PWD Pulse width distortion(1) |tPHL – tPLH| Circuit and Voltage Waveforms 0.36 5.1 ns
tsk(pp) Part-to-part skew time(3) 6 ns
tr Output signal rise time See Switching Characteristics Test 2 3.26 ns
tPHZ 237 326 ns
output
tPLZ 236 325 ns
output
228 360 ns
tPZH
228 360 ns
227 350 ns
tPZL
227 350 ns



otherwise noted)
tPLH, tPHL Propagation delay time See Switching Characteristics Test 7.5 15 21.5 ns
PWD Pulse width distortion(1) |tPHL – tPLH| Circuit and Voltage Waveforms 0 5.8 ns
tr Output signal rise time See Switching Characteristics Test 1.9 3 ns
tf Output signal fall time Circuit and Voltage Waveforms 1.8 3 ns
tPHZ 260 410 ns
output
tPLZ 260 406 ns
output
240 444 ns
tPZH
240 444 ns
237 439 ns
tPZL
237 439 ns


7.23 Insulation Characteristics Curves
550
VDD = VIO = VISOIN = 3.6 V
500
VDD = VIO = VISOIN = 5.5 V
450
Safety Limiting Current (mA)
400
350
300
250
200
150
100
50
0
0 20 40 60 80 100 120 140 160
Ambient Temperature (C)
Figure 7-1. Thermal Derating Curve for Safety Figure 7-2. Thermal Derating Curve for Safety
Limiting Current for DFM-20 Package Limiting Power for DFM-20 Package

7.24 Typical Characteristics
3.4 5.1
VDD = 5 V
3.38 VDD = 3.3 V 5.08
3.36 5.06
3.34 5.04
Output Voltage (V)
Output Voltage (V)

3.32 5.02
3.3 5
3.28 4.98
3.26 4.96
3.24 4.94
3.22 4.92
3.2 4.9
0 20 40 60 80 100 120 140 0 10 20 30 40 50 60 70 80 90 100 110 120
Load Current (mA) Load Current (mA)
VSEL = GND2 TA = 25°C VISOOUT = 3.3 V VSEL = VISOOUT TA = 25°C VISOOUT = 5 V
Figure 7-3. Isolated Supply Voltage (VISOOUT) vs Figure 7-4. Isolated Supply Voltage (VISOOUT) vs
Load Current (IISOOUT) Load Current (IISOOUT)
270 48
240 45
210 42
Input Supply Current (mA)
180 39
Efficiency (%)
150 36
120 33
90 30
VDD = 5 V, VISOOUT = 5 V VDD = 5 V, VISOOUT = 5 V
60 VDD = 3.3 V, VISOOUT = 3.3 V 27 VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V VDD = 5 V, VISOOUT = 3.3 V
30 24
0 21
0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140
Load Current (mA) Load Current (mA)
TA = 25°C TA = 25°C
Figure 7-5. Supply Current (IDD) vs Load Current Figure 7-6. Efficiency vs Load Current (IVISOOUT)
(IISOOUT)
800 3.35
Output Power Supply Voltage, VISOOUT (V)
3.34
700
3.33
600
Power Dissipation (mW)
3.32
500 3.31
400 3.3
3.29
300
3.28
200 VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V 3.27
100 VDD = 5 V, VISOOUT = 3.3 V 3.26
0 3.25
0 20 40 60 80 100 120 140 -40 -25 -10 5 20 35 50 65 80 95 110 125
Output Load Current (mA) Temperature (C)
TA = 25°C VSEL = GND2 VDD = 5 V No VISOOUT Load
Figure 7-7. Power Dissipation vs Load Current Figure 7-8. 3.3-V Isolated Supply Voltage (VISOOUT)
(IISOOUT) vs Free-Air Temperature

5.05 340
Output Power Supply Voltage, VISOOUT (V)
5.04 320
Short-Circuit Supply Current (mA)

5.03 300
5.02
280
5.01
260
5
240
4.99
4.98 220
4.97 200
4.96 180
4.95 160
-40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Temperature (C) Input Supply Voltage, VDD (mA)
VSEL = VISOOUT VDD = 5 V No VISOOUT Load VSEL = VISOOUT VISOOUT = GND2 TA = 25°C = GND1
Figure 7-9. 5-V Isolated Supply Voltage (VISOOUT) vs Figure 7-10. Short-Circuit Supply Current (ICC) vs
Free-Air Temperature Supply Voltage (VCC)
24 20
IIO, VIO = 5 V IIO, VIO = 5 V
22 18
IISOIN, VISOIN = 5 V IISOIN, VISOIN = 5 V
20 IIO, VIO = 3.3 V IIO, VIO = 3.3 V
IISOIN, VISOIN = 3.3 V 16 IISOIN, VISOIN = 3.3 V
18
Supply Current (mA)
Supply Current (mA)

14
16
14 12
12 10
10
8
8
6
6
4 4
2 2
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Data Rate (Mbps) Data Rate (Mbps)
CL = 15 pF TA = 25°C CL = 0 pF TA = 25°C
Figure 7-11. ISOW7741-Q1 Channel Supply Figure 7-12. ISOW7741-Q1 Channel Supply
Currents vs Data Rate For CL = 15 pF Currents vs Data Rate For CL = 0 pF
18
IIO, VIO = 5 V
16 IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
14 IISOIN, VISOIN = 3.3 V
Supply Current (mA)
12
10
2
0 10 20 30 40 50 60 70 80 90 100
Data Rate (Mbps)
CL = 15 pF TA = 25°C CL = 0 pF TA = 25°C
Figure 7-13. ISOW7742-Q1 Channel Supply Figure 7-14. ISOW7742-Q1 Channel Supply
Currents vs Data Rate For CL = 15 pF Currents vs Data Rate For CL = 0 pF

3 17
tPHL, VIO = 5 V, VISOIN = 5 V
tPLH, VIO = 5 V, VISOIN = 5 V
Power Supply UVLO Threshold (V)
2.75 16
tPHL, VIO = 5 V, VISOIN = 3.3 V
Propogation Delay Time (ns)

15 tPLH, VIO = 5 V, VISOIN = 3.3 V
2.5 tPHL, VIO = 3.3 V, VISOIN = 3.3 V
VIO UVLO+ 14 tPLH, VIO = 3.3 V, VISOIN = 3.3 V
2.25 VIO UVLO-
VISOIN UVLO+ 13
2 VISOIN UVLO-
VDD UVLO+
12
VDD UVLO-
1.75
11
1.5
10
1.25
9
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
Figure 7-16. Propagation Delay Time vs Free-Air

Figure 7-15. Power-Supply Undervoltage Temperature
Threshold vs Free Air Temperature
5 0.8
High-Level Output Voltage (V)
Low-Level Output Voltage (V)

4.5
0.6
VSO = 3.3 V
VSO = 5 V
4
0.4
3.5
0.2
3
VSO = 3.3 V
VSO = 5 V
2.5 0
-15 -12 -9 -6 -3 0 0 3 6 9 12 15
High-Level Output Current (mA) Low-Level Output Current (mA)
TA = 25°C TA = 25°C
Figure 7-17. High-Level Output Voltage vs High- Figure 7-18. Low-Level Output Voltage vs Low-
Level Output Current Level Output Current
VDD = 5 V VISOOUT = 3.3 TA = 25°C VDD = 5 V VISOOUT = 3.3 10 uF

V V Capacitor on
VISOOUT
Figure 7-19. 10-mA to 110-mA Load Transient
Response Figure 7-20. Soft Start at 10-mA Load For VISOOUT =
3.3 V

VDD = 5 V VISOOUT = 3.3 10 uF VDD = 5 V VISOOUT = 3.3 10 uF

V Capacitor on V Capacitor on
VISOOUT VISOOUT
Figure 7-21. Soft Start at 50-mA Load For VISOOUT = Figure 7-22. Soft Start at 110-mA Load For VISOOUT
3.3 V = 3.3 V
VDD = 5 V VISOOUT = 5 V 10 uF VDD = 5 V VISOOUT = 5 V 10 uF

Capacitor on Capacitor on
VISOOUT VISOOUT
Figure 7-23. Soft Start at 10-mA Load For VISOOUT = Figure 7-24. Soft Start at 50-mA Load For VISOOUT =
5V 5V
VDD = 3.3 V VISOOUT = 3.3 10 uF

V Capacitor on
VDD = 5 V VISOOUT = 5 V 10 uF
VISOOUT
Capacitor on
VISOOUT Figure 7-26. VISOOUT Ripple Voltage at 3.3 V with 10
Figure 7-25. Soft Start at 110-mA Load For VISOOUT uF Capacitor and 60 mA load
=5V

VDD = 5 V VISOOUT = 5 V 10 uF VDD = 3.3 V VISOOUT = 3.3 100 uF

Capacitor on V Capacitor on
VISOOUT VISOOUT
Figure 7-27. VISOOUT Ripple Voltage at 5 V with 10 Figure 7-28. VISOOUT Ripple Voltage at 3.3 V with
uF Capacitor and 110 mA load 100 uF Capacitor and 60 mA load
VDD = 5 V VISOOUT = 5 V 100 uF

Capacitor on
VISOOUT TA = 25°C
Figure 7-29. VISOOUT Ripple Voltage at 5 V with 100 Figure 7-30. VISOOUT Ripple Voltage vs Load
uF Capacitor and 110 mA load Capacitor

8 Parameter Measurement Information

In the below images, VCCI and VCCO refers to the power supplies VIO and VISOIN, respectively.
VCCI
Isolation Barrier
VI 50% 50%
IN OUT
0V
tPLH tPHL
Input Generator CL
(See Note A) VI 50 VO See Note B VOH
50% 90% 50%
VO
10%
VOL
tr tf
Copyright © 2016, Texas Instruments Incorporated
A. CL = 15 pF and The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns,
tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-1. Switching Characteristics Test Circuit and Voltage Waveforms

VCC1
VCC / 2 VCC / 2
VI
Isolation Barrier
0V
VO tPZH
IN OUT
0 V or 3 V VOH
50% 0.5 V
VO
EN
RL = 1 k ±1% tPHZ 0V
CL
Input See Note B tPZL tPLZ
Generator VI VOH
(See Note A) 50
0.5 V
VO 50%
VOL
A. A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO
= 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
VCCI
See Note B
VCCI
VI 1.4 V
Isolation Barrier
0V
IN = 0 V (Devices without suffix F) IN OUT
VO tDO
IN = VCC (Devices with suffix F)
default high
VOH
CL
See Note A VO 50%
VOL
default low
Note
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Note
B. Power Supply Ramp Rate = 10 mV/ns.
Figure 8-3. Default Output Delay Time Test Circuit and Voltage Waveforms
5V
Connected to Visoout on PCB
VIO VISOIN
10uF 1uF 0.01uF 0.01uF 1uF 10uF
VIO
GND1
IN OUT
GND1 5V
VDD
CL
10uF 1uF 0.01uF
GND1 GND2
+ –
VCM
Note
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Note
Pass-fail criteria: Outputs must remain stable.
Figure 8-4. Common-Mode Transient Immunity Test Circuit

9 Detailed Description
9.1 Overview
The ISOW774x-Q1 family of devices have low-noise, low-emissions isolated DC-DC converter, and four high-
speed isolated data channels. Section 9.2 shows the functional block diagram of the ISOW774x device.
9.1.1 Power Isolation
The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce
radiated emissions and achieve upto 46% typical efficiency. The integrated transformer uses thin film polymer
as the insulation barrier. Output voltage of power converter can be controlled to 3.3 V or 5 V using VSEL
pin. The DC-DC converter can be switched off using the EN/FLT pin to save power. The output voltage,
VISOOUT , is monitored and feedback information is conveyed to the primary side through a dedicated isolation
channel. VISOOUT needs to be connected to VISOIN to ensure the feedback channel is properly powered to
regulate the DC-DC converter. This can be achieved by connecting the pins directly or through an LDO that
remains powered up at all times. A ferrite bead is recommended between Visoout and Visoin to further reduce
emissions. See the Section 10.2 section. The duty cycle of the primary switching stage is adjusted accordingly.
The fast feedback control loop of the power converter ensures low overshoots and undershoots during load
transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VIO, VDD and VISOIN supplies
which ensures robust fails-safe system performance under noisy conditions. An integrated soft-start mechanism
ensures controlled inrush current and avoids any overshoot on the output during power up.
9.1.2 Signal Isolation

The integrated signal isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier
across the barrier to represent one state and sends no signal to represent the other state. The receiver
demodulates the signal after signal conditioning and produces the output through a buffer stage. The signal-
isolation channels incorporate advanced circuit techniques to maximize the CMTI performance and minimize the
radiated emissions from the high frequency carrier and IO buffer switching. Figure 9-1 shows a functional block
diagram of a typical signal isolation channel. In order to keep any noise coupling from power converter away
from signal path, power supplies on side 1 for power converter (VDD) and signal path(VIO) are kept separate.
Similarly on side 2, power converter output (VISOOUT) needs to be connected to VISOIN externally on PCB.
Emissions can be further improved by placing a ferrite bead between VISOOUT and VISOIN as well as between the
GND2 pins. For more details, refer to the Layout Guidelines section.

9.2 Functional Block Diagram

VIO VISOIN
Isolation Barrier
VISOOUT and
Data Channels Data Channels VISOIN needs to
(4) (4) be directly
I/O Channels I/O Channels connected or
through an
Vref LDO on board
FB Channel (Rx) FB Channel (Tx) FB Controller
that is always
powered.
Thermal
Shutdown,
UVLO, Soft-start
UVLO, Soft-start
Power Transformer
Driver Rectifier
Controller
VISOOUT
VDD
Transformer
Figure 9-1. Block Diagram
Transmitter Receiver
OOK
Modulation
TX IN SiO2 based
TX Signal Capacitive RX Signal Envelope RX OUT
Conditioning Isolation Conditioning Detection
Barrier
Emissions
Oscillator Reduction
Techniques
Figure 9-2. Conceptual Block Diagram of a Capacitive Data Channel

Figure 9-3 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through

isolation barrier
RX OUT
Figure 9-3. On-Off Keying (OOK) Based Modulation Scheme
9.3 Feature Description

Table 9-1 shows an overview of the device features.
Table 9-1. Device Features
DEFAULT OUTPUT
PART NUMBER(1) CHANNEL DIRECTION MAXIMUM DATA RATE RATED ISOLATION(2)
STATE
ISOW7741-Q1 High
ISOW7741-Q1 with F 3 forward, 1 reverse
Low
suffix
100 Mbps 5 kVRMS / 7071 VPK
ISOW7742-Q1 High
ISOW7742-Q1 with F 2 forward, 2 reverse
Low
suffix
(1) The F suffix is part of the orderable part number. See the Section 14 section for the full orderable part number.
(2) For detailed isolation ratings, see the Section 7.7 table.
9.3.1 Electromagnetic Compatibility (EMC) Considerations

The ISOW7741-Q1 and ISOW7742-Q1 devices use emissions reduction schemes for the internal oscillator and
advanced internal layout scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISOW7741-Q1 and ISOW7742-Q1 devices incorporate many chip-level design improvements for overall system
robustness. Some of these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
• Power path and signal path separated to minimize internal high frequency coupling and allowing for an
external filtering knob using ferrite beads available to further reduce emissions
• Reduced power converter switching frequency to 25 Mhz to reduce strength of high frequency components in
emissions spectrum

9.3.2 Power-Up and Power-Down Behavior

The ISOW774x-Q1 device has built-in UVLO on the VIO, VDD, and VISOIN supplies with positive-going and
negative-going thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need
to be present for the device to work. If either of them is below its UVLO, both the signal path and the power
converter are disabled.
When the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter
initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits
primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner,
avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VIO or VDD
voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the
secondary side VISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The
regulation loop takes over and the isolated data channels go to the normal state defined by the respective input
channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load
capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.
When either VIO or VDD power is lost, the primary side DC-DC controller turns off when the UVLO lower
threshold is reached. The VISOOUT capacitor then discharges depending on the external load. The isolated data
outputs on the VISOIN side are returned to the default state for the brief time that the VISOIN voltage takes to
discharge to zero.
9.3.3 Protection Features
The ISOW7741-Q1 and ISOW7742-Q1 devices have multiple protection features to create a robust system level
solution.
• The Enable DC-DC / FAULT protection feature (EN/FLT) can be used as either an input pin, to enable or
disable the integrated DC-DC power converter, or as an output pin, which works as an alert signal if the
power converter is not operating properly. In the /FAULT use case, an alert is reported if VDD > 7 V, VDD < 2.5
V, or if the junction temperature >170°C. When a fault is detected, this pin will go low, disabling the DC-DC
converter to prevent any damage.
5 kΩ EN/FLT Powers Down Isolator Channels
MCU OUTPUT and DC-DC Converter.
IQ < 1 mA Typical
MCU INPUT
Fault Reported If
VDD < 2.5 V
VDD > 7 V
Junction Temp > 170° C
Figure 9-4. EN/FLT Fault Pin Diagram

• An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6 V, when VSEL =
VISOOUT, or 4 V, when VSEL = GND2, if there is an increase in voltage seen on VISOOUT. It is recommended
that the VISOOUT stays lower than the over-clamp voltage for device reliability.
• Over-voltage lock out on VDD will occur when a voltage higher than 7 V is seen. The device will go into a low
power state and the EN/FLT pin will go low.
• The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT
short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.

• Thermal protection is also integrated to help prevent the device from getting damaged during overload
and short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to
increase. When the temperature goes above 165°C, thermal shutdown activates and the primary controller
turns off which removes the energy supplied to the VISOOUT load, which causes the device to cool off.
When the junction temperature goes below 150°C, the device starts to function normally. If an overload or
output short-circuit condition prevails, this protection cycle is repeated. Care should be taken in the design to
prevent the device junction temperatures from reaching such high values.

9.4 Device Functional Modes

Table 9-2 lists the supply configurations for these devices.
Table 9-2. Supply Configuration Function Table
(1)
VDD VIO VSEL VISOOUT(3)
< VDD(UVLO+) >VIO(UVLO+) X OFF
>VDD(UVLO+) <VIO(UVLO+) X OFF
5V 1.71 V to 5.5 V High (shorted to VISOOUT) 5V
(2)
5 V or 3.3 V 1.71 V to 5.5 V Low (shorted to GND2) 3.3 V
(1) VDD= 3.3 V, VSEL shorted to VISOOUT(essentially VISOOUT = 5 V) is not the recommended mode of operation
(2) The VSEL pin has a weak pulldown internally. Therefore for VISOOUT = 3.3 V, the VSEL pin should be strongly connected to the GND2
pin in noisy system scenarios.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN=High
Table 9-3 lists the channel isolators functional modes for these devices.
Table 9-3. Channel Isolator Function Table
CHANNEL IO ENABLE
CHANNEL INPUT OUTPUT
(1) OUTPUT INPUT (INx) COMMENTS
SUPPLY (VCCI) (1) (EN_IOx) (OUTx)
SUPPLY (VCCO)
H or
H H Normal Operation: A channel output
Open
assumes the logic state of its input.
L H or Open L
Default mode(2): When INx is open, the
PU PU Open H or Open Default corresponding channel output goes to its
default logic state.
A low value of output enable causes
the outputs of the same side to be high
X L Z and Default
impedance and the output of opposite
side to be fail-safe default state.
Default mode(2): When VCCI is
unpowered, a channel output assumes
the logic state based on the selected
default option. When VCCI transitions
from unpowered to powered-up, a
PD PU X H or Open Default
channel output assumes the logic state
of the input. When VCCI transitions
from powered-up to unpowered, channel
output assumes the selected default
state.
(1) VCCI = Input-side VIO or VISOIN; VCCO = Output-side VIO or VISOIN; PU = Powered up (VIO > 1.7 V, VISOIN > 1.7 V); PD = Powered down
(VIO < 1 V, VISOIN < 1 V); X = Irrelevant; H = High level; L = Low level.
(2) In the default condition, the output is high for the ISOW774x-Q1 device and low with the F suffix.

9.4.1 Device I/O Schematics
INx (Devices without F suffix) INx (Devices with F suffix)

VCC I VCC I VCC I VCC I VCC I VCC I VCC I
1.5 M
INx INx
1.5 M
OUTx VSEL
VCC O
VISOOU T VISOOU T VISOOU T
a
OUTx SEL
2M
EN_IOx EN/FLT
VCC I VCC I VCC I VCC I VIO VIO VIO VIO
550 k 550 k
INx INx
Fault
1mA
Figure 9-5. Device I/O Schematics

10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information

The device is a high-performance, quad channel digital isolator with integrated DC-DC converter. Typically digital
isolators require two power supplies isolated from each other to power up both sides of device. Due to the
integrated DC-DC converter in the device, the isolated supply is generated inside the device that can be used
to power isolated side of the device and peripherals on isolated side, thus saving board space. The device uses
single-ended CMOS-logic switching technology. When designing with digital isolators, keep in mind that because
of the single-ended design structure, digital isolators do not conform to any specific interface standard and are
only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between
the data controller (that is Microcontroller or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
The device is suitable for applications that have limited board space and desire more integration. The device
is also suitable for very high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
10.2 Typical Application
Figure 10-1 shows the typical schematic for SPI isolation.
Reference
10 F 1 F 10 nF 10 nF 1 F 10 F
3.3 VIN
VIO VISOIN
3.3VOUT
DVCC AVDD DVDD
CS INA OUTA CS REF HV+ to
SCLK INB OUTB SCLK Chassis
MCU ADC
HV- to
SDO INC OUTC SDI Chassis
SDI OUTD IND SDO AGND DGND
ISOW7741
DVSS GNDIO GISOIN
330 at 100 MHz
VSEL (BLM15EX331SN
VISOOUT 1D)
VDD IN OUT
10 F 1 F 10 nF 10 nF 1 F 10 F GND
GND1 GND2
330 at 100 MHz
(BLM15EX331SN Optional LDO
1D)
Figure 10-1. Isolated Power and SPI for ADC Sensing Application with ISOW7741-Q1

10.2.1 Design Requirements

To design with this device, use the parameters listed in Table 10-1.
Table 10-1. Design Parameters
PARAMETER VALUE
VDD input voltage 3 V to 5.5 V
VIO input voltage 1.71 V to 5.5 V
VISOIN input voltage 1.71 V to 5.5 V
VDD decoupling capacitors 10 µF + 1 µF + 0.01 µF + optional additional capacitance
VIO decoupling capacitors 0.1 µF + optional additional capacitance
VISOIN decoupling capacitors 0.1 µF + optional additional capacitance
VISOOUT decoupling capacitors 10 µF + 1 µF + 0.01 µF + optional additional capacitance
VISOOUT to VISOIN series inductor BLM15ELX9331SN1D
GND2 to GISOIN series inductor BLM15ELX9331SN1D
VIO series inductor BLM15ELX9331SN1D
VDD series inductor BLM15ELX9331SN1D
GND1 to GNDIO series inductor BLM15ELX9331SN1D
Because of very-high current flowing through the ISOW7741-Q1 device device VDD and VISOOUT supplies,
higher decoupling capacitors typically provide better noise and ripple performance. Although a 10-µF capacitor
is adequate, higher decoupling capacitors (such as 47 µF) on both the VDD and VISOOUT pins to the respective
grounds are strongly recommended to achieve the best performance.
10.2.2 Detailed Design Procedure
The devices requires specific placement of external bypass capacitors and ferrite beads to operate at high
performance. These low-ESR ceramic bypass capacitors must be placed as close to the chip pads as possible.

10 F 10 F
VIO
1 F 330 at 100 MHz

1 F
(BLM15EX331SN1D)
10 nF 10 nF
VISOIN
1 20
INA 2 19 OUTA
INB 3 18 OUTB
INC 4 17 OUTC
OUTD 5 16 IND
GNDIO GISOIN
6 15
EN_IO1 EN_IO2
VIO 7 14 VISOIN
EN/FLT VSEL
FAULT OUT 8 13 VISOOUT
330
at 100 MHz 330 at 100 MHz
(BLM15EX331SN1D) (BLM15EX331SN1D)
VISOOUT
VDD 9 12 VISOIN
10 F 1 F 10 nF GND1 GND2 10 nF 1 F 10 F
10 11
330 at 100 MHz 330 at 100 MHz
(BLM15EX331SN1D) (BLM15EX331SN1D)
Figure 10-2. Typical ISOW7741-Q1 Circuit Hook-Up
10.2.3 Application Curve

The following typical eye diagrams of the ISOW774x-Q1 device indicates low jitter and wide open eye at the data
rate of 50 Mbps.
0.75 V/ div
1 V/ div
Time = 5 ns / div Time = 5 ns / div
Figure 10-3. Eye Diagram at 50 Mbps PRBS 216 – 1, Figure 10-4. Eye Diagram at 50 Mbps PRBS 216 – 1,
5 V and 25°C 3.3 V and 25°C
10.2.4 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 10-5 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million

(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 10-6 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
A
Vcc 1 Vcc 2
Time Counter
DUT > 1 mA
GND 1 GND 2
VS
Oven at 150 °C
Figure 10-5. Test Setup for Insulation Lifetime Measurement
Figure 10-6. Insulation Lifetime Projection Data

11 Power Supply Recommendations

To help make sure that operation is reliable at data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. VISOOUT needs to be connected to VISOIN to ensure the
feedback channel is properly powered to regulate the DC-DC converter. If VISOOUT and VISOIN are not connected,
the DC-DC converter will run open loop and the VISOOUT voltage will drift until the over-voltage clamp clamps at 6
V. There are two ways to connect VISOOUTand VISOIN:
1) connect VISOOUT and VISOIN directly with a ferrite bead. A ferrite bead is recommended between VISOOUTand
VISOIN to further reduce emissions.
2) connect VISOOUT and VISOIN with a ferrite bead through an LDO that remains powered up at all times. If the
LDO has an EN pin then keep the EN high at all times.
The input supply (VIO and VDD) must have an appropriate current rating to support output load and switching at
the maximum data rate required by the end application. For more information, refer to the Section 10.2 section.
For an output load current of 110 mA, it is recommended to have >600 mA of input current limit and for lower
output load currents, the input current limit can be proportionally lower.

12 Layout
12.1 Layout Guidelines
A low cost two layer PCB should be sufficient to achieve good EMC performance:
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND
pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the
device from rising to unacceptable levels.
Figure 12-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must
be followed to meet application EMC requirements:
• High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 1 mm
distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure
that these capacitors are 0402 size so that they offer least inductance (ESL).
• Bulk capacitors of atleast 10 μF must be placed on power converter input (VDD) and output (VISOOUT) supply
pins.
• Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2
must be symmetric.
• Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on VISOOUT and GND2 path so that any
high frequency noise from power converter output sees a high impedance before it goes to other components
on PCB.
• Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT pin12
and GND2 pin11. VSEL pin is also in VISOOUT domain and should be shorted to either pin 11 or pin 12 for
output voltage selection.
• Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated
emissions design.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.

12.2 Layout Example
Ground plane on Ground plane on

side 1 <2mm
side 2
<2mm
C C C C C C
FB
Input supply 1 5 10 F 1 F 10 nF
VIO 1 20 VISOIN 10 nF 1 F 10 F
INA 2 19 OUTA
INB 3 18 OUTB
INC 4 OUTC
I S O L A TI O N
17
OUTD 5 16 IND
Ground plane on side 1 GNDIO 6 15 GISOIN
EN_IO1 7 14 EN_IO2
Ground
plane on
EN/FLT 8 13 VSEL side 2
10 F 1 F 10 nF
10 nF 1 F 10 F
Input supply 2 FB
4
VDD 9 12 VISOOUT FB
1
C C C
FB
C C C FB
Ground plane 3 GND1 10 11 GND2 2
on side 1 <1mm 2-4mm
2-4mm <1mm
Keep-out zone for any metal
Figure 12-1. Layout Example

13 Device and Documentation Support

13.1 Device Support
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.




PACKAGE OPTION ADDENDUM
www.ti.com 16-Dec-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
ISOW7741FQDFMRQ1 ACTIVE SOIC DFM 20 850 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7741F Samples
ISOW7741QDFMRQ1 ACTIVE SOIC DFM 20 850 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7741 Samples
ISOW7742FQDFMRQ1 ACTIVE SOIC DFM 20 850 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7742F Samples
ISOW7742QDFMRQ1 ACTIVE SOIC DFM 20 850 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ISOW7742 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 16-Dec-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISOW7741-Q1, ISOW7742-Q1 :
• Catalog : ISOW7741, ISOW7742
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISOW7741FQDFMRQ1 SOIC DFM 20 850 330.0 24.4 10.85 13.4 4.0 16.0 24.0 Q1
ISOW7741QDFMRQ1 SOIC DFM 20 850 330.0 24.4 10.85 13.4 4.0 16.0 24.0 Q1
ISOW7742FQDFMRQ1 SOIC DFM 20 850 330.0 24.4 10.85 13.4 4.0 16.0 24.0 Q1
ISOW7742QDFMRQ1 SOIC DFM 20 850 330.0 24.4 10.85 13.4 4.0 16.0 24.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISOW7741FQDFMRQ1 SOIC DFM 20 850 350.0 350.0 43.0
ISOW7741QDFMRQ1 SOIC DFM 20 850 350.0 350.0 43.0
ISOW7742FQDFMRQ1 SOIC DFM 20 850 350.0 350.0 43.0
ISOW7742QDFMRQ1 SOIC DFM 20 850 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DFM0020A SCALE 1.250
SOIC - 3.55 mm max height
SMALL OUTLINE PACKAGE
C
10.63 TYP
A 9.97
0.1 C
PIN 1 INDEX AREA SEATING
18X 1.27 PLANE
20
1
2X
12.93 11.43
12.73
NOTE 3
10
11
20X 0.51
0.31
7.6 3.55 MAX.
B 0.15 C A B
7.4
NOTE 4
0.33
0.1
(3.18)
0.25
GAGE PLANE
SEE DETAIL A
0.30
0-8 0.95 0.10
0.65
DETAIL A
A 10
TYPICAL
4225640/A 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Ref. JEDEC registration MS-013
www.ti.com
EXAMPLE BOARD LAYOUT
DFM0020A SOIC - 3.55 mm max height
SYMM
20X (2.1)
(R0.05) TYP
1
20X (0.6) 20
20X (1.27)
SYMM
10 11
(9.7)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4225640/A 01/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DFM0020A SOIC - 3.55 mm max height
SYMM
20X (2.1)
(R0.05) TYP
1
20X (0.6) 20
20X (1.27)
SYMM
10 11
(9.7)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
4225640/A 01/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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ISOW7741-Q1, ISOW7742-Q1

SLLSFK3 – NOVEMBER 2022

ISOW774x-Q1 Quad-Channel Digital Isolator with Integrated Low-Emissions, Low-

– ±8 kV IEC 61000-4-2 contact discharge EN_IO2

• Reinforced and Basic isolation options INB Tx Rx OUTB

– VDE reinforced and basic insulation per DIN OUTD Rx Tx IND

GB 4943.1-2011 certifications VDD VSEL

– ISOW774xB devices are planned DC-DC

ISOW7741-Q1 Simplified Schematic

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOW7741-Q1 ISOW7742-Q1

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: ISOW7741-Q1 ISOW7742-Q1

6 Pin Configuration and Functions

Figure 6-1. ISOW7741-Q1 DFM Package 20-Pin SOIC-WB Top View

Figure 6-2. ISOW7742-Q1 DFM Package 20-Pin SOIC-WB Top View

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISOW7741-Q1 ISOW7742-Q1

INB 3 3 I Input channel B

INC 4 17 I Input channel C

IND 16 16 I Input channel D

OUTA 19 19 O Output channel A

OUTB 18 18 O Output channel B

OUTC 17 4 O Output channel C

OUTD 5 5 O Output channel D

VDD 9 9 — Side 1 DC-DC converter power supply.

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7.2 ESD Ratings

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7.3 Recommended Operating Conditions

Power converter supply 3.3 V operation 2.97 3.3 3.63 V

(1) This current is for data output channel.

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7.4 Thermal Information

7.5 Power Ratings

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7.6 Insulation Specifications

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7.7 Safety-Related Certifications

7.8 Safety Limiting Values

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7.9 Electrical Characteristics - Power Converter

IISOOUT = 110 mA, CLOAD = 0.01 µF || 10 µF;

IISOOUT = 140 mA, CLOAD = 0.01 µF || 10 µF;

IISOOUT = 60 mA, CLOAD = 0.01 µF || 10 µF;

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7.10 Supply Current Characteristics - Power Converter

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7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V

(1) VSI = input side supply; VSO = output side supply