2023 - EG 211

Computer architecture
4 credits
No separate lab credits (No EG201P in timetable)

Nanditha Rao

1
 Pre-requisites
●
Basics of digital design/logic design
– FSMs?
– Registers
– ALU? Decoders? Mux?
– Memories? (SRAM, DRAM)
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C/Verilog/Python?

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 EG 211– Computer architecture
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2 weeks: Topic 1: Introduction
Chapter-1,2 William Stallings
– Stored program concept, RISC vs CISC
– Harvard vs Von Neumann architecture
– History of architecture advances
– IAS computer architecture
– Assignment: Implementation

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 Brief Overview
Topic 4: MIPS
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2 weeks: MIPS instruction set, MIPS assembly
programming, Procedure and stacks
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1-2 weeks: data and control path design, ALU design
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3-4 weeks: Pipelining, data and control path design,
hazards: data, control, structural hazard, Performance
evaluation
●
Assignment: Implementation

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 Brief Overview
Topic 5: Memory
●
3 weeks: Memory: Cache memory, memory hierarchies,
performance evaluation (AMAT), Read/Write stategies
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Assignment: Implementation
●
2 weeks: Exceptions, forwarding,Loop
optimisation/unrolling
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2 weeks: Branch predictors
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1 week: Case study of a modern day processor
architecture
●
Overview of advanced computer architecture

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 References
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Computer Organisation and Architecture - by William Stallings
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Computer-Organization and Design- MIPS version -5th-Edition
Hennessy and Patterson
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Digital design and computer architecture- Harris and Harris
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Tools
– MARS MIPS Simulator

●
Youtube: Digital design and Computer architecture Prof Onur
Mutlu
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Edx: MITx Computation Structures -2

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●
Why study this course?
– Understand the functioning of a processor, memory and its
interfaces
– Follow up course: Advanced architecture course
●
CS or ECE?
– Taught as CS course in most institutes
– ECE contents can be slightly different
●
Course contents
– Differs based on the semester in which it is taught
– 2nd semester vs 7th semester
●
Method of teaching
– Classroom sessions
– Few modules will be recorded + live interaction
– All slides will be uploaded on LMS
– Use LMS or slack or whatsapp with Tas for discussions 8
 Mode of teaching
●
Mostly Classroom
●
Flipped classroom mode for few modules (Data
path design, pipelining, Caches)
– 2 Recorded sessions per week. 30 - 40 mins each
– 1 classroom session for discussions and problem
solving

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 Tutorials/labs
●
No separate credit for lab
●
Activities to be done in tutorials
– Problem solving
– Discussion
– Tool demos
– Labs- RV-FPGA Labs
– Examples from the modern day processor architecture
– Case studies
– Demos by senior students on their work
– Prospectives and applications of computer architecture

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 Grading
Weightage

Quizes (2-3) 25%

Midterm 25%
Endterm 30%
Assignments/Demo 20%

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 Policy towards cheating
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All assignments/codes/reports will be run through a
plagiarism check tool
●
Cheating – 0 marks for the assignments
●
Write your own code!
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Repeat offence/Cheating in exam – Grade penalty

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 Teaching assistants
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Ravi Kiran Reddy Gogireddy MT2022515
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Vinay Rayapati MT2022522
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Brij Bidhin Desai IMT2021067
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Rakshit.Bang IMT2020105
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Varad Purushottam Bharadiya IMT2021532
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Yash.Mogal IMT2020537
●
Yathin.Kumar IMT2020550
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Saketh.Gajawada IMT2020531
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Asmita Zigyasu IMT2020507

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A motherboard

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A processor core
What is a processor?

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Different options for CS and ECE after learning architecture

Programming Architecture
languages – specifications
parallelism

Circuit design
Algorithms

Interconnect
design
Compiler
optimizations Power
optimizations

Memory
management Memory design

Simulation
models Device
technology
ISA
What are the other topics in
architecture?

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●
Processor Microarchitecture:
– Register renaming using Register alias table,
– Multiple issue processors: Static mutliple issue- VLIW ,
– Dynamic multiple issue/Superscalar processors -7-stage pipeline,
Hardware of OOO – Re-order buffer and Reservation stations.
– Algorithms for Out-of-Order (OOO) Execution – Tomasulo with RoB
and without RoB, Scoreboard technique
– Dynamic scheduling/Tomasulo on multiple issue processors; Without
and with hardware speculation
– Overview of loop unrolling
– Memory disambiguation/dependencies in Out of order processors.
Usage of Load store queues.
●
Inclusive, exclusive caches Prefetching: Software and hardware
prefetching. Next line and stride prefetching
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Cache coherence protocols in multi-core processors (MSI, MESI,
MOESI), consistency models. Multithreading. Parallelism in
instructions: SIMD/Vector processors, Memory banks, Main
memory management
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Branch Predictors – 1 bit, 2 bit, dynamic, Branch target buffer,
branch history table, global predictor, Gshare, Pshare,
tournament predictor, perceptron based predictor
●
Virtual memory, Page tables, translation look aside buffer (TLB),
TLB + Cache. PIPT, VIVT, VIPT cache, AMD Opteron case study
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From literature: Miscellaneous: Die stacking architecture, Fault
tolerant architecture, Cache compression and compaction: YACC,
SCC/DCC cache, Cache side channel attacks and security
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Hardware accelerator/architectures for machine learning, Systolic
arrays, GPU/TPUs, Heterogeneous architectures
 Backup
Course contents of other institutes

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 IIT Delhi
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ELL 305/COL 216 – Computer architecture
– http://www.cse.iitd.ernet.in/cse/newcurriculum-contents/
newcourses.html#CSL211
– http://www.cse.iitd.ac.in/~srsarangi/courses/ell305_2019/index.html
– Number systems, floating point representations
– Assembly language, procedures: ARM assembly language
– SRAM, DRAM, and CAM Cells
– Adders, multipliers
– SimpleRisc Processor, Pipelining, Hazards
– Memory system, Caches, Virtual memory
– Multi-core processors, Cache coherency
– Vector instructions, GPU
– Interconnects
 IIT Delhi
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ELL 782 - Advanced Computer architecture
– http://www.cse.iitd.ac.in/~sumantra/courses/arch/arch.h
tml
– Pipelining,
– Hazards
– Caches
– Multi-core
– Vector processing
– SIMD, MIMD
– Dynamic scheduling
 IIT Bombay/Mandi
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CP-226 Computer architecture
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https://www.ee.iitb.ac.in/~viren/Courses/2013/CA-iitmandi.htm
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1. Digital Logic and Digital Systems:
– Overview and history of computer architecture, combinational vs sequential logic

– 2. Instruction Set Architecture:

– Introduction to instruction set architecture, Basic organization of computing machine:
fetch, decode, and execute; Instruction set types, instruction format, addressing modes,
subroutine call and return mechanisms;
– 3. Computer Arithmetic: Representation of numeric data, signed and unsigned
arithmetic; Range, precision and errors in floating-point arithmetic; Design of arithmetic
and logic unit (ALU).
– 4. Processor Architecture: CISC vs RISC Designs, simple implementation schemes,
datapath design, control unit: hardwired realization vs micro-programmed realization,
multi-cycle implementation. Instruction level parallelism, instruction pipelining, pipeline
hazards.
– 5. Memory Architecture:
– Storage systems, introduction to memory hierarchy: importance of temporal and spatial
locality; main memory organization, cache memory: address mapping, block size,
replacement, and store policies; virtual memory system: page table and TLB.
– 6. Interfacing and I/O Organization:
– External storage; IO fundamentals: handshaking, buffering, programmed IO, interrupt
driven IO; Interrupt handling mechanism, Buses: protocols, arbitration, direct memory
 IIT Bombay
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CS683/EE748 – Advanced Computer architecture
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https://www.ee.iitb.ac.in/~viren/Courses/2015/EE748.htm
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Overview Superscalar and VLIW architectures. Limits of instruction
level parallelism (ILP). Simultaneous multi-threaded (SMT)
architecture,
– Performance enhancement through branch prediction and value
prediction, BulkSMT, Thread level speculation. Run ahead execution,
proactive instruction fetch, multi-core architectures, data marshaling for
multi-core architectures, power constrained CMPs, heterogeneous core
design,
– Core Fusion, Transactional memories. Performance evaluation of complex
microarchitectures. On-chip interconnects (Network-on-Chip). Architectural
vulnerabilities and reliable architectures. Patchable design. Secure
architectures.
– Energy efficient architectures. Power management. Cache design, energy
efficient cache partitioning, fast thread migration, thread throatling.
 Wisconsin

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CS/ECE 552 - Introduction to Computer Architecture.
– https://guide.wisc.edu/courses/comp_sci/
– http://homepages.cae.wisc.edu/~hu/ece552/description.html
– https://ece552.ece.wisc.edu/video.shtml
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ALU design: Adders, subtracters, logic operations control
structures and microprogramming;
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MIPS: Processor design, instruction set design, and
addressing;Instruction formats, instruction sets and their design
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Memory management, caches, and memory hierarchies; and
interrupts and I/O structures. E C E 551 or knowledge of Verilog
is recommended.
 Wisconsin
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CS/ECE 752 - Advanced Computer Architecture I.
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https://ece752.ece.wisc.edu/#description
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ECE/CS 552 is a firm prerequisite; if you are a transfer or graduate student
without this course background, you should be very familiar with logic design
and should have already designed a working instruction set processor. You
should be very familiar with pipelined execution, data hazards, and basic control
speculation, along with simple cache memories and virtual memory. If you do
not have this background, you will have to do some catch-up reading to keep up
in this course.
– Pipelining Review from ECE 552, Lecture 15: Pipelining, Lecture 16: Pipeline Hazards,
– Lecture 04: Pipelining to Superscalar, Lecture 05: Superscalar Organization
– Lecture 06: Caches and Memory Hierarchy from ECE 552, Lecture 19: Cache Concepts
– Lecture 20: Cache Design, Lecture 21: Cache Performance
– Lecture 22: Virtual Memory, Lecture 07: Instruction Flow
– Lecture 08: Register Data Flow, Lecture 09: Memory Data Flow
– Lecture 10: Pentium Pro Case Study, Lecture 11: Advanced Caches
– Lecture 12: Main Memory
– Lecture 13: Advanced Microarchitecture,
– Lecture 14: Executing Multiple Threads
 Wisconsin
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CS/ECE 757 - Advanced Computer Architecture II.
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https://ece752.ece.wisc.edu/#description
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Analyze pertinent research papers, including writing reviews of them.
– Understand how semiconductor technology and information technology
applications influence parallel computer systems.
– Implement parallel computer programs in multiple paradigms (e.g., data
parallel, shared-memory, and message-passing) and understand trade-offs
among the paradigms.
– Understand and evaluate different synchronization mechanisms, memory
consistency models, cache coherence protocols
– Understand and evaluate interconnection network goals and mechanisms.
– Analyze and evaluate parallel computer systems by user and enhancing at
least one simulator of such systems.
– Understand and evaluate emerging heterogeneous parallelism design
approaches, e.g., single instruction multiple data (SIMD), single instruction
multiple thread (SIMT), and other accelerators.
– Either (a) create a novel parallel computer architecture research idea