PIC16F753/HV753: 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F753/HV753
14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers
High-Performance RISC CPU eXtreme Low-Power (XLP) Features

• Only 35 Instructions to Learn: • Sleep Current:
- All single-cycle instructions except branches - 50 nA @ 2.0V, typical
• Operating Speed: • Operating Current:
- DC – 20 MHz clock input - 11 uA @ 32 kHz, 2.0V, typical
- DC – 200 ns instruction cycle - 260 uA @ 4 MHz, 2.0V, typical
• 2048 x 14 On-chip Flash Program Memory • Watchdog Timer Current:
• Self-Read/Write Program Memory • <1 uA @ 2.0V, typical
• 128 x 8 General Purpose Registers (SRAM)
• Interrupt Capability Peripheral Features
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes • 11 I/O Pins and one Input-only Pin
• High Current Source/Sink:
Microcontroller Features - 50 mA I/O, (two pins)
• Precision Internal Oscillator: - 25 mA I/O, (nine pins)
- Factory calibrated to ±1%, typical • Two High-Speed Analog Comparator modules:
- Software selectable frequency: - 50 ns response time
8 MHz, 4 MHz, 1 MHz or 31 kHz - Fixed Voltage Reference (FVR)
- Software tunable - Programmable on-chip voltage reference via
• Power-Saving Sleep mode integrated 9-bit DAC
• Voltage Range (PIC16F753): - Internal/external inputs and outputs
- 2.0V to 5.5V (selectable)
• Shunt Voltage Regulator (PIC16HV753): - Built-in Hysteresis (software selectable)
- 2.0V to user defined • A/D Converter:
- 5-volt regulation - 10-bit resolution
- 1 mA to 50 mA shunt range - Eight external channels
• Multiplexed Master Clear with Pull-up/Input Pin - Two internal reference voltage channels
• Interrupt-on-Change Pins • Operational Amplifier:
• Individually Programmable Weak Pull-ups - Three terminal operations
• Power-on Reset (POR) - Internal connections to DAC and FVR
• Power-up Timer (PWRT) • Digital-to-Analog Converter (DAC):
• Brown-out Reset (BOR) - 9-bit resolution
• Watchdog Timer (WDT) with Internal Oscillator for - Full Range output
Reliable Operation - 4 mV steps @ 2.0V (Limited Range)
• Industrial and Extended Temperature Range • Fixed Voltage Reference (FVR), 1.2V Reference
• High Endurance Flash: • Capture, Compare, PWM (CCP) module:
- 100,000 write Flash endurance - 16-bit Capture, max. resolution = 12.5 ns
- Flash retention: >40 years - 16-bit Compare, max. resolution = 200 ns
- 10-bit PWM, max. frequency = 20 kHz
• Programmable Code Protection
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• In-Circuit Debug (ICD) via Two Pins • Enhanced Timer1:
• In-Circuit Serial Programming™ (ICSP™) via Two - 16-bit Timer/Counter with Prescaler
Pins - External Timer1 Gate (count enable)
- Four Selectable Clock sources
• Timer2: 8-Bit Timer/Counter with Prescaler
- 8-Bit Period Register and Postscaler
• Two Hardware Limit Timers (HLT):
- 8-bit Timer with Prescaler
- 8-bit period register and postscaler
- Asynchronous H/W Reset sources
 2013-2016 Microchip Technology Inc. DS40001709D-page 1

PIC16F753/HV753
• Complementary Output Generator (COG):
- Complementary Waveforms from selectable
sources
- Two I/O (50 mA) for direct MOSFET drive
- Rising and/or Falling edge dead-band control
- Phase control, Blanking control
- Auto-shutdown
- Slope Compensation Circuit for use with
SMPS power supplies
TABLE 1: PIC16F753/HV753 FAMILY TYPES
Output Generator
Program Memory
Data Sheet Index
Shunt Regulator
Complementary
Self-Read/Write
10-bit ADC (ch)

Flash Memory
Flash (words)
Comparators
Data SRAM
(8/16-bit)
Debug(1)
Op Amp
(bytes)
Timers
(COG)
I/Os(2)
DAC
CCP
XLP
Device
PIC12F752 (1) 1K Y 64 6 4 2 3/1 1 Y 5-bit N N H Y

PIC12HV752 (1) 1K Y 64 6 4 2 3/1 1 Y 5-bit N Y H Y
PIC16F753 (2) 2K Y 128 12 8 2 3/1 1 Y 9-bit Y N I/H Y
PIC16HV753 (2) 2K Y 128 12 8 2 3/1 1 Y 9-bit Y Y I/H Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001576 PIC12F752/HV752 Data Sheet, 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers.
2: DS40001709 PIC16F753/HV753 Data Sheet, 14/16-Pin Flash-based, 8-Bit CMOS Microcontrollers.
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
FIGURE 1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM
VDD 1 14 VSS
PIC16F753/HV753
RA5 2 13 RA0/ICSPDAT
RA4 3 12 RA1/ICSPCLK
MCLR/VPP/RA3 4 11 RA2
RC5 5 10 RC0
RC4 6 9 RC1
RC3 7 8 RC2
Note: See Table 2 for location of all peripheral functions.
DS40001709D-page 2  2013-2016 Microchip Technology Inc.

PIC16F753/HV753
FIGURE 2: 16-PIN QFN (4X4) DIAGRAM
VDD
VSS
NC
NC
16 15 14 13
RA5 1 12 RA0/ICSPDAT
RA4 2 PIC16F753/HV75311 RA1/ICSPCLK
MCLR/VPP/RA3 3 10 RA2
RC5 4 9 RC0
5 6 7 8
RC4
RC3
RC2
RC1
Note: See Table 2 for location of all peripheral functions.
TABLE 2: 14/16-PIN ALLOCATION TABLE FOR PIC16F753/HV753

14-Pin PDIP/SOIC/TSSOP
Slope Compensation
Comparator
16-Pin QFN
Reference
Interrupt
Op Amp
Pull-up
Timer
Basic
ADC
CCP
I/O
RA0 13 12 AN0 FVROUT — C1IN0+ — — IOC Y — ICSPDAT

DACOUT
RA1 12 11 AN1 VREF+ — C1IN0- — — IOC Y — ICSPCLK
FVRIN C2IN0-
RA2 11 10 AN2 COG1FLT — C1OUT T0CKI — INT Y — —
IOC
RA3 4 3 — — — — T1G(2) — IOC Y — MCLR/
VPP
RA4 3 2 AN3 — — — T1G(1) — IOC Y — CLKOUT
RA5 2 1 — — — — T1CKI — IOC Y — CLKIN
RC0 10 9 AN4 — OPA1IN+ C2IN0+ — — IOC — — —
RC1 9 8 AN5 — OPA1IN- C1IN1- — — IOC — — —
C2IN1-
RC2 8 7 AN6 — OPA1OUT C1IN2- — — IOC — SLPCIN —
C2IN2-
RC3 7 6 AN7 — — C1IN3- — — IOC — — —
C2IN3-
RC4 6 5 — COG1OUT1 — C2OUT — — IOC — — —
RC5 5 4 — COG1OUT0 — — — CCP1 IOC — — —
VDD 1 16 — — — — — — — — — VDD
VSS 14 13 — — — — — — — — — VSS
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.

PIC16F753/HV753
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 6
2.0 Memory Organization ................................................................................................................................................................... 9
3.0 Flash Program Memory Self-Read/Self-Write Control................................................................................................................ 25
4.0 Oscillator Module........................................................................................................................................................................ 34
5.0 I/O Ports ..................................................................................................................................................................................... 39
6.0 Timer0 Module............................................................................................................................................................................ 54
7.0 Timer1 Module with Gate Control............................................................................................................................................... 57
8.0 Timer2 Module............................................................................................................................................................................ 68
9.0 Hardware Limit Timer (HLT) Module .......................................................................................................................................... 70
10.0 Capture/Compare/PWM Modules............................................................................................................................................... 74
11.0 Complementary Output Generator (COG) Module..................................................................................................................... 81
12.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 104
13.0 Fixed Voltage Reference (FVR)................................................................................................................................................ 115
14.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 117
15.0 Comparator Module.................................................................................................................................................................. 123
16.0 Operational Amplifier (OPA) Module ........................................................................................................................................ 132
17.0 Slope Compensation (SC) Module ........................................................................................................................................... 135
18.0 Instruction Set Summary .......................................................................................................................................................... 140
19.0 Special Features of the CPU .................................................................................................................................................... 149
20.0 Shunt Regulator (PIC16HV753 Only)....................................................................................................................................... 168
21.0 Development Support............................................................................................................................................................... 169
22.0 Electrical Specifications ............................................................................................................................................................ 173
23.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 197
24.0 Packaging Information.............................................................................................................................................................. 215
Appendix A: Data Sheet Revision History.......................................................................................................................................... 226
The Microchip Website....................................................................................................................................................................... 227
Customer Change Notification Service .............................................................................................................................................. 227
Customer Support .............................................................................................................................................................................. 227
Product Identification System............................................................................................................................................................. 228

PIC16F753/HV753
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PIC16F753/HV753
1.0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices
are shown in Figure 1-1 and Table 1-1.
The PIC16F753/HV753 devices are covered by this
data sheet. They are available in 14-pin PDIP, SOIC,
TSSOP and 16-pin QFN packages.
FIGURE 1-1: PIC16F753/HV753 BLOCK DIAGRAM
INT
Configuration
13 8 PORTA
Data Bus
Program Counter
Flash RA0
2K X 14 RA1
Program RAM RA2
Memory 8-Level Stack 64 Bytes RA3
(13-Bit) File RA4
Registers RA5
Program
14
Bus RAM Addr 9
PORTC
Addr MUX
Instruction Reg
RC0
Direct Addr 7 Indirect RC1
8 Addr
RC2
FSR Reg RC3
RC4
STATUS Reg RC5
8
3
MUX
Instruction Power-up
Decode & Timer
ALU
Control Power-on
Reset 8
CLKIN Timing Watchdog
Timer W Reg Capture/
Generation Compare/
Brown-out PWM
CLKOUT
Reset (CCP)
Shunt Regulator Hardware

Internal Limit
Oscillator (PIC16HV753 only)
Timer1
Block (HLT)
MCLR VDD VSS
T1G
T1CKI
Timer0 Timer1 Timer2 Complementary
T0CKI Output
Generator
(COG)
Dual Range
DAC Analog Comparator
Slope Fixed Voltage
Compensator Reference and Reference
(FVR)
C1OUT/C2OUT
C2IN1-
C1IN1-
C1IN0-/C2IN0-
C1IN0+/C2IN0+
Op Amp

PIC16F753/HV753
TABLE 1-1: PIC16F753/HV753 PINOUT DESCRIPTION

Input Output
Name Function Description
Type Type
RA0/AN0/C1IN0+/DACOUT/ RA0 TTL HP General purpose I/O with IOC and WPU.
FVROUT/ICSPDAT AN0 AN — A/D Channel 0 input.
C1IN0+ AN — Comparator C1 positive input.
DACOUT — AN DAC unbuffered Voltage Reference output.
FVROUT — AN DAC/FVR buffered Voltage Reference output.
ICSPDAT ST HP Serial Programming Data I/O.
RA1/AN1/C1IN0-/C2IN0-/ RA1 TTL CMOS General purpose I/O with IOC and WPU.
VREF+/FVRIN/ICSPCLK AN1 AN — A/D Channel 1 input.
C1IN0- AN — Comparator C1 negative input.
VREF+ AN — A/D Positive Voltage Reference input.
FVRIN AN — Voltage reference input.
ICSPCLK ST — Serial Programming Clock.
RA2/AN2/INT/C1OUT/ RA2 ST HP General purpose I/O with IOC and WPU.
T0CKI/COG1FLT AN2 AN — A/D Channel 2 input.
INT ST — External interrupt.
C1OUT — HP Comparator C1 output.
T0CKI ST — Timer0 clock input.
COG1FLT ST — COG auto-shutdown fault input.
RA3(1)/T1G(3)/VPP/MCLR(4) RA3 TTL — General purpose input with WPU.
T1G ST — Timer1 Gate input.
VPP HV — Programming voltage.
MCLR ST — Master Clear w/internal pull-up.
(2)
RA4/AN3/T1G /CLKOUT RA4 TTL CMOS General purpose I/O with IOC and WPU.
AN3 AN — A/D Channel 3 input.
T1G ST — Timer1 Gate input.
CLKOUT — CMOS FOSC/4 output.
(3)
RA5/T1CKI/COG1OUT0 / RA5 TTL CMOS General purpose I/O with IOC and WPU.
C2IN1-/CLKIN T1CKI ST — Timer1 clock input.
CLKIN ST — External Clock input (EC mode).
RC0/AN4/OPA1IN+/C2IN0+ RC0 TTL CMOS General purpose I/O with IOC and WPU.
OPA1IN+ AN — Op amp positive input.
C2IN0+ AN — Comparator C2 positive input.
RC1/AN5/OPA1IN-/C1IN1-/ RC1 TTL CMOS General purpose I/O with IOC and WPU.
C2IN1- AN5 AN — A/D Channel 5 input.
OPA1IN- AN — Op amp negative input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HP = High Power HV = High Voltage
* Alternate pin function.
Note 1: Input only.
2: Default pin function via the APFCON register.
3: Alternate pin function via the APFCON register.
4: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

PIC16F753/HV753
TABLE 1-1: PIC16F753/HV753 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name Function Description
Type Type
RC2/AN6/SLPCIN/ RC2 TTL CMOS General purpose I/O with IOC and WPU.
OPA1OUT/C1IN2-/C2IN2- AN6 AN — A/D Channel 6 input.
OPA1OUT AN HP Op amp output.
RC3/AN7/C1IN3-/C2IN3- RC3 TTL CMOS General purpose I/O with IOC and WPU.
RC4/COG1OUT1/C2OUT RC4 TTL CMOS General purpose I/O with IOC and WPU.
COG1OUT1 — CMOS COG output Channel 1.
C2OUT — HP Comparator C2 output.
RC5/COG1OUT0/CCP1 RC5 TTL CMOS General purpose I/O with IOC and WPU.
COG1OUT0 — CMOS COG output Channel 0.
CCP1 — HP Capture/Compare/PWM 1.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HP = High Power HV = High Voltage
* Alternate pin function.
Note 1: Input only.
2: Default pin function via the APFCON register.
3: Alternate pin function via the APFCON register.
4: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

PIC16F753/HV753
2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into four
2.1 Program Memory Organization banks, which contain the General Purpose Registers
The PIC16F753/HV753 has a 13-bit program counter (GPR) and the Special Function Registers (SFR). The
capable of addressing an 8K x 14 program memory Special Function Registers are located in the first 32
space. Only the first 2K x 14 (0000h-07FFh) is locations of each bank. Register locations 40h-6Fh in
physically implemented. Accessing a location above Bank 0 are General Purpose Registers, implemented as
these boundaries will cause a wrap-around within the static RAM. Register locations 70h-7Fh in Bank 0 are
first 2K x 14 space for PIC16F753/HV753. The Reset Common RAM and shared as the last 16 addresses in
vector is at 0000h and the interrupt vector is at 0004h all Banks. All other RAM is unimplemented and returns
(see Figure 2-1). ‘0’ when read. The RP<1:0> bits of the STATUS register
are the bank select bits.
FIGURE 2-1: PROGRAM MEMORY MAP RP1 RP0
AND STACK FOR THE 0 0  Bank 0 is selected
PIC16F753/HV753 0 1  Bank 1 is selected
PC<12:0> 1 0  Bank 2 is selected
CALL, RETURN 13 1 1  Bank 3 is selected
RETFIE, RETLW
Stack Level 1
2.2.1 GENERAL PURPOSE REGISTER
Stack Level 2
FILE
The register file is organized as 64 x 8 in the
Stack Level 8 PIC16F753/HV753. Each register is accessed, either
directly or indirectly, through the File Select Register
Reset Vector 0000h (FSR) (see Section 2.5 “Indirect Addressing, INDF
and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS

Interrupt Vector 0004h The Special Function Registers are registers used by
0005h the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
On-chip Program registers are static RAM.
Memory
The special registers can be classified into two sets:
07FFh
core and peripheral. The Special Function Registers
0400h associated with the “core” are described in this section.
Shadows 0-07FFh Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
1FFFh

PIC16F753/HV753
FIGURE 2-2: DATA MEMORY MAP OF THE PIC16F753/HV753
BANK 0 BANK 1 BANK 2 BANK 3

INDF 00h INDF 80h INDF 100h INDF 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h LATA 105h ANSELA 185h
— 06h — 86h — 106h — 186h
PORTC 07h TRISC 87h LATC 107h ANSELC 187h
IOCAF 08h IOCAP 88h IOCAN 108h APFCON 188h
IOCCF 09h IOCCP 89h IOCCN 109h OSCTUNE 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch WPUA 10Ch PMCON1 18Ch
PIR2 0Dh PIE2 8Dh WPUC 10Dh PMCON2 18Dh
— 0Eh — 8Eh SLRCONC 10Eh PMADRL 18Eh
TMR1L 0Fh OSCCON 8Fh PCON 10Fh PMADRH 18Fh
TMR1H 10h FVR1CON0 90h TMR2 110h PMDATL 190h
T1CON 11h DAC1CON0 91h PR2 111h PMDATH 191h
T1GCON 12h DAC1REFL 92h T2CON 112h COG1PHR 192h
CCPR1L 13h DAC1REFH 93h HLTMR1 113h COG1PHF 193h
CCPR1H 14h — 94h HLTPR1 114h COG1BKR 194h
CCP1CON 15h — 95h HLT1CON0 115h COG1BKF 195h
— 16h OPA1CON0 96h HLT1CON1 116h COG1DBR 196h
— 17h — 97h HLTMR2 117h COG1DBF 197h
— 18h — 98h HLTPR2 118h COG1CON0 198h
— 19h — 99h HLT2CON0 119h COG1CON1 199h
— 1Ah — 9Ah HLT2CON1 11Ah COG1RIS 19Ah
— 1Bh CM2CON0 9Bh — 11Bh COG1RSIM 19Bh
ADRESL 1Ch CM2CON1 9Ch — 11Ch COG1FIS 19Ch
ADRESH 1Dh CM1CON0 9Dh — 11Dh COG1FSIM 19Dh
ADCON0 1Eh CM1CON1 9Eh SLPCCON0 11Eh COG1ASD0 19Eh
ADCON1 1Fh CMOUT 9Fh SLPCCON1 11Fh COG1ASD1 19Fh
20h A0h 120h 1A0h
General Purpose
Register
32 Bytes
General BFh
Purpose Unimplemented Unimplemented
C0h
Register Read as ‘0’ Read as ‘0’
80 Bytes
Unimplemented
Read as ‘0’
6Fh EFh 16Fh 1EFh

70h F0h 170h 1F0h
Common RAM Common RAM Common RAM
Common RAM
(Accesses (Accesses (Accesses
16 Bytes
70h – 7Fh) 70h – 7Fh) 70h – 7Fh)
7Fh FFh 17Fh 1FFh
Legend: = Unimplemented data memory locations, read as ‘0’.

PIC16F753/HV753
TABLE 2-1: PIC16F753/HV753 SPECIAL REGISTERS SUMMARY BANK 0
Value on
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR/BOR
Resets
Bank 0
00h INDF INDF<7:0> xxxx xxxx xxxx xxxx
01h TMR0 TMR0<7:0> xxxx xxxx uuuu uuuu
02h PCL PCL<7:0> 0000 0000 0000 0000
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
04h FSR FSR<7:0> xxxx xxxx uuuu uuuu
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
06h — Unimplemented — —
07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu
08h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
09h IOCCF — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 --00 0000 --00 0000
0Ah PCLATH — — — PCLATH<4:0> ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 0000 0000 0000 0000
0Ch PIR1 TMR1GIF ADIF — — HLTMR2IF HLTMR1IF TMR2IF TMR1IF 00--0000 00--0000
0Dh PIR2 — — C2IF C1IF — COG1IF — CCP1IF --00 -0-0 --00 -0-0
0Eh — Unimplemented — —
0Fh TMR1L TMR1L<7:0> xxxx xxxx uuuu uuuu
10h TMR1H TMR1H<7:0> xxxx xxxx uuuu uuuu
11h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 0000 00-0
12h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 0000 0x00
DONE
13h CCPR1L CCPR1L<7:0> xxxx xxxx uuuu uuuu
14h CCPR1H CCPR1H<7:0> xxxx xxxx uuuu uuuu
15h CCP1CON — — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch ADRESL Least Significant two bits of the left shifted result or eight bits of the right shifted result xxxx xxxx uuuu uuuu
1Dh ADRESH Most Significant eight bits of the left shifted A/D result or two bits of the right shifted result xxxx xxxx uuuu uuuu
1Eh ADCON0 ADFM — CHS<3:0> GO/DONE ADON 0-00 0000 0-00 0000
1Fh ADCON1 — ADCS<2:0> — — — ADPREF1 -000 ---0 -000 ---0
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented.

PIC16F753/HV753
Values on
Value on
POR/BOR
Resets
Bank 1
80h INDF INDF<7:0> xxxx xxxx uuuu uuuu
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS<2:0> 1111 1111 1111 1111
82h PCL PCL<7:0> 0000 0000 0000 0000
84h FSR FSR xxxx xxxx uuuu uuuu
85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
87h TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
88h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
89h IOCCP — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 --00 0000 --00 0000
8Ah PCLATH — — — PCLATH<4:0> ---0 0000 ---0 0000
8Ch PIE1 TMR1GIE ADIE — — HLTMR2IE HLTMR1IE TMR2IE TMR1IE 00-- 0000 00-- 0000
8Dh PIE2 — — C2IE C1IE — COG1IE — CCP1IE --00 -0-0 --00 -0-0
8Eh — Unimplemented — —
8Fh OSCCON — — IRCF<1:0> — HTS LTS — --01 -00- --uu -uu-
90h FVR1CON0 FVREN FVRRDY FVROE FVRBUFSS1 FVRBUFSS0 — — FVRBUFEN 0000 0--0 0000 0--0
91h DAC1CON0 DACEN DACFM DACOE — DACPSS1 DACPSS0 — — 000- 00-- 000- 00--
92h DAC1REFL Least Significant bit of the left shifted result or eight bits of the right shifted DAC setting 0000 0000 0000 0000
93h DAC1REFH Most Significant eight bits of the left shifted DAC setting or first bit of the right shifted result 0000 0000 0000 0000
96h OPA1CON OPA1EN — — OPA1UGM OPA1NCH<1:0> OPA1PCH<1:0> 0--0 0000 0--0 0000
9Ah — Unimplemented — —
9Bh CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100
9Ch CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000
9Dh CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100
9Eh CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000
9Fh CMOUT — — — — — — MCOUT2 MCOUT1 ---- --00 ---- --00

PIC16F753/HV753
Value on
Value on
POR/BOR
Resets
Bank 2
100h INDF INDF<7:0> xxxx xxxx xxxx xxxx
101h TMR0 TMR0<7:0> xxxx xxxx uuuu uuuu
102h PCL PCL<7:0> 0000 0000 0000 0000
105h LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu
107h LATC — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 --xx xxxx --uu uuuu
108h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
109h IOCCN — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 --00 0000 --00 0000
10Ah PCLATH — — — PCLATH<4:0> ---0 0000 ---0 0000
10Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
10Dh WPUC — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 --11 1111 --11 1111
10Eh SLRCONC — — SLRC5 SLRC4 — — — — --00 ---- --00 ----
10Fh PCON — — — — — — POR BOR ---- --qq ---- --uu
110h TMR2 TMR2<7:0> 0000 0000 0000 0000
111h PR2 PR2<7:0> 1111 1111 1111 1111
112h T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
113h HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Count 0000 0000 0000 0000
114h HLTPR1 HLTMR1 Module Period Register 1111 1111 1111 1111
115h HLT1CON0 — H1OUTPS<3:0> H1ON H1CKPS<1:0> -000 0000 -000 0000
116h HLT1CON1 H1FES H1RES — H1ERS<2:0> H1FEREN H1REREN 11-0 0000 11-0 0000
117h HLTMR2 Holding Register for the 8-bit Hardware Limit Timer2 Count 0000 0000 0000 0000
118h HLTPR2 HLTMR2 Module Period Register 1111 1111 1111 1111
119h HLT2CON0 — H2OUTPS<3:0> H2ON H2CKPS<1:0> -000 0000 -000 0000
11Ah HLT2CON1 H2FES H2RES — H2ERS<2:0> H2FEREN H2REREN 11-0 0000 11-0 0000
11Bh — Unimplemented — —
11Ch — Unimplemented — —
11Dh — Unimplemented — —
11Eh SLPCCON0 SC1EN — — SC1POL SC1TSS<1:0> — SC1INS 0-00 00-0 0-00 00-0
11Fh SLPCCON1 — — — SC1RNG SC1ISET<3:0> ---0 0000 ---0 0000

PIC16F753/HV753
TABLE 2-4: PIC16F753/HV753 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Values on
Value on
POR/BOR
Resets
Bank 3
180h INDF INDF<7:0> xxxx xxxx uuuu uuuu
181h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS<2:0> 1111 1111 1111 1111
182h PCL PCL<7:0> 0000 0000 0000 0000
185h ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
187h ANSELC — — — — ANSC3 ANSC2 ANSC1 ANSC0 ---- 0000 ---- 0000
188h APFCON — — — T1GSEL — — — — ---0 ---- ---0 ----
189h OSCTUNE — — — TUN<4:0> ---0 0000 ---0 0000
18Ah PCLATH — — — PCLATH<4:0> ---0 0000 ---0 0000
18Ch PMCON1 — — — — — WREN WR RD ---- -000 ---- -000
18Dh PMCON2 Program Memory Control Register 2 ---- ---- ---- ----
18Eh PMADRL PMADRL<7:0> 0000 0000 0000 0000
18Fh PMADRH — — — — — — PMADRH<1:0> ---- --00 ---- --00
190h PMDATL PMDATL<7:0> 0000 0000 0000 0000
191h PMDATH — — PMDATH<5:0> --00 0000 --00 0000
192h COG1PHR — — — — G1PHR<3:0> ---- xxxx ---- uuuu
193h COG1PHF — — — — G1PHF<3:0> ---- xxxx ---- uuuu
194h COG1BKR — — — — G1BKR<3:0> ---- xxxx ---- uuuu
195h COG1BKF — — — — G1BKF<3:0> ---- xxxx ---- uuuu
196h COG1DBR — — — — G1DBR<3:0> ---- xxxx ---- uuuu
197h COG1DBF — — — — G1DBF<3:0> ---- xxxx ---- uuuu
198h COG1CON0 G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD — G1MD 0000 00-0 0000 00-0
199h COG1CON1 G1RDBTS G1FDBTS — — — — G1CS<1:0> 00-- --00 00-- --00
19Ah COG1RIS — G1RIHLT2 G1RIHLT1 G1RIT2M G1RIFLT G1RICCP1 G1RIC2 G1RIC1 0000 0000 0000 0000
19Bh COG1RSIM — G1RMHLT2 G1RMHLT1 G1RMT2M G1RMFLT G1RMCCP1 G1RMC2 G1RMC1 0000 0000 0000 0000
19Ch COG1FIS — G1FIHLT2 G1FIHLT1 G1FIT2M G1FIFLT G1FICCP1 G1FIC2 G1FIC1 0000 0000 0000 0000
19Dh COG1FSIM — G1FMHLT2 G1FMHLT1 G1FMT2M G1FMFLT G1FMCCP1 G1FMC2 G1FMC1 0000 0000 0000 0000
19Eh COG1ASD0 C1ASDE C1ARSEN G1ASD1L<1:0> G1ASD0L<1:0> — — 0000 00-- 0000 00--
19Fh COG1ASD1 — — — G1ASDSHLT2 G1ASDSHLT1 G1ASDSC2 G1ASDSC1 G1ASDSFLT 0000 0000 0000 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented

PIC16F753/HV753
2.3 Global SFRs writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
2.3.1 STATUS REGISTER intended.
The STATUS register, shown in Register 2-1, contains: For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
• the arithmetic status of the ALU
as ‘000u u1uu’ (where u = unchanged).
• the Reset status
It is recommended, therefore, that only BCF, BSF,
• the bank select bits for data memory (RAM)
SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits, see Section 18.0
the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”.
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
(1)
IRP RP1 RP0 TO PD Z DC C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6 RP1: Register Bank Select bit (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 5 RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h-FFh)
0 = Bank 0 (00h-7Fh)
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit(2) (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(2) (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
2: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

PIC16F753/HV753
2.3.2 OPTION REGISTER
The OPTION register is a readable and writable Note: To achieve a 1:1 prescaler assignment for
register, which contains various control bits to Timer0, assign the prescaler to the WDT
configure: by setting PSA bit to ‘1’ of the OPTION
• Timer0/WDT prescaler register. See Section 6.1.3 “Software
Programmable Prescaler”.
• External RA2/INT interrupt
• Timer0
• Weak pull-ups on PORTA
REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RAPU INTEDG T0CS T0SE PSA PS<2:0>
bit 7 bit 0
Legend:
bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
BIT VALUE TIMER0 RATE WDT RATE
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

PIC16F753/HV753
2.3.3 INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt
The INTCON register is a readable and writable
condition occurs, regardless of the state of
register, which contains the various enable and flag bits
its corresponding enable bit or the Global
for TMR0 register overflow, IOCIE change and external
Enable bit, GIE of the INTCON register.
RA2/INT pin interrupts.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit(1)
1 = Enables the IOC change interrupt
0 = Disables the IOC change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 1 INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit
1 = An IOC pin has changed state and generated an interrupt
0 = No pin interrupts have been generated
Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.

PIC16F753/HV753
2.3.4 PIE1 REGISTER
The PIE1 register contains the Peripheral Interrupt
Note: Bit PEIE of the INTCON register must be
Enable bits, as shown in Register 2-4.
set to enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR1GIE ADIE — — HLTMR2IE HLTMR1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
bit 7 TMR1GIE: ADC Interrupt Enable bit

1 = Enables the TMR1 gate interrupt
0 = Disables the TMR1 gate interrupt
bit 6 ADIE: ADC Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5-4 Unimplemented: Read as ‘0’
bit 3 HLTMR2IE: HLT2 Interrupt Enable bit
1 = Enables the HLT2 interrupt
0 = Disables the HLT2 interrupt
bit 2 HLTMR1IE: HLT1 Interrupt Enable bit
1 = Enables the HLT1 interrupt
0 = Disables the HLT1 interrupt
bit 1 TMR2IE: Timer2 Interrupt Enable bit
bit 0 TMR1IE: Timer1 Interrupt Enable bit

PIC16F753/HV753
2.3.5 PIE2 REGISTER
The PIE2 register contains the Peripheral Interrupt
Note: Bit PEIE of the INTCON register must be
Enable bits, as shown in Register 2-5.
set to enable any peripheral interrupt.
REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
— — C2IE C1IE — COG1IE — CCP1IE
bit 7 bit 0
Legend:

bit 5 C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt
bit 4 C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 COG1IE: COG 1 Interrupt Flag bit
1 = COG1 interrupt enabled
0 = COG1 interrupt disabled
bit 0 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

PIC16F753/HV753
2.3.6 PIR1 REGISTER
The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-6.
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR1GIF ADIF — — HLTMR2IF HLTMR1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
bit 7 TMR1GIF: TMR1 Gate Interrupt Flag bit

1 = Timer1 gate interrupt is pending
0 = Timer1 gate interrupt is not pending
bit 6 ADIF: ADC Interrupt Flag bit
1 = ADC conversion complete
0 = ADC conversion has not completed or has not been started
bit 3 HLTMR2IF: HLT2 to HLTPR2 Match Interrupt Flag bit
1 = HLT2 to HLTPR2 match occurred (must be cleared in software)
0 = HLT2 to HLTPR2 match did not occur
bit 2 HLTMR1IF: HLT1 to HLTPR1 Match Interrupt Flag bit
1 = HLT1 to HLTPR1 match occurred (must be cleared in software)
0 = HLT1 to HLTPR1 match did not occur
bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match did not occur
bit 0 TMR1IF: Timer1 Interrupt Flag bit
1 = Timer1 rolled over (must be cleared in software)
0 = Timer1 has not rolled over

PIC16F753/HV753
2.3.7 PIR2 REGISTER
The PIR2 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-7.
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
— — C2IF C1IF — COG1IF — CCP1IF
bit 7 bit 0
Legend:

bit 5 C2IF: Comparator 1 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 4 C1IF: Comparator 1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 2 COG1IF: COG 1 Interrupt Flag bit
1 = COG1 has generated an auto-shutdown interrupt
0 = COG1 has NOT generated an auto-shutdown interrupt
bit 0 CCP1IF: ECCP Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode

PIC16F753/HV753
2.3.8 PCON REGISTER
The Power Control (PCON) register (see Table 19-2)
contains flag bits to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-8.
REGISTER 2-8: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-q/u R/W-q/u
— — — — — — POR BOR
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = unchanged

bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

PIC16F753/HV753
2.4 PCL and PCLATH 2.4.2 STACK
The Program Counter (PC) is 13 bits wide. The low byte The PIC16F753/HV753 Family has an 8-level x 13-bit
comes from the PCL register, which is a readable and wide hardware stack (see Figure 2-1). The stack space
writable register. The high byte (PC<12:8>) is not directly is not part of either program or data space and the
readable or writable and comes from PCLATH. On any Stack Pointer is not readable or writable. The PC is
Reset, the PC is cleared. Figure 2-3 shows the two PUSHed onto the stack when a CALL instruction is exe-
situations for the loading of the PC. The upper example cuted or an interrupt causes a branch. The stack is
in Figure 2-3 shows how the PC is loaded on a write to POPed in the event of a RETURN, RETLW or a RETFIE
PCL (PCLATH<4:0>  PCH). The lower example in instruction execution. PCLATH is not affected by a
Figure 2-3 shows how the PC is loaded during a CALL or PUSH or POP operation.
GOTO instruction (PCLATH<4:3>  PCH). The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
FIGURE 2-3: LOADING OF PC IN push overwrites the value that was stored from the first
DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and
so on).
PCH PCL
Instruction with
12 8 7 0 PCL as
Note 1: There are no Status bits to indicate Stack
PC Destination Overflow or Stack Underflow conditions.
PCLATH<4:0> 8 2: There are no instructions/mnemonics

5 ALU Result called PUSH or POP. These are actions
that occur from the execution of the
PCLATH CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
PCH PCL interrupt address.
12 11 10 8 7 0
PC GOTO, CALL
2.5 Indirect Addressing, INDF and
2
PCLATH<4:3> 11
OPCODE <10:0>
FSR Registers
The INDF register is not a physical register. Addressing
PCLATH the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
2.4.1 MODIFYING PCL register. Any instruction using the INDF register
Executing any instruction with the PCL register as the actually accesses data pointed to by the File Select
destination simultaneously causes the Program Register (FSR). Reading INDF itself indirectly will
Counter PC<12:8> bits (PCH) to be replaced by the produce 00h. Writing to the INDF register indirectly
contents of the PCLATH register. This allows the entire results in a no operation (although Status bits may be
contents of the program counter to be changed by affected). An effective 9-bit address is obtained by
writing the desired upper five bits to the PCLATH concatenating the 8-bit FSR and the IRP bit of the
register. When the lower eight bits are written to the STATUS register, as shown in Figure 2-4.
PCL register, all 13 bits of the program counter will A simple program to clear RAM location 40h-7Fh using
change to the values contained in the PCLATH register indirect addressing is shown in Example 2-1.
and those being written to the PCL register.
A computed GOTO is accomplished by adding an offset EXAMPLE 2-1: INDIRECT ADDRESSING
to the program counter (ADDWF PCL). Care should be MOVLW 0x40 ;initialize pointer
exercised when jumping into a look-up table or MOVWF FSR ;to RAM
program branch table (computed GOTO) by modifying NEXT CLRF INDF ;clear INDF register
the PCL register. Assuming that PCLATH is set to the INCF FSR ;inc pointer
table start address, if the table length is greater than BTFSS FSR,7 ;all done?
GOTO NEXT ;no clear next
255 instructions or if the lower eight bits of the memory
CONTINUE ;yes continue
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
Implementing a Table Read (DS00556).

PIC16F753/HV753
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F753/HV753
Direct Addressing Indirect Addressing
RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0
Bank Select Location Select Bank Select Location Select

00 01 10 11
00h 180h
Data
Memory
7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
For memory map detail, see Figure 2-2.

PIC16F753/HV753
3.0 FLASH PROGRAM MEMORY 3.1 PMADRH and PMADRL Registers
SELF-READ/SELF-WRITE The PMADRH and PMADRL registers can address up
CONTROL to a maximum of 1K words of program memory.
The Flash program memory is readable and writable When selecting a program address value, the Most
during normal operation (full VDD range). This memory Significant Byte (MSB) of the address is written to the
is not directly mapped in the register file space. PMADRH register and the Least Significant Byte
Instead, it is indirectly addressed through the Special (LSB) is written to the PMADRL register.
Function Registers (see Registers 3-1 to 3-5). There
are six SFRs used to read and write this memory: 3.2 PMCON1 and PMCON2 Registers
• PMCON1 PMCON1 is the control register for the data program
• PMCON2 memory accesses.
• PMDATL Control bits RD and WR initiate read and write,
• PMDATH respectively. These bits cannot be cleared, only set in
• PMADRL software. They are cleared in hardware at completion
• PMADRH of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
When interfacing the program memory block, the termination of a write operation.
PMDATL and PMDATH registers form a two-byte word
which holds the 14-bit data for read/write, and the The WREN bit, when set, will allow a write operation.
PMADRL and PMADRH registers form a two-byte On power-up, the WREN bit is clear.
word which holds the 10-bit address of the Flash loca- PMCON2 is not a physical register. Reading PMCON2
tion being accessed. These devices have 1K words of will read all ‘0’s. The PMCON2 register is used
program Flash with an address range from 0000h to exclusively in the Flash memory write sequence.
03FFh.
The program memory allows a single-word read and a
four-word write. A four-word write automatically erases
the row of the location and writes the new data (erase
before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash program memory.
Depending on the settings of the Flash Program
Memory Enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory; however, reads of the program memory are
allowed.
When the Flash program memory Code Protection
(CP) bit in the Configuration Word register is enabled,
the program memory is code-protected, and the
device programmer (ICSP™) cannot access data or
program memory.

PIC16F753/HV753
3.3 Register Definitions: Flash Program Memory Control
REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

PMDATL<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMDATL<7:0>: Eight Least Significant Data bits to Write or Read from Program Memory
REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

PMADRL<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMADRL<7:0>: Eight Least Significant Address bits for Program Memory Read/Write Operation
REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — PMDATH<5:0>
bit 7 bit 0
Legend:

bit 5-0 PMDATH<5:0>: Six Most Significant Data bits from Program Memory
REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — PMADRH<1:0>
bit 7 bit 0
Legend:

bit 1-0 PMADRH<1:0>: Specifies the two Most Significant Address bits or High bits for Program Memory Reads.

PIC16F753/HV753
REGISTER 3-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
— — — — — WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0 RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software.
0 = Does not initiate a program Flash read
REGISTER 3-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 Flash Memory Unlock Pattern bits:

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.

PIC16F753/HV753
3.4 Reading the Flash Program
Memory
To read a program memory location, the user must
write two bytes of the address to the PMADRL and
PMADRH registers, and then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle after to read the data. This causes the
second instruction immediately following the “BSF
PMCON1,RD” instruction to be ignored. The data is
available in the very next cycle in the PMDATL and
PMDATH registers; it can be read as two bytes in the
following instructions. PMDATL and PMDATH regis-
ters will hold this value until another read or until it is
written to by the user (during a write operation).
EXAMPLE 3-1: FLASH PROGRAM READ

BANKSEL PM_ADR ; Change STATUS bits RP1:0 to select bank with PMADRL
MOVLW MS_PROG_PM_ADDR ;
MOVWF PMADRH ; MS Byte of Program Address to read
MOVLW LS_PROG_PM_ADDR ;
MOVWF PMADRL ; LS Byte of Program Address to read
BANKSEL PMCON1 ; Bank to containing PMCON1
BSF PMCON1, RD ; PM Read
NOP ; First instruction after BSF PMCON1,RD executes normally
NOP ; Any instructions here are ignored as program

; memory is read in second cycle after BSF PMCON1,RD
;
BANKSEL PMDATL ; Bank to containing PMADRL
MOVF PMDATL, W ; W = LS Byte of Program PMDATL
MOVF PMDATH, W ; W = MS Byte of Program PMDATL

PIC16F753/HV753
FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR PC PC + 1 PMADRH,PMADRL PC+3

PC +3 PC + 4 PC + 5
Flash DATA INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)
INSTR (PC - 1) BSF PMCON1,RD INSTR (PC + 1) NOP INSTR (PC + 3) INSTR (PC + 4)
Executed here Executed here Executed here Executed here Executed here Executed here
RD bit
PMDATH
PMDATL
Register
PMRHLT

PIC16F753/HV753
3.5 Writing the Flash Program which the erase takes place (i.e., the last word of the
Memory sixteen-word block erase). This is not Sleep mode as
the clocks and peripherals will continue to run. After
A word of the Flash program memory may only be the four-word write cycle, the processor will resume
written to if the word is in an unprotected segment of operation with the third instruction after the PMCON1
memory. write instruction. The above sequence must be
Flash program memory must be written in four-word repeated for the higher 12 words.
blocks. See Figure 3-2 and Figure 3-3 for more details.
A block consists of four words with sequential 3.6 Protection Against Spurious Write
addresses, with a lower boundary defined by an
There are conditions when the device should not write
address, where PMADRL<1:0> = 00. All block writes to
to the program memory. To protect against spurious
program memory are done as 16-word erase by four-
writes, various mechanisms have been built in. On
word write operations. The write operation is edge-
power-up, WREN is cleared. Also, the Power-up Timer
aligned and cannot occur across boundaries.
(64 ms duration) prevents program memory writes.
To write program data, it must first be loaded into the
The write initiate sequence and the WREN bit help
buffer registers (see Figure 3-2). This is accomplished
prevent an accidental write during brown-out, power
by first writing the destination address to PMADRL and
glitch or software malfunction.
PMADRH and then writing the data to PMDATL and
PMDATH. After the address and data have been set
up, then the following sequence of events must be 3.7 Operation During Code-Protect
executed: When the device is code-protected, the CPU is able to
1. Write 55h, then AAh, to PMCON2 (Flash read and write unscrambled data to the program
programming sequence). memory.
2. Set the WR control bit of the PMCON1 register.
All four buffer register locations should be written to 3.8 Operation During Write Protect
with correct data. If less than four words are being When the program memory is write-protected, the CPU
written to in the block of four words, then a read from can read and execute from the program memory. The
the program memory location(s) not being written to portions of program memory that are write-protected
must be performed. This takes the data from the can be modified by the CPU using the PMCON
program location(s) not being written and loads it into registers, but the protected program memory cannot be
the PMDATL and PMDATH registers. Then the modified using ICSP mode.
sequence of events to transfer data to the buffer
registers must be executed.
To transfer data from the buffer registers to the program
memory, the PMADRL and PMADRH must point to the
last location in the four-word block (PMADRL<1:0> =
11). Then the following sequence of events must be
executed:
1. Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
2. Set control bit WR of the PMCON1 register to
begin the write operation.
The user must follow the same specific sequence to
initiate the write for each word in the program block,
writing each program word in sequence (000, 001,
010, 011). When the write is performed on the last
word (PMADRL<1:0> = 11), a block of sixteen words is
automatically erased and the content of the four-word
buffer registers are written into the program memory.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in

PIC16F753/HV753
FIGURE 3-2: BLOCK WRITES TO 1K FLASH PROGRAM MEMORY
7 5 0 7 0 If at a new row
PMDATH PMDATL sixteen words of
Flash are erased,
then four buffers
6 8 are transferred
to Flash
automatically
First word of block after this word
to be written is written
14 14 14 14
PMADRL<1:0> = 00 PMADRL<1:0> = 01 PMADRL<1:0> = 10 PMADRL<1:0> = 11
Buffer Register Buffer Register Buffer Register Buffer Register
Program Memory
FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash PC + 1 PMADRH,PMADRL PC + 2 PC + 3 PC + 4
ADDR
INSTR INSTR ignored

Flash read PMDATH,PMDATL INSTR (PC+2) INSTR (PC+3)
DATA (PC) (PC + 1)
Processor halted (INSTR (PC + 2)

BSF PMCON1,WR INSTR (PC + 1) NOP INSTR (PC + 3)
Executed here PM Write Time NOP
Executed here Executed here Executed here Executed here
Flash
Memory
Location
WR bit
PMWHLT

PIC16F753/HV753
An example of the complete four-word write sequence
is shown in Example 3-2. The initial address is loaded
into the PMADRH and PMADRL register pair; the four
words of data are loaded using indirect addressing.
EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
; A valid starting address (the least significant bits = '00')
; is loaded in ADDRH:ADDRL
; ADDRH, ADDRL and DATADDR are all located in data memory
;
BANKSEL PMADRH
MOVF ADDRH,W ;Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVF DATAADDR,W ;Load initial data address
MOVWF FSR ;
LOOP MOVF INDF,W ;Load first data byte into lower
MOVWF PMDATL ;
INCF FSR,F ;Next byte
MOVF INDF,W ;Load second data byte into upper
MOVWF PMDATH ;
INCF FSR,F ;
BANKSEL PMCON1
BSF PMCON1,WREN ;Enable writes
BCF INTCON,GIE ;Disable interrupts (if using)
BTFSC INTCON,GIE ;See AN576
GOTO $-2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Required Sequence
MOVLW 55h ;Start of required write sequence:
MOVWF PMCON2 ;Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ;Write 0AAh
BSF PMCON1,WR ;Set WR bit to begin write
NOP ;Required to transfer data to the buffer
NOP ;registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF PMCON1,WREN ;Disable writes
BSF INTCON,GIE ;Enable interrupts (comment out if not using interrupts)
BANKSEL PMADRL
MOVF PMADRL, W
INCF PMADRL,F ;Increment address
ANDLW 0x03 ;Indicates when sixteen words have been programmed
SUBLW 0x03 ;Change value for different size write blocks
;0x0F = 16 words
;0x0B = 12 words
;0x07 = 8 words
;0x03 = 4 words
BTFSS STATUS,Z ;Exit on a match,
GOTO LOOP ;Continue if more data needs to be written

PIC16F753/HV753
TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
PMCON1 — — — — — WREN WR RD 27
PMCON2 Program Memory Control Register 2 27
PMADRL PMADRL<7:0> 26
PMADRH — — — — — — PMADRH<1:0> 26
PMDATL PMDATL<7:0> 26
PMDATH — — PMDATH<5:0> 26
INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 17
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
* Page provides register information.
TABLE 3-2: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — — DEBUG CLKOUTEN WRT<1:0> BOREN<1:0>

CONFIG(1) 150
7:0 — CP MCLRE PWRTE WDTE — — FOSC0
Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by Flash program memory.
Note 1: See Configuration Word register (Register 19-1) for operation of all register bits.

PIC16F753/HV753
4.0 OSCILLATOR MODULE The internal oscillator module provides the following
selectable system clock modes:
4.1 Overview • 8 MHz (HFINTOSC)
• 4 MHz (HFINTOSC Postscaler)
The oscillator module has a variety of clock sources
and selection features that allow it to be used in a wide • 1 MHz (HFINTOSC Postscaler)
range of applications while maximizing performance • 31 kHz (LFINTOSC)
and minimizing power consumption. Figure 4-1
illustrates a block diagram of the oscillator module.
The oscillator module can be configured in one of two
clock modes.
1. EC (external clock)
2. INTOSC (internal oscillator)
Clock Source modes are configured by the FOSC bit in
the Configuration Word register (CONFIG).
FIGURE 4-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
EC Enable
(Figure 4-2)
EC
CLKIN 1
Internal Oscillator Prescaler
MUX
÷1 11 System Clock
(CPU and
HFINTOSC Enable HFINTOSC Peripherals)
÷2 10
(Figure 4-2) 8 MHz 0
÷8 01
LFINTOSC Enable LFINTOSC 00 FOSC

31 kHz
(Figure 4-2)
IRCF<1:0>
COG Clock Source
WDT Clock Source
FIGURE 4-2: OSCILLATOR ENABLE
FOSC0
EC Enable
Sleep
FOSC0
IRCF<1:0>  00 HFINTOSC Enable
Sleep
FOSC0
IRCF<1:0> = 00
Sleep LFINTOSC Enable
WDTE

PIC16F753/HV753
4.2 Clock Source Modes 4.2.2 INTERNAL CLOCK MODE
Clock Source modes can be classified as external or Internal Clock mode configures the internal oscillators
internal: as the system clock source. The Internal Clock mode is
selected when the FOSC0 bit of the Configuration
• The External Clock mode relies on an external Word is cleared. The source and frequency are
clock for the clock source. For example, a clock selected with the IRCF<1:0> bits of the OSCCON
module or clock output from another circuit. register.
• Internal clock sources are contained internally
When one of the HFINTOSC frequencies is selected,
within the oscillator module. The oscillator module
the frequency of the internal oscillator can be trimmed
has four selectable clock frequencies:
by adjusting the TUN<4:0> bits of the OSCTUNE
- 8 MHz register.
- 4 MHz
Operation after a Power-on Reset (POR) or wake-up
- 1 MHz from Sleep is delayed by the oscillator start-up time.
- 31 kHz Delays are typically longer for the LFINTOSC than
The system clock can be selected between external or HFINTOSC because of the very low-power operation
internal clock sources via the FOSC0 bit of the and relatively narrow bandwidth of the LF internal
Configuration Word register (CONFIG). oscillator. However, when another peripheral keeps the
oscillator running during Sleep, the start-up time is
4.2.1 EC MODE delayed to allow the memory bias to stabilize.
The External Clock (EC) mode allows an externally
generated logic as the system clock source. The EC FIGURE 4-4: INTERNAL CLOCK MODE
clock mode is selected when the FOSC0 bit of the OPERATION
Configuration Word is set.
When operating in this mode, an external clock source I/O CLKIN(1)
must be connected to the CLKIN input. The CLKOUT is
PIC® MCU
available for either general purpose I/O or system clock
output. Figure 4-3 shows the pin connections for EC I/O CLKOUT(1)
mode.
Because the PIC® MCU design is fully static, stopping
Note 1: Alternate pin functions are listed in
the external clock input will have the effect of halting the
Section 1.0 “Device Overview”.
device while leaving all data intact. Upon restarting the
external clock, the device will resume operation as if no
time had elapsed. 4.2.2.1 Oscillator Ready Bits
The HTS and LTS bits of the OSCCON register indicate
FIGURE 4-3: EXTERNAL CLOCK (EC) the status of the HFINTOSC and LFINTOSC,
MODE OPERATION respectively. When either bit is set, it indicates that the
corresponding oscillator is running and stable.
Clock from CLKIN

Ext. System
PIC® MCU
I/O CLKOUT(1)
Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

PIC16F753/HV753
4.3 System Clock Output 4.4 Oscillator Delay upon Wake-Up,
The CLKOUT pin is available for general purpose I/O or
Power-Up, and Base Frequency
system clock output. The CLKOUTEN bit of the Change
Configuration Word controls the function of the In applications where the OSCTUNE register is used to
CLKOUT pin. shift the HFINTOSC frequency, the application should
When the CLKOUTEN bit is cleared, the CLKOUT pin not expect the frequency to stabilize immediately. In
is driven by the selected internal oscillator frequency this case, the frequency may shift gradually toward the
divided by 4. The corresponding I/O pin always reads new value. The time for this frequency shift is less than
‘0’ in this configuration. eight cycles of the base frequency.
The CLKOUT signal may be used to provide a clock for A short delay is invoked upon power-up and when
external circuitry, synchronization, calibration, test or waking from sleep to allow the memory bias circuitry to
other application requirements. stabilize. Table 4-1 shows examples where the oscillator
When the CLKOUTEN bit is set, the system clock out delay is invoked.
function is disabled and the CLKOUT pin is available for
general purpose I/O.
TABLE 4-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay
Sleep/POR INTOSC 31 kHz to 8 MHz 10 s internal delay to allow memory
Sleep/POR EC DC – 20 MHz bias to stabilize.

PIC16F753/HV753
4.5 Register Definitions: Oscillator Control
REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 U-0 R/W-0/u R/W-1/u U-0 R-0/u R-0/u U-0
— — IRCF<1:0> — HTS LTS —
bit 7 bit 0
Legend:

bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits
11 = 8 MHz
10 = 4 MHz
01 = 1 MHz (Reset default)
00 = 31 kHz (LFINTOSC)
bit 2 HTS: HFINTOSC Status bit
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Status bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable

PIC16F753/HV753
4.5.1 OSCTUNE REGISTER The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
The oscillator is factory-calibrated, but can be adjusted
in software by writing to the OSCTUNE register When the OSCTUNE register is modified, the frequency
(Register 4-2). will begin shifting to the new frequency. Code execution
continues during this shift. There is no indication that the
shift has occurred.
REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — TUN<4:0>
bit 7 bit 0
Legend:

bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register
on Page
OSCCON — — IRCF<1:0> — HTS LTS — 37
OSCTUNE — — — TUN<4:0> 38
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
clock sources.
TABLE 4-3: SUMMARY OF CONFIGURATION WORD CLOCK SOURCES

Register
on Page

CONFIG(1) 150
Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by clock sources.
Note 1: See Configuration Word register (Register 19-1) for operation of all register bits.

PIC16F753/HV753
5.0 I/O PORTS EXAMPLE 5-1: INITIALIZING PORTA
; This code example illustrates
Depending on the device selected and peripherals ; initializing the PORTA register. The
enabled, there are up to two ports available. In general, ; other ports are initialized in the same
when a peripheral is enabled, that pin may not be used ; manner.
as a general purpose I/O pin.
Each port has three standard registers for its operation. BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
These registers are: BANKSEL LATA ;Data Latch
• TRISx registers (data direction) CLRF LATA ;
BANKSEL ANSELA ;
• PORTx registers (reads the levels on the pins of CLRF ANSELA ;digital I/O
the device) BANKSEL TRISA ;
• LATx registers (output latch) MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
Some ports may have one or more of the following ;outputs
additional registers. These registers are:
• ANSELx (analog select)
• WPUx (weak pull-up)
• SLRCONx registers (slew rate)
The Data Latch (LATx registers) is useful for read-
modify-write operations on the values that the I/O pins
are driving.
A write operation to the LATx register has the same
affect as a write to the corresponding PORTx register.
A read of the LATx register reads the values held in the
I/O PORT latches, while a read of the PORTx register
reads the actual I/O pin value.
Ports with analog functions also have an ANSELx
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure 5-1.
FIGURE 5-1: GENERIC I/O PORTA

OPERATION
Read LATA
TRISA
D Q
Write LATA
Write PORTA
CK VDD
Data Register
Data Bus
I/O pin
Read PORTA
To peripherals
VSS
ANSELA

PIC16F753/HV753
5.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 5-1. For this device family, the
following functions can be moved between different
pins.
• Timer1 Gate
• COG1
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
5.2 Register Definitions: Alternate Pin Function Control

REGISTER 5-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0 U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0
— — — T1GSEL — — — —
bit 7 bit 0
Legend:
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

bit 4 T1GSEL: Timer 1 Gate Input Pin Selection bit
1 = T1G function is on RA3
0 = T1G function is on RA4

PIC16F753/HV753
5.3 PORTA and TRISA Registers
TABLE 5-1: PORTA OUTPUT PRIORITY
PORTA is a 6-bit wide port with five bidirectional and one
input-only pin. The corresponding data direction register Pin Name Function Priority
is TRISA (Register 5-2). Setting a TRISA bit (= 1) will RA0 ICSPDAT
make the corresponding PORTA pin an input (i.e., FVROUT
disable the output driver). Clearing a TRISA bit (= 0) will DACOUT
make the corresponding PORTA pin an output (i.e., C1IN0+
enables output driver and puts the contents of the output RA0
latch on the selected pin). The exception is RA3, which RA1 FVRIN
is input-only and its TRIS bit will always read as ‘1’. ICSPCLK
Example 5-1 shows how to initialize PORTA. VREF+
C1IN0-
Reading the PORTA register (Register 5-2) reads the C2IN0-
status of the pins, whereas writing to it will write to the RA1
PORT latch. All write operations are read-modify-write
RA2 COG1FLT
operations. Therefore, a write to a port implies that the T0CKI
port pins are read, this value is modified and then C1OUT
written to the PORT data latch. RA3 reads ‘0’ when INT
MCLRE = 1. RA2
The TRISA register controls the direction of the RA3 MCLR
PORTA pins, even when they are being used as analog VPP
inputs. The user must ensure the bits in the TRISA T1G
register are maintained set when using them as analog RA3
inputs. I/O pins configured as analog input always read RA4 CLKOUT
‘0’. T1G
RA4
Note: The ANSEL register must be initialized to
RA5 CLKIN
configure an analog channel as a digital T1CKI
input. Pins configured as analog inputs will RA5
read ‘0’ and cannot generate an interrupt.
5.3.1 PORTA FUNCTIONS AND OUTPUT

PRIORITIES
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 5-1.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as comparator inputs, are
not shown in the priority lists. These inputs are active
when the peripheral is enabled and the input multiplexer
for the pin is selected. The Analog mode, set with the
ANSELA register, disables the digital input buffer
thereby preventing excessive input current when the
analog input voltage is between logic states. Digital
output functions may control the pin when it is in Analog
mode with the priority shown in Table 5-1.

PIC16F753/HV753
5.4 Additional Pin Functions 5.4.3 INTERRUPT-ON-CHANGE
Every PORTA pin on the PIC16F753 has an interrupt- Each PORTA pin is individually configurable as an
on-change option and a weak pull-up option. The next interrupt-on-change pin. Control bits IOCA enable or
three sections describe these functions. disable the interrupt function for each pin. Refer to
Register 5-7. The interrupt-on-change is disabled on a
5.4.1 ANSELA REGISTER Power-on Reset.
The ANSELA register (Register 5-5) is used to For enabled interrupt-on-change pins, the values are
configure the Input mode of an I/O pin to analog. compared with the old value latched on the last read of
Setting the appropriate ANSELA bit high will cause all PORTA. The ‘mismatch’ outputs of the last read are
digital reads on the pin to be read as ‘0’ and allow OR’d together to set the PORTA Change Interrupt Flag
analog functions on the pin to operate correctly. bit (IOCIF) in the INTCON register (Register 2-3).
The state of the ANSELA bits has no effect on digital This interrupt can wake the device from Sleep. The
output functions. A pin with TRIS clear and ANSEL set user, in the Interrupt Service Routine, clears the
will still operate as a digital output, but the Input mode interrupt by:
will be analog. This can cause unexpected behavior a) Any read of PORTA AND Clear flag bit IOCIF.
when executing read-modify-write instructions on the This will end the mismatch condition;
affected port.
OR
Note: The ANSELA bits default to the Analog b) Any write of PORTA AND Clear flag bit IOCIF
mode after Reset. To use any pins as will end the mismatch condition;
digital general purpose or peripheral
inputs, the corresponding ANSEL bits A mismatch condition will continue to set flag bit IOCIF.
must be initialized to ‘0’ by user software. Reading PORTA will end the mismatch condition and
allow flag bit IOCIF to be cleared. The latch holding the
5.4.2 WEAK PULL-UPS last read value is not affected by a MCLR nor BOR
Reset. After these Resets, the IOCIF flag will continue
Each of the PORTA pins, except RA3, has an to be set if a mismatch is present.
individually configurable internal weak pull-up. Control
bits WPUx enable or disable each pull-up. Refer to Note: If a change on the I/O pin should occur
Register 5-6. Each weak pull-up is automatically turned when any PORTA operation is being
off when the port pin is configured as an output. The executed, then the IOCIF interrupt flag
pull-ups are disabled on a Power-on Reset by the may not get set.
RAPU bit of the OPTION_REG register. A weak pull-up
is automatically enabled for RA3 when configured as
MCLR and disabled when RA3 is an I/O. There is no
software control of the MCLR pull-up.

PIC16F753/HV753
5.5 Register Definitions: PORTA Control
REGISTER 5-2: PORTA: PORTA REGISTER
U-0 U-0 R/W-x/u R/W-x/u R-x/x R/W-x/u R/W-x/u R/W-x/u
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin
values.
REGISTER 5-3: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISA5 TRISA4 TRISA3(1) TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:

bit 5-0 TRISA<5:0>: PORTA Tri-State Control bits(1)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA3 always reads ‘1’.
REGISTER 5-4: LATA: PORTA DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
— — LATA5 LATA4 — LATA2 LATA1 LATA0
bit 7 bit 0
Legend:

bit 5-4 LATA<5:4>: PORTA Output Latch Value bits(1)
bit 2-0 LATA<2:0>: PORTA Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.

PIC16F753/HV753
REGISTER 5-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— — — ANSA4 — ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:

bit 4 ANSA4: Analog Select Between Analog or Digital Function on Pin RA4 bit
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
bit 2-0 ANSA<2:0> Analog Select Between Analog or Digital Function on Pin RA<2:0> bits
1 = Analog input. Pin is assigned as analog input.(1)
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-
change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of
the voltage on the pin.
REGISTER 5-6: WPUA: WEAK PULL-UP PORTA REGISTER

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:

bit 5-0 WPUA<5:0>: Weak Pull-up Control bits(1,2,3)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled
as an input and reads as ‘0’.

PIC16F753/HV753
REGISTER 5-7: IOCAP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
bit 7 bit 0
Legend:

bit 5-0 IOCAP<5:0>: Interrupt-on-Change Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 5-8: IOCAN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
bit 7 bit 0
Legend:

bit 5-0 IOCAN<5:0>: Interrupt-on-Change Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will
be set upon detecting an edge.
REGISTER 5-9: IOCAF: INTERRUPT-ON-CHANGE FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 5-0 IOCAF<5:0>: Interrupt-on-Change Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RBx, or when IOCANx = 1 and a falling edge was
detected on RAx.
0 = No change was detected, or the user cleared the detected change.

PIC16F753/HV753
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
ADCON0 ADFM — CHS<3:0> GO/DONE ADON 109

ADCON1 — ADCS<2:0> — — — ADPREF1 110
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 44
APFCON — — — T1GSEL — — — — 40
CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 129
CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 130
DAC1CON0 DACEN DACFM DACOE — DACPSS1 DACPSS0 — — 120
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 45
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 45
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 45
LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 43
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS<2:0> 16
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 43
TRISA — — TRISA5 TRISA4 TRISA3(1) TRISA2 TRISA1 TRISA0 43
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

PIC16F753/HV753
5.6 PORTC Registers
TABLE 5-3: PORTC OUTPUT PRIORITY
PORTC is a 6-bit wide port with five bidirectional and one
input-only pin. The corresponding data direction register Pin Name Function Priority
is TRISC (Register 5-2). Setting a TRISC bit (= 1) will RC0 OPA1IN+
make the corresponding PORTC pin an input (i.e., C2IN0+
disable the output driver). Clearing a TRISC bit (= 0) will RC0
make the corresponding PORTC pin an output (i.e., RC1 OPA1IN-
enables output driver and puts the contents of the output C1IN1-
latch on the selected pin). The exception is RA3, which C2IN1-
is input-only and its TRIS bit will always read as ‘1’. RC1
Example 5-1 shows how to initialize PORTC. RC2 SLPCIN
Reading the PORTC register (Register 5-2) reads the OPA1OUT
status of the pins, whereas writing to it will write to the C1IN2-
C2IN2-
PORT latch. All write operations are read-modify-write
RC2
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then RC3 C1IN3-
C2IN3-
written to the PORT data latch. RC3 reads ‘0’ when
RC3
MCLRE = 1.
RC4 COG1OUT1
The TRISC register controls the direction of the C2OUT
PORTC pins, even when they are being used as RC4
analog inputs. The user must ensure the bits in the RC5 COG1OUT0
TRISC register are maintained set when using them as CCP1
analog inputs. I/O pins configured as analog input RC5
always read ‘0’.
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
5.6.1 PORTC FUNCTIONS AND OUTPUT

PRIORITIES
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 5-1.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as comparator inputs, are
not shown in the priority lists. These inputs are active
when the peripheral is enabled and the input multiplexer
for the pin is selected. The Analog mode, set with the
ANSELC register, disables the digital input buffer
thereby preventing excessive input current when the
analog input voltage is between logic states. Digital
output functions may control the pin when it is in Analog
mode with the priority shown in Table 5-1.

PIC16F753/HV753
5.7 Additional Pin Functions 5.7.3 INTERRUPT-ON-CHANGE
Every PORTC pin on the PIC16F753 has an interrupt- Each PORTC pin is individually configurable as an
on-change option and a weak pull-up option. The next interrupt-on-change pin. Control bit IOCC enables or
three sections describe these functions. disables the interrupt function for each pin. Refer to
Register 5-7. The interrupt-on-change is disabled on a
5.7.1 ANSELC REGISTER Power-on Reset.
The ANSELC register (Register 5-5) is used to For enabled interrupt-on-change pins, the values are
configure the Input mode of an I/O pin to analog. compared with the old value latched on the last read of
Setting the appropriate ANSELC bit high will cause all PORTC. The ‘mismatch’ outputs of the last read are
digital reads on the pin to be read as ‘0’ and allow OR’d together to set the PORTC Change Interrupt Flag
analog functions on the pin to operate correctly. bit (IOCIF) in the INTCON register (Register 2-3).
The state of the ANSELC bits has no effect on digital This interrupt can wake the device from Sleep. The
output functions. A pin with TRIS clear and ANSEL set user, in the Interrupt Service Routine, clears the
will still operate as a digital output, but the Input mode interrupt by:
will be analog. This can cause unexpected behavior a) Any read of PORTC AND Clear flag bit IOCIF.
when executing read-modify-write instructions on the This will end the mismatch condition;
affected port.
OR
Note: The ANSELC bits default to the Analog b) Any write of PORTC AND Clear flag bit IOCIF
mode after Reset. To use any pins as will end the mismatch condition;
digital general purpose or peripheral
inputs, the corresponding ANSEL bits A mismatch condition will continue to set flag bit IOCIF.
must be initialized to ‘0’ by user software. Reading PORTC will end the mismatch condition and
allow flag bit IOCIF to be cleared. The latch holding the
5.7.2 WEAK PULL-UPS last read value is not affected by a MCLR nor BOR
Reset. After these Resets, the IOCIF flag will continue
Each of the PORTC pins, except RC3, has an to be set if a mismatch is present.
individually configurable internal weak pull-up. Control
bits WPUx enable or disable each pull-up. Refer to Note: If a change on the I/O pin should occur
Register 5-6. Each weak pull-up is automatically turned when any PORTC operation is being
off when the port pin is configured as an output. The executed, then the IOCIF interrupt flag
pull-ups are disabled on a Power-on Reset by the may not get set.
RAPU bit of the OPTION_REG register. A weak pull-up
is automatically enabled for RC3 when configured as 5.7.4 SLEW RATE CONTROL
MCLR and disabled when RC3 is an I/O. There is no Two of the PORTC pins, RC4 and RC5, are equipped
software control of the MCLR pull-up. with high current driver circuitry. The SLRCONC register
provides reduced slew rate control to mitigate possible
EMI radiation from these pins.

PIC16F753/HV753
5.8 Register Definitions: PORTC Control
REGISTER 5-10: PORTC: PORTC REGISTER

U-0 U-0 R/W-x/u R/W-x/u R-x/x R/W-x/u R/W-x/u R/W-x/u
— — RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:

bit 5-0 RC<5:0>: PORTC I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
REGISTER 5-11: TRISC: PORTC TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:

bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
REGISTER 5-12: LATC: PORTC DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:

bit 5-0 LATC<5:0>: PORTC Output Latch Value bits(1)
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.

PIC16F753/HV753
REGISTER 5-13: SLRCONC: SLEW RATE CONTROL REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0
— — SLRC5 SLRC4 — — — —
bit 7 bit 0
Legend:

bit 5-4 SLRC<5:4>: Slew Rate Control Register bit
1 = Slew rate control enabled
0 = Slew rate control disabled
REGISTER 5-14: ANSELC: PORTC ANALOG SELECT REGISTER

U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — ANSC3 ANSC2 ANSC1 ANSC0
bit 7 bit 0
Legend:

bit 3-0 ANSC<3:0>: Analog Select Between Analog or Digital Function on Pin RC<3:0> bits
1 = Analog input. Pin is assigned as analog input.(1)
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-
change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of
the voltage on the pin.

PIC16F753/HV753
REGISTER 5-15: WPUC: WEAK PULL-UP PORTC REGISTER

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
bit 7 bit 0
Legend:

bit 5-0 WPUC<5:0>: Weak Pull-up Control bits(1,2,3)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISC = 0).
3: The RC3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled
as an input and reads as ‘0’.
REGISTER 5-16: IOCCP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
bit 7 bit 0
Legend:

bit 5-0 IOCCP<5:0>: Interrupt-on-Change Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.

PIC16F753/HV753
REGISTER 5-17: IOCCN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
bit 7 bit 0
Legend:

bit 5-0 IOCCN<5:0>: Interrupt-on-Change Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
REGISTER 5-18: IOCCF: INTERRUPT-ON-CHANGE FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 5-0 IOCCF<5:0>: Interrupt-on-Change Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCCPx = 1 and a rising edge was detected on RBx, or when IOCCNx = 1 and a falling
edge was detected on RCx.
0 = No change was detected, or the user cleared the detected change.

PIC16F753/HV753
TABLE 0-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register
on Page

ANSELC — — — — ANSC3 ANSC2 ANSC1 ANSC0 44
APFCON — — — T1GSEL — — — — 40
CM2CON1 C2NTP C2INTN C2PCH<2:0> C2NCH<2:0> 130
IOCCF — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 45
IOCCN — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 45
IOCCP — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 45
LATC — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 43
PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 43
SLRCONC — — SLRC5 SLRC4 — — — — 50
TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 43
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16F753/HV753
6.0 TIMER0 MODULE 6.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used
following features: as either an 8-bit timer or an 8-bit counter.
• 8-bit timer/counter register (TMR0)
6.1.1 8-BIT TIMER MODE
• 8-bit prescaler (shared with Watchdog Timer)
When used as a timer, the Timer0 module will
• Programmable internal or external clock source
increment every instruction cycle (without prescaler).
• Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the
• Interrupt on overflow OPTION register to ‘0’.
Figure 6-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
6.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION_REG register. Counter mode is
selected by setting the T0CS bit of the OPTION register
to ‘1’.
FIGURE 6-1: TIMER0 WITH SHARED PRESCALE BLOCK DIAGRAM
FOSC/4
Data Bus
0
8
1
Sync
1
2 TCY TMR0
Shared Prescale
T0CKI 0
pin 0
T0SE T0CS PSA Set Flag bit T0IF
8-bit
on Overflow
Prescaler
1
PSA
8
PS<2:0> 1
Watchdog
WDT
Timer
Time-out
LFINTOSC
2 0
(Figure 4-1)
PSA
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in Register 6-1.

2: WDTE bit is in Register 19-1.

PIC16F753/HV753
6.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the
PRESCALER WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 6-2).
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler EXAMPLE 6-2: CHANGING PRESCALER
assignment is controlled by the PSA bit of the OPTION (WDT  TIMER0)
register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and
must be cleared to a ‘0’. ;prescaler
BANKSEL OPTION_REG ;
There are eight prescaler options for the Timer0 mod-
MOVLW b’11110000’ ;Mask TMR0 select and
ule ranging from 1:2 to 1:256. The prescale values are
ANDWF OPTION_REG,W ;prescaler bits
selectable via the PS<2:0> bits of the OPTION register. IORLW b’00000011’ ;Set prescale to 1:16
In order to have a 1:1 prescaler value for the Timer0 MOVWF OPTION_REG ;
module, the prescaler must be assigned to the WDT
module.
6.1.4 TIMER0 INTERRUPT
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to Timer0 will generate an interrupt when the TMR0
the TMR0 register will clear the prescaler. register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
When the prescaler is assigned to WDT (PSA = 1), a TMR0 register overflows, regardless of whether or not
CLRWDT instruction will clear the prescaler along with the Timer0 interrupt is enabled. The T0IF bit must be
the WDT. cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
6.1.3.1 Switching Prescaler Between
Timer0 and WDT Modules Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
As a result of having the prescaler assigned to either
frozen during Sleep.
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
6.1.5 USING TIMER0 WITH AN
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence EXTERNAL CLOCK
shown in Example 6-1 must be executed. When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
EXAMPLE 6-1: CHANGING PRESCALER accomplished by sampling the prescaler output on the
(TIMER0  WDT) Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
BANKSEL TMR0 ;
clock source must meet the timing requirements as
CLRWDT ;Clear WDT
shown in Section 22.0 “Electrical Specifications”.
CLRF TMR0 ;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W ;bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ;to 1:32

PIC16F753/HV753
6.2 Register Definitions: Option and Timer0 Control
REGISTER 6-1: OPTION_REG: OPTION REGISTER

RAPU INTEDG T0CS T0SE PSA PS<2:0>
bit 7 bit 0
Legend:
bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values in WPU register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register on
Page
TMR0 TMR0<7:0> 54*
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
module.

PIC16F753/HV753
7.0 TIMER1 MODULE WITH GATE • Gate Toggle mode
CONTROL • Gate Single-pulse mode
• Gate Value Status
The Timer1 module is a 16-bit timer/counter with the
• Gate Event Interrupt
following features:
Figure 7-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Selectable internal or external clock sources
• 2-bit prescaler
• Synchronous or asynchronous operation
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
• Selectable Gate Source Polarity
FIGURE 7-1: TIMER1 BLOCK DIAGRAM

T1GSS<1:0>
T1GSPM
T1G 00
T0_overflow 01
1
C1OUT_sync 10 0 Single Pulse D Q T1GVAL
0
C2OUT_sync 11 1 Acq. Control
Q1
D Q
T1GPOL T1GGO/DONE
CK Q
TMR1ON Interrupt
set bit
R
T1GTM det TMR1GIF
TMR1GE
set flag bit
TMR1IF
TMR1ON
EN
(2)
TMR1
T1_overflow Synchronized Clock Input
TMR1H TMR1L Q D 0
1
T1CLK
T1SYNC
TMR1CS<1:0>
LFINTOSC 11
(1)
T1CKI 10 Prescaler
FOSC Synchronize(3)
01 1,2,4,8
Internal Clock det
00
2
FOSC/4 FOSC/2
Internal Clock T1CKPS<1:0> Internal Sleep
Clock Input
Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.

PIC16F753/HV753
7.1 Timer1 Operation 7.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> bits of the T1CON register are used
which is accessed through the TMR1H:TMR1L register to select the clock source for Timer1. Table 7-2 displays
pair. Writes to TMR1H or TMR1L directly update the the clock source selections.
counter.
When used with an internal clock source, the module is TABLE 7-2: CLOCK SOURCE
a timer and increments on every instruction cycle. SELECTIONS
When used with an external clock source, the module
can be used as either a timer or counter and TMR1CS<1:0> Clock Source
increments on every selected edge of the external 11 Temperature Sense Oscillator
source.
10 External Clocking on T1CKI Pin
Timer1 is enabled by configuring the TMR1ON and
01 System Clock (FOSC)
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 7-1 displays the Timer1 enable 00 Instruction Clock (FOSC/4)
selections.
7.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TABLE 7-1: TIMER1 ENABLE
TMR1H:TMR1L register pair will increment on multiples
SELECTIONS of FOSC or FOSC/4 as determined by the Timer1
Timer1 prescaler.
TMR1ON TMR1GE
Operation
7.2.2 EXTERNAL CLOCK SOURCE
0 0 Off
When the external clock source is selected, the Timer1
0 1 Off
module may work as a timer or a counter. When enabled
1 0 Always On to count, Timer1 is incremented on the rising edge of the
1 1 Count Enabled external clock input T1CKI.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge (see Figure 7-2)
after any one or more of the following
conditions:
• Timer1 enabled after POR Reset
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON = 1) when T1CKI
is low.
7.2.3 WDT OSCILLATOR

When the Watchdog is selected, Timer 1 will use the
LFINTOSC that is used to operate the Watchdog
Timer. This is the same oscillator as the LFINTOSC
used as the system clock. Selecting this option will
enable the oscillator even when the LFINTOSC or the
Watchdog are not in use. This oscillator will continue
to operate when in Sleep mode.

PIC16F753/HV753
7.3 Timer1 Prescaler 7.5 Timer1 Gate
Timer1 has four prescaler options allowing one, two, four Timer1 can be configured to count freely or the count
or eight divisions of the clock input. The T1CKPS bits of can be enabled and disabled using Timer1 gate
the T1CON register control the prescale counter. The circuitry. This is also referred to as Timer1 gate count
prescale counter is not directly readable or writable; enable.
however, the prescaler counter is cleared upon a write to Timer1 gate can also be driven by multiple selectable
TMR1H or TMR1L. sources.
7.4 Timer1 Operation in 7.5.1 TIMER1 GATE COUNT ENABLE

Asynchronous Counter Mode The Timer1 gate is enabled by setting the TMR1GE bit
If control bit T1SYNC of the T1CON register is set, the of the T1GCON register. The polarity of the Timer1 gate
external clock input is not synchronized. The timer is configured using the T1GPOL bit of the T1GCON
increments asynchronously to the internal phase register.
clocks. If external clock source is selected then the When Timer1 Gate (T1G) input is active, Timer1 will
timer will continue to run during Sleep and can increment on the rising edge of the Timer1 clock
generate an interrupt on overflow, which will wake-up source. When Timer1 gate input is inactive, no
the processor. However, special precautions in incrementing will occur and Timer1 will hold the current
software are needed to read/write the timer (see count. See Figure 7-3 for timing details.
Section 7.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
TABLE 7-3: TIMER1 GATE ENABLE
Note: When switching from synchronous to SELECTIONS
asynchronous operation, it is possible to
skip an increment. When switching from T1CLK T1GPOL T1G Timer1 Operation
asynchronous to synchronous operation,  0 0 Counts
it is possible to produce an additional  0 1 Holds Count
increment.
 1 0 Holds Count
7.4.1 READING AND WRITING TIMER1 IN  1 1 Counts
ASYNCHRONOUS COUNTER
MODE 7.5.2 TIMER1 GATE SOURCE
SELECTION
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid The Timer1 gate source can be selected from one of
read (taken care of in hardware). However, the user four different sources. Source selection is controlled by
should keep in mind that reading the 16-bit timer in two the T1GSS bits of the T1GCON register. The polarity
8-bit values itself, poses certain problems, since the for each available source is also selectable. Polarity
timer may overflow between the reads. selection is controlled by the T1GPOL bit of the
T1GCON register.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers, TABLE 7-4: TIMER1 GATE SOURCES
while the register is incrementing. This may produce an
T1GSS Timer1 Gate Source
unpredictable value in the TMR1H:TMR1L register pair.
11 SYNCC2OUT
10 SYNCC1OUT
01 Overflow of Timer0
(TMR0 increments from FFh to 00h)
00 Timer1 Gate Pin

PIC16F753/HV753
7.5.2.1 T1G Pin Gate Operation 7.5.5 TIMER1 GATE VALUE STATUS
The T1G pin is one source for Timer1 gate control. It When Timer1 gate value status is utilized, it is possible
can be used to supply an external source to the Timer1 to read the most current level of the gate control value.
gate circuitry. The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
7.5.2.2 Timer0 Overflow Gate Operation gate is not enabled (TMR1GE bit is cleared).
When Timer0 increments from FFh to 00h, a low-to-
high pulse will automatically be generated and 7.5.6 TIMER1 GATE EVENT INTERRUPT
internally supplied to the Timer1 gate circuitry. When Timer1 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
7.5.2.3 C1OUT/C2OUT Gate Operation of a gate event. When the falling edge of T1GVAL
The outputs from the Comparator C1 and C2 modules occurs, the TMR1GIF flag bit in the PIR1 register will be
can be used as gate sources for the Timer1 module. set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
7.5.3 TIMER1 GATE TOGGLE MODE The TMR1GIF flag bit operates even when the Timer1
When Timer1 Gate Toggle mode is enabled, it is gate is not enabled (TMR1GE bit is cleared).
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single-level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 7-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
7.5.4 TIMER1 GATE SINGLE-PULSE

MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/DONE bit. See Figure 7-5 for
timing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 7-6 for timing
details.

PIC16F753/HV753
7.6 Timer1 Interrupt 7.8 CCP Capture/Compare Time Base
The Timer1 register pair (TMR1H:TMR1L) increments The CCP module uses the TMR1H:TMR1L register
to FFFFh and rolls over to 0000h. When Timer1 rolls pair as the time base when operating in Capture or
over, the Timer1 interrupt flag bit of the PIR1 register is Compare mode.
set. To enable the interrupt on rollover, you must set In Capture mode, the value in the TMR1H:TMR1L
these bits: register pair is copied into the CCPR1H:CCPR1L
• TMR1ON bit of the T1CON register register pair on a configured event.
• TMR1IE bit of the PIE1 register In Compare mode, an event is triggered when the value
• PEIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in
• GIE bit of the INTCON register the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine. For more information, see Section 10.0 “Capture/
Compare/PWM Modules”.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
7.9 CCP Special Event Trigger
enabling interrupts.
When the CCP is configured to trigger a special event,
7.7 Timer1 Operation During Sleep the trigger will clear the TMR1H:TMR1L register pair.
This special event does not cause a Timer1 interrupt.
Timer1 can only operate during Sleep when set up in The CCP module may still be configured to generate a
Asynchronous Counter mode or with the internal CCP interrupt.
watchdog clock source. In this mode, the clock source
In this mode of operation, the CCPR1H:CCPR1L
can be used to increment the counter. To set up the
register pair becomes the period register for Timer1.
timer to wake the device:
Timer1 should be synchronized to the FOSC/4 to utilize
• TMR1ON bit of the T1CON register must be set
the Special Event Trigger. Asynchronous operation of
• TMR1IE bit of the PIE1 register must be set Timer1 can cause a Special Event Trigger to be
• PEIE bit of the INTCON register must be set missed.
• T1SYNC bit of the T1CON register must be set In the event that a write to TMR1H or TMR1L coincides
• TMR1CS bits of the T1CON register must be with a Special Event Trigger from the CCP, the write will
configured take precedence.
• TMR1GE bit of the T1GCON register must be For more information, see Section 12.2.5 “Special
configured Event Trigger”.
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
FIGURE 7-2: TIMER1 INCREMENTING EDGE
T1CKI
T1CKI
TMR1 enabled
Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

PIC16F753/HV753
FIGURE 7-3: TIMER1 GATE COUNT ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4
FIGURE 7-4: TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

PIC16F753/HV753
FIGURE 7-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL

PIC16F753/HV753
FIGURE 7-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4
Set by hardware on Cleared by

TMR1GIF Cleared by software falling edge of T1GVAL software

PIC16F753/HV753
7.10 Register Definitions: Timer1 Control
REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON
bit 7 bit 0
Legend:
bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Watchdog timer oscillator
10 = External clock from T1CKI pin (on the rising edge)
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
bit 3 T1OSCEN: This bit is ignored.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 gate flip-flop

PIC16F753/HV753
REGISTER 7-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0>
bit 7 bit 0
Legend:
bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle mode bit
1 = Timer1 Gate Toggle mode is enabled.
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single-Pulse mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2 T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits
11 = SYNCC2OUT
10 = SYNCC1OUT
01 = Timer0 overflow output
00 = Timer1 gate pin

PIC16F753/HV753

Register
on Page
APFCON — — — T1GSEL — — — — 40
CCP1CON — — DC1B<1:0> CCP1M<3:0> 80
PIE1 TMR1GIE ADIE — — HLTMR2IE HLTMR1IE TMR2IE TMR1IE 18
PIR1 TMR1GIF ADIF — — HLTMR2IF HLTMR1IF TMR2IF TMR1IF 20
TMR1H TMR1H<7:0> 57*
TMR1L TMR1L<7:0> 57*
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 43
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 65
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0>
66
DONE
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC16F753/HV753
8.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
The Timer2 module is an 8-bit timer with the following 00h and the PR2 register is set to FFh.
features:
Timer2 is turned on by setting the TMR2ON bit in the
• 8-bit timer register (TMR2) T2CON register to a ‘1’. Timer2 is turned off by clearing
• 8-bit period register (PR2) the TMR2ON bit to a ‘0’.
• Interrupt on TMR2 match with PR2 The Timer2 prescaler is controlled by the T2CKPS bits
• Software programmable prescaler (1:1, 1:4, 1:16, in the T2CON register. The Timer2 postscaler is
1:64) controlled by the T2OUTPS bits in the T2CON register.
• Software programmable postscaler (1:1 to 1:16) The prescaler and postscaler counters are cleared
when:
See Figure 8-1 for a block diagram of Timer2.
• A write to TMR2 occurs.
8.1 Timer2 Operation • A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
The clock input to the Timer2 module is the system Reset, Watchdog Timer Reset, or Brown-out
instruction clock (FOSC/4). The clock is fed into the Reset).
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescaler is then used to Note: TMR2 is not cleared when T2CON is
increment the TMR2 register. written.
The values of TMR2 and PR2 are constantly compared

to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 8-1: TIMER2 BLOCK DIAGRAM

T2_match
Prescaler To Peripherals
TMR2 R
Fosc/4 1:1, 1:4, 1:16, 1:64
2
Postscaler set bit
T2CKPS<1:0> Comparator
1:1 to 1:16 TMR2IF
PR2 T2OUTPS<3:0>

PIC16F753/HV753
8.2 Register Definitions: Timer2 Control
REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0>
bit 7 bit 0
Legend:

bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is ON
0 = Timer2 is OFF
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
10 = Prescaler is 16

Register on
Page
PR2 PR2<7:0> 68*
TMR2 TMR2<7:0> 68*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 69
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

PIC16F753/HV753
9.0 HARDWARE LIMIT TIMER (HLT) The HLT module incorporates the following features:
MODULE • 8-bit Read-Write Timer Register (HLTMRx)
• 8-bit Read-Write Period register (HLTPRx)
The Hardware Limit Timer (HLT) module is a version of
the Timer2-type modules. In addition to all the Timer2- • Software programmable prescaler:
type features, the HLT can be reset on rising and falling - 1:1
events from selected peripheral outputs. - 1:4
The HLT primary purpose is to act as a timed hardware - 1:16
limit to be used in conjunction with asynchronous - 1:64
analog feedback applications. The external Reset • Software programmable postscaler
source synchronizes the HLTMRx to an analog - 1:1 to 1:16, inclusive
application.
• Interrupt on HLTMRx match with HLTPRx
In normal operation, the external Reset source from the • Eight selectable timer Reset inputs (two reserved)
analog application should occur before the HLTMRx
• Reset on rising and falling event
matches the HLTPRx. This resets HLTMRx for the next
period and prevents the HLTimerx Output from going Refer to Figure 9-1 for a block diagram of the HLT.
active.
When the external Reset source fails to generate a
signal within the expected time, (allowing the HLTMRx
to match the HLTPRx), then the HLTimerx Output
becomes active.
FIGURE 9-1: HLTMRx BLOCK DIAGRAM
HxRES
CCP1 out 000
C1OUT 001
HxREREN Detect 1
C2OUT 010
0
COG1FLT 011
COG1OUT0 100
0
COG1OUT1 101
HxFEREN 1
‘0’ 110 Detect
‘0’ 111 HLT Output
HxFES
To COG module
Fosc/4 Prescaler
HLTMRx
HxON 1:1, 1:4, 1:16, 1:64
Postscaler
HxCKPS<1:0> Comparator HLTMRxIF
1:1 to 1:16
HLTPRx HxOUTPS<3:0>

PIC16F753/HV753
9.1 HLT Operation 9.3 Peripheral Resets
The clock input to the HLT module is the system Resets driven from the selected peripheral output
instruction clock (FOSC/4). HLTMRx increments on prevents the HLTMRx from matching the HLTPRx
each rising clock edge. register and generating an output. In this manner, the
A 4-bit counter/prescaler on the clock input provides the HLT can be used as a hardware time limit to other
following prescale options: peripherals.
• Direct input In this device, the primary purpose of the HLT is to limit
the COG PWM duty cycle. Normally, the COG opera-
• Divide-by-4
tion uses analog feedback to determine the PWM duty
• Divide-by-16 cycle. The same feedback signal is used as an HLT
• Divide-by-64 Reset input. The HLTPRx register is set to occur at the
The prescale options are selected by the prescaler maximum allowed duty cycle. If the analog feedback to
control bits, HxCKPS<1:0> of the HLTxCON0 register. the COG exceeds the maximum time, then an
HLTMRx-to-HLTPRx match will occur and generate the
The value of HLTMRx is compared to that of the Period output needed to limit the COG drive output.
register, HLTPRx, on each clock cycle. When the two
values match,then the comparator generates a match The HLTMRx can be reset by one of several selectable
signal as the HLTimerx output. This signal also resets peripheral sources. Reset inputs include:
the value of HLTMRx to 00h on the next clock rising • CCP1 output
edge and drives the output counter/postscaler (see • Comparator 1 output
Section 9.2 “HLT Interrupt”).
• Comparator 2 output
The HLTMRx and HLTPRx registers are both directly • COGxFLT pin
readable and writable. The HLTMRx register is cleared
• COG1OUT0
on any device Reset, whereas the HLTPRx register
initializes to FFh. Both the prescaler and postscaler • COG1OUT1
counters are cleared on any of the following events: The external Reset input is selected with the
• A write to the HLTMRx register HxERS<2:0> bits of the HLTxCON1 register. High and
low Reset enables are selected with the HxREREN and
• A write to the HLTxCON0 register
HxFEREN bits, respectively. Setting the HxRES and
• Power-on Reset (POR) HxFES bits makes the respective rising and falling
• Brown-out Reset (BOR) Reset events edge sensitive. Reset inputs that are not
• MCLR Reset edge sensitive are level sensitive.
• Watchdog Timer (WDT) Reset HLTMRx Resets are synchronous with the HLT clock.
• Stack Overflow Reset In other words, HLTMRx is cleared on the rising edge
• Stack Underflow Reset of the HLT clock after the enabled Reset event occurs.
• RESET Instruction If an enabled external Reset occurs at the same time a
write occurs to the TMR4A register, the write to the
Note: HLTMRx is not cleared when HLTxCON0 is
timer takes precedence and pending Resets are
written.
cleared.
9.2 HLT Interrupt 9.4 HLTimerx Output

The HLT can also generate an optional device interrupt. The unscaled output of HLTMRx is available only to the
The HLTMRx output signal (HLTMRx-to-HLTPRx match) COG module, where it is used as a selectable limit to
provides the input for the 4-bit counter/postscaler. The the maximum COG period.
overflow output of the postscaler sets the HLTMRxIF bit
of the PIR1 register. The interrupt is enabled by setting
the HLTMRx Match Interrupt Enable bit, HLTMRxIE of
9.5 HLT Operation During Sleep
the PIE1 register. The HLT cannot be operated while the processor is in
A range of 16 postscale options (from 1:1 through 1:16 Sleep mode. The contents of the HLTMRx register will
inclusive) can be selected with the postscaler control remain unchanged while the processor is in Sleep
bits, HxOUTPS<3:0>, of the HLTxCON0 register. mode.

PIC16F753/HV753
9.6 Register Definitions: HLT Control Registers
REGISTER 9-1: HLTxCON0: HLTx CONTROL REGISTER 0

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— HxOUTPS<3:0> HxON HxCKPS<1:0>
bit 7 bit 0
Legend:

bit 6-3 HxOUTPS<3:0>: Hardware Limit Timerx Output Postscaler Select bits
bit 2 HxON: Hardware Limit Timerx On bit
1 = Timer is ON
0 = Timer is OFF
bit 1-0 HxCKPS<1:0>: Hardware Limit Timer x Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4

PIC16F753/HV753
REGISTER 9-2: HLTxCON1: HLTx CONTROL REGISTER 1

R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
HxFES HxRES — HxERS<2:0> HxFEREN HxREREN
bit 7 bit 0
Legend:
bit 7 HxFES: Hardware Limit Timerx Falling Edge Sensitivity bit

1 = Edge sensitive
0 = Level sensitive
bit 6 HxRES: Hardware Limit Timerx Rising Edge Sensitivity bit
1 = Edge sensitive
0 = Level sensitive
bit 4-2 HxERS<2:0>: Hardware Limit Timerx External Reset Source Select bits
000 = CCP1 Out
001 = C1OUT
010 = C2OUT
011 = COG1FLT
100 = COG1OUT0
101 = COG1OUT1
110 = Reserved - ‘0’ input
111 = Reserved - ‘0’ input
bit 1 HxFEREN: Hardware Limit Timerx Falling Event Reset Enable bit
1 = HLTMRx will reset on the first clock after a falling event of selected Reset source
0 = Falling events of selected source have no effect
bit 0 HxREREN: Hardware Limit Timerx Rising Event Reset Enable bit
1 = HLTMRx will reset on the first clock after a rising event of selected Reset source
0 = Rising events of selected source have no effect
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH HLT

Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 80

HLTMRx Holding Register for the 8-bit Hardware Limit TimerX Count 70*
HLTPRx HLTMRx Module Period Register 70*
HLTxCON0 — HxOUTPS<3:0> HxON HxCKPS<1:0> 72
HLTxCON1 HxFES HxRES — HxERS<2:0> HxFEREN HxREREN 73
Legend: — = unimplemented location, read as ‘0’. Shaded cells do not affect the HLT module operation.

PIC16F753/HV753
10.0 CAPTURE/COMPARE/PWM 10.1.2 TIMER1 MODE RESOURCE
MODULES Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP1 module to use the capture
The Capture/Compare/PWM module is a peripheral feature. In Asynchronous Counter mode, the capture
which allows the user to time and control different operation may not work.
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows See Section 7.0 “Timer1 Module with Gate Control”
the timing of the duration of an event. The Compare for more information on configuring Timer1.
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The 10.1.3 SOFTWARE INTERRUPT MODE
PWM mode can generate Pulse-Width Modulated When the Capture mode is changed, a false capture
signals of varying frequency and duty cycle. interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE2 register clear to
10.1 Capture Mode avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR2 register
Capture mode makes use of the 16-bit Timer1 following any change in Operating mode.
resource. When an event occurs on the CCP1 pin, the
16-bit CCPR1H:CCPR1L register pair captures and Note: Clocking Timer1 from the system clock
stores the 16-bit value of the TMR1H:TMR1L register (FOSC) should not be used in Capture
pair, respectively. An event is defined as one of the mode. In order for Capture mode to
following and is configured by the CCP1M<3:0> bits of recognize the trigger event on the CCP1
the CCP1CON register: pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
• Every falling edge external clock source.
• Every rising edge
• Every 4th rising edge 10.1.4 CCP1 PRESCALER
• Every 16th rising edge There are four prescaler settings specified by the
When a capture is made, the Interrupt Request Flag bit CCP1M<3:0> bits of the CCP1CON register.
CCP1IF of the PIR2 register is set. The interrupt flag Whenever the CCP1 module is turned off, or the CCP1
must be cleared in software. If another capture occurs module is not in Capture mode, the prescaler counter
before the value in the CCPR1H, CCPR1L register pair is cleared. Any Reset will clear the prescaler counter.
is read, the old captured value is overwritten by the new Switching from one capture prescaler to another does not
captured value. clear the prescaler and may generate a false interrupt. To
Figure 10-1 shows a simplified diagram of the Capture avoid this unexpected operation, turn the module off by
operation. clearing the CCP1CON register before changing the
prescaler. Example 10-1 demonstrates the code to
10.1.1 CCP1 PIN CONFIGURATION perform this function.
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit. EXAMPLE 10-1: CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If the CCP1 pin is configured as an output,
a write to the port can cause a capture BANKSEL CCP1CON ;Set Bank bits to point
;to CCP1CON
condition.
CLRF CCP1CON ;Turn CCP1 module off
MOVLW NEW_CAPT_PS ;Load the W reg with
FIGURE 10-1: CAPTURE MODE ;the new prescaler
OPERATION BLOCK ;move value and CCP1 ON
MOVWF CCP1CON ;Load CCP1CON with this
DIAGRAM
;value
Set Flag bit CCP1IF
(PIR2 register)
Prescaler
 1, 4, 16
CCP1 CCPR1H CCPR1L
pin
and Capture
Edge Detect Enable
TMR1H TMR1L
CCP1M<3:0>
System Clock (FOSC)

PIC16F753/HV753
10.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. If the Timer1 clock input source is a
clock that is not disabled during Sleep, Timer1 will con-
tinue to operate and Capture mode will operate during
Sleep to wake the device. The T1CKI is an example of
a clock source that will operate during Sleep.
When the input source to Timer1 is disabled during
Sleep, such as the HFINTOSC, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 80
CCPR1L CCPR1L<7:0> 74
CCPR1H CCPR1H<7:0> 74
PIE2 — — C2IE C1IE — COG1IE — CCP1IE 19
PIR2 — — C2IF C1IF — COG1IF — CCP1IF 21
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 66
DONE
(1)
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.

PIC16F753/HV753
10.2 Compare Mode 10.2.2 TIMER1 MODE RESOURCE
Compare mode makes use of the 16-bit Timer1 In Compare mode, Timer1 must be running in either
resource. The 16-bit value of the CCPR1H:CCPR1L Timer mode or Synchronized Counter mode. The
register pair is constantly compared against the 16-bit compare operation may not work in Asynchronous
value of the TMR1H:TMR1L register pair. When a Counter mode.
match occurs, one of the following events can occur: See Section 7.0 “Timer1 Module with Gate Control”
• Toggle the CCP1 output for more information on configuring Timer1.
• Set the CCP1 output Note: Clocking Timer1 from the system clock
• Clear the CCP1 output (FOSC) should not be used in Compare
• Generate a Special Event Trigger mode. In order for Compare mode to
recognize the trigger event on the CCP1
• Generate a Software Interrupt
pin, TImer1 must be clocked from the
The action on the pin is based on the value of the instruction clock (FOSC/4) or from an
CCP1M<3:0> control bits of the CCP1CON register. At external clock source.
the same time, the interrupt flag CCP1IF bit is set.
All Compare modes can generate an interrupt. 10.2.3 SOFTWARE INTERRUPT MODE
Figure 10-2 shows a simplified diagram of the When Generate Software Interrupt mode is chosen
Compare operation. (CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
FIGURE 10-2: COMPARE MODE register).
OPERATION BLOCK
10.2.4 SPECIAL EVENT TRIGGER
DIAGRAM
When Special Event Trigger mode is chosen
CCP1M<3:0> (CCP1M<3:0> = 1011), the CCP1 module does the
Mode Select
following:
Set CCP1IF Interrupt Flag • Resets Timer1
(PIR2)
CCP1 4 • Starts an ADC conversion if ADC is enabled
Pin CCPR1H CCPR1L
The CCP1 module does not assert control of the CCP1
Q S pin in this mode.
Output Comparator
R Logic Match
The Special Event Trigger output of the CCP1 occurs
TMR1H TMR1L immediately upon a match between the TMR1H,
TRIS
Output Enable TMR1L register pair and the CCPR1H, CCPR1L regis-
ter pair. The TMR1H, TMR1L register pair is not reset
Special Event Trigger
until the next rising edge of the Timer1 clock. The
Special Event Trigger output starts an A/D conversion
(if the A/D module is enabled). This allows the
10.2.1 CCP1 PIN CONFIGURATION
CCPR1H, CCPR1L register pair to effectively provide a
The user must configure the CCP1 pin as an output by 16-bit programmable period register for Timer1.
clearing the associated TRIS bit. TABLE 10-2: SPECIAL EVENT TRIGGER
Device CCP1
Note: Clearing the CCP1CON register will force
PIC16F753 CCP1
the CCP1 compare output latch to the
PIC16HV753
default low level. This is not the PORT I/O
data latch. Refer to Section 12.0 “Analog-to-Digital Converter
(ADC) Module” for more information.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.

PIC16F753/HV753
10.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 80
CCPR1L CCPR1L<7:0> 74
CCPR1H CCPR1H<7:0> 74
PIE1 TMR1- ADIE — — HLTMR2IE HLTMR1IE TMR2IE TMR1IE 18
GIE
PIR1 TMR1- ADIF — — HLTMR2IF HLTMR1IF TMR2IF TMR1IF 20
GIF
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 66
DONE
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

PIC16F753/HV753
10.3 PWM Overview FIGURE 10-3: CCP1 PWM OUTPUT
SIGNAL
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between Period
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is Pulse Width
considered the on state and the low portion of the signal TMR2 = PR2
is considered the off state. The high portion, also known TMR2 = CCPR1H:CCP1CON<5:4>
as the pulse width, can vary in time and is defined in
TMR2 = 0
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The FIGURE 10-4: SIMPLIFIED PWM BLOCK
PWM period is defined as the duration of one complete DIAGRAM
cycle or the total amount of on and off time combined.
CCP1CON<5:4>
Duty Cycle Registers
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher CCPR1L
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on CCPR1H(2) (Slave)
CCP1
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty Comparator R Q
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied. (1) S
TMR2
Figure 10-3 shows a typical waveform of the PWM TRIS
signal.
Comparator
Clear Timer,
10.3.1 STANDARD PWM OPERATION toggle CCP1 pin and
latch duty cycle
The standard PWM mode generates a Pulse-Width PR2
Modulation (PWM) signal on the CCP1 pin with up to 10
Note 1: The 8-bit timer TMR2 register is concatenated
bits of resolution. The period, duty cycle, and resolution
with the 2-bit internal system clock (FOSC), or
are controlled by the following registers:
two bits of the prescaler, to create the 10-bit
• PR2 registers time base.
• T2CON registers 2: In PWM mode, CCPR1H is a read-only register.
• CCPR1L registers
• CCP1CON registers
Figure 10-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the
CCP1 pin.
2: Clearing the CCP1CON register will
relinquish control of the CCP1 pin.

PIC16F753/HV753
10.3.2 SETUP FOR PWM OPERATION When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
The following steps should be taken when configuring
the CCP1 module for standard PWM operation: • TMR2 is cleared
1. Disable the CCP1 pin output driver by setting • The CCP1 pin is set. (Exception: If the PWM duty
the associated TRIS bit. cycle = 0%, the pin will not be set.)
2. Load the PR2 register with the PWM period • The PWM duty cycle is latched from CCPR1L into
value. CCPR1H.
3. Configure the CCP1 module for the PWM mode
by loading the CCP1CON register with the Note: The Timer postscaler (see Section 8.1
appropriate values. “Timer2 Operation”) is not used in the
determination of the PWM frequency.
4. Load the CCPR1L register and the DC1B<1:0>
bits of the CCP1CON register, with the PWM
10.3.4 PWM DUTY CYCLE
duty cycle value.
5. Configure and start Timer2: The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
• Clear the TMR2IF interrupt flag bit of the
DC1B<1:0> bits of the CCP1CON register. The
PIR1 register. See Note below.
CCPR1L contains the eight MSbs and the DC1B<1:0>
• Configure the T2CKPS bits of the T2CON bits of the CCP1CON register contain the two LSbs.
register with the Timer prescale value. CCPR1L and DC1B<1:0> bits of the CCP1CON
• Enable the Timer by setting the TMR2ON register can be written to at any time. The duty cycle
bit of the T2CON register. value is not latched into CCPR1H until after the period
6. Enable PWM output pin: completes (i.e., a match between PR2 and TMR2
• Wait until the Timer overflows and the registers occurs). While using the PWM, the CCPR1H
TMR2IF bit of the PIR1 register is set. See register is read-only.
Note below. Equation 10-2 is used to calculate the PWM pulse
• Enable the CCP1 pin output driver by clear- width.
ing the associated TRIS bit. Equation 10-3 is used to calculate the PWM duty cycle
Note: In order to send a complete duty cycle and ratio.
period on the first PWM output, the above
steps must be included in the setup EQUATION 10-2: PULSE WIDTH
sequence. If it is not critical to start with a
complete PWM signal on the first output, Pulse Width =  CCPR1L:CCP1CON<5:4>  
then step 6 may be ignored.
T OSC  (TMR2 Prescale Value)
10.3.3 PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the EQUATION 10-3: DUTY CYCLE RATIO
formula of Equation 10-1.
 CCPRxL:CCPxCON<5:4> 
Duty Cycle Ratio = -----------------------------------------------------------------------
EQUATION 10-1: PWM PERIOD 4  PRx + 1 
PWM Period =   PR2  + 1   4  T OSC  The CCPR1H register and a 2-bit internal latch are
(TMR2 Prescale Value) used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Note 1: TOSC = 1/FOSC
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR1H and
2-bit latch, then the CCP1 pin is cleared (see
Figure 10-4).

PIC16F753/HV753
10.4 Register Definitions: CCP Control
REGISTER 10-1: CCP1CON: CCP1 CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — DC1B<1:0> CCP1M<3:0>
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0 CCP1M<3:0>: CCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0001 = Reserved
0010 = Compare mode: toggle output on match
0011 = Reserved
0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCP1 pin low; set output on compare match (set CCP1IF)
1001 = Compare mode: initialize CCP1 pin high; clear output on compare match (set CCP1IF)
1010 = Compare mode: generate software interrupt only; CCP1 pin reverts to I/O state
1011 = Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D conversion
if A/D module is enabled)
11xx = PWM mode

PIC16F753/HV753
11.0 COMPLEMENTARY OUTPUT cycle. The COG converts this single PWM input into a
dual complementary PWM output. The frequency and
GENERATOR (COG) MODULE
duty cycle of the dual PWM output match those of the
The primary purpose of the Complementary Output single input PWM signal. The off-to-on transition of
Generator (COG) is to convert a single output PWM each output can be delayed from the on-to-off transition
signal into a two output complementary PWM signal. of the other output, thereby creating a time immediately
The COG can also convert two separate input events after the PWM transition where neither output is driven.
into a single or complementary PWM output. This is referred to as dead time and is covered in
Section 11.5 “Dead-Band Control”.
The COG PWM frequency and duty cycle are
determined by a rising event input and a falling event A typical operating waveform, with dead band, generated
input. The rising event and falling event may be the from a single CCP1 input is shown in Figure 11-4.
same source. Sources may be synchronous or
asynchronous to the COG_clock. 11.1.2 PUSH-PULL MODE
The rate at which the rising event occurs determines In Push-Pull mode, the COG generates a single PWM
the PWM frequency. The time from the rising event output that alternates every PWM period, between the
input to the falling event input determines the duty two COG output pins. The output drive activates with
cycle. the rising input event and terminates with the falling
event input. Each rising event starts a new period and
A selectable clock input is used to generate the phase
causes the output to switch to the COG pin not used in
delay, blanking and dead-band times.
the previous period.
A simplified block diagram of the COG is shown in
A typical push-pull waveform generated from a single
Figure 11-1.
CCP1 input is shown in Figure 11-6.
The COG module has the following features:
Push-Pull mode is selected by setting the GxMD bit of
• Two modes of operation: the COGxCON0 register.
- Synchronous PWM
- Push-pull 11.1.3 ALL MODES
• Selectable clock source In addition to generating a complementary output from
• Independently selectable rising event sources a single PWM input, the COG can also generate PWM
waveforms from a periodic rising event and a separate
• Independently selectable falling event sources
falling event. In this case, the falling event is usually
• Independently selectable edge or level event derived from analog feedback within the external PWM
sensitivity driver circuit. In this configuration, high-power
• Independent output enables switching transients may trigger a false falling event
• Independent output polarity selection that needs to be blanked out. The COG can be
• Phase delay with independent rising and falling configured to blank falling (and rising) event inputs for
delay times a period of time immediately following the rising (and
falling) event drive output. This is referred to as input
• Dead-band control with:
blanking and is described in Section 11.6 “Blanking
- Independent rising and falling event Control”.
dead-band times
It may be necessary to guard against the possibility of
- Synchronous and asynchronous timing
circuit faults. In this case, the active drive must be
• Blanking control with independent rising and terminated before the Fault condition causes damage.
falling event blanking times This is referred to as auto-shutdown and is described in
• Auto-shutdown control with: Section 11.8 “Auto-shutdown Control”.
- Independently selectable shutdown sources A feedback falling event arriving too late or not at all can
- Auto-restart enable be terminated with auto-shutdown or by enabling one of
- Auto-shutdown pin override control (high, the Hardware Limit Timer (HLT) event inputs. See
low, off, and High-Z) Section 9.0 “Hardware Limit Timer (HLT) Module”
for more information about the HLT.
11.1 Fundamental Operation The COG can be configured to operate in phase
delayed conjunction with another PWM. The active
11.1.1 SYNCHRONOUS PWM MODE drive cycle is delayed from the rising event by a phase
In synchronous PWM mode, the COG generates a two delay timer. Phase delay is covered in more detail in
output complementary PWM waveform from rising and Section 11.7 “Phase Delay”. A typical operating
falling event sources. In the simplest configuration, the waveform, with phase delay and dead band, generated
rising and falling event sources have the same signal, from a single CCP1 input, is shown in Figure 11-5.
which is a PWM signal with the desired period and duty

FIGURE 11-1: SIMPLIFIED COG BLOCK DIAGRAM
DS40001709D-page 82
PIC16F753/HV753
HFINTOSC 10
COG_clock
Fosc/4 01
Fosc GxASD0L<1:0>
00
‘0 ’ 00
GxCS<1:0> Rising Input Block ‘1 ’ 01
Rising Dead-band Block High-Z 11 GxOE0
Reserved src7 clock
src6 clock 10 COG1OUT0
HLTimer2 1
HLTimer1 src5 Reset Dominates signal_out 0
TImer2=PR2 src4 rising_event S Q signal_in 1 0
COGxFLT src3
CCP1 src2 R Q GxPOL0
C2OUT src1
src0 count_en GxASD1L<1:0>
C1OUT
GxMD ‘0 ’ 00
Falling Input Block Falling Dead-band Block ‘1 ’ 01 GxOE1
src7 High-Z 11
Reserved clock COG1OUT1
src6 clock 10 1
HLTimer2 signal_out 0
HLTimer1 src5
signal_in 1 0
Timer2=PR2 src4
COGxFLT src3 falling_event GxPOL1
CCP1 src2 Push-Pull
C2OUT src1
C1OUT src0 count_en D Q
Q
COGxFLT S
D Q
GxASDSFLT GxEN
C1OUT
GxASDSC1 Auto-shutdown source GxASDE
 2013-2016 Microchip Technology Inc.
S Q
C2OUT
GxARSEN
GxASDSC2 Write GxASDE Low R
HLTimer2 output Set Dominates
GxASDSHLT2
HLTimer1 output
GxASDSHLT1
Write GxASDE High

PIC16F753/HV753
FIGURE 11-2: COG (RISING/FALLING) INPUT BLOCK
clock
GxPH(R/F)<3:0>
Blanking
count_en =
Cnt/Clr Phase
Delay
GxBLK(F/R)<3:0>
src7
Gx(R/F)IS7 D Q 1
(rising/falling)_event
LE 0
Gx(R/F)SIM7
src6
Gx(R/F)IS6 D Q 1
LE 0
Gx(R/F)SIM6
src5
Gx(R/F)IS5 D Q 1
0
LE
Gx(R/F)SIM5
src4
Gx(R/F)IS4 D Q 1
LE 0
Gx(R/F)SIM4
src3
Gx(R/F)IS3 D Q 1
LE 0
Gx(R/F)SIM3
src2
Gx(R/F)IS2 D Q 1
LE 0
Gx(R/F)SIM2
src1
Gx(R/F)IS1 D Q 1
LE 0
Gx(R/F)SIM1
src0
Gx(R/F)IS0 D Q 1
LE 0
Gx(R/F)SIM0
FIGURE 11-3: COG (RISING/FALLING) DEAD-BAND BLOCK
Gx(R/F)DBTS
clock Synchronous
Delay
=
Cnt/Clr
0 0
1 GxDBR<3:0> 1
Asynchronous
Delay Chain
signal_out
signal_in

PIC16F753/HV753
FIGURE 11-4: TYPICAL COG OPERATION WITH CCP1
COG_clock
Source
CCP1
COGxOUT0
Rising Source Dead Band

Falling Source Dead Band Falling Source Dead Band
COGxOUT1
FIGURE 11-5: COG OPERATION WITH CCP1 AND PHASE DELAY
COG_clock
Source
CCP1
COGxOUT0
Rising Source
Dead Band
Falling Source Dead Band Phase Delay Falling Source
Dead Band
COGxOUT1
FIGURE 11-6: COG OPERATION IN PUSH-PULL MODE WITH CCP1
CCP1
COGxOUT0
COGxOUT1

PIC16F753/HV753
11.2 Clock Sources output stays low and without a high-to-low tran-
sition to trigger the edge sense, the drive of the
The COG_clock is used as the reference clock to the COG output will be stuck in a constant drive-on
various timers in the peripheral. Timers that use the condition. See Figure 11-7.
COG_clock include:
• Rising and falling dead-band time FIGURE 11-7: EDGE VS. LEVEL SENSE
• Rising and falling blanking time
• Rising and falling event phase delay Rising (CCP1)
Clock sources available for selection include:
Falling (C1OUT)
• 8 MHz HFINTOSC (active during Sleep)
• Instruction clock (FOSC/4) hyst
C1IN-
• System clock (FOSC)
The clock source is selected with the GxCS<1:0> bits
COGOUT
of the COGxCON1 register (Register 11-2).
Edge Sensitive
11.3 Selectable Event Sources
The COG uses any combination of independently Rising (CCP1)
selectable event sources to generate the
complementary waveform. Sources fall into two Falling (C1OUT)
categories:
• Rising event sources C1IN- hyst
• Falling event sources
The rising event sources are selected by setting bits in COGOUT
the COGxRIS register (Register 11-3). The falling event
Level Sensitive
sources are selected by setting bits in the COGxFIS
register (Register 11-5). All selected sources are ‘OR’d
together to generate the corresponding event signal. 11.3.2 RISING EVENT
Refer to Figure 11-2.
The rising event starts the PWM output active duty
cycle period. The rising event is the low-to-high
11.3.1 EDGE VS. LEVEL SENSING
transition of the rising_event output. When the rising
Event input detection may be selected as level or event phase delay and dead-band time values are zero,
edge-sensitive. The Detection mode is individually select- the COGxOUT0 output starts immediately. Otherwise,
able for every source. Rising source detection modes are the COGxOUT0 output is delayed. The rising event
selected with the COGxRSIM register (Register 11-4). source causes all the following actions:
Falling source detection modes are selected with the
• Start rising event phase delay counter (if enabled).
COGxFSIM register (Register 11-6). A set bit enables
edge detection for the corresponding event source. A • Clear COGxOUT1 after phase delay.
cleared bit enables level detection. • Start falling event input blanking (if enabled).
In general, events that are driven from a periodic source • Start dead-band delay (if enabled).
should be edge-detected and events that are derived from • Set COGxOUT0 output after dead-band delay
voltage thresholds at the target circuit should be expires.
level-sensitive. Consider the following two examples:
11.3.3 FALLING EVENT
1. The first example is an application in which the
period is determined by a 50% duty cycle clock The falling event terminates the PWM output active
and the COG output duty cycle is determined by duty cycle period. The falling event is the high-to-low
a voltage level fed back through a comparator. If transition of the falling_event output. When the falling
the clock input is level sensitive, duty cycles less event phase delay and dead-band time values are
than 50% will exhibit erratic operation. zero, the COGxOUT1 output starts immediately.
Otherwise, the COGxOUT1 output is delayed. The
2. The second example is similar to the first,
falling event source causes all the following actions:
except that the duty cycle is close to 100%. The
feedback comparator high-to-low transition trips • Start falling event phase delay counter (if enabled).
the COG drive off, but almost immediately the • Clear COGxOUT0.
period source turns the drive back on. If the off • Start rising event input blanking (if enabled).
cycle is short enough, the comparator input may
• Start falling event dead-band delay (if enabled).
not reach the low side of the hysteresis band
precluding an output change. The comparator • Set COGxOUT1 output after dead-band delay expires.

PIC16F753/HV753
11.4 Output Control 11.5.1 ASYNCHRONOUS DELAY CHAIN
DEAD-BAND DELAY
Upon disabling, or immediately after enabling the COG
module, the complementary drive is configured with Asynchronous dead-band delay is determined by the
COGxOUT0 drive inactive and COGxOUT1 drive time it takes the input to propagate through a series of
active. delay elements. Each delay element is a nominal five
nanoseconds.
11.4.1 OUTPUT ENABLES Set the COGxDBR register (Register 11-9) value to the
Each COG output pin has an individual output enable desired number of delay elements in the COGxOUT0
control. Output enables are selected with the GxOE0 and dead band. Set the COGxDBF register (Register 11-10)
GxOE1 bits of the COGxCON0 register (Register 11-1). value to the desired number of delay elements in the
When an output enable control is cleared, the module COGxOUT1 dead band. When the value is zero,
asserts no control over the pin. When an output enable is dead-band delay is disabled.
set, the override value or PWM waveform is applied to
the pin per the port priority selection. 11.5.2 SYNCHRONOUS COUNTER
DEAD-BAND DELAY
The device pin output enable control bits are
independent of the GxEN bit of the COGxCON0 Synchronous counter dead band is timed by counting
register, which enables the COG. When GxEN is COG_clock periods from zero up to the value in the
cleared, and shutdown is not active, the Reset state dead-band count register. Use Equation 11-1 to
PWM levels are present on the COG output pins. The calculate dead-band times.
PWM levels are affected by the polarity controls. If Set the COGxDBR count register value to obtain the
shutdown is active when GxEN is cleared, the desired dead-band time of the COGxOUT0 output. Set
shutdown override levels will be present on the COG the COGxDBF count register value to obtain the
output pins. Note that setting the GxASE bit while the desired dead-band time of the COGxOUT1 output.
GxEN bit is cleared will activate shutdown which can When the value is zero, dead-band delay is disabled.
only be cleared by either a rising event while the GxEN
bit is set, or a device Reset. 11.5.3 SYNCHRONOUS COUNTER
DEAD-BAND TIME UNCERTAINTY
11.4.2 POLARITY CONTROL
When the rising and falling events that trigger the
The polarity of each COG output can be selected dead-band counters come from asynchronous inputs,
independently. When the output polarity bit is set, the it creates uncertainty in the synchronous counter
corresponding output is active-low. Clearing the output dead-band time. The maximum uncertainty is equal to
polarity bit configures the corresponding output as one COG_clock period. Refer to Equation 11-1 for
active-high. However, polarity does not affect the more detail.
shutdown override levels.
When event input sources are asynchronous with no
Output polarity is selected with the GxPOL0 and phase delay, use the asynchronous delay chain
GxPOL1 bits of the COGxCON0 register (Register 11-1). dead-band mode to avoid the dead-band time
uncertainty.
11.5 Dead-Band Control
The dead-band control provides for non-overlapping
PWM output signals to prevent shoot-through current
in the external power switches.
The COG contains two dead-band timers. One
dead-band timer is used for rising event dead-band
control. The other is used for falling event dead-band
control. Timer modes are selectable as either:
• Asynchronous delay chain
• Synchronous counter
The dead-band Timer mode is selected for the
COGxOUT0 and COGxOUT1 dead-band times with
the respective GxRDBTS and GxFDBTS bits of the
COGxCON1 register (Register 11-2).

PIC16F753/HV753
11.5.4 RISING EVENT DEAD BAND falling input events. Once started, blanking extends for
the time specified by the corresponding blanking
Rising event dead band adds a delay between the
counter.
COGxOUT1 signal deactivation and the COGxOUT0
signal activation. The rising event dead-band time Blanking is timed by counting COG_clock periods from
starts when the rising_event output goes true. zero up to the value in the blanking count register. Use
Equation 11-1 to calculate blanking times.
See Section 11.5.1, Asynchronous Delay Chain
Dead-band Delay and Section 11.5.2, Synchronous
11.6.1 FALLING EVENT BLANKING OF
Counter Dead-band Delay for more information on
RISING EVENT INPUTS
setting the rising edge dead-band time.
The falling event blanking counter inhibits rising event
11.5.5 FALLING EVENT DEAD BAND inputs from triggering a rising event. The falling event
Falling event dead band adds a delay between the blanking time starts when the rising event output drive
COGxOUT1 signal deactivation and the COGxOUT0 goes false.
signal activation. The falling event dead-band time The falling event blanking time is set by the value
starts when the falling_event output goes true. contained in the COGxBKF register (Register 11-12).
See Section 11.5.1, Asynchronous Delay Chain Blanking times are calculated using the formula shown
Dead-band Delay and Section 11.5.2, Synchronous in Equation 11-1.
Counter Dead-band Delay for more information on When the COGxBKF value is zero, the falling event
setting the rising edge dead-band time. blanking is disabled and the blanking counter output is
true, thereby allowing the event signal to pass straight
11.5.6 DEAD-BAND OVERLAP through to the event trigger circuit.
There are two cases of dead-band overlap:
11.6.2 RISING EVENT BLANKING OF
• Rising-to-falling FALLING EVENT INPUTS
• Falling-to-rising
The rising event blanking counter inhibits falling event
11.5.6.1 Rising-to-Falling Overlap inputs from triggering a falling event. The rising event
blanking time starts when the falling event output drive
In this case, the falling event occurs while the rising goes false.
event dead-band counter is still counting. When this
happens, the COGxOUT0 drive is suppressed and the The rising event blanking time is set by the value
dead band extends by the falling event dead-band contained in the COGxBKR register (Register 11-11).
time. At the termination of the extended dead-band When the COGxBKR value is zero, the rising event
time, the COGxOUT1 drive goes true. blanking is disabled and the blanking counter output is
true, thereby allowing the event signal to pass straight
11.5.6.2 Falling-to-Rising Overlap through to the event trigger circuit.
In this case, the rising event occurs while the falling
event dead-band counter is still counting. When this 11.6.3 BLANKING TIME UNCERTAINTY
happens, the COGxOUT1 drive is suppressed and the When the rising and falling sources that trigger the
dead band extends by the rising event dead-band blanking counters are asynchronous to the
time. At the termination of the extended dead-band COG_clock, it creates uncertainty in the blanking time.
time, the COGxOUT0 drive goes true. The maximum uncertainty is equal to one COG_clock
period. Refer to Equation 11-1 and Example 11-2 for
11.6 Blanking Control more detail.
Input blanking is a function, whereby the event inputs 11.7 Phase Delay
can be masked or blanked for a short period of time.
This is to prevent electrical transients caused by the It is possible to delay the assertion of either or both the
turn-on/off of power components from generating a rising event and falling event. This is accomplished by
false input event. placing a non-zero value in COGxPHR or COGxPHF
The COG contains two blanking counters: one phase delay count register, respectively
triggered by the rising event and the other triggered by (Register 11-13 and Register 11-14). Refer to
the falling event. The counters are cross-coupled with Figure 11-5 for COG operation with CCP1 and phase
the events they are blanking. The falling event delay. The delay from the input rising event signal
blanking counter is used to blank rising input events switching to the actual assertion of the events is
and the rising event blanking counter is used to blank calculated the same as the dead-band and blanking
delays. Please see Equation 11-1.

PIC16F753/HV753
When the phase delay count value is zero, phase EQUATION 11-2: TIMER UNCERTAINTY
delay is disabled and the phase delay counter output
Given:
is true, thereby allowing the event signal to pass
Count = Ah = 10d
straight through to complementary output driver flop.
F = 8MHz
COG_Clock
11.7.1 CUMULATIVE UNCERTAINTY
Therefore:
It is not possible to create more than one COG_clock of 1
T = ---------------------------------
uncertainty by successive stages. Consider that the uncertainty F COG_clock
phase delay stage comes after the blanking stage, the
dead-band stage comes after either the blanking or 1 = 125ns
= ----------------
phase delay stages, and the blanking stage comes 8MHz
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily
synchronous with the COG_clock, which removes any Proof:
possibility of uncertainty in the succeeding stage. T
Count
= ---------------------------------
min F
COG_clock
EQUATION 11-1: PHASE, DEAD-BAND AND
BLANKING TIME = 125ns  10d = 1.25s
CALCULATION
Count + 1
T = ---------------------------------
max F COG_clock
T min = Count
F COG_clock
= 125ns   10d + 1 
Count + 1
T max = --------------------------
F COG_clock = 1.375s
Therefore:
T uncertainty = T max – T min
T = T –T
Also: uncertainty max min
1
T uncertainty = -------------------------- = 1.375s – 1.25s
F COG_clock
= 125ns
Where:
T Count
Rising Phase Delay COGxPHR
Falling Phase Delay COGxPHF
Rising Dead Band COGxDBR
Falling Dead Band COGxDBF
Rising Event Blanking COGxBKR
Falling Event Blanking COGxBKF

PIC16F753/HV753
11.8 Auto-shutdown Control 11.8.2 PIN OVERRIDE LEVELS
Auto-shutdown is a method to immediately override The levels driven to the output pins, while the
the COG output levels with specific overrides that shutdown is active, are controlled by the
allow for safe shutdown of the circuit. GxASD0L<1:0> and GxASD1L<1:0> bits of the
COGxASD0 register (Register 11-7). GxASD0L<1:0>
The shutdown state can be either cleared controls the GxOUT0 override level and
automatically or held until cleared by software. In GxASD1L<1:0> controls the GxOUT1 override level.
either case, the shutdown overrides remain in effect There are four override options for each output:
until the first rising event after the shutdown is cleared.
• Forced low
11.8.1 SHUTDOWN • Forced high
The shutdown state can be entered by either of the • Tri-state
following two mechanisms: • PWM inactive state (same state as that caused by
• Software generated a falling event)
• External Input Note: The polarity control does not apply to the
forced low and high override levels.
11.8.1.1 Software Generated Shutdown
Setting the GxASDE bit of the COGxASD0 register 11.8.3 AUTO-SHUTDOWN RESTART
(Register 11-7) will force the COG into the shutdown After an auto-shutdown event has occurred, there are
state. two ways to have the module resume operation:
When auto-restart is disabled, the shutdown state will • Software controlled
persist until the first rising event after the GxASDE bit • Auto-restart
is cleared by software.
The restart method is selected with the GxARSEN bit
When auto-restart is enabled, the GxASDE bit will of the COGxASD0 register. Waveforms of a software
clear automatically and resume operation on the first controlled automatic restart are shown in Figure 11-8.
rising event after the shutdown input clears. See
Figure 11-8 and Section 11.8.3.2 “Auto-Restart”. 11.8.3.1 Software Controlled Restart
11.8.1.2 External Shutdown Source When the GxARSEN bit of the COGxASD0 register is
cleared, software must clear the GxASDE bit to restart
External shutdown inputs provide the fastest way to COG operation after an auto-shutdown event.
safely suspend COG operation in the event of a Fault
condition. When any of the selected shutdown inputs The COG will resume operation on the first rising
goes true, the output drive latches are reset and the event after the GxASDE bit is cleared. Clearing the
COG outputs immediately go to the selected override shutdown state requires all selected shutdown inputs
levels without software delay. to be false, otherwise, the GxASDE bit will remain set.
Any combination of the input sources can be selected 11.8.3.2 Auto-Restart

to cause a shutdown condition. Shutdown input
sources include: When the GxARSEN bit of the COGxASD0 register is
set, the COG will restart from the auto-shutdown state
• HLTimer1 output automatically.
• HLTimer2 output
The GxASDE bit will clear automatically and the COG
• C2OUT (low true) will resume operation on the first rising event after all
• C1OUT (low true) selected shutdown inputs go false.
• COG1FLT pin (low true)
Shutdown inputs are selected independently with bits
of the COGxASD1 register (Register 11-8).
Note: Shutdown inputs are level-sensitive, not

edge-sensitive. The shutdown state
cannot be cleared as long as the
shutdown input level persists, except by
disabling auto-shutdown.

FIGURE 11-8: AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT SOURCE
DS40001709D-page 90
PIC16F753/HV753
1 2 3 4 5
CCP1
GxARSEN
Next rising event

Shutdown Input
Next rising event Cleared in hardware

GxASDE Cleared in software
GxASDL0
GxASDL1
COGxOUT0
COGxOUT1
Operating State
Normal Output Shutdown Normal Output Shutdown Normal Output
Software Controlled Restart Auto-Restart

PIC16F753/HV753
11.9 Buffer Updates 11.12 Configuring the COG
Changes to the phase, dead-band, and blanking count The following steps illustrate how to properly configure
registers need to occur simultaneously during COG the COG to ensure a synchronous start with the rising
operation to avoid unintended operation that may event input:
occur as a result of delays between each register 1. Configure the desired COGxFLT input,
write. This is accomplished with the GxLD bit of the COGxOUT0 and COGxOUT1 pins with the
COGxCON0 register and double buffering of the corresponding bits in the APFCON register.
phase, blanking, and dead-band count registers.
2. Clear all ANSELA register bits associated with
Before the COG module is enabled, writing the count pins that are used for COG functions.
registers loads the count buffers without need of the 3. Ensure that the TRIS control bits corresponding
GxLD bit. However, when the COG is enabled, the to COGxOUT0 and COGxOUT1 are set so that
count buffers updates are suspended after writing the both are configured as inputs. These will be set
count registers until after the GxLD bit is set. When the as outputs later.
GxLD bit is set, the phase, dead-band, and blanking
4. Clear the GxEN bit, if not already cleared.
register values are transferred to the corresponding
buffers synchronous with COG operation. The GxLD 5. Set desired dead-band times with the COGxDBR
bit is cleared by hardware when the transfer is and COGxDBF registers.
complete. 6. Set desired blanking times with the COGxBKR
and COGxBKF registers.
11.10 Alternate Pin Selection 7. Set desired phase delay with the COGxPHR
and COGxPHF registers.
The COGxOUT0, COGxOUT1 and COGxFLT
8. Select the desired shutdown sources with the
functions can be directed to alternate pins with control
COGxASD1 register.
bits of the APFCON register. Refer to Register 5-1.
9. Set up the following controls in COGxASD0
Note: The default COG outputs have high drive auto-shutdown register:
strength capability, whereas the alternate • Select both output overrides to the desired
outputs do not. levels (this is necessary, even if not using
auto-shutdown because start-up will be from
11.11 Operation During Sleep a shutdown state).
• Set the GxASDE bit and clear the GxARSEN
The COG continues to operate in Sleep provided that
bit.
the COG_clock, rising event, and falling event sources
remain active. 10. Select the desired rising and falling event sources
with the COGxRIS and COGxFIS registers.
The HFINTSOC remains active during Sleep when the
11. Select the desired rising and falling event modes
COG is enabled and the HFINTOSC is selected as the
with the COGxRSIM and COGxFSIM registers.
COG_clock source.
12. Configure the following controls in the
COGxCON1 register:
• Select the desired clock source
• Select the desired dead-band timing sources
13. Configure the following controls in the
COGxCON0 register:
• Select the desired output polarities.
• Set the output enables of the outputs to be
used.
14. Set the GxEN bit.
15. Clear TRIS control bits corresponding to
COGxOUT0 and COGxOUT1 to be used,
thereby configuring those pins as outputs.
16. If auto-restart is to be used, set the GxARSEN bit
and the GxASDE will be cleared automatically.
Otherwise, clear the GxASDE bit to start the
COG.

PIC16F753/HV753
11.13 Register Definitions: COG Control
REGISTER 11-1: COGxCON0: COG CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
GxEN GxOE1 GxOE0 GxPOL1 GxPOL0 GxLD — GxMD
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 GxEN: COGx Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 GxOE1: COGxOUT1 Output Enable bit
1 = COGxOUT1 is available on associated I/O pin
0 = COGxOUT1 is not available on associated I/O pin
bit 5 GxOE0: COGxOUT0 Output Enable bit
1 = COGxOUT0 is available on associated I/O pin
0 = COGxOUT0 is not available on associated I/O pin
bit 4 GxPOL1: COGxOUT1 Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 3 GxPOL0: COGxOUT0 Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 2 GxLD: COGx Load Buffers bit
1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events
0 = Register to buffer transfer is complete
bit 0 GxMD: COGx Mode bit
1 = COG outputs operate in Push-Pull mode
0 = COG outputs operate in Synchronous mode

PIC16F753/HV753
REGISTER 11-2: COGxCON1: COG CONTROL REGISTER 1

R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
GxRDBTS GxFDBTS — — — — GxCS<1:0>
bit 7 bit 0
Legend:
bit 7 GxRDBTS: COGx Rising Event Dead-band Timing Source Select bit
1 = Delay chain and COGxDBR are used for dead-band timing generation
0 = COGx_clk and COGxDBR are used for dead-band timing generation
bit 6 GxFDBTS: COGx Falling Event Dead-band Timing Source Select bit
1 = Delay chain and COGxDF are used for dead-band timing generation
0 = COGx_clk and COGxDBF are used for dead-band timing generation
bit 1-0 GxCS<1:0>: COGx Clock Source Select bits
11 = Reserved
10 = HFINTOSC (stays active during Sleep)
01 = FOSC/4
00 = FOSC

PIC16F753/HV753
REGISTER 11-3: COGxRIS: COG RISING EVENT INPUT SELECTION REGISTER

— GxRIHLT2 GxRIHLT1 GxRIT2M GxRIFLT GxRICCP1 GxRIC2 GxRIC1
bit 7 bit 0
Legend:

bit 6 GxRIHLT2: COGx Rising Event Input Source 6 Enable bit
1 = HLTimer2 output is enabled as a rising event input
0 = HLTimer2 has no effect on the rising event
bit 5 GxRIHLT1: COGx Rising Event Input Source 5 Enable bit
1 = HLTimer1 output is enabled as a rising event input
0 = HLTimer1 has no effect on the rising event
bit 4 GxRIT2M: COGx Rising Event Input Source 4 Enable bit
1 = Timer2 match with PR2 is enabled as a rising event input
0 = Timer2 match with PR2 has no effect on the rising event
bit 3 GxRIFLT: COGx Rising Event Input Source 3 Enable bit
1 = COGxFLT pin is enabled as a rising event input
0 = COGxFLT pin has no effect on the rising event
bit 2 GxRICCP1: COGx Rising Event Input Source 2 Enable bit
1 = CCP1 output is enabled as a rising event input
0 = CCP1 has no effect on the rising event
bit 1 GxRIC2: COGx Rising Event Input Source 1 Enable bit
1 = Comparator 2 output is enabled as a rising event input
0 = Comparator 2 output has no effect on the rising event
bit 0 GxRIC1: COGx Rising Event Input Source 0 Enable bit
1 = Comparator 1 output is enabled as a rising event input
0 = Comparator 1 output has no effect on the rising event

PIC16F753/HV753
REGISTER 11-4: COGxRSIM: COG RISING EVENT SOURCE INPUT MODE REGISTER
— GxRMHLT2 GxRMHLT1 GxRMT2M GxRMFLT GxRMCCP1 GxRMC2 GxRMC1
bit 7 bit 0
Legend:

bit 6 GxRMHLT2: COGx Rising Event Input Source 6 Mode bit(1)
GxRIHLT2 = 1:
1 = HLTimer2 low-to-high transition will cause a rising event after rising event phase delay
0 = HLTimer2 high level will cause an immediate rising event
GxRIHLT2 = 0:
HLTimer2 has no effect on rising event
bit 5 GxRMHLT1: COGx Rising Event Input Source 5 Mode bit(1)
GxRIHLT1 = 1:
1 = HLTimer1 low-to-high transition will cause a rising event after rising event phase delay
0 = HLTimer1 high level will cause an immediate rising event
GxRIHLT1 = 0:
HLTimer1 has no effect on rising event
bit 4 GxRMT2M: COGx Rising Event Input Source 4 Mode bit(1)
GxRIT2M = 1:
1 = Timer2 match with PR2 low-to-high transition will cause a rising event after rising event phase delay
0 = Timer2 match with PR2 high level will cause an immediate rising event
GxRIT2M = 0:
Timer2 match with PR2 has no effect on rising event
bit 3 GxRMFLT: COGx Rising Event Input Source 3 Mode bit
GxRIFLT = 1:
1 = COGxFLT pin low-to-high transition will cause a rising event after rising event phase delay
0 = COGxFLT pin high level will cause an immediate rising event
GxRIFLT = 0:
COGxFLT pin has no effect on rising event
bit 2 GxRMCCP1: COGx Rising Event Input Source 2 Mode bit
GxRICCP1 = 1:
1 = CCP1 low-to-high transition will cause a rising event after rising event phase delay
0 = CCP1 high level will cause an immediate rising event
GxRICCP1 = 0:
CCP1 has no effect on rising event
bit 1 GxRMC2: COGx Rising Event Input Source 1 Mode bit
GxRIC2 = 1:
1 = Comparator 2 low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 2 high level will cause an immediate rising event
GxRIC2 = 0:
Comparator 2 has no effect on rising event
bit 0 GxRMC1: COGx Rising Event Input Source 0 Mode bit
GxRIC1 = 1:
1 = Comparator 1 low-to-high transition will cause a rising event after rising event phase delay
0 = Comparator 1 high level will cause an immediate rising event
GxRIC1 = 0:
Comparator 1 has no effect on rising event
Note 1: These sources are pulses and therefore the only benefit of Edge mode over Level mode is that they can be
delayed by rising event phase delay.

PIC16F753/HV753
REGISTER 11-5: COGxFIS: COG FALLING EVENT INPUT SELECTION REGISTER

— GxFIHLT2 GxFIHLT1 GxFIT2M GxFIFLT GxFICCP1 GxFIC2 GxFIC1
bit 7 bit 0
Legend:

bit 6 GxFIHLT2: COGx Falling Event Input Source 6 Enable bit
1 = HLTimer2 output is enabled as a falling event input
0 = HLTimer2 has no effect on the falling event
bit 5 GxFIHLT1: COGx Falling Event Input Source 5 Enable bit
1 = HLTimer1 output is enabled as a falling event input
0 = HLTimer1 has no effect on the falling event
bit 4 GxFIT2M: COGx Falling Event Input Source 4 Enable bit
1 = Timer2 match with PR2 is enabled as a falling event input
0 = Timer2 match with PR2 has no effect on the falling event
bit 3 GxFIFLT: COGx Falling Event Input Source 3 Enable bit
1 = COGxFLT pin is enabled as a falling event input
0 = COGxFLT pin has no effect on the falling event
bit 2 GxFICCP1: COGx Falling Event Input Source 2 Enable bit
1 = CCP1 output is enabled as a falling event input
0 = CCP1 has no effect on the falling event
bit 1 GxFIC2: COGx Falling Event Input Source 1 Enable bit
1 = Comparator 2 output is enabled as a falling event input
0 = Comparator 2 output has no effect on the falling event
bit 0 GxFIC1: COGx Falling Event Input Source 0 Enable bit
1 = Comparator 1 output is enabled as a falling event input
0 = Comparator 1 output has no effect on the falling event

PIC16F753/HV753
REGISTER 11-6: COGxFSIM: COG FALLING EVENT SOURCE INPUT MODE REGISTER
— GxFMHLT2 GxFMHLT1 GxFMT2M GxFMFLT GxFMCCP1 GxFMC2 GxFMC1
bit 7 bit 0
Legend:

bit 6 GxFMHLT2: COGx Falling Event Input Source 6 Mode bit(1)
GxFIHLT2 = 1:
1 = HLTimer2 low-to-high transition will cause a falling event after falling event phase delay
0 = HLTimer2 high level will cause an immediate falling event
GxFIHLT2 = 0:
HLTimer2 has no effect on falling event
bit 5 GxFMHLT1: COGx Falling Event Input Source 5 Mode bit(1)
GxFIHLT1 = 1:
1 = HLTimer1 low-to-high transition will cause a falling event after falling event phase delay
0 = HLTimer1 high level will cause an immediate falling event
GxFIHLT1 = 0:
HLTimer1 has no effect on falling event
bit 4 GxFMT2M: COGx Falling Event Input Source 4 Mode bit(1)
GxFIT2M = 1:
1 = Timer2 match with PR2 low-to-high transition will cause a falling event after falling event phase delay
0 = Timer2 match with PR2 high level will cause an immediate falling event
GxFIT2M = 0:
Timer2 match with PR2 has no effect on falling event
bit 3 GxFMFLT: COGx Falling Event Input Source 3 Mode bit
GxFIFLT = 1:
1 = COGxFLT pin low-to-high transition will cause a falling event after falling event phase delay
0 = COGxFLT pin high level will cause an immediate falling event
GxFIFLT = 0:
COGxFLT pin has no effect on falling event
bit 2 GxFMCCP1: COGx Falling Event Input Source 2 Mode bit
GxFICCP1 = 1:
1 = CCP1 low-to-high transition will cause a falling event after falling event phase delay
0 = CCP1 high level will cause an immediate falling event
GxFICCP1 = 0:
CCP1 has no effect on falling event
bit 1 GxFMC2: COGx Falling Event Input Source 1 Mode bit
GxFIC2 = 1:
1 = Comparator 2 low-to-high transition will cause a falling event after falling event phase delay
0 = Comparator 2 high level will cause an immediate falling event
GxFIC2 = 0:
Comparator 2 has no effect on falling event
bit 0 GxFMC1: COGx Falling Event Input Source 0 Mode bit
GxFIC1 = 1:
1 = Comparator 1 low-to-high transition will cause a falling event after falling event phase delay
0 = Comparator 1 high level will cause an immediate falling event
GxFIC1 = 0:
Comparator 1 has no effect on falling event
Note 1: These sources are pulses and therefore the only benefit of Edge mode over Level mode is that they can be
delayed by falling event phase delay.

PIC16F753/HV753
REGISTER 11-7: COGxASD0: COG AUTO-SHUTDOWN CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0
GxASDE GxARSEN GxASD1L<1:0> GxASD0L<1:0> — —
bit 7 bit 0
Legend:
bit 7 GxASDE: Auto-Shutdown Event Status bit

1 = COG is in the shutdown state
0 = COG is either not in the shutdown state or will exit the shutdown state on the next rising event
bit 6 GxARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-4 GxASD1L<1:0>: COGxOUT1 Auto-Shutdown Override Level Select bits
11 = COGxOUT1 is tri-stated when shutdown is active
10 = The inactive state of the pin, including polarity, is placed on COGxOUT1 when shutdown is active
01 = A logic ‘1’ is placed on COGxOUT1 when shutdown is active
00 = A logic ‘0’ is placed on COGxOUT1 when shutdown is active
bit 3-2 GxASD0L<1:0>: COGxOUT0 Auto-Shutdown Override Level Select bits
11 = COGxOUT0 is tri-stated when shutdown is active
10 = The inactive state of the pin, including polarity, is placed on COGxOUT0 when shutdown is active
01 = A logic ‘1’ is placed on COGxOUT0when shutdown is active
00 = A logic ‘0’ is placed on COGxOUT0when shutdown is active

PIC16F753/HV753
REGISTER 11-8: COGxASD1: COG AUTO-SHUTDOWN CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — GxASDSHLT2 GxASDSHLT1 GxASDSC2 GxASDSC1 GxASDSFLT
bit 7 bit 0
Legend:

bit 4 GxASDSHLT2: COGx Auto-Shutdown Source Enable bit 4
1 = COGx is shutdown when HLTMR2 equals HLTPR2
0 = HLTimer 2 has no effect on shutdown
bit 3 GxASDSHLT1: COGx Auto-Shutdown Source Enable bit 3
1 = COGx is shutdown when HLTMR1 equals HLTPR1
0 = HLTimer 1 has no effect on shutdown
bit 2 GxASDSC2: COGx Auto-Shutdown Source Enable bit 2
1 = COGx is shutdown when Comparator 2 output is low
0 = Comparator 2 output has no effect on shutdown
bit 1 GxASDSC1: COGx Auto-Shutdown Source Enable bit 1
1 = COGx is shutdown when Comparator 1 output is low
0 = Comparator 1 output has no effect on shutdown
bit 0 GxASDSFLT: COGx Auto-Shutdown Source Enable bit 0
1 = COGx is shutdown when COGxFLT pin is low
0 = COGxFLT pin has no effect on shutdown

PIC16F753/HV753
REGISTER 11-9: COGxDBR: COG RISING EVENT DEAD-BAND COUNT REGISTER

U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — GxDBR<3:0>
bit 7 bit 0
Legend:

bit 3-0 GxDBR<3:0>: Rising Event Dead-band Count Value bits
GxRDBTS = 1:
= Number of delay chain element periods to delay primary output after rising event
GxRDBTS = 0:
= Number of COGx clock periods to delay primary output after rising event
REGISTER 11-10: COGxDBF: COG FALLING EVENT DEAD-BAND COUNT REGISTER

— — — — GxDBF<3:0>
bit 7 bit 0
Legend:

bit 3-0 GxDBF<3:0>: Falling Event Dead-Band Count Value bits
GxFDBTS = 1:
= Number of delay chain element periods to delay complementary output after falling event input
GxFDBTS = 0:
= Number of COGx clock periods to delay complementary output after falling event input

PIC16F753/HV753
REGISTER 11-11: COGxBKR: COG RISING EVENT BLANKING COUNT REGISTER

— — — — GxBKR<3:0>
bit 7 bit 0
Legend:

bit 3-0 GxBKR<3:0>: Rising Event Blanking Count Value bits
= Number of COGx clock periods to inhibit falling event inputs
REGISTER 11-12: COGxBKF: COG FALLING EVENT BLANKING COUNT REGISTER

— — — — GxBKF<3:0>
bit 7 bit 0
Legend:

bit 3-0 GxBKF<3:0>: Falling Event Blanking Count Value bits
= Number of COGx clock periods to inhibit rising event inputs

PIC16F753/HV753
REGISTER 11-13: COGxPHR: COG RISING EDGE PHASE DELAY COUNT REGISTER
— — — — GxPHR<3:0>
bit 7 bit 0
Legend:

bit 3-0 GxPHR<3:0>: Rising Edge Phase Delay Count Value bits
= Number of COGx clock periods to delay rising edge event
REGISTER 11-14: COGxPHF: COG FALLING EDGE PHASE DELAY COUNT REGISTER
— — — — GxPHF<3:0>
bit 7 bit 0
Legend:

bit 3-0 GxPHF<3:0>: Falling Edge Phase Delay Count Value bits
= Number of COGx clock periods to delay falling edge event

PIC16F753/HV753
TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH COG

Register
on Page

APFCON — — — T1GSEL — — — — 40
COG1PHR — — — — G1PHR<3:0> 102
COG1PHF — — — — G1PHF<3:0> 102
COG1BKR — — — — G1BKR<3:0> 101
COG1BKF — — — — G1BKF<3:0> 101
COG1DBR — — — — G1DBR<3:0> 100
COG1DBF — — — — G1DBF<3:0> 100
COG1RIS — G1RIHLT2 G1RIHLT1 G1RIT2M G1RIFLT G1RICCP1 G1RIC2 G1RIC1 94
COG1RSIM — G1RMHLT2 G1RMHLT1 G1RMT2M G1RMFLT G1RMCCP1 G1RMC2 G1RMC1 95
COG1FIS — G1FIHLT2 G1FIHLT1 G1FIT2M G1FIFLT G1FICCP1 G1FIC2 G1FIC1 96
COG1FSIM — G1FMHLT2 G1FMHLT1 G1FMT2M G1FMFLT G1FMCCP1 G1FMC2 G1FMC1 97
COG1CON0 G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD — G1MD 92
COG1CON1 G1RDBTS G1FDBTS — — — — G1CS<1:0> 93
COG1ASD0 G1ASDE G1ARSEN G1ASD1L<1:0> G1ASD0L<1:0> — — 98
COG1ASD1 — — — G1ASDSHLT2 G1ASDSHLT1 G1ASDSC2 G1ASDSC1 G1ASDSFLT 99
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG.

PIC16F753/HV753
12.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
Note: The ADRESL and ADRESH registers are
The Analog-to-Digital Converter (ADC) allows read-only.
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake up the
device from Sleep.
Figure 12-1 shows the block diagram of the ADC.
FIGURE 12-1: ADC BLOCK DIAGRAM
VDD
ADPREF = 0
VREF+ ADPREF = 1
AN0 0000
AN1 0001
AN2 0010
AN3 0011 A/D
AN4 0100 10
GO/DONE
AN5 0101
AN6 0110 0 = Left Justify

ADFM 1 = Right Justify
AN7 0111
DAC output 1110 ADON 10
Fixed Voltage Reference 1111
VSS ADRESH ADRESL
CHS<3:0>

PIC16F753/HV753
12.1 ADC Configuration 12.1.3 ADC VOLTAGE REFERENCE
When configuring and using the ADC the following The ADPREF1 bit of the ADCON1 register provides
functions must be considered: control of the positive voltage reference. The positive
voltage reference can be either VDD or an external
• Port configuration voltage source. The negative voltage reference is
• Channel selection always connected to the ground reference.
• ADC voltage reference selection
• ADC conversion clock source 12.1.4 CONVERSION CLOCK
• Interrupt control The source of the conversion clock is software
• Results formatting selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
12.1.1 PORT CONFIGURATION • FOSC/2
The ADC can be used to convert both analog and digital • FOSC/4
signals. When converting analog signals, the I/O pin • FOSC/8
should be configured for analog by setting the associated • FOSC/16
TRIS and ANSEL bits. See the corresponding port
• FOSC/32
section for more information.
• FOSC/64
Note: Analog voltages on any pin that is defined • FRC (dedicated internal oscillator)
as a digital input may cause the input
buffer to conduct excess current. The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
12.1.2 CHANNEL SELECTION as shown in Figure 12-2.
The CHS bits of the ADCON0 register determine which For correct conversion, the appropriate TAD specification
channel is connected to the sample and hold circuit. must be met. See A/D conversion requirements in
Section 22.0 “Electrical Specifications” for more
When changing channels, a delay is required before information. Table gives examples of appropriate ADC
starting the next conversion. Refer to Section 12.2 clock selections.
“ADC Operation” for more information.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.

PIC16F753/HV753
TABLE 12-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz

FOSC/2 000 100 ns (2)
250 ns (2)
500 ns (2)
2.0 s
FOSC/4 100 200 ns(2) 500 ns(2) 1.0 s(2) 4.0 s
FOSC/8 001 400 ns(2) 1.0 s(2) 2.0 s 8.0 s(3)
FOSC/16 101 800 ns(2) 2.0 s 4.0 s 16.0 s(3)
FOSC/32 010 1.6 s 4.0 s 8.0 s(3) 32.0 s(3)
FOSC/64 110 3.2 s 8.0 s (3)
16.0 s (3)
64.0 s(3)
FRC x11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 12-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit

ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
12.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.

PIC16F753/HV753
12.1.6 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 12-4 shows the two output formats.
FIGURE 12-3: 10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result
12.2 ADC Operation 12.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This
12.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the
ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the
DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be
Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit should not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 12.2.6 “A/D Conver-
module is turned off after the conversion completes,
sion Procedure”.
although the ADON bit remains set.
12.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
When the conversion is complete, the ADC module will: conversion to be aborted and the ADC module is
• Clear the GO/DONE bit turned off, although the ADON bit remains set.
• Set the ADIF flag bit
12.2.5 SPECIAL EVENT TRIGGER
• Update the ADRESH:ADRESL registers with new
conversion result The CCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
12.2.3 TERMINATING A CONVERSION this trigger occurs, the GO/DONE bit is set by hardware
If a conversion must be terminated before completion, and the Timer1 counter resets to zero.
the GO/DONE bit can be cleared in software. The Using the Special Event Trigger does not assure proper
ADRESH:ADRESL registers will not be updated with ADC timing. It is the user’s responsibility to ensure that
the partially complete Analog-to-Digital conversion the ADC timing requirements are met.
sample. Instead, the ADRESH:ADRESL register pair See Section 10.0 “Capture/Compare/PWM
will retain the value of the previous conversion. Addi- Modules” for more information.
tionally, a 2 TAD delay is required before another acqui-
sition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.

PIC16F753/HV753
12.2.6 A/D CONVERSION PROCEDURE EXAMPLE 12-1: A/D CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd reference, Frc clock
;and RA0 input.
1. Configure Port:
;
• Disable pin output driver (See TRIS register) ;Conversion start & polling for completion
• Configure pin as analog ; are included.
2. Configure the ADC module: ;
BANKSEL TRISA ;
• Select ADC conversion clock BSF TRISA,0 ;Set RA0 to input
• Configure voltage reference BANKSEL ADCON1 ;
• Select ADC input channel MOVLW B’01110000’ ;ADC Frc clock,
IORWF ADCON1 ; and RA0 as analog
• Select result format BANKSEL ADCON0 ;
• Turn on ADC module MOVLW B’10000001’ ;Right justify,
3. Configure ADC interrupt (optional): MOVWF ADCON0 ;Vdd Vref, AN0, On
CALL SampleTime ;Acquisiton delay
• Clear ADC interrupt flag
BSF ADCON0,GO ;Start conversion
• Enable ADC interrupt TEST AGAIN
• Enable peripheral interrupt BTFSC ADCON0,GO ;Is conversion done?
• Enable global interrupt(1) GOTO TEST AGAIN ;No, test again
BANKSEL ADRESH ;
4. Wait the required acquisition time(2). MOVF ADRESH,W ;Read upper 2 bits
5. Start conversion by setting the GO/DONE bit. MOVWF RESULTHI ;Store in GPR space
6. Wait for ADC conversion to complete by one of BANKSEL ADRESL ;
the following: MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: See Section 12.4 “A/D Acquisition
Requirements”.

PIC16F753/HV753
12.3 Register Definitions: ADC Control
REGISTER 12-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — CHS<3:0> GO/DONE ADON
bit 7 bit 0
Legend:
bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justified
0 = Left justified
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = AN0
0001 = AN1
0010 = AN2
0011 = AN3
0100 = AN4
0101 = AN5
0110 = AN6
0111 = AN7
1110 = DAC output
1111 = Fixed Voltage Reference
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

PIC16F753/HV753
REGISTER 12-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
— ADCS<2:0> — — — ADPREF1
bit 7 bit 0
Legend:

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from an internal oscillator with a divisor of 16)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 0 ADPREF1: ADC Positive Voltage Reference Selection bit
0 = VDD
1 = VREF+

PIC16F753/HV753
REGISTER 12-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY)
R-x R-x R-x R-x R-x R-x R-x R-x
ADRESH<9:2>
bit 7 bit 0
Legend:
bit 7-0 ADRESH<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result
REGISTER 12-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY)
R-x R-x U-0 U-0 U-0 U-0 U-0 U-0
ADRESL<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADRESL<7:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result
REGISTER 12-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY)
U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x
— — — — — — ADRESH<9:8>
bit 7 bit 0
Legend:

bit 1-0 ADRESH<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result
REGISTER 12-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY)
R-x R-x R-x R-x R-x R-x R-x R-x
ADRESL<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADRESL<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

PIC16F753/HV753
12.4 A/D Acquisition Requirements an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
For the ADC to meet its specified accuracy, the charge time, Equation 12-1 may be used. This equation
holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the
charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed
Input model is shown in Figure 12-4. The source for the ADC to meet its specified resolution.
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 12-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
EQUATION 12-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
V AP PLIE D  1 – ------------ = V CHOLD

1
;[1] VCHOLD charged to within 1/2 lsb
 2047
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
V AP P LIED  1 – e  = V A P PLIE D  1 – ------------
RC 1 ;combining [1] and [2]
   2047
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2µs + 1.37µs +   50°C- 25°C   0.05µs/°C  
= 4.67µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

PIC16F753/HV753
FIGURE 12-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
RS ANx Ric  1k SS Rss
VA CPIN ILEAKAGE
Vt = 0.6V CHOLD = 10 pF
5 pF ± 500 nA
VSS/VREF-
6V
5V RSS
Legend: CPIN = Input Capacitance VDD 4V
VT = Threshold Voltage 3V
ILEAKAGE = Leakage current at the pin due to 2V
various junctions
RIC = Interconnect Resistance 5 6 7 8 9 10 11
SS = Sampling Switch Sampling Switch
CHOLD = Sample/Hold Capacitance (k)
FIGURE 12-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
1 LSB ideal
3FBh
Full-Scale
004h Transition
003h
002h
001h
000h Analog Input Voltage
1 LSB ideal
VSS/VREF- Zero-Scale VDD/VREF+

Transition

PIC16F753/HV753
TABLE 12-2: SUMMARY OF ASSOCIATED ADC REGISTERS

Register
on Page

ADRESH(2) Most Significant eight bits of the left shifted A/D result or two bits of the right shifted result 111*
ADRESL(2) Least Significant two bits of the left shifted result or eight bits of the right shifted result 109*
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
2: Read-only register.

PIC16F753/HV753
13.0 FIXED VOLTAGE REFERENCE 13.2 FVR Stabilization Period
(FVR) When the Fixed Voltage Reference module is enabled, it
The Fixed Voltage Reference (FVR) is a stable voltage requires time for the reference circuit to stabilize. Once
reference, independent of VDD, with 1.2V output level. the circuit stabilizes and is ready for use, the FVRRDY bit
The output of the FVR can be configured to supply a of the FVRCON register will be set. See Section 22.0
reference voltage to the following: “Electrical Specifications” for the minimum delay
requirement.
• ADC input channel
• Comparator 1 positive input (C1VP) 13.3 Operation During Sleep
• Comparator 2 positive input (C2VP)
When the device wakes up from Sleep through an
• FVR_out pin
interrupt or a Watchdog Timer time-out, the contents of
• Shunt regulator the FVRCON register are not affected. To minimize
On the PIC16F753, the FVR is enabled by setting the current consumption in Sleep mode, the FVR voltage
FVREN bit of the FVRCON register. The FVR is always reference should be disabled.
enabled on the PIC16HV753 device.
13.4 Effects of a Reset
13.1 Fixed Voltage Reference Output
A device Reset clears the FVRCON register. As a result:
The FVR output can be applied to the FVROUT pin by • The FVR module is disabled
setting the FVRBUFSS and FVRBUFEN bits of the
• The FVR voltage output is disabled on the
FVRCON register. The FVRBUFSS bit selects the op
FVROUT pin
amp, FVR or DAC output reference to the FVROUT pin
buffer. The FVRBUFEN bit enables the output buffer to
the FVROUT pin.
Enabling the FVROUT pin automatically overrides any
digital input or output functions of the pin. Reading the
FVROUT pin when it has been configured for a
reference voltage output will always return a ‘0’.
FIGURE 13-1: VOLTAGE REFERENCE BLOCK DIAGRAM
FVR_ref
To Peripherals
VDD FVR_buffer1
To Peripherals
FVROE
00
DAC_out 01
+ x1 FVR_out
OPA_out 10
1.2V
FVRIN 11
- FVRBUFEN
rdy FVRRDY
FVREN(1) EN
VSS FVRBUFSS
Note 1: If using PIC16HV753, the FVR will be enabled.

PIC16F753/HV753
13.5 Register Definitions: FVR Control
REGISTER 13-1: FVR1CON0: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0
FVREN FVRRDY FVROE FVRBUFSS1 FVRBUFSS0 — — FVRBUFEN
bit 7 bit 0
Legend:
bit 7 FVREN: Fixed Voltage Reference Enable bit

0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit
0 = Fixed Voltage Reference output is not ready or not enabled bit
1 = Fixed Voltage Reference output is ready for use
bit 5 FVROE: Voltage Reference Output Pin Buffer Enable bit
0 = Output pass gate is disabled
1 = Output pass gate is enabled
bit 4-3 FVRBUFSS<1:0>: Voltage Reference Pin Buffer Source Select bits
00 = Selects the output of the band gap as the input
01 = DAC output
10 = Op amp buffered output
11 = Selects FVRIN (RA1)
bit 0 FVRBUFEN: Voltage Reference Output Pin Buffer Enable bit
0 = Output buffer is disabled
1 = Output buffer is enabled
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Register
on Page
FVR1CON0 FVREN FVRRDY FVROE FVRBUFSS1 FVRBUFSS0 — — FVRBUFEN 116
Legend: Shaded cells are not used with the Fixed Voltage Reference.

PIC16F753/HV753
14.0 DIGITAL-TO-ANALOG 14.1 Output Voltage Selection
CONVERTER (DAC) MODULE The DAC has 512 voltage level ranges. The 512 levels
The Digital-to-Analog Converter supplies a variable are set with the DACR<8:1> bits of the DACxREFH
voltage reference, ratiometric with the input source, register and DACR0 of the DACxREFL.
with 512 selectable output levels. The DAC output voltage is determined by Equation 14-1:
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DACXOUT pin
• Op amp
The Digital-to-Analog Converter (DAC) is enabled by
setting the DACEN bit of the DACxCON0 register.
EQUATION 14-1: DAC OUTPUT VOLTAGE

IF DACEN = 1
DACR  8 
VOUT =   VSOURCE+ – VSOURCE-   ------------------------ + VSOURCE-
 9 
2
VSOURCE+ = VDD, VREF, OPA1OUTor FVR BUFFER 2
VSOURCE- = VSS
14.2 Ratiometric Output Level 14.4 DAC Justification

The DAC output value is derived using a resistor ladder The DAC can be configured to be left or right justified
with each end of the ladder tied to a positive and based on application needs. In order for justification to
negative voltage reference input source. If the voltage work properly, all 16 bits of the DAC buffer register
of either input source fluctuates, a similar fluctuation will (DACxREFH:DACxREFL register pair) must be loaded
result in the DAC output value. in the correct sequence to get the effective 9-bit result.
The value of the individual resistors within the ladder In most applications, DACxREFL is written prior to
can be found in Section 22.0 “Electrical DACxREFH, regardless of justification. The DAC buffer
Specifications”. is loaded at the end of the write cycle that writes
DACxREFH register.
14.3 DAC Voltage Reference Output
The DAC voltage can be output to the DACxOUT pins
by setting the DACOE1 bit of the DACxCON0 register.
Selecting the DAC reference voltage for output on the
DACXOUT pin automatically overrides the digital
output buffer and digital input threshold detector
functions of that pin. Reading the DACXOUT pin when
it has been configured for DAC reference voltage
output will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to either DACXOUT pin.
Figure 14-2 shows a buffering technique example.

PIC16F753/HV753
FIGURE 14-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC)

DACxREFH DACxREFL
9-bit Latch write to

OPA1_out DACxREFH
(not visible to user)
FVR_buffer1 VSOURCE+
VDD
VREF+ 9
R
DACPSS<1:0> R
2
DACEN R
512-to-1 MUX
512 DAC_output
To Peripherals
Steps
R DACxOUT1
DACOE1
R
VSOURCE-
VSS
FIGURE 14-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
R
Module
+
Voltage DACXOUT Buffered DAC Output
–
Reference
Output
Impedance

PIC16F753/HV753
14.5 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACxCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.

A device Reset affects the following:
• DAC is disabled
• DAC output voltage is removed from the
DACXOUT pin
• The DACR<8:0> range select bits are cleared

PIC16F753/HV753
14.7 Register Definitions: DAC Control
REGISTER 14-1: DACxCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0
DACEN DACFM DACOE — DACPSS<1:0> — —
bit 7 bit 0
Legend:
bit 7 DACEN: DAC Enable bit

1 = DACx is enabled
0 = DACx is disabled
bit 6 DACFM: DAC Output Format bit
1 = DACx output result is right justified
0 = DACx output result is left justified
bit 5 DACOE: DAC Voltage Output Enable bit
1 = DACx voltage level is also an output on the DACxOUT pin
0 = DACx voltage level is disconnected from the DACxOUT pin
bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits
11 = FVR output
10 = VREF+ pin
01 = OPA1OUT pin
00 = VDD

PIC16F753/HV753
REGISTER 14-2: DACxREFH: DAC REFERENCE HIGH REGISTER (DACxFM = 0)

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
DACR<8:1>
bit 7 bit 0
Legend:
bit 7-0 DACR<8:1>: DAC Reference Selection bits

DACxOUT = (DACR<8:0> x (Vdac_ref)/512)
REGISTER 14-3: DACxREFL: DAC REFERENCE LOW REGISTER (DACxFM = 0)

R/W-0/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
DACR0 — — — — — — —
bit 7 bit 0
Legend:
bit 7 DACR0: DAC Reference Selection bits

DACxOUT = (DACR<8:0> x (Vdac_ref)/512)

PIC16F753/HV753
REGISTER 14-4: DACxREFH: DAC REFERENCE HIGH REGISTER (DACxFM = 1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — DACR8
bit 7 bit 0
Legend:

bit 0 DACR8: DAC Reference Selection bits
DACxOUT = (DACR<8:0> x (Vdac_ref) / 512)
REGISTER 14-5: DACxREFL: DAC REFERENCE LOW REGISTER (DACxFM = 1)

DACR<7:0>
bit 7 bit 0
Legend:
bit 7-0 DACR<7:0>: DAC Reference Selection bits

DACxOUT = (DACR<8:0> x (Vdac_ref) / 512)
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Register
on Page
DACxCON0 DACEN DACFM DACOE — DACPSS<1:0> — — 120
DACxREFH DACR<8:1> 121
DACxREFH — — — — — — — DACR8 122
DACxREFL DACR<7:0> 121
DACxREFL DACR0 — — — — — — — 122
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

PIC16F753/HV753
15.0 COMPARATOR MODULE FIGURE 15-1: SINGLE COMPARATOR
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and VIN+ +
providing a digital indication of their relative magnitudes. Output
Comparators are very useful mixed-signal building VIN- –
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Independent comparator control VIN-
• Programmable input selection VIN+
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep Output
• Programmable Speed/Power optimization
• PWM shutdown
Note: The black areas of the output of the
• Programmable and Fixed Voltage Reference
comparator represents the uncertainty
15.1 Comparator Overview due to input offsets and response time.
A single comparator is shown in Figure 15-1 along with

the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.

FIGURE 15-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
DS40001709D-page 124
PIC16F753/HV753
CxNCH<1:0>
CxON(1)
2 Interrupt CxINTP
det
CXIN0- 0
CXIN1- 1
Set CxIF
CXIN2- Interrupt CxINTN
2
CXIN3- 3 CXZLF det
CxSP
CXPOL
Slope 4-7 CxVN
Compensator - 0 CXOUT To Data Bus
D Q D Q
Cx MCOUTX
Zero Latency 1
+ Filter
CxVP
EN Q1 EN
CXIN+ 0
MUX CxHYS
DAC_OUT 1 (2)
To COG Module, Slope test output
2 icd_freeze
FVR Reference
Slope 3
Compensator CXSYNC
CXOE
4-7 TRIS bit
CxON CXOUT
AGND 0
D Q 1
CXPCH<2:0>
From Timer1
3 To Timer1
tmr1_clk
SYNCCXOUT
Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output.
2: When CxON = 0, all multiplexer inputs are disconnected.

PIC16F753/HV753
15.2 Comparator Control 15.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally
and CMxCON1. equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
The CMxCON0 registers (see Register 15-1) contain setting the CxPOL bit of the CMxCON0 register.
Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output.
• Enable Table 15-1 shows the output state versus input
• Output selection conditions, including polarity control.
• Output pin enable TABLE 15-1: COMPARATOR OUTPUT
• Output polarity STATE VS. INPUT
• Speed/Power selection CONDITIONS
• Hysteresis enable Input Condition CxPOL CxOUT
• Output synchronization
CxVN > CxVP 0 0
The CMxCON1 registers (see Register 15-2) contain
CxVN < CxVP 0 1
Control bits for the following:
CxVN > CxVP 1 1
• Interrupt edge polarity (rising and/or falling)
CxVN < CxVP 1 0
• Positive input channel selection
• Negative input channel selection 15.2.4 COMPARATOR SPEED/POWER
15.2.1 COMPARATOR ENABLE SELECTION
The trade-off between speed or power can be
Setting the CxON bit of the CMxCON0 register enables
optimized during program execution with the CxSP
the comparator for operation. Clearing the CxON bit
control bit. The default state for this bit is ‘1’ which
disables the comparator resulting in minimum current
selects the normal speed mode. Device power
consumption.
consumption can be optimized at the cost of slower
15.2.2 COMPARATOR OUTPUT comparator propagation delay by clearing the CxSP bit
to ‘0’.
SELECTION
The output of the comparator can be monitored by 15.3 Comparator Hysteresis
reading either the CxOUT bit of the CMxCON0 register
or the MCOUTx bit of the CMOUT register. In order to A selectable amount of separation voltage can be
make the output available for an external connection, added to the input pins of each comparator to provide a
the following conditions must be true: hysteresis function to the overall operation. Hysteresis
• CxOE bit of the CMxCON0 register must be set is enabled by setting the CxHYS bit of the CMxCON0
register.
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set See Section 22.0 “Electrical Specifications” for more
information.
Note 1: The CxOE bit of the CMxCON0 register 15.4 Timer1 Gate Operation
overrides the PORT data latch. Setting
The output resulting from a comparator operation can
the CxON bit of the CMxCON0 register
be used as a source for gate control of Timer1. See
has no impact on the port override.
Section 7.5 “Timer1 Gate” for more information. This
2: The internal output of the comparator is feature is useful for timing the duration or interval of an
latched with each instruction cycle. analog event.
Unless otherwise specified, external
It is recommended that the comparator output be
outputs are not latched.
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.

PIC16F753/HV753
15.4.1 COMPARATOR OUTPUT 15.6 Comparator Positive Input
SYNCHRONIZATION Selection
The output from either comparator, C1 or C2, can be Configuring the CxPCH<1:0> bits of the CMxCON1
synchronized with Timer1 by setting the CxSYNC bit of register directs an internal voltage reference or an
the CMxCON0 register. analog pin to the non-inverting input of the comparator:
Once enabled, the comparator output is latched on the • CxIN0+ analog pin
falling edge of the Timer1 source clock. If a prescaler is
• DAC Reference Voltage (DAC_REF)
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the • FVR Reference Voltage (FVR_REF)
comparator output is latched on the falling edge of the • VSS (Ground)
Timer1 clock source and Timer1 increments on the See Section 13.0 “Fixed Voltage Reference (FVR)”
rising edge of its clock source. See the Comparator for more information on the Fixed Voltage Reference
Block Diagram (Figure 15-2) and the Timer1 Block module.
Diagram (Figure 7-1) for more information.
See Section 14.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
15.5 Comparator Interrupt signal.
An interrupt can be generated upon a change in the Any time the comparator is disabled (CxON = 0), all
output value of the comparator for each comparator, a comparator inputs are disabled.
rising edge detector and a falling edge detector are
present. 15.7 Comparator Negative Input
When either edge detector is triggered and its Selection
associated enable bit is set (CxINTP and/or CxINTN
bits of the CMxCON1 register), the Corresponding The CxNCH0 bit of the CMxCON0 register selects the
Interrupt Flag bit (CxIF bit of the PIR2 register) will be analog input pin to the comparator inverting input.
set. Note: To use CxIN0+ and CxIN1x- pins as
To enable the interrupt, you must set the following bits: analog input, the appropriate bits must be
• CxON, CxPOL and CxSP bits of the CMxCON0 set in the ANSEL register and the
register corresponding TRIS bits must also be set
to disable the output drivers.
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection) 15.8 Comparator Response Time
• CxINTN bit of the CMxCON1 register (for a falling The comparator output is indeterminate for a period of
edge detection) time after the change of an input source or the selection
• PEIE and GIE bits of the INTCON register of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
The associated interrupt flag bit, CxIF bit of the PIR2
differs from the settling time of the voltage reference.
register, must be cleared in software. If another edge is
Therefore, both of these times must be considered when
detected while this flag is being cleared, the flag will still
determining the total response time to a comparator
be set at the end of the sequence.
input change. See the Comparator and Voltage Refer-
Note: Although a comparator is disabled, an ence Specifications in Section 22.0 “Electrical Specifi-
interrupt can be generated by changing cations” for more details.
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching 15.9 Interaction with the COG Module
the comparator on or off with the CxON bit
of the CMxCON0 register. The comparator outputs can be brought to the COG
module in order to facilitate auto-shutdown. If auto-
restart is also enabled, the comparators can be
configured as a closed loop analog feedback to the
COG, thereby creating an analog controlled PWM.

PIC16F753/HV753
15.10 Zero Latency Filter
In high-speed operation, and under proper circuit
conditions, it is possible for the comparator output to
oscillate. This oscillation can have adverse effects on
the hardware and software relying on this signal.
Therefore, a digital filter has been added to the
comparator output to suppress the comparator output
oscillation. Once the comparator output changes, the
output is prevented from reversing the change for a
nominal time of 20 ns. This allows the comparator
output to stabilize without affecting other dependent
devices. Refer to Figure 15-3.
FIGURE 15-3: COMPARATOR ZERO LATENCY FILTER OPERATION
CxOUT From Comparator
CxOUT From ZLF

TZLF
Output waiting for TZLF to expire before an output change is allowed
TZLF has expired so output change of ZLF is immediate based on

comparator output change

PIC16F753/HV753
15.11 Analog Input Connection
Considerations Note 1: When reading a PORT register, all pins
A simplified circuit for an analog input is shown in configured as analog inputs will read as a
Figure 15-4. Since the analog input pins share their ‘0’. Pins configured as digital inputs will
connection with a digital input, they have reverse convert as an analog input, according to
biased ESD protection diodes to VDD and VSS. The the input specification.
analog input, therefore, must be between VSS and VDD. 2: Analog levels on any pin defined as a
If the input voltage deviates from this range by more digital input, may cause the input buffer to
than 0.6V in either direction, one of the diodes is consume more current than is specified.
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 15-4: ANALOG INPUT MODEL

VDD
Analog
Input
pin VT  0.6V RIC
Rs < 10K
To Comparator
CPIN ILEAKAGE(1)
VA
5 pF VT  0.6V
Vss
Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
Note 1: See Section 22.0 “Electrical Specifications”.

PIC16F753/HV753
15.12 Register Definitions: Comparator Control
REGISTER 15-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0
CxON CxOUT CxOE CxPOL CxZLF CxSP CxHYS CxSYNC
bit 7 bit 0
Legend:
bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 CxOE: Comparator Output Enable bit
1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0 = CxOUT is internal only
bit 4 CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3 CxZLF: Zero Latency Filter Enable bit
1 = Zero latency filter is enabled
0 = Zero latency filter is disabled
bit 2 CxSP: Comparator Speed/Power Select bit
1 = Comparator operates in normal power, higher speed mode
0 = Comparator operates in low-power, low-speed mode
bit 1 CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous.

PIC16F753/HV753
REGISTER 15-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

CxINTP CxINTN CxPCH<1:0> CxNCH<2:0>
bit 7 bit 0
Legend:
bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bit

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bit
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-3 CxPCH<1:0>: Comparator Positive Input Channel Select bits
000 = CxVP connects to CxIN+ pin
001 = CxVP connects to dac_out
010 = CxVP connects to FVR
011 = CxVP connects to Slope Compensator Output
1xx = CxVP connects to AGND
bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits
000 = CxVN connects to CxIN0- pin
1xx = CxVN connects to Slope Compensator Output
REGISTER 15-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MCOUT2 MCOUT1
bit 7 bit 0
Legend:

bit 1 MCOUT2: Mirror Copy of C2OUT bit
bit 0 MCOUT1: Mirror Copy of C1OUT bit

PIC16F753/HV753
TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register
on Page
CMOUT — — — — — — MCOUT2 MCOUT1 130
DAC1REFL Least Significant bit of the left shifted result or eight bits of the right shifted DAC setting 122
FVR1CON0 FVREN FVRRDY FVROE FVRBUFSS1 FVRBUFSS0 — — FVRBUFEN 116
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

PIC16F753/HV753
16.0 OPERATIONAL AMPLIFIER 16.3 OPA Module Performance
(OPA) MODULE Common AC and DC performance specifications for
The Operational Amplifier (OPA) is a standard three- the OPA module:
terminal device requiring external feedback to operate. • Common Mode Voltage Range
The OPA module has the following features: • Leakage Current
• External Connections to I/O Ports • Input Offset Voltage
• Selectable Unity Gain Bandwidth Product Option • Open Loop Gain
• Low-Leakage Inputs • Gain Bandwidth Product
• Factory-Calibrated Input Offset Voltage Common mode voltage range is the specified voltage
range for the OPAx+ and OPAx- inputs, for which the
16.1 OPAxCON0 Register OPA module will perform within its specifications. The
OPA module is designed to operate with input voltages
The OPAxCON0 register, shown in Register 16-1, between VSS and VDD. Behavior for Common mode
controls the OPA module. voltages greater than VDD or below VSS is not
The OPA module is enabled by setting the OPAxEN bit guaranteed.
of the OPAxCON register. When enabled, the OPA Leakage current is a measure of the small source or
forces the output driver of the OPAxOUT pin into tri- sink currents on the OPAx+ and OPAx- inputs. To
state to prevent contention between the driver and the minimize the effect of leakage currents, the effective
OPA output. impedances connected to the OPAx+ and OPAx- inputs
The OPAxUGM bit of the OPAxCON register enables should be kept as small as possible and equal. Input
the Unity Gain Bandwidth mode (voltage follower) of offset voltage is a measure of the voltage difference
the amplifier. In Unity Gain mode, the OPAxNCH<1:0> between the OPAx+ and OPAx- inputs in a closed loop
inputs are disabled. The default mode is normal three- circuit with the OPA in its linear region. The offset
terminal operation. voltage will appear as a DC offset in the output equal to
the input offset voltage, multiplied by the gain of the
circuit.
Note: When the OPA module is enabled, the The input offset voltage is also affected by the Common
OPAxOUT pin is driven by the op amp mode voltage. The OPA is factory-calibrated to
output, not by the PORT digital driver. minimize the input offset voltage of the module. Open
Refer to Section 22.0 “Electrical loop gain is the ratio of the output voltage to the
Specifications” for the op amp output differential input voltage (OPAx+) - (OPAx-). The gain is
drive capability. greatest at DC and falls off with frequency.
Gain Bandwidth Product or GBWP is the frequency at
16.2 Effects of a Reset which the open loop gain falls off to 0 dB. The lower
A device Reset forces all registers to their Reset state. GBWP is optimized for systems requiring low-fre-
This disables the OPA module. quency response and low-power consumption.

PIC16F753/HV753
FIGURE 16-1: OPA MODULE BLOCK DIAGRAM
OPAxNCH<1:0>
FVR_buffer1 11
1
DACx_output 10
0
01
OPAxIN- 00
OPAxUGM OPAx-
-
OPAx OPAxOUT
OPAx+ OPAx_output
FVR_buffer1 11
+
DACx_output 10
OPAxEN
SLOPE_output 01
OPAxIN+ 00
OPAxPCH<1:0>

PIC16F753/HV753
16.4 Register Definitions: OPA Control
REGISTER 16-1: OPAxCON0: OP AMP CONTROL REGISTER
R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
OPAxEN — — OPAxUGM OPAxNCH<1:0> OPAxPCH<1:0>
bit 7 bit 0
Legend:
bit 7 OPAxEN: OPAx Enable bit

1 = OPAx is enabled
0 = OPAx is disabled
bit 4 OPAxUGM: OPAx Unity Gain Mode Enable bit
1 = OPAx is in Unity gain mode
0 = OPAx is not in Unity gain mode - operates as a three-terminal op amp
bit 3-2 OPAxNCH<1:0>: OPAx Negative Input Source Selection bit
11 = OPAx- connects to FVR_buffer1
10 = OPAx- connects to DAC1_output
0x = OPAx- connects to OPAxIN- pin
bit 1-0 OPAxPCH<1:0>: OPAx Positive Input Source Selection bit
11 = OPAx+ connects to FVR_buffer1
10 = OPAx+ connects to DAC1_output
01 = OPAx+ connects to SLOPE_output
00 = OPAx+ connects to OPAxIN+ pin
TABLE 16-1: REGISTERS ASSOCIATED WITH THE OPA MODULE

Register
on Page
OPA1CON0 OPA1EN — — OPA1UGM OPA1NCH<1:0> OPA1PCH<1:0> 134
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for the OPA module.

PIC16F753/HV753
17.0 SLOPE COMPENSATION (SC) 17.1 Theory of Operation
MODULE The SC module works by quickly discharging an internal
The Slope Compensation (SC) module is designed to capacitor at the beginning of each PWM period. An
provide the necessary slope compensation for fixed internal current sink charges this capacitor at a program-
frequency, continuous current, and current mode mable rate. As the capacitor charges, the capacitor volt-
switched power supplies. Slope compensation is a age is subtracted from the reference voltage, producing
necessary feature of these power supplies because it a linear voltage decay at the required rate. The current
prevents frequency instabilities at duty cycles greater reference voltage can be supplied by either an I/O pin or
than 50%. by the buffered output of the FVR peripheral. The FVR
module provides either a fixed voltage or a programma-
ble DAC output. The Reset source can be derived from
either the COG output or the synchronized output of
either comparator. Additionally, the Reset source can be
inverted before triggering the Reset. The slope voltage
can be sent to either comparator or the op amp.
The core of the SC module is:
• an on-chip capacitor in series with the voltage
source,
• a shorting switch across the capacitor, and
• a calibrated current sink.
A one-shot pulse generator ensures that the switch is
closed long enough to completely discharge the
capacitor. This typically takes 50 ns.
FIGURE 17-1: SIMPLIFIED SC MODULE BLOCK DIAGRAM
SCxINS
SLPCIN 0 SLOPE_output
FVR_buffer1 1 to
peripherals
SCxPOL
COG1_output0 00
COG1_output1 01 One Shot
C1OUT_sync 10
C2OUT_sync 11
SCxTSS<1:0>
SCxISET * 0.75/15 + 0.2V/µS

0
SCxISET<3:0>
1
SCxISET + 1.0V/µS
SCxRNG

PIC16F753/HV753
FIGURE 17-2: SLOPE COMPENSATION TIMING DIAGRAM
Slope Compensation Trigger

COG or Comparator Output
One Shot Output
Slope Compensation Reference Voltage
Slope Compensation Output
17.2 Using the SC Module For example, when the circuit is using a 1 current
sense resistor and the peak current is 1A, then the
The slope compensator input reference voltage should peak current expressed as a voltage (VREF) is 1V. If
be set to the target circuit peak current sense voltage. your power supply is running at 1 MHz, then the period
The slope compensator output voltage starts at the is 1 s. Therefore, the desired slope is:
input reference voltage and should fall at a rate less
than half the target circuit current sense voltage rate of
EQUATION 17-2: SLOPE COMPENSATION
rise. Therefore, the compensator slope expressed as
VOLTAGE
volts per µs can be computed as shown in
Equation 17-2.
V REF 1
EQUATION 17-1: SC MODULE ------------- ---
2 2
-------------------------------------------- = --------- = 0.5V   s
PWM Period (  s  1s
V REF
-------------
V 2
------  --------------------------------------------
 s PWM Period (  s  Note: The setting for 0.5V/s is
SCxISET<3:0> = 6 and SCxRNG = 0.

PIC16F753/HV753
FIGURE 17-3: EXAMPLE SLOPE COMPENSATION CIRCUIT
VIN
L1
D1
COGxOUTx
COG C1
-
+ CxINx- R2
R1
SC
SLPCIN DAC
OPAxOUT
+ OPAxIN- R4 R3
-
C2
R5
C3
17.3 Inputs
The SC module connects to the following inputs:
• COG1
• COG2
• Comparator C1
• Comparator C2
17.4 Outputs
The SC module connects to the following outputs:
• Comparator C1
• Comparator C2
• Op amp
17.5 Operation During Sleep

The SC module is unaffected by Sleep.

The SC module resets to a disabled condition.

PIC16F753/HV753
17.7 Register Definitions: Slope Compensation Control
REGISTER 17-1: SLPCCON0: SLOPE COMPENSATION CONTROL 0 REGISTER
R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
SCxEN — — SCxPOL SCxTSS<1:0> — SCxINS
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7 SCxEN: Slope Compensation Enable bit

1 = Slope compensation is enabled
0 = Slope compensation is disabled
bit 4 SCxPOL: Slope Compensation Input Polarity bit
1 = Signal is inverted polarity (active-low)
0 = Signal is normal polarity (active-high)
bit 3-2 SCxTSS<1:0>: Slope Compensation Timing Select bits
11 = C2OUT_sync
10 = C1OUT_sync
01 = COG1_output1
00 = COG1_output0
bit 0 SCxINS: Slope Compensation Input Select bit
1 = FVR_buffer1 is selected
0 = SLPC1IN pin is selected
REGISTER 17-2: SLPCCON1: SLOPE COMPENSATION CONTROL 1 REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — SCxRNG SCxISET<3:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits

bit 4 SCxRNG: Slope Compensator Range bit
1 = Range setting is SCxISET +1.0V/s
0 = Range setting is SCxISET * 0.75/15 +0.2V/s
bit 3-0 SCxISET<3:0>: Slope Compensator Current Sink Set bits
xxxxx = SC module Slope Selection

PIC16F753/HV753
TABLE 17-1: SLOPE COMPENSATOR CURRENT SETTINGS

Current Setting Slope Value Current Setting Slope Value
SC1ISET Value SC1ISET Value
(uA) (V/us) (uA) (V/us)
0h 2 0.2 10h 10 1.0
1h 2.5 0.25 11h 11 1.1
2h 3 0.3 12h 12 1.2
3h 3.5 0.35 13h 13 1.3
4h 4 0.4 14h 14 1.4
5h 4.5 0.45 15h 15 1.5
6h 5 0.5 16h 16 1.6
7h 5.5 0.55 17h 17 1.7
8h 6 0.6 18h 18 1.8
9h 6.5 0.65 19h 19 1.9
Ah 7 0.7 1Ah 20 2.0
Bh 7.5 0.75 1Bh 21 2.1
Ch 8 0.8 1Ch 22 2.2
Dh 8.5 0.85 1Dh 23 2.3
Eh 9 0.9 1Eh 24 2.4
Fh 9.5 0.95 1Fh 25 2.5
TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE SC MODULE

Register
on Page
SLPCCON0 SC1EN — — SC1POL SC1TSS<1:0> — SC1INS 138
SLPCCON1 — — — SC1RNG SC1ISET<3:0> 138
PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 49
WPUC — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the slope compensation module.

PIC16F753/HV753
18.0 INSTRUCTION SET SUMMARY
TABLE 18-1: OPCODE FIELD
The PIC16F753/HV753 instruction set is highly
DESCRIPTIONS
orthogonal and is comprised of three basic categories:
• Byte-oriented operations Field Description
• Bit-oriented operations f Register file address (0x00 to 0x7F)
• Literal and control operations W Working register (accumulator)
Each PIC16 instruction is a 14-bit word divided into an b Bit address within an 8-bit file register
opcode, which specifies the instruction type and one or k Literal field, constant data or label
more operands, which further specify the operation of x Don’t care location (= 0 or 1).
the instruction. The formats for each of the categories
The assembler will generate code with x = 0.
is presented in Figure 18-1, while the various opcode
It is the recommended form of use for
fields are summarized in Table 18-1.
compatibility with all Microchip software tools.
Table 18-2 lists the instructions recognized by the d Destination select; d = 0: store result in W,
MPASMTM assembler. d = 1: store result in file register f.
For byte-oriented instructions, ‘f’ represents a file Default is d = 1.
register designator and ‘d’ represents a destination PC Program Counter
designator. The file register designator specifies which
TO Time-out bit
file register is to be used by the instruction.
C Carry bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is DC Digit carry bit
placed in the W register. If ‘d’ is one, the result is placed Z Zero bit
in the file register specified in the instruction. PD Power-down bit
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the FIGURE 18-1: GENERAL FORMAT FOR
operation, while ‘f’ represents the address of the file in INSTRUCTIONS
which the bit is located.
Byte-oriented file register operations
For literal and control operations, ‘k’ represents an
13 8 7 6 0
8-bit or 11-bit constant, or literal value.
OPCODE d f (FILE #)
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal d = 0 for destination W
d = 1 for destination f
instruction execution time of 1 s. All instructions are f = 7-bit file register address
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
Bit-oriented file register operations
changed as a result of an instruction. When this occurs,
13 10 9 7 6 0
the execution takes two instruction cycles, with the
OPCODE b (BIT #) f (FILE #)
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to b = 3-bit bit address
f = 7-bit file register address
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
Literal and control operations
18.1 Read-Modify-Write Operations General

13 8 7 0
Any instruction that specifies a file register as part of OPCODE k (literal)
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified, k = 8-bit immediate value
and the result is stored according to either the instruc-
tion or the destination designator ‘d’. A read operation CALL and GOTO instructions only
is performed on a register even if the instruction writes 13 11 10 0
to that register.
OPCODE k (literal)
For example, a CLRF PORTA instruction will read
k = 11-bit immediate value
PORTA, clear all the data bits, then write the result back
to PORTA. This example would have the unintended
consequence of clearing the condition that set the
IOCIF flag.

PIC16F753/HV753
TABLE 18-2: PIC16F753/HV753 INSTRUCTION SET

Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP – No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE – Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.

PIC16F753/HV753
18.2 Instruction Descriptions
ADDLW Add literal and W BCF Bit Clear f
Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b

Operands: 0  k  255 Operands: 0  f  127
0b7
Operation: (W) + k  (W)
Operation: 0  (f<b>)
Status Affected: C, DC, Z
Status Affected: None
Description: The contents of the W register
are added to the 8-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared.
and the result is placed in the
W register.
ADDWF Add W and f BSF Bit Set f
Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b

Operands: 0  f  127 Operands: 0  f  127
d 0,1 0b7
Operation: (W) + (f)  (destination) Operation: 1  (f<b>)
Status Affected: C, DC, Z Status Affected: None
Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set.
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b

0b7
Operation: (W) .AND. (k)  (W)
Operation: skip if (f<b>) = 0
Status Affected: Z
Description: The contents of W register are
AND’ed with the 8-bit literal ‘k’. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
The result is placed in the W instruction is executed.
register. If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
2-cycle instruction.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0  f  127
d 0,1
Operation: (W) .AND. (f)  (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.

PIC16F753/HV753
BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer
Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT

Operands: 0  f  127 Operands: None
0b<7 Operation: 00h  WDT
Operation: skip if (f<b>) = 1 0  WDT prescaler,
1  TO
1  PD
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Status Affected: TO, PD
instruction is executed.
If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the
instruction is discarded and a NOP Watchdog Timer. It also resets the
is executed instead, making this a prescaler of the WDT.
2-cycle instruction. Status bits TO and PD are set.
CALL Call Subroutine COMF Complement f

Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d
Operation: (PC)+ 1 TOS, d  [0,1]
k  PC<10:0>, Operation: (f)  (destination)
(PCLATH<4:3>)  PC<12:11>
Status Affected: Z
Description: The contents of register ‘f’ are
Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the
address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’,
the stack. The 11-bit immediate the result is stored back in
address is loaded into PC bits register ‘f’.
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a 2-cycle instruction.
CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
Operation: 00h  (f) d  [0,1]
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’,
cleared and the Z bit is set. the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.

PIC16F753/HV753
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.
If the result is ‘1’, the next If the result is ‘1’, the next
instruction is executed. If the instruction is executed. If the
result is ‘0’, then a NOP is result is ‘0’, a NOP is executed
executed instead, making it a instead, making it a 2-cycle
2-cycle instruction. instruction.
GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<4:3>  PC<12:11> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. OR’ed with the 8-bit literal ‘k’. The
The 11-bit immediate value is result is placed in the
loaded into PC bits <10:0>. The W register.
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
2-cycle instruction.
INCF Increment f IORWF Inclusive OR W with f
Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d

d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Inclusive OR the W register with
incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is
is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.

PIC16F753/HV753
MOVF Move f MOVWF Move W to f

Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f
d  [0,1] Operation: (W)  (f)
Operation: (f)  (dest) Status Affected: None
Status Affected: Z Description: Move data from W register to
Description: The contents of register ‘f’ is register ‘f’.
moved to a destination dependent Words: 1
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1, Cycles: 1
the destination is file register ‘f’ Example: MOVW OPTION
itself. d = 1 is useful to test a file F
register since Status flag Z is Before Instruction
affected. OPTION = 0xFF
Words: 1 W = 0x4F
Cycles: 1 After Instruction
OPTION = 0x4F
Example: MOVF FSR, 0 W = 0x4F
After Instruction
W = value in FSR
register
Z = 1
MOVLW Move literal to W NOP No Operation

Syntax: [ label ] MOVLW k Syntax: [ label ] NOP
Operands: 0  k  255 Operands: None
Operation: k  (W) Operation: No operation
Description: The 8-bit literal ‘k’ is loaded into W Description: No operation.
register. The “don’t cares” will Words: 1
assemble as ‘0’s.
Cycles: 1
Words: 1
Example: NOP
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A

PIC16F753/HV753
RETFIE Return from Interrupt RETLW Return with literal in W

Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k
Operands: None Operands: 0  k  255
Operation: TOS  PC, Operation: k  (W);
1  GIE TOS  PC
Description: Return from Interrupt. Stack is Description: The W register is loaded with the
POPed and Top-of-Stack (TOS) is 8-bit literal ‘k’. The program
loaded in the PC. Interrupts are counter is loaded from the top of
enabled by setting Global the stack (the return address).
Interrupt Enable bit, GIE (INT- This is a 2-cycle instruction.
CON<7>). This is a 2-cycle Words: 1
instruction.
Cycles: 2
Words: 1
Example: CALL TABLE;W contains
Cycles: 2 ;table offset
Example: RETFIE ;value
After Interrupt GOTO DONE
PC = TOS TABLE •
GIE = 1 •
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ;End of table
DONE
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine

Syntax: [ label ] RETURN
Operands: None
Operation: TOS  PC
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a 2-cycle instruc-
tion.

PIC16F753/HV753
RLF Rotate Left f through Carry SLEEP Enter Sleep mode

Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP
Operands: 0  f  127 Operands: None
d  [0,1] Operation: 00h  WDT,
Operation: See description below 0  WDT prescaler,
Status Affected: C 1  TO,
0  PD
Description: The contents of register ‘f’ are
rotated 1 bit to the left through the Status Affected: TO, PD
Carry flag. If ‘d’ is ‘0’, the result is Description: The power-down Status bit, PD is
placed in the W register. If ‘d’ is cleared. Time-out Status bit, TO
‘1’, the result is stored back in is set. Watchdog Timer and its
register ‘f’. prescaler are cleared.
C Register f The processor is put into Sleep
mode with the oscillator stopped.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1
RRF Rotate Right f through Carry SUBLW Subtract W from literal

Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k
Operands: 0  f  127 Operands: 0 k 255
d  [0,1] Operation: k - (W) W)
Operation: See description below Status Affected: C, DC, Z
Status Affected: C Description: The W register is subtracted (2’s
Description: The contents of register ‘f’ are complement method) from the 8-bit
rotated 1 bit to the right through literal ‘k’. The result is placed in the
the Carry flag. If ‘d’ is ‘0’, the W register.
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed Result Condition
back in register ‘f’. C=0 Wk
C Register f C=1 Wk
DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>

PIC16F753/HV753
SUBWF Subtract W from f XORWF Exclusive OR W with f

Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF f,d
Operands: 0 f 127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination)
Status Affected: C, DC, Z Status Affected: Z
Description: Subtract (2’s complement method) Description: Exclusive OR the contents of the
W register from register ‘f’. If ‘d’ is W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’. stored back in register ‘f’.
C=0 Wf
C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>
SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d
Operands: 0  f  127
d  [0,1]
Operation: (f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the 8-bit
literal ‘k’. The result is placed in
the W register.

PIC16F753/HV753
19.0 SPECIAL FEATURES OF THE 19.1 Configuration Bits
CPU The Configuration bits can be programmed (read as
The PIC16F753/HV753 has a host of features intended ‘0’), or left unprogrammed (read as ‘1’) to select various
to maximize system reliability, minimize cost through device configurations as shown in Register 19-1.
elimination of external components, provide power- These bits are mapped in program memory location
saving features and offer code protection. 2007h.
These features are:

Note: Address 2007h is beyond the user program
• Reset memory space. It belongs to the special
- Power-on Reset (POR) configuration memory space (2000h-
- Power-up Timer (PWRT) 3FFFh), which can be accessed only during
- Brown-out Reset (BOR) programming. See the PIC16F753/HV753
Flash Memory Programming Specification
• Interrupts
(DS41686) for more information.
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming™
The Power-up Timer (PWRT), which provides a fixed
delay of 64 ms (nominal) on power-up only, is designed
to keep the part in Reset while the power supply
stabilizes. There is also circuitry to reset the device if a
brown-out occurs, which can use the Power-up Timer
to provide at least a 64 ms Reset. With these functions-
on-chip, most applications need no external Reset
circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake up from Sleep
through:
• External Reset
• Watchdog Timer Wake-up
• An interrupt
Oscillator selection options are available to allow the
part to fit the application. The INTOSC options save
system cost, while the External Clock (EC) option
provides a means for specific frequency and accurate
clock sources. Configuration bits are used to select
various options (see Register 19-1).

PIC16F753/HV753
REGISTER 19-1: CONFIGURATION WORD

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DEBUG CLKOUTEN WRT<1:0> BOREN<1:0>
bit 13 bit 8
U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 R/P-1

— CP MCLRE PWRTE WDTE — — FOSC0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 DEBUG: Debug Mode Enable bit(2)

1 = Background debugger is disabled
0 = Background debugger is enabled
bit 12 CLKOUTEN: Clock Out Enable bit
1 = Clock out function disabled. CLKOUT pin acts as I/O pin
0 = General purpose I/O disabled. CLKOUT pin acts as CLKOUT
bit 11-10 WRT<1:0>: Flash Program Memory Self-Write Enable bit
11 = Write protection off
10 = 000h to FFh write-protected, 100h to 3FFh may be modified by PMCON1 control
01 = 000h to 1FFh write-protected, 200h to 3FFh may be modified by PMCON1 control
00 = 000h to 3FFh write-protected, entire program is write-protected
bit 8-9 BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
0x = BOR disabled
bit 6 CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: MCLR/VPP Pin Function Select bit
1 = MCLR pin is MCLR function and weak internal pull-up is enabled
0 = MCLR pin is input function, MCLR function is internally disabled
bit 4 PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 0 FOSC: Oscillator Selection bits
1 = EC oscillator selected: CLKIN on RA5/CLKIN
0 = Internal oscillator: I/O function on RA5/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The Configuration bit is managed automatically by the device development tools. The user should not attempt to man-
ually write this bit location. However, the user should ensure that this location has been programmed to a ‘1’ and the
device checksum is correct for proper operation of production software.

PIC16F753/HV753
19.2 Calibration Bits Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
The 8 MHz internal oscillator is factory-calibrated. other Reset. Most other registers are reset to a “Reset
These calibration values are stored in fuses located in state” on:
the Calibration Word (2008h). The Calibration Word is
not erased when using the specified bulk erase • Power-on Reset
sequence in the PIC16F753/HV753 Flash Memory • MCLR Reset
Programming Specification (DS41686) and thus, does • MCLR Reset during Sleep
not require reprogramming. • WDT Reset
• Brown-out Reset (BOR)
19.3 Reset
WDT wake-up does not cause register Resets in the
The PIC16F753/HV753 device differentiates between same manner as a WDT Reset since wake-up is
various kinds of Reset: viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
a) Power-on Reset (POR)
situations, as indicated in Table 19-2. Software can use
b) WDT Reset during normal operation these bits to determine the nature of the Reset. See
c) WDT Reset during Sleep Table 19-4 for a full description of Reset states of all
d) MCLR Reset during normal operation registers.
e) MCLR Reset during Sleep A simplified block diagram of the On-Chip Reset Circuit
f) Brown-out Reset (BOR) is shown in Figure 19-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 22.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 19-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
S
PWRT Chip_Reset
On-Chip 11-bit Ripple Counter R Q
RC OSC
Enable PWRT
Note 1: Refer to the Configuration Word register (Register 19-1).

PIC16F753/HV753
TABLE 19-1: TIME-OUT IN VARIOUS SITUATIONS

Power-up Brown-out Reset Wake-up from
Oscillator Configuration
PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Sleep
EC, INTOSC TPWRT — TPWRT — —
TABLE 19-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR BOR TO PD Condition
0 x 1 1 Power-on Reset
u 0 1 1 Brown-out Reset
u u 0 u WDT Reset
u u 0 0 WDT Wake-up
u u u u MCLR Reset during normal operation
u u 1 0 MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
19.3.1 POWER-ON RESET (POR) during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
The on-chip POR circuit holds the chip in Reset until
directly to VDD. The use of an RC network, as shown in
VDD has reached a high enough level for proper
Figure 19-2, is suggested.
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This An internal MCLR option is enabled by clearing the
will eliminate external RC components usually needed MCLRE bit in the Configuration Word register. When
to create Power-on Reset. A maximum rise time for MCLRE = 0, the Reset signal to the chip is generated
VDD is required. See Section 22.0 “Electrical internally. When the MCLRE = 1, the MCLR pin
Specifications” for details. If the BOR is enabled, the becomes an external Reset input. In this mode, the
maximum rise time specification does not apply. The MCLR pin has a weak pull-up to VDD.
BOR circuitry will keep the device in Reset until VDD
reaches VBOR (see Section 19.3.4 “Brown-out Reset FIGURE 19-2: RECOMMENDED MCLR
(BOR)”). CIRCUIT
Note: The POR circuit does not produce an VDD
internal Reset when VDD declines. To re-
enable the POR, VDD must reach Vss for PIC®
a minimum of 100 s. R1 MCU
1 kor greater)
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e., R2
voltage, frequency, temperature, etc.) must be met to MCLR
ensure proper operation. If these conditions are not 100 
SW1 needed with capacitor)
met, the device must be held in Reset until the (optional)
operating conditions are met.
C1
For additional information, refer to Application Note 0.1 F
AN607, Power-up Trouble Shooting (DS00607). (optional, not critical)
19.3.2 MCLR
PIC16F753/HV753 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification

PIC16F753/HV753
19.3.3 POWER-UP TIMER (PWRT) 19.3.4 BROWN-OUT RESET (BOR)
The Power-up Timer provides a fixed 64 ms (nominal) The BOREN<1:0> bits in the Configuration Word
time-out on power-up only, from POR or Brown-out register select one of three BOR modes. One mode
Reset. The Power-up Timer operates from an internal has been added to allow control of the BOR enable for
RC oscillator. For more information, see Section 4.2.2 lower current during Sleep. By selecting
“Internal Clock Mode”. The chip is kept in Reset as BOREN<1:0> = 10, the BOR is automatically disabled
long as PWRT is active. The PWRT delay allows the in Sleep to conserve power and enabled on wake-up.
VDD to rise to an acceptable level. A Configuration bit, See Register 19-1 for the Configuration Word
PWRTE, can disable (if set) or enable (if cleared or definition.
programmed) the Power-up Timer. The Power-up A brown-out occurs when VDD falls below VBOR for
Timer should be enabled when Brown-out Reset is greater than parameter TBOR (see Section 22.0
enabled, although it is not required. “Electrical Specifications”). The brown-out condition
The Power-up Timer delay will vary from chip-to-chip will reset the device. This will occur regardless of VDD
due to: slew rate. A Brown-out Reset may not occur if VDD falls
• VDD variation below VBOR for less than parameter TBOR.
• Temperature variation On any Reset (Power-on, Brown-out Reset, Watchdog
• Process variation timer, etc.), the chip will remain in Reset until VDD rises
above VBOR (see Figure 19-3). If enabled, the Power-
See DC parameters for details (Section 22.0 up Timer will be invoked by the Reset and keep the chip
“Electrical Specifications”). in Reset an additional 64 ms.
Note: The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
Note: Voltage spikes below VSS at the MCLR
register.
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis- If VDD drops below VBOR while the Power-up Timer is
tor of 50-100 should be used when running, the chip will go back into a Brown-out Reset
applying a “low” level to the MCLR pin, and the Power-up Timer will be re-initialized. Once VDD
rather than pulling this pin directly to VSS. rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
Table 19-2 summarizes the registers associated with
BOR.
FIGURE 19-3: BROWN-OUT SITUATIONS

VDD
VBOR
Internal
Reset 64 ms(1)
VDD
VBOR
Internal < 64 ms
Reset 64 ms(1)
VDD
VBOR
Internal
Reset 64 ms(1)
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

PIC16F753/HV753
TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Register on
Page
PCON — — — — — — POR BOR 22

STATUS IRP RP1 RP0 TO PD Z DC C 15
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Shaded cells are not used by BOR.
19.3.5 TIME-OUT SEQUENCE 19.3.6 POWER CONTROL (PCON)

On power-up, the time-out sequence is as follows: REGISTER
• PWRT time-out is invoked after POR has expired. The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
• OST is activated after the PWRT time-out has
last.
expired.
Bit 0 is BOR (Brown-out). BOR is unknown on Power-
The total time-out will vary based on oscillator
on Reset. It must then be set by the user and checked
configuration and PWRTE bit status. For example, in EC
on subsequent Resets to see if BOR = 0, indicating that
mode with PWRTE bit erased (PWRT disabled), there
a Brown-out has occurred. The BOR Status bit is a
will be no time-out at all. Figure 19-4, Figure 19-5 and
“don’t care” and is not necessarily predictable if the
Figure 19-6 depict time-out sequences.
brown-out circuit is disabled (BOREN<1:0> = 00 in the
Since the time-outs occur from the POR pulse, if MCLR Configuration Word register).
is kept low long enough, the time-outs will expire. Then,
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
bringing MCLR high will begin execution immediately
Reset and unaffected otherwise. The user must write a
(see Figure 19-5). This is useful for testing purposes or
‘1’ to this bit following a Power-on Reset. On a subse-
to synchronize more than one PIC16F753/HV753
quent Reset, if POR is ‘0’, it will indicate that a Power-
device operating in parallel.
on Reset has occurred (i.e., VDD may have gone too
Table shows the Reset conditions for some special low).
registers, while Table 19-4 shows the Reset conditions
For more information, see Section 19.3.4 “Brown-out
for all the registers.
Reset (BOR)”.
FIGURE 19-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset

PIC16F753/HV753
FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset
FIGURE 19-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset

PIC16F753/HV753
TABLE 19-4: INITIALIZATION CONDITION FOR REGISTERS

Wake-up from Sleep through
MCLR Reset
Interrupt
Register Address Power-on Reset WDT Reset
Brown-out Reset(1)
WDT Time-out
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/ xxxx xxxx xxxx xxxx uuuu uuuu
100h/180h
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/ 0000 0000 0000 0000 PC + 1(3)
102h/182h
STATUS 03h/83h/ 0001 1xxx 000q quuu(4) uuuq quuu(4)
103h/183h
FSR 04h/84h/ xxxx xxxx uuuu uuuu uuuu uuuu
104h/184h
PORTA 05h --xx xxxx --uu uuuu --uu uuuu
IOCAF 08h --00 0000 --00 0000 --uu uuuu
PCLATH 0Ah/8Ah/ ---0 0000 ---0 0000 ---u uuuu
10Ah/18Ah
INTCON 0Bh/8Bh/ 0000 0000 0000 0000 uuuu uuuu(2)
10Bh/18Bh
PIR1 0Ch 00-- -0-0 00-- -0-0 uu-- -u-u(2)
PIR2 0Dh --00 -0-0 --00 -0-0 --uu -u-u(2)
TMR1L 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 10h xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 11h 0000 00-0 uuuu uu-u uuuu uu-u
T1GCON 12h 0000 0x00 0000 0x00 uuuu uuuu
CCPR1L(1) 13h xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H(1) 14h xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON(1) 15h --00 0000 --00 0000 --uu uuuu
ADRESL(1) 1Ch xxxx xxxx uuuu uuuu uuuu uuuu
ADRESH(1) 1Dh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0(1) 1Eh 0000 0000 0000 0000 uuuu uuuu
ADCON1(1) 1Fh -000 ---- -000 ---- -uuu ----
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h --11 1111 --11 1111 --uu uuuu
IOCAP 88h --00 0000 --00 0000 --uu uuuu
PIE1 8Ch 00-- -000 00-- -000 uu-- -uuu
PIE2 8Dh --00 -0-0 --00 -0-0 --uu -u-u
OSCCON 8Fh --01 -00- --uu -uu- --uu -uu-
FVRCON 90h 0000 ---- 0000 ---- uuuu ----
DACCON0 91h 000- -0-- 000- -0-- uuu- -u--
DACCON1 92h ---0 0000 ---0 0000 ---u uuuu
CM2CON0 9Bh 0000 0100 0000 0100 uuuu uuuu
CM2CON1 9Ch 0000 ---0 0000 ---0 uuuu ---u
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 19-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

PIC16F753/HV753
TABLE 19-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
MCLR Reset
Interrupt
Register Address Power-on Reset WDT Reset
Brown-out Reset(1)
WDT Time-out
CM1CON0 9Dh 0000 0100 0000 0100 uuuu uuuu
CM1CON1 9Eh 0000 ---0 0000 ---0 uuuu ---u
CMOUT 9Fh ---- --00 ---- --00 ---- --uu
LATA 105h --xx -xxx --uu -uuu --uu -uuu
IOCAN 108h --00 0000 --00 0000 --uu uuuu
WPUA 10Ch --00 0000 --00 0000 --uu uuuu
SLRCON0 10Dh ---- -0-0 ---- -0-0 ---- -u-u
(1, 5)
PCON 10Fh ---- --qq ---- --uu ---- --uu
TMR2 110h 0000 0000 0000 0000 uuuu uuuu
PR2 111h 1111 1111 1111 1111 uuuu uuuu
T2CON 112h -000 0000 -000 0000 -uuu uuuu
HLTMR1 113h 0000 0000 0000 0000 uuuu uuuu
HLTPR1 114h 1111 1111 1111 1111 uuuu uuuu
HLT1CON0 115h -000 0000 -000 0000 -uuu uuuu
HLT1CON1 116h ---0 0000 ---0 0000 ---u uuuu
ANSELA 185h --11 -111 --11 -111 --uu -uuu
APFCON 188h ---0 -000 ---0 -000 ---u -uuu
OSCTUNE 189h ---0 0000 ---u uuuu ---u uuuu
PMCON1 18Ch ---- -000 ---- -000 ---- -uuu
PMCON2 18Dh ---- ---- ---- ---- ---- ----
PMADRL 18Eh 0000 0000 0000 0000 uuuu uuuu
PMADRH 18Fh ---- --00 ---- --00 ---- --uu
PMDATL 190h 0000 0000 0000 0000 uuuu uuuu
PMDATH 191h --00 0000 --00 0000 --uu uuuu
COG1PH 192h ---- xxxx ---- uuuu ---- uuuu
COG1BLK 193h xxxx xxxx uuuu uuuu uuuu uuuu
COG1DB 194h xxxx xxxx uuuu uuuu uuuu uuuu
COG1CON0 195h 0000 0000 0000 0000 uuuu uuuu
COG1CON1 196h --00 0000 --00 0000 --uu uuuu
COG1ASD 197h 0000 0000 0000 0000 uuuu uuuu
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 19-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

PIC16F753/HV753
TABLE 19-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program Status PCON
Condition
Counter Register Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during Sleep 000h 0001 0uuu ---- --uu

WDT Reset 000h 0000 uuuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
(1)
Interrupt Wake-up from Sleep PC + 1 uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.

PIC16F753/HV753
19.4 Interrupts For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
The PIC16F753/HV753 has multiple sources of three or four instruction cycles. The exact latency
interrupt: depends upon when the interrupt event occurs (see
• External Interrupt (INT pin) Figure 19-8). The latency is the same for one or two-
• Interrupt-On-Change (IOC) Interrupts cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
• Timer0 Overflow Interrupt
determined by polling the interrupt flag bits. The
• Timer1 Overflow Interrupt interrupt flag bit(s) must be cleared in software before
• Timer2 Match Interrupt re-enabling interrupts to avoid multiple interrupt
• Hardware Limit Timer (HLT) Interrupt requests.
• Comparator Interrupt (C1/C2) Note 1: Individual interrupt flag bits are set,
• ADC Interrupt regardless of the status of their
• Complementary Output Generator (COG) corresponding mask bit or the GIE bit.
• CCP1 Interrupt 2: When an instruction that clears the GIE
• Flash Memory Self-Write bit is executed, any interrupts that were
The Interrupt Control register (INTCON) and Peripheral pending for execution in the next cycle
Interrupt Request Registers (PIRx) record individual are ignored. The interrupts, which were
interrupt requests in flag bits. The INTCON register ignored, are still pending to be serviced
also has individual and global interrupt enable bits. when the GIE bit is set again.
The Global Interrupt Enable bit, GIE of the INTCON For additional information on Timer1, Timer2,
register, enables (if set) all unmasked interrupts, or comparators, ADC, Enhanced CCP modules, refer to
disables (if cleared) all interrupts. Individual interrupts the respective peripheral section.
can be disabled through their corresponding enable
bits in the INTCON register and PIEx registers. GIE is 19.4.1 RA2/INT INTERRUPT
cleared on Reset. The external interrupt on the RA2/INT pin is edge-
When an interrupt is serviced, the following actions triggered; either on the rising edge if the INTEDG bit of
occur automatically: the OPTION register is set, or the falling edge, if the
INTEDG bit is clear. When a valid edge appears on the
• The GIE is cleared to disable any further interrupt. RA2/INT pin, the INTF bit of the INTCON register is set.
• The return address is pushed onto the stack. This interrupt can be disabled by clearing the INTE
• The PC is loaded with 0004h. control bit of the INTCON register. The INTF bit must
The Return from Interrupt instruction, RETFIE, exits be cleared by software in the Interrupt Service Routine
the interrupt routine, as well as sets the GIE bit, which before re-enabling this interrupt. The RA2/INT interrupt
re-enables unmasked interrupts. can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 19.7
The following interrupt flags are contained in the “Power-Down Mode (Sleep)” for details on Sleep and
INTCON register: Figure 19-10 for timing of wake-up from Sleep through
• INT Pin Interrupt RA2/INT interrupt.
• Interrupt-On-Change (IOC) Interrupts Note: The ANSEL register must be initialized to
• Timer0 Overflow Interrupt configure an analog channel as a digital
The peripheral interrupt flags are contained in the PIR1 input. Pins configured as analog inputs
and PIR2 registers. The corresponding interrupt enable will read ‘0’ and cannot generate an
bit is contained in the PIE1 and PIE2 registers. interrupt.
The following interrupt flags are contained in the PIR1
register:
• A/D Interrupt
• Comparator Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Enhanced CCP Interrupt

PIC16F753/HV753
19.4.2 TIMER0 INTERRUPT
An overflow (FFh  00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 6.0 “Timer0 Module”
for operation of the Timer0 module.
19.4.3 PORTA INTERRUPT-ON-CHANGE

An input change on PORTA sets the IOCIF bit of the
INTCON register. The interrupt can be enabled/
disabled by setting/clearing the IOCIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note: If a change on the I/O pin should occur
when any PORTA operation is being
executed, then the IOCIF interrupt flag
may not get set.
FIGURE 19-7: INTERRUPT LOGIC
T0IF Wake-up
T0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF Interrupt
(TMR1IF) PIR1<0> IOCIE to CPU
PEIE
PIRn<7>
PIEn<7> GIE

PIC16F753/HV753
FIGURE 19-8: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag (5) Interrupt Latency (2)
(INTCON reg.)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Dummy Cycle Dummy Cycle Inst (0004h)

Executed Inst (PC – 1) Inst (PC)
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 22.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 19-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register
on Page
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 45
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 45
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 45
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.

PIC16F753/HV753
19.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary holding registers W_TEMP and
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Figure 2-2). These 16 locations are
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in Example 19-1 can be used to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
Note: The PIC16F753/HV753 does not require
saving the PCLATH. However, if
computed GOTOs are used in both the ISR
and the main code, the PCLATH must be
saved and restored in the ISR.
EXAMPLE 19-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
19.6 Watchdog Timer (WDT) 19.6.1 WDT PERIOD

The Watchdog Timer is a free running timer, using The WDT has a nominal time-out period of 18 ms (with
LFINTOSC oscillator as its clock source. The WDT is no prescaler). The time-out periods vary with
enabled by setting the WDTE bit of the Configuration temperature, VDD and process variations from part to
Word (default setting). When WDTE is set, the part (see DC specs). If longer time-out periods are
LFINTOSC will always be enabled to provide a clock desired, a prescaler with a division ratio of up to 1:128
source to the WDT module. can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
During normal operation, a WDT time-out generates a
up to 2.3 seconds can be realized.
device Reset. If the device is in Sleep mode, a WDT
time-out causes the device to wake-up and continue The CLRWDT and SLEEP instructions clear the WDT
with normal operation. and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The WDT can be permanently disabled by
programming the Configuration bit, WDTE, as clear The TO bit in the STATUS register will be cleared upon
(Section 19.1 “Configuration Bits”). a Watchdog Timer time-out.

PIC16F753/HV753
19.6.2 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst-
case conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
FIGURE 19-9: WATCHDOG TIMER WITH SHARED PRESCALE BLOCK DIAGRAM
FOSC/4
Data Bus
0
8
1
Sync
1 2 TCY TMR0
Shared Prescale
T0CKI 0
pin 0
T0CS PSA Set Flag bit T0IF
T0SE 8-bit
on Overflow
Prescaler
1
PSA
8
PS<2:0> 1
Watchdog
WDT
Timer
Time-out
LFINTOSC
2 0
(Figure 4-1)
PSA
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.
2: WDTE bit is in the Configuration Word register.
TABLE 19-7: WDT STATUS

Conditions WDT
WDTE = 0
CLRWDT Command Cleared
Exit Sleep
TABLE 19-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Register on
Page

Legend: Shaded cells are not used by the Watchdog Timer.

PIC16F753/HV753
TABLE 19-9: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Register
on Page

CONFIG(1) 150
Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by Watchdog Timer.
Note 1: See Register 19-1 for operation of all Configuration Word register bits.

PIC16F753/HV753
19.7 Power-Down Mode (Sleep) When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
The Power-Down mode is entered by executing a wake-up through an interrupt event, the corresponding
SLEEP instruction. interrupt enable bit must be set (enabled). Wake-up is
If the Watchdog Timer is enabled: regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
• WDT will be cleared but keeps running
instruction after the SLEEP instruction. If the GIE bit is
• PD bit in the STATUS register is cleared set (enabled), the device executes the instruction after
• TO bit is set the SLEEP instruction, then branches to the interrupt
• Oscillator driver is turned off address (0004h). In cases where the execution of the
• I/O ports maintain the status they had before SLEEP instruction following SLEEP is not desirable, the user
was executed (driving high, low or high-impedance). should have a NOP after the SLEEP instruction.
For lowest current consumption in this mode, all I/O pins Note: If the global interrupts are disabled (GIE is
should be either at VDD or VSS, with no external circuitry cleared) and any interrupt source has both
drawing current from the I/O pin and the comparators, its interrupt enable bit and the correspond-
DAC and FVR should be disabled. I/O pins that are high- ing interrupt flag bits set, the device will
impedance inputs should be pulled high or low externally immediately wake-up from Sleep.
to avoid switching currents caused by floating inputs.
The WDT is cleared when the device wakes up from
The T0CKI input should also be at VDD or VSS for lowest
Sleep, regardless of the source of wake-up.
current consumption. The contribution from on-chip pull-
ups on PORTA should be considered.
19.7.2 WAKE-UP USING INTERRUPTS
The MCLR pin must be at a logic high level.
When global interrupts are disabled (GIE cleared) and
Note: It should be noted that a Reset generated any interrupt source has both its interrupt enable bit
by a WDT time-out does not drive MCLR and interrupt flag bit set, one of the following will occur:
pin low. • If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
19.7.1 WAKE-UP FROM SLEEP complete as a NOP. Therefore, the WDT and WDT
The device can wake-up from Sleep through one of the prescaler and postscaler (if enabled) will not be
following events: cleared, the TO bit will not be set and the PD bit
will not be cleared.
1. External Reset input on MCLR pin.
• If the interrupt occurs during or after the
2. Watchdog Timer wake-up.
execution of a SLEEP instruction, the device will
3. Interrupt from INT pin. Immediately wake-up from Sleep. The SLEEP
4. Interrupt-On-Change input change. instruction is executed. Therefore, the WDT and
5. Peripheral interrupt. WDT prescaler and postscaler (if enabled) will be
cleared, the TO bit will be set and the PD bit will
The first event will cause a device Reset. The other
be cleared.
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register Even if the flag bits were checked before executing a
can be used to determine the cause of device Reset. SLEEP instruction, it may be possible for flag bits to
The PD bit, which is set on power-up, is cleared when become set before the SLEEP instruction completes. To
Sleep is invoked. TO bit is cleared if WDT wake-up determine whether a SLEEP instruction executed, test
occurred. the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
The following peripheral interrupts can wake the device
from Sleep: To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction. See
1. Timer1 interrupt. Timer1 must be operating as
Figure 19-10 for more details.
an asynchronous counter.
2. CCP Capture mode interrupt.
3. A/D conversion (when A/D clock source is RC).
4. Comparator output changes state.
5. Interrupt-on-change.
6. External Interrupt from INT pin.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.

PIC16F753/HV753
FIGURE 19-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN
CLKOUT TIOSCST
INT pin
INTF flag
(INTCON reg.) Interrupt Latency (3)
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle
Executed Inst(PC – 1) Inst(0004h)
Note 1: HFINTOSC Oscillator mode assumed.

2: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.
19.8 Code Protection

If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note: The entire Flash program memory will be
erased when the code protection is turned
off. See the PIC16F753/HV753 Flash
Memory Programming Specification
(DS41686) for more information.
19.9 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant seven bits of the ID locations
are reported when using MPLAB® IDE.

PIC16F753/HV753
19.10 In-Circuit Serial Programming™
The PIC16F753/HV753 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with five connections for:
• clock
• data
• power
• ground
• programming voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a Program/Verify mode by
holding the ICSPDAT and ICSPCLK pins low, while
raising the MCLR (VPP) pin from VIL to VIHH. See the
PIC16F753/HV753 Flash Memory Programming
Specification (DS41686) for more information.
ICSPDAT becomes the programming data and
ICSPCLK becomes the programming clock. Both
ICSPDAT and ICSPCLK are Schmitt Trigger inputs in
Program/Verify mode.
A typical In-Circuit Serial Programming connection is
shown in Figure 19-11.
FIGURE 19-11: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector *
Signals PIC16F753/HV753
+5V VDD
0V VSS
VPP MCLR/VPP
CLK ICSPCLK
Data I/O ICSPDAT
* * *
To Normal
Connections
* Isolation devices (as required)
Note: To erase the device, VDD must be above

the Bulk Erase VDD minimum given in the
PIC16F753/HV753 Flash Memory
Programming Specification (DS41686).

PIC16F753/HV753
20.0 SHUNT REGULATOR An external current limiting resistor, RSER, located
between the unregulated supply, VUNREG, and the VDD
(PIC16HV753 ONLY) pin, drops the difference in voltage between VUNREG
The PIC16HV753 devices include a permanent internal and VDD. RSER must be between RMAX and RMIN as
5 volt (nominal) shunt regulator in parallel with the VDD defined by Equation 20-1.
pin. This eliminates the need for an external voltage
regulator in systems sourced by an unregulated supply. EQUATION 20-1: RSER LIMITING RESISTOR
All external devices connected directly to the VDD pin
will share the regulated supply voltage and contribute (VUMIN - 5V)
to the total VDD supply current (ILOAD). RMAX =
1.05 • (1 MA + ILOAD)
20.1 Regulator Operation

(VUMAX - 5V)
A shunt regulator generates a specific supply voltage RMIN =
0.95 • (50 MA)
by creating a voltage drop across a pass resistor RSER.
The voltage at the VDD pin of the microcontroller is
monitored and compared to an internal voltage refer- Where:
ence. The current through the resistor is then adjusted, RMAX = maximum value of RSER (ohms)
based on the result of the comparison, to produce a
RMIN = minimum value of RSER (ohms)
voltage drop equal to the difference between the supply
voltage VUNREG and the VDD of the microcontroller. VUMIN = minimum value of VUNREG
See Figure 20-1 for voltage regulator schematic. VUMAX = maximum value of VUNREG
VDD = regulated voltage (5V nominal)
FIGURE 20-1: SHUNT REGULATOR
ILOAD = maximum expected load current in mA
VUNREG including I/O pin currents and external
circuits connected to VDD.
ILOAD
ISUPPLY RSER 1.05 = compensation for +5% tolerance of RSER
VDD
0.95 = compensation for -5% tolerance of RSER
ISHUNT
CBYPASS Feedback
20.2 Regulator Considerations
VSS The supply voltage VUNREG and load current are not
constant. Therefore, the current range of the regulator
Device
is limited. Selecting a value for RSER must take these
three factors into consideration.
Since the regulator uses the band gap voltage as the
regulated voltage reference, this voltage reference is
permanently enabled in the PIC16HV753 devices.
The shunt regulator will still consume current when
below operating voltage range for the shunt regulator.
20.3 Design Considerations

For more information on using the shunt regulator and
managing current load, see Application Note AN1035,
Designing with HV Microcontrollers (DS01035).

PIC16F753/HV753
21.0 DEVELOPMENT SUPPORT 21.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

PIC16F753/HV753
21.2 MPLAB XC Compilers 21.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other related modules together
relocatable object files and archives to create an exe-
• Flexible creation of libraries with easy module
cutable file. MPLAB XC Compiler uses the assembler
listing, replacement, deletion and extraction
to produce its object file. Notable features of the
assembler include:
21.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
21.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

PIC16F753/HV753
21.6 MPLAB X SIM Software Simulator 21.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 21.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
21.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 21.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

PIC16F753/HV753
21.11 Demonstration/Development 21.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

PIC16F753/HV753
22.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)

Ambient temperature under bias..........................................................................................................-40° to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16HV753 ......................................................................................................... -0.3V to +6.5V
PIC16F753 ............................................................................................................. -0.3V to +6.5V
on MCLR ......................................................................................................................... -0.3V to +13.5V
on all other pins........................................................................................ ...............-0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C  TA  +85°C ............................................................................................................. 95 mA
-40°C  TA  +125°C ........................................................................................................... 95 mA
on VDD pin(1)
-40°C  TA  +85°C ............................................................................................................. 95 mA
-40°C  TA  +125°C ........................................................................................................... 95 mA
on RA1, RA4, RA5 .......................................................................................................................... 25 mA
on RC4, RC5................................................................................................................................... 50 mA
Clamp current, IK (VPIN < 0 or VPIN >VDD)20 mA
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characteristics. See Table 22-6 to calculate device specific
limitations.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

PIC16F753/HV753
22.1 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16F753
VDDMIN (FOSC  8 MHz) ........................................................................................................... +2.0V
VDDMIN (8 MHz FOSC  10 MHz)........................................................................................... +3.0V
VDDMAX (10 MHz FOSC  20 MHz)........................................................................................ +5.5V
PIC16HV753
VDDMIN (FOSC  8 MHz) ........................................................................................................... +2.0V
VDDMIN (8 MHz FOSC  10 MHz)........................................................................................... +3.0V
VDDMAX (10 MHz FOSC  20 MHz)........................................................................................ +5.0V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1: See Parameter D001, DS Characteristics: Supply Voltage.

PIC16F753/HV753
FIGURE 22-1: PIC16F753 VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.5
5.0
4.5
VDD (V)
4.0
3.5
3.0
2.5
2.0
0 8 10 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 22-2: PIC16HV753 VOLTAGE-FREQUENCY GRAPH,

-40°C TA +125°C
5.0
4.5
VDD (V)
4.0
3.5
3.0
2.5
2.0
0 8 10 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

PIC16F753/HV753
22.2 DC Characteristics
TABLE 22-1: SUPPLY VOLTAGE
PIC16F753 Standard Operating Conditions (unless otherwise stated)
PIC16HV753
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
D001 VDD Supply Voltage
VDDMIN VDDMAX
2.0 — 5.5 V FOSC  8 MHz
3.0 — 5.5 V FOSC  10 MHz
4.5 — 5.5 V FOSC 20 MHz
D001 2.0 — 5.0 V FOSC  8 MHz(2)
3.0 — 5.0 V FOSC  10 MHz(2)
4.5 — 5.0 V FOSC  20 MHz(2)
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002 1.5 — — V Device in Sleep mode
D003* VPOR VDD Start Voltage to ensure internal Power-on Reset signal
— 1.6 — V
D003 — 1.6 — V
D004* SVDD VDD Rise Rate to ensure VDD Rise Rate internal Power-on Reset signal
0.05 — — V/ms See Table for details.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: On the PIC16HV753, VDD is regulated by a Shunt Regulator and is dependent on series resistor
(connected between the unregulated supply voltage and the VDD pin) to limit the current to 50 mA. See
Section 20.0 “Shunt Regulator (PIC16HV753 Only)” for design requirements.

PIC16F753/HV753
TABLE 22-2: SUPPLY CURRENT (IDD)(1,2)

PIC16HV753
Param Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. 85°C 125°C VDD Note
(1, 2)
Supply Current (IDD)
D010 — 10 31 31 A 2.0 FOSC = 31 kHz
— 15 36 36 A 3.0 LFINTOSC mode
— 28 62 62 A 5.0
D010 — 75 158 158 A 2.0 FOSC = 31 kHz
— 151 192 192 A 3.0 LFINTOSC mode
— 201 385 385 A 4.5
D011 — 97 140 140 A 2.0 FOSC = 1 MHz
— 155 235 235 A 3.0 EC Oscillator mode
— 334 475 475 A 5.0
D011 — 135 225 225 A 2.0 FOSC = 1 MHz
— 395 595 595 A 4.5
D012 — 172 260 260 A 2.0 FOSC = 1 MHz
— 220 360 360 A 3.0 HFINTOSC mode
— 398 516 516 A 5.0

D012 — 210 338 338 A 2.0 FOSC = 1 MHz
— 334 432 432 A 3.0 HFINTOSC mode
— 461 680 680 A 4.5

D013 — 243 333 333 A 2.0 FOSC = 4 MHz
— 762 956 956 A 5.0
D013 — 261 385 385 A 2.0 FOSC = 4 MHz
— 710 1045 1045 A 4.5
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.

PIC16F753/HV753
TABLE 22-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC16HV753
Param Max. Max. Conditions

Device Characteristics Min. Typ† Units
No. 85°C 125°C VDD Note
(1, 2)
Supply Current (IDD)
D014 — 318 382 382 A 2.0 FOSC = 4 MHz
— 450 502 502 A 3.0 HFINTOSC mode
— 825 100 100 A 5.0
D014 — 330 485 485 A 2.0 FOSC = 4 MHz
— 526 658 658 A 3.0 HFINTOSC mode
— 775 980 980 A 4.5
D015 — 505 595 595 A 2.0 FOSC = 8 MHz
— 740 1200 1200 A 3.0 HFINTOSC mode
— 1.5 1.8 1.8 mA 5.0
D015 — 500 690 690 A 2.0 FOSC = 8 MHz
— 800 1100 1100 A 3.0 HFINTOSC mode
— 1.23 1.7 1.7 mA 4.5
D016 — 2.6 3.08 3.08 mA 4.5 FOSC = 20 MHz
— 2.97 3.53 3.53 mA 5.0 EC Oscillator mode
D016 — 2.6 3.3 3.3 mA 4.5 FOSC = 20 MHz
EC Oscillator mode
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.

PIC16F753/HV753
TABLE 22-3: POWER-DOWN CURRENTS (IPD) (1,2)

Standard Operating Conditions (unless otherwise stated)
PIC16F753
Sleep mode
PIC16HV753
Param Device Max. Max. Conditions

Min. Typ† Units
No. Characteristics 85°C 125°C VDD Note
Power-down Base Current (IPD) (2)
D020 — 0.05 0.50 3.50 A 2.0 WDT, BOR, Comparator, VREF and
— 0.15 1.00 4.00 A 3.0 T1OSC disabled
— 0.35 1.50 5.00 A 5.0
D020 — 70 130 140 A 2.0
— 140 175 185 A 3.0
— 175 230 250 A 4.5
(2, 3)
Power-down Base Current (IPD)
D021 — 0.96 1.30 3.72 A 2.0 WDT Current(1)
— 1.05 2.10 6.50 A 3.0
— 1.87 2.92 6.86 A 5.0
D021 — 66 127 141 A 2.0
— 137 172 176 A 3.0
— 176 228 233 A 4.5
D022 — 4 7 10 A 3.0 BOR Current(1)
— 5 8 11 A 5.0
D022 — 140 175 180 A 3.0
— 178 230 236 A 4.5
D023 — 160 345 375 A 2.0 CxSP = 1, Comparator Current(1),
— 180 370 405 A 3.0 single comparator enabled
— 220 410 445 A 5.0
D023 — 225 380 380 A 2.0
— 250 420 420 A 3.0
— 381 500 500 A 4.5
D024 — 50 105 115 A 2.0 CxSP = 0, Comparator Current(1),
— 55 110 120 A 3.0 single comparator enabled
— 70 120 132 A 5.0
D024 — 115 200 200 A 2.0
— 150 220 220 A 3.0
— 240 277 277 A 4.5
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max values
should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: Shunt regulator is always ON and always draws operating current.

PIC16F753/HV753
TABLE 22-3: POWER-DOWN CURRENTS (IPD) (CONTINUED)(1,2)
PIC16F753
Sleep mode
PIC16HV753
Param Device Max. Max. Conditions

Min. Typ† Units
No. Characteristics 85°C 125°C VDD Note
Power-down Base Current (IPD)(2, 3)
D025 — 0.10 0.41 3.51 A 3.0 A/D Current(1), no conversion in
— 0.12 0.55 4.41 A 5.0 progress
D025 — 145 171 175 A 3.0
— 185 226 231 A 4.5
D026 — 20 37 37 A 2.0 DAC Current(1)
— 30 46 46 A 3.0
— 50 76 76 A 5.0
D026 — 85 155 155 A 2.0
— 165 213 213 A 3.0
— 215 284 284 A 4.5
D027 — 115 185 203 A 2.0 FVR Current(1), FVRBUFEN = 1,
— 120 193 219 A 3.0 FVROUT buffer enabled
— 125 196 224 A 5.0
D027 — 65 126 145 A 2.0
— 136 171 182 A 3.0
— 175 226 231 A 4.5
D028 — 1 2 4 A 2.0 T1OSC Current,
— 2 3 5 A 3.0 TMR1CS <1:0> = 11
— 9 20 21 A 5.0
D028 — 65 126 140 A 2.0
— 136 172 180 A 3.0
— 175 228 235 A 4.5
D029 — 140 258 265 A 2.0 Op-Amp Current(1)
— 155 326 340 A 3.0
— 165 421 422 A 5.0
D029 — 140 260 265 A 2.0
— 155 325 340 A 3.0
— 165 400 410 A 4.5
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max values
should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: Shunt regulator is always ON and always draws operating current.

PIC16F753/HV753
TABLE 22-4: I/O PORTS

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param
No.
VIL Input Low Voltage
I/O PORT:
D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D030A — — 0.15 VDD V 2.0V  VDD  4.5V
D031 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
VIH Input High Voltage
I/O PORT:
D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D040A 0.25 VDD + 0.8 — — V 2.0V  VDD  4.5V
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
D042 MCLR 0.8 VDD — — V
(1)
IIL Input Leakage Current
D060 I/O ports — 0.1 1 A VSS VPIN VDD,
Pin at high-impedance, 85°C
D061 RA3/MCLR(2) — 0.7 5 A VSS VPIN VDD,
Pin at high-impedance, 85°C
D063 — 0.1 5 A EC Configuration
(3)
IPUR Weak Pull-up Current
D070* 50 250 400 A VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage
D080 I/O Ports (excluding RC4, RC5) — — 0.6 V IOL = 7 mA, VDD = 4.5V
-40°C TA +125°C
IOL = 8.5 mA, VDD = 4.5V
-40°C TA +85°C
I/O Ports RC4 and RC5 — — 0.6 V IOL = 14 mA, VDD = 4.5V
-40°C TA +125°C
IOL = 17 mA, VDD = 4.5V
-40°C TA +85°C
VOH Output High Voltage
D090 I/O Ports (excluding RC4, RC5) VDD-0.7 — — V IOH = -2.5 mA, VDD = 4.5V
-40°C TA +125°C
IOH = -3 mA, VDD = 4.5V
-40°C TA +85°C
I/O Ports RC4 and RC5 VDD-0.7 — — V IOH = -5 mA, VDD = 4.5V
-40°C TA +125°C
IOH = -6 mA, VDD = 4.5V
-40°C TA +85°C
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: This specification applies to all weak pull-up pins, including the weak pull-up found on RA3/MCLR. When RA3/MCLR is
configured as MCLR Reset pin, the weak pull-up is always enabled.

PIC16F753/HV753
TABLE 22-4: I/O PORTS (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param
No.
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS, LP modes when
D101A* CIO All I/O pins — — 50 pF external clock is used to drive
OSC1
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: This specification applies to all weak pull-up pins, including the weak pull-up found on RA3/MCLR. When RA3/MCLR is
configured as MCLR Reset pin, the weak pull-up is always enabled.
TABLE 22-5: MEMORY PROGRAMMING SPECIFICATIONS

Param.
No.
Program Memory
Programming Specifications
D110 VIHH Voltage on MCLR/VPP pin 10.0 — 13.0 V (Note 2)
D112 VBE VDD for Bulk Erase 4.5 — VDDMAX V
D113 VPEW VDD for Write or Row Erase 4.5 — VDDMAX V
D114 IPPPGM Current on MCLR/VPP during — 300 1000 A
Erase/Write
Program Flash Memory
D121 EP Cell Endurance 10K 100K — E/W -40C  TA +85C
(Note 1)
D121A EP Cell Endurance 1K 10K — E/W -40C  TA +125C
(Note 1)
D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention 40 — — Year Provided no other
specifications are violated
D125 EHEFC High-Endurance Flash Cell N/A — — E/W 0°C to +60°C, Lower byte
last 128 addresses
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.

PIC16F753/HV753
TABLE 0-2: OPERATIONAL AMPLIFIER (OPA) MODULE

Param
Symbol Parameters Min. Typ† Max. Units Conditions
No.
OPA01* VOS Input Offset Voltage — ±8 ±15 mV
OPA02* IB Input Bias Current — ±2 — nA
OPA03* IOS Input Offset Bias Current — ±1 — pA
OPA04* VCM Common Mode Input Range VSS — VDD - 1.4 V
OPA05* CMR Common Mode Rejection Ratio 60 70 ±5 dB
OPA06* AOL DC Open Loop Gain — — — dB
OPA07* VOUT Output Voltage Swing VSS - 50 — VSS + 50 mV
OPA08* ISC Output Short Circuit Current — 10 15 mA
OPA10* PSR Power Supply Rejection — 60 — dB
Note 1: See Section 23.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20mV.
3: Input offset voltage is measured with one comparator input at (VDD - 1.5V)/2.

PIC16F753/HV753
TABLE 22-6: THERMAL CHARACTERISTICS

Param
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to Ambient 84.6 °C/W 8-pin PDIP package
149.5 °C/W 8-pin SOIC package
60 °C/W 8-pin DFN 3x3mm package
TH02 JC Thermal Resistance Junction to Case 41.2 °C/W 8-pin PDIP package
39.9 °C/W 8-pin SOIC package
9 °C/W 8-pin DFN 3x3mm package
TH03 TJMAX Maximum Junction Temperature 150 °C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD
- VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient temperature; TJ = Junction Temperature

PIC16F753/HV753
22.3 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O Port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-Impedance) V Valid
L Low Z High-Impedance
FIGURE 22-3: LOAD CONDITIONS
Load Condition
Pin CL
VSS
Note: CL = 50 pF for all pins.

PIC16F753/HV753
22.4 AC Characteristics: PIC16F753/HV753 (Industrial, Extended)
FIGURE 22-4: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
CLKIN
OS02
OS04 OS04
OS03
CLKOUT
CLKOUT
(CLKOUT Mode)
TABLE 22-7: CLOCK OSCILLATOR TIMING REQUIREMENTS

Param
No.
OS01 FOSC External CLKIN Frequency(1) DC — 20 MHz EC Oscillator mode
OS02 TOSC External CLKIN Period(1) 50 —  ns EC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC16F753/HV753
TABLE 22-8: OSCILLATOR PARAMETERS

Param Freq.
No. Tolerance
OS06 TWARM Internal Oscillator Switch when — — — 2 TOSC
running
OS07 INTOSC Internal Calibrated 1% 3.96 4.0 4.04 MHz VDD = 3.5V, TA = 25°C
INTOSC Frequency(1) 2% 3.92 4.0 4.08 MHz 2.5V VDD  5.5V,
(4 MHz) 0°C  TA  +85°C
5% 3.80 4.0 4.20 MHz 2.0V VDD  5.5V,
-40°C  TA  +85°C (Ind.),
-40°C  TA  +125°C (Ext.)
OS08 HFOSC Internal Calibrated 1% 7.92 8 8.08 MHz VDD = 3.5V, TA = 25°C
HFINTOSC Frequency(1) 2% 7.84 8 8.16 MHz 2.5V VDD  5.5V,
0°C  TA  +85°C
5% 7.60 8 8.40 MHz 2.0V VDD  5.5V,
-40°C  TA  +85°C (Ind.),
-40°C  TA  +125°C (Ext.)
OS09 LFOSC Internal LFINTOSC — — 31 — kHz
Frequency
OS10* TIOSC ST HFINTOSC Wake-up from — — 12 24 s VDD = 2.0V -40°C  TA  +85°C
Sleep Start-up Time — 7 14 s VDD = 3.0V -40°C  TA  +85°C
— 6 11 s VDD = 5.0V -40°C  TA  +85°C
not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.

PIC16F753/HV753
FIGURE 22-5: CLKOUT AND I/O TIMING
Cycle Write Fetch Read Execute
Q4 Q1 Q2 Q3
FOSC
OS20
CLKOUT OS21
OS19 OS18
OS16
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin New Value

Old Value
(Output)
OS18, OS19
TABLE 22-9: CLKOUT AND I/O TIMING PARAMETERS

Param Typ Unit

Sym. Characteristic Min. Max. Conditions
No. † s
OS13 TCKL2IOV CLKOUT to Port out valid(1) — — 20 ns
OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TOSH2IOV FOSC (Q1 cycle) to Port out valid — 50 70* ns VDD =5.0V
OS16 TOSH2IOI FOSC (Q2 cycle) to Port input invalid 50 — — ns VDD =5.0V
(I/O in setup time)
OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18* TIOR Port output rise time — 40 72 ns VDD =2.0V
— 15 32 ns VDD =5.0V
OS19* TIOF Port output fall time — 28 55 ns VDD =2.0V
— 15 30 ns VDD =5.0V
OS20* TINP INT pin input high or low time 25 — — ns
OS21* TIOC Interrupt-on-change new input level TCY — — ns
time
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

PIC16F753/HV753
FIGURE 22-6: RESET, WATCHDOG TIMER AND POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note: Asserted low.
FIGURE 22-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR + VHYST
VBOR
(Device in Brown-out Reset) (Device not in Brown-out Reset)
37
Reset
33*
(due to BOR)
* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.

PIC16F753/HV753
TABLE 22-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Param Unit
Sym. Characteristic Min. Typ† Max. Conditions
No. s
30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C

5 — — s VDD = 5V, -40°C to +125°C
31 TWDTLP Low-Power Watchdog Timer 10 20 30 ms VDD = 5V, -40°C to +85°C
Time-out Period 10 20 35 ms VDD = 5V, -40°C to +125°C
32* TPWRT Power-up Timer Period, 40 65 140 ms
PWRTE = 0 (No Prescaler)
33* TIOZ I/O high impedance from — — 2.0 s
MCLR Low or Watchdog Timer
Reset
34 VBOR Brown-out Reset Voltage (1) 2 2.15 2.3 V
35* VHYST Brown-out Reset Hysteresis — 100 — mV -40°C  TA  +85°C
36* TBOR Brown-out Reset DC Minimum — 100 — s VDD  VBOR
Detection Period
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device
as possible. 0.1 F and 0.01 F values in parallel are recommended.

PIC16F753/HV753
FIGURE 22-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
TABLE 22-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale
20 or TCY + 40 value
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale
Period 30 or TCY + 40 value
N
49* TCKEZT- Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
MR1 Increment mode
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

PIC16F753/HV753
FIGURE 22-9: PIC16F753/HV753 CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP1
(Capture mode)
CC01 CC02
CC03
Note: Refer to Figure 22-3 for load conditions.
TABLE 22-12: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Param
No.
CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns
CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns
CC03* TccP CCP1 Input Period 3TCY + 40 — — ns N = prescale
N value (1, 4 or
16)
TABLE 22-13: COMPARATOR SPECIFICATIONS(1)

VDD = 5.0V, -40°C  TA  +125°C
Param
Sym. Characteristics Min. Typ† Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage(3) —  10  20 mV CxSP = 1
 10  20 mV CxSP = 0
CM02 VICM Input Common Mode Voltage(2) 0 — VDD – 1.5 V
CM03 CMRR Common Mode Rejection Ratio — 55 — dB
CM04A* TRT(2) Response Time — 55 70 ns CxSP = 1
— 65 100 ns CxSP = 0
CM05* TMC20V Comparator Mode Change to Output Valid — — 10 s
CM06 CHYSTER Comparator Hysteresis — 20 50 mV
Note 1: See Section 23.0 “DC and AC Characteristics Graphs and Charts”and Section 22.0 “Electrical
Specifications” for operating characterization.
2: Response time is measured with one comparator input at (VDD - 1.5V)/2 - 100 mV to (VDD - 1.5V)/
2 + 20 mV. The other input is at (VDD -1.5V)/2.
3: Input offset voltage is measured with one comparator input at (VDD - 1.5V)/2.

PIC16F753/HV753
TABLE 22-14: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1)

VDD = 3.0V, TA = 25°C
Param
Sym. Characteristics Min. Typ† Max. Units Comments
No.
DAC01* CLSB Step Size — VDD/512 — V
DAC02 CACC Absolute Accuracy —  1/2 2 LSb
DAC03* CR Unit Resistor Value (R) — 5K — 
DAC04* CST Settling Time (2)
— — 10 s
Note 1: See Section 23.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
TABLE 22-15: FIXED VOLTAGE REFERENCE SPECIFICATIONS

VDD = 3.0V, TA = 25°C
Param
Symbol Characteristics Min. Typ. Max. Units Comments
No.
VR01* VFVR FVR Voltage Output 1.128 1.2 1.272 V
VR02* TSTABLE FVR Turn On Time — 200 — s
TABLE 22-16: SHUNT REGULATOR SPECIFICATIONS (PIC16HV753 only)

VDD = 3.0V, TA = 25°C
Param
Symbol Characteristics Min. Typ. Max. Units Comments
No.
SR01 VSHUNT Shunt Voltage 4.75 5 5.5 V
4.70 5 5.5 V TA = -40°C
SR02 ISHUNT Shunt Current 1 — 50 mA
SR03* TSETTLE Settling Time — — 150 ns To 1% of final value
SR04 CLOAD Load Capacitance 0.01 — 10 F Bypass capacitor on VDD
pin
SR05 ISNT Regulator operating current — 180 — A Includes band gap
reference current

PIC16F753/HV753
TABLE 22-17: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3)
VDD = 3.0V, TA = 25°C
Param Unit
Sym. Characteristic Min. Typ† Max. Conditions
No. s
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — — 1 LSb VREF = 3.0V
AD03 EDL Differential Error — — 1 LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — 1.5 3.0 LSb VREF = 3.0V
AD05 EGN Gain Error — — 1.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage 2.2 — — V Absolute minimum to ensure 1 LSb
2.5 — VDD accuracy
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended — — 10 k Can go higher if external 0.01 F
Impedance of Analog capacitor is present on input pin.
Voltage Source
AD09* IREF VREF Input Current 10 — 1000 A During VAIN acquisition.
Based on differential of VHOLD to
VAIN.
— — 50 A During A/D conversion cycle.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: See Section 23.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

PIC16F753/HV753
TABLE 22-18: ADC CONVERSION REQUIREMENTS

VDD = 3.0V, TA = 25°C
Param
No.
AD130 TAD ADC Internal FRC 3.0 6.0 9.0 s At VDD = 2.5V
* Oscillator Period
1.6 4.0 6.0 s At VDD = 5.0V
ADC Clock Period 1.6 — 9.0 s FOSC-based, VREF 3.0V
3.0 — 9.0 s TOSC-based, VREF full range(2)
AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to conversion
(not including complete
Acquisition Time)(1)
AD132 TACQ Acquisition Time — 11.5 — s
*
AD133 TAMP Amplifier Settling — — 5 s
* Time
AD134 TGO Q4 to A/D Clock Start — TOSC/2 — —
THCD Holding Capacitor — 1/2 TAD — — FOSC-based
Disconnect Time — 1/2 TAD + 1 — ADCS<2:0> = x11 (ADC FRC mode)
TCY
Note 1: The ADRES register may be read on the following TCY cycle. See Section 12.4 “A/D Acquisition
Requirements” for minimum conditions.
2: Full range for PIC16HV753 powered by the shunt regulator is the 5V regulated voltage.
FIGURE 22-10: PIC16F753/HV753 A/D CONVERSION TIMING (ADC CLOCK FOSC-BASED)
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2)
AD131
Q4
AD130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 TCY
GO DONE
Sampling Stopped
AD132
Sample

PIC16F753/HV753
FIGURE 22-11: PIC16F753/HV753 A/D CONVERSION TIMING (ADC CLOCK FROM FRC)
BSF ADCON0, GO
AD134 (TOSC/2 + TCY) 1 TCY
AD131
Q4
AD130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 TCY
GO DONE
Sampling Stopped
AD132
Sample
TABLE 22-19: OPERATIONAL AMPLIFIER (OPA)

Standard Operating Conditions (unless otherwise stated):
DC CHARACTERISTICS
VDD = 3.0 Temperature 25°C, High-Power Mode
Param
Symbol Parameters Min. Typ† Max. Units Conditions
No.
OPA12 GBWP Gain Bandwidth Product — 3 — MHz
OPA13* TON Turn on Time — — 10 s
OPA14* PM Phase Margin — 60 — degrees
OPA15* SR Slew Rate 2 — — V/s
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min”
values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle
time limit is “DC” (no clock) for all devices.

PIC16F753/HV753
23.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.

PIC16F753/HV753
FIGURE 23-1: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16HV753 ONLY
300
250 Typical: 25°C 4 MHz
200
IDD (µA)
150
100
1 MHz
50
0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-2: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16HV753 ONLY

300
Max: 85°C + 3ı 4 MHz

250
200
IDD (µA)
150
100
1 MHz
50
0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)

PIC16F753/HV753
FIGURE 23-3: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F753 ONLY
350
4 MHz
300 Typical: 25°C
250
IDD (µA)
200
150 1 MHz
100
50
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 23-4: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F753 ONLY
400
350 Max: 85°C + 3ı 4 MHz
300
250
IDD (µA)
200
1 MHz
150
100
50
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-5: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16HV753 ONLY
2.5
Typical: 25°C 20 MHz

2.0
1.5
IDD (mA)
1.0
4 MHz
0.5 1 MHz
0.0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-6: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16HV753 ONLY
2.5
Max: 85°C + 3ı 20 MHz

2.0
1.5
IDD (mA)
1.0 4 MHz
0.5
1 MHz
0.0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)

PIC16F753/HV753
FIGURE 23-7: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16F753 ONLY
2.5
Typical: 25°C
2.0 20 MHz
1.5
IDD (mA)
1.0
4 MHz
0.5
1 MHz
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 23-8: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16F753 ONLY
2.5
Max: 85°C + 3ı 20 MHz

2.0
1.5
IDD (mA)
4 MHz
1.0
0.5 1 MHz
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-9: IDD, LFINTOSC, FOSC = 31 kHz, PIC16HV753 ONLY
350
Max.
300 Max: 85°C + 3ı
Typical: 25°C
250
Typical
IDD (µA)
200
150
100
50
0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-10: IDD, LFINTOSC, FOSC = 31 kHz, PIC16F753 ONLY
60
Max: 85°C + 3ı Max.

50 Typical: 25°C
40
IDD (µA)
Typical
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-11: IDD TYPICAL, HFINTOSC, PIC16HV753 ONLY
1.4
1.2 Typical: 25°C 8 MHz
1.0
IDD (mA)
0.8 4 MHz
0.6
1 MHz
0.4
0.2
0.0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-12: IDD MAXIMUM, HFINTOSC, PIC16HV753 ONLY
1.6
1.4 Max: 85°C + 3ı 8 MHz
1.2
1.0
4 MHz
IDD (mA)
0.8
1 MHz
0.6
0.4
0.2
0.0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)

PIC16F753/HV753
FIGURE 23-13: IDD MAXIMUM, HFINTOSC, PIC16F753 ONLY
1.6
1.4 Max: 85°C + 3ı 16 MHz
1.2
1.0
8 MHz
IDD (mA)
0.8 4 MHz
2 MHz
0.6 1 MHz
0.4
0.2
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-14: IPD BASE, LOW-POWER SLEEP MODE, PIC16HV753 ONLY
250
Max.
Max: 85°C + 3ı
200
Typical: 25°C
Typical
150
(nA)
IPD (nA
100
50
0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-15: IPD BASE, LOW-POWER SLEEP MODE, PIC16F753 ONLY
0.8
0.7 Max: 85°C + 3ı Max.

Typical: 25°C
0.6
0.5
(µA)
IPD (µA
0.4
0.3 Typical
0.2
0.1
0.0
15
1.5 2
2.0
0 2
2.5
5 3
3.0
0 3
3.5
5 4
4.0
0 4
4.5
5 5
5.0
0 5
5.5
5 6
6.0
0
VDD (V)

PIC16F753/HV753
FIGURE 23-16: IPD, WATCHDOG TIMER (WDT), PIC16HV753 ONLY
250

Typical: 25°C
200
Typical
150
IPD (µA)
100
50
0
1 6
1.6 2 0
2.0 2 4
2.4 2 8
2.8 3 2
3.2 3 6
3.6 4 0
4.0 4 4
4.4 4 8
4.8
VDD (V)
FIGURE 23-17: IPD, WATCHDOG TIMER (WDT), PIC16F753 ONLY
3.5
3.0 Max: 85°C + 3ı

Typical: 25°C
Max.
2.5
(µA)
2.0
IPD (µA
Typical
1.5
15
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-18: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16HV753 ONLY
250
Max: 85°C + 3ı
Max.
Typical: 25°C
200
150 Typical
IPD (µA)
100
50
0
1.6
16 2.0
2 0 2.4
2 4 2.8
2 8 3.2
3 2 3.6
3 6 4.0
4 0 4.4
4 4 4.8
4 8
VDD (V)
FIGURE 23-19: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F753 ONLY
175
Max.
150
125
(µA)
IPD (µA
Typical
100
75 Max: 85°C + 3ı
Typical: 25 C
25°C
50
15
1.5 2 0
2.0 2 5
2.5 3 0
3.0 3 5
3.5 4 0
4.0 4 5
4.5 5 0
5.0 5 5
5.5 6 0
6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-20: IPD, BROWN-OUT RESET (BOR), PIC16HV753 ONLY
250
225 Max: 85°C + 3ı Max.

Typical: 25°C
200
Typical
175
IPD ((µA)
150
125
100
75
50
24
2.4 2 6
2.6 2 8
2.8 3 0
3.0 3 2
3.2 3 4
3.4 3 6
3.6 3 8
3.8 4 0
4.0 4 2
4.2 4 4
4.4 4 6
4.6
VDD (V)
FIGURE 23-21: IPD, BROWN-OUT RESET (BOR), PIC16F753 ONLY
6
Max: 85°C + 3ı
Typical: 25°C Max
Max.
5
IPD (µA)
4 Typical
2
2 0
2.0 2 5
2.5 3 0
3.0 3 5
3.5 4 0
4.0 4 5
4.5 5 0
5.0 5 5
5.5 6 0
6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-22: IPD, DAC, PIC16HV753 ONLY
300

250 Typical: 25°C
200
Typical
(µA)
IPD (µA
150
100
50
0
1 6
1.6 2 0
2.0 2 4
2.4 2 8
2.8 3 2
3.2 3 6
3.6 4 0
4.0 4 4
4.4 4 8
4.8
VDD (V)
FIGURE 23-23: IPD, DAC, PIC16F753 ONLY
80
Max: 85°C + 3ı
70 Typical: 25°C Max.
60
Typical
50
(µA)
IDD (µA
40
30
20
10
0
1 5
1.5 2 0
2.0 2 5
2.5 3 0
3.0 3 5
3.5 4 0
4.0 4 5
4.5 5 0
5.0 5 5
5.5 6 0
6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-24: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16HV753 ONLY
250

Typical: 25°C
200
150 Typical
(µA)
IPD (µA
100
50
0
1 6
1.6 2 0
2.0 2 4
2.4 2 8
2.8 3 2
3.2 3 6
3.6 4 0
4.0 4 4
4.4 4 8
4.8
VDD (V)
FIGURE 23-25: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16F753 ONLY
20
Max: 85°C + 3ı
Typical: 25°C Max.
15
Typical
IPD (µA)
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-26: IPD, OP AMP, PIC16HV753 ONLY
350
Max: 85°C + 3
M 3ı
250
200
IPD(µA)
Typical
150
100
50
0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-27: IPD, OP AMP, PIC16F753 ONLY
350
Max: 8
M 85°C
°C + 3
3ı Max.
300 Typical: 25°C
250
200
(µA)
Typical
IPD (µA
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-28: IPD, ADC NO CONVERSION IN PROGRESS, PIC16HV753 ONLY
250

Typical: 25°C
200
Typical
150
IPD (µA)
100
50
0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-29: IPD, ADC NO CONVERSION IN PROGRESS, PIC16F753 ONLY
0.8
0.7 Max: 85°C + 3ı

Typical: 25°C
0.6 Max.
0.5
IPD (µA)
0.4
0.3
0.2 Typical
0.1
0.0
15
1.5 2
2.0
0 2
2.5
5 3
3.0
0 3
3.5
5 4
4.0
0 4
4.5
5 5
5.0
0 5
5.5
5 6
6.0
0
VDD (V)

PIC16F753/HV753
FIGURE 23-30: IPD, COMPARATOR, LOW-POWER MODE, PIC16HV753 ONLY
100
Max: 85°C + 3ı
Typical: 25°C Max.
80
Typical
(µA)
60
IPD (µ
40
20
0
1 6
1.6 2 0
2.0 2 4
2.4 2 8
2.8 3 2
3.2 3 6
3.6 4 0
4.0 4 4
4.4 4 8
4.8
VDD (V)
FIGURE 23-31: IPD, COMPARATOR, LOW-POWER MODE, PIC16F753 ONLY
120
Max: 85°C + 3
M 3ı
Typical: 25°C Max.
100
80
Typical
(µA)
IPD (µA
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
FIGURE 23-32: IPD, COMPARATOR, HIGH-POWER MODE, PIC16HV753 ONLY
350
Max 85°C + 3
M 3ı
Typical: 25°C
300 85°C
250
(µA)
IPD (µA
200
25°C
150
100
50
0
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
VDD (V)
FIGURE 23-33: IPD, COMPARATOR, HIGH-POWER MODE, PIC16F753 ONLY
400
Max: 85°C + 3ı
300
250
Typical
(µA)
IPD (µA
200
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16F753/HV753
24.0 PACKAGING INFORMATION
24.1 Package Marking Information
14-Lead PDIP (300 mil) Example
PIC16F753
-I/P
1306017
14-Lead SOIC (3.90 mm) Example
PIC16F753
-I/SL
1306017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3)
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.

PIC16F753/HV753
24.2 Package Marking Information
14-Lead TSSOP (4.4 mm) Example
XXXXXXXX 753/ST
YYWW 1306
NNN 017
16-Lead QFN (4x4x0.9 mm) Example
PIC16
PIN 1 PIN 1
F753
-I/ML
306017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3)
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.

PIC16F753/HV753
24.3 Package Details
The following sections give the technical details of the packages.

3 % & %! % 4" ) ' % 4 $% %"%
%% 255)))& &5 4
NOTE 1
E1
1 2 3
A A2
L c
A1
b1
b e eB
6% 7+8-
& 9&% 7 7: ;
7!&( $ 7
% 1+
% % < <
""4 4 0 , 0
1 % % 0 < <
!" % !" ="% - , ,0
""4="% - 0 >
: 9% ,0 0 0
% % 9 0 , 0
9" 4 > 0
6 9"="% ( 0 ?
9 ) 9"="% ( >
: ) * 1 < < ,

!"#$%! & '(!%&! %( %")% % % "
*$%+ % %
, & "-" %!"& "$ % ! "$ % ! %#". "
& "% -/0
1+21 & %#%! ))% !%%
) +01

PIC16F753/HV753
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

PIC16F753/HV753

PIC16F753/HV753
3 % & %! % 4" ) ' % 4 $% %"%
%% 255)))& &5 4

PIC16F753/HV753

PIC16F753/HV753

PIC16F753/HV753

PIC16F753/HV753
! " # $ %& ' (()* "#

3 % & %! % 4" ) ' % 4 $% %"%
%% 255)))& &5 4
D D2
EXPOSED
PAD
E E2
2 2 b
1 1
K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW
A A3
A1
6% 99- -

& 9&% 7 7: ;
7!&( $ 7 ?
% ?01+
: 8 % >
%" $$ 0
+ %% 4 , -3
: ="% - 1+
-# ""="% - 0 ?0 >
: 9% 1+
-# ""9% 0 ?0 >
+ %%="% ( 0 , ,0
+ %%9% 9 , 0
+ %%% -# "" V < <

!"#$%! & '(!%&! %( %")% % % "
4 ) !%"
, & "% -/0
1+2 1 & %#%! ))% !%%
-32 $ & '! !)% !%% '$ $ &% !
) +1

PIC16F753/HV753

PIC16F753/HV753
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (05/2013)
Original release of this document.
Revision B (11/2013)
Electrical Specification chapter updated,
Characterization Data chapter updated. Miscellaneous
corrections to the following chapters: Device Overview,
Memory Organization, I/O Ports, COG Module, Fixed
Voltage Reference (FVR), Slope Compensation (SC)
Module.
Revision C (03/2015)
Updated Figures 2-2, 13-1, 14-1, 17-1, and 17-2;
Registers 5-11, 5-12, 11-11, and 11-12; Sections 5.5.4
and 22.0; Table 1-1, 22-3, 22-4, 22-15, and 22-17.
Revision D (06/2016)
Updated the ‘eXtreme Low-Power (XLP) Features’
section; Other minor corrections.

PIC16F753/HV753
THE MICROCHIP WEBSITE CUSTOMER SUPPORT
Microchip provides online support via our website at Users of Microchip products can receive assistance
www.microchip.com. This website is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the website contains the following information:
• Field Application Engineer (FAE)
• Product Support – Data sheets and errata,
• Technical Support
application notes and sample programs, design
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or Field Application Engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the website
program member listing at: http://www.microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

PIC16F753/HV753
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX

Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16F753-I/ML301
Option Range Tape and Reel,
Industrial temperature,
QFN 4x43 package,
QTP pattern #301
Device: PIC16F753 b) PIC16F753-E/P
PIC16HV753 Extended temperature
PDIP package
c) PIC16F753-E/SL
Tape and Reel Blank = Standard packaging (tube or tray) Extended temperature,
Option: T = Tape and Reel(1) SOIC package
d) PIC16HV753-E/ST
Extended temperature,
Temperature I = -40C to +85C (Industrial) TSSOP 4.4 mm package
Range: E = -40C to +125C (Extended)
Package: P = 14-lead Plastic Dual In-line (PDIP)

SL = 14-lead Plastic Small Outline (3.90 mm) (SOIC) Note 1: Tape and Reel identifier only appears in the
ST = 14-lead Plastic Thin Shrink Small Outline catalog part number description. This
(4.4 mm) (TSSOP) identifier is used for ordering purposes and is
ML = 16-lead Plastic Quad Flat, No Lead Package not printed on the device package. Check
(4x4x0.9 mm) (QFN) with your Microchip Sales Office for package
availability with the Tape and Reel option.
Pattern: QTP, SQTP, Code or Special Requirements

(blank otherwise)

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate,
and may be superseded by updates. It is your responsibility to
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
ensure that your application meets with your specifications. KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MICROCHIP MAKES NO REPRESENTATIONS OR MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology
OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company,
FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load,
arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated
the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A.
hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of
Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries.
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademarks of Microchip Technology
devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM © 2013-2016, Microchip Technology Incorporated, Printed in
CERTIFIED BY DNV the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0737-9
== ISO/TS 16949 ==

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06/23/16

PIC16F753/HV753: 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

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PIC16F753/HV753

14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

High-Performance RISC CPU eXtreme Low-Power (XLP) Features

 2013-2016 Microchip Technology Inc. DS40001709D-page 1

TABLE 1: PIC16F753/HV753 FAMILY TYPES

10-bit ADC (ch)

PIC12F752 (1) 1K Y 64 6 4 2 3/1 1 Y 5-bit N N H Y

FIGURE 1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM

Note: See Table 2 for location of all peripheral functions.

DS40001709D-page 2  2013-2016 Microchip Technology Inc.

TABLE 2: 14/16-PIN ALLOCATION TABLE FOR PIC16F753/HV753

RA0 13 12 AN0 FVROUT — C1IN0+ — — IOC Y — ICSPDAT

 2013-2016 Microchip Technology Inc. DS40001709D-page 3

DS40001709D-page 4  2013-2016 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

 2013-2016 Microchip Technology Inc. DS40001709D-page 5

FIGURE 1-1: PIC16F753/HV753 BLOCK DIAGRAM

Shunt Regulator Hardware

DS40001709D-page 6  2013-2016 Microchip Technology Inc.

TABLE 1-1: PIC16F753/HV753 PINOUT DESCRIPTION

 2013-2016 Microchip Technology Inc. DS40001709D-page 7

DS40001709D-page 8  2013-2016 Microchip Technology Inc.

2.2.2 SPECIAL FUNCTION REGISTERS

 2013-2016 Microchip Technology Inc. DS40001709D-page 9

BANK 0 BANK 1 BANK 2 BANK 3

6Fh EFh 16Fh 1EFh

Legend: = Unimplemented data memory locations, read as ‘0’.

DS40001709D-page 10  2013-2016 Microchip Technology Inc.

 2013-2016 Microchip Technology Inc. DS40001709D-page 11

DS40001709D-page 12  2013-2016 Microchip Technology Inc.

 2013-2016 Microchip Technology Inc. DS40001709D-page 13

DS40001709D-page 14  2013-2016 Microchip Technology Inc.

REGISTER 2-1: STATUS: STATUS REGISTER

 2013-2016 Microchip Technology Inc. DS40001709D-page 15

REGISTER 2-2: OPTION_REG: OPTION REGISTER

bit 7 RAPU: PORTA Pull-up Enable bit

000 1:2 1:1

DS40001709D-page 16  2013-2016 Microchip Technology Inc.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

bit 7 GIE: Global Interrupt Enable bit

Note 1: IOC register must also be enabled.

 2013-2016 Microchip Technology Inc. DS40001709D-page 17

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

bit 7 TMR1GIE: ADC Interrupt Enable bit

DS40001709D-page 18  2013-2016 Microchip Technology Inc.

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1

bit 7-6 Unimplemented: Read as ‘0’

 2013-2016 Microchip Technology Inc. DS40001709D-page 19

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

bit 7 TMR1GIF: TMR1 Gate Interrupt Flag bit

DS40001709D-page 20  2013-2016 Microchip Technology Inc.

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

bit 7-6 Unimplemented: Read as ‘0’

 2013-2016 Microchip Technology Inc. DS40001709D-page 21

REGISTER 2-8: PCON: POWER CONTROL REGISTER

bit 7-2 Unimplemented: Read as ‘0’

DS40001709D-page 22  2013-2016 Microchip Technology Inc.