CSE231 Lecture 9

CSE231 – Digital Logic Design
Lecture – 9 Lesson Outcomes
Programmable
After completing this lecture, students will be able to
• Describe the difference between an PAL and GAL
• Explain the principle of operation of PAL and PLA
Logic Devices
• Explain the difference of SPLD and CPLD
• Apply PAL and PLA for CPLDs, for example, PROM and
FPGA
CSE231 Lecture 9 Page 1/30

Digital Systems Family Tree

Digital Systems Family Tree
TTL : Transistor Transistor Logic

CMOS: Complementary Metal-Oxide Semiconductor
ECL : Emitter Coupled Logic
SPLD : Simple Programmable Logic Device
CPLD : Complex Programmable Logic Device
HCPLD: High Capacity Programmable Logic Device
PAL : Programmable Array Logic
GAL : Generic Array Logic
PLA : Programable Logic Array
FPGA : Field Programable Gate Array
EPROM: Erasable Programmable Read Only Memory
EEPROM: Electrically Erasable Programmable Read Only Memory
SRAM : Static Random Access Memory

PLDs (Programmable Logic Devices) – symbology
Programmable Logic Devices - example Simplified PLD Symbology

PLAs – Programmable Logic Arrays

PLAs – Example

PAL AND PLA: basic difference

Example
PROBLEM. Determine the Boolean output expression for the simple PAL array shown
in Figure. The Xs represent connected links.

Example
PROBLEM. Show how

the PAL-type array in
Figure should be
programmed to
implement each of the
following SOP
expressions. Use an X to
indicate a connected
link.

Example
PROBLEM. Determine the output of

the array in Figure. The Xs represent
connected links.
PROBLEM. Modify the array in Figure to

produce an output

Example
PROBLEM. Determine
the output expressions
for X1 and X2 from
macrocells 1 and 2 in
Figure.

PROM
(a) PROM architecture makes (b) fuses are blown to program A PROM used to generate a logic function on O3.
it suitable for PLDs outputs for given functions
PROM – Programmable Logic Array
(a) Typical PAL architecture; (b) the same PAL programmed for the given functions.
PAL / GAL – General Block Diagram

Basic types of PAL / GAL macrocells

Programmable AND matrix and OLMC in GAL devices
OLMC = Output Logic Macrocell

CPLD – Complex Programmable Logic Device
 A CPLD (complex programmable

logic device) consists basically of
multiple SPLD arrays with
programmable interconnections.
PIA = programmable interconnect array

Block diagram of a typical CPLD

Simplified block diagram of a typical CPLD

Shared expander
FIGURE. Example of how a shared expander can be used in a microcell to increase

the number of product terms
CPLD producing SOP using shared expander
FIGURE. Simplified illustration of

using a shared expander term
from another macrocell to
increase an SOP expression. The
red Xs and lines represent the
connections produced in the
hardware by the software
compiler running the
programmed design

CPLD producing SOP using parallel expander
Basic concept of the parallel expander

FPGA – Field Programmable Gate Array
 An FPGA (field-programmable gate

array) differs in architecture, does
not use PAL/PLA type arrays, and has
much greater densities than CPLDs.
 A typical FPGA has many times more
equivalent gates than a typical CPLD.
 The logic-producing elements in
FPGAs are generally much smaller
than in CPLDs, and there are many
more of them.

FPGA – Field Programmable Gate Array
 The three basic elements in

an FPGA are
 the configurable logic
block (CLB),
 the interconnections, and
 the input/output (I/O)
blocks

Basic configurable logic blocks (CLBs)

FPGA logic module and look-up table (LUT)
FPGA logic module
number of memory cells equal

to 2n, where n is the number of
input variables

Possible look-up table (LUT) configuration in a logic module
FIGURE. Expansion of a logic module (LM) to produce

a 7-variable SOP function in the extended LUT mode

Example
PROBLEM. A logic module is

configured in the extended LUT
mode, as shown in Figure 10–30.
For the specific LUT outputs
shown, determine the final SOP
output

References
1. Digital Fundamentals by Thomas Floyd, Pearson International Edition,

11th Edition, Chapter 9, Page 561-627.
2. Digital Systems: Principles and Applications by Ronald Tocci, Neal

Widmer and Greg Moss, Pearson International Edition, 12th Edition,
Chapter 7, Page 941-961.

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CSE231 – Digital Logic Design

Lecture – 9 Lesson Outcomes

CSE231 Lecture 9 Page 1/30

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TTL : Transistor Transistor Logic

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Programmable Logic Devices - example Simplified PLD Symbology

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PROBLEM. Show how

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PROBLEM. Determine the output of

PROBLEM. Modify the array in Figure to

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 A CPLD (complex programmable

PIA = programmable interconnect array

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FIGURE. Example of how a shared expander can be used in a microcell to increase

FIGURE. Simplified illustration of

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Basic concept of the parallel expander

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 An FPGA (field-programmable gate

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 The three basic elements in

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FPGA logic module

number of memory cells equal

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FIGURE. Expansion of a logic module (LM) to produce

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PROBLEM. A logic module is

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1. Digital Fundamentals by Thomas Floyd, Pearson International Edition,

2. Digital Systems: Principles and Applications by Ronald Tocci, Neal

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