14/11/2023, 14:36 Tap Cell Usage Guidlines Reading Notes-CSDN Blog

Tap Cell Usage GuidelinesReading Notes

Clara_D Published on 2022-01-07 21:43:21 Reading volume: 3.1k Collection 54 Likes 4
Classification column: IC Article tags: Digital backend synthesis IC

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Recently, I am learning digital back-end synthesis, and I will encounter a problem of selecting a library when selecting a reference library.
Taking the TSMC process library as an example, those with bwp in their names are so-called tap-less libraries. This article will share what tap-less l

note: tap-less means no well-tap connection, eg no pickups.

1. What is a tap cell?

The tap cell is the unit where the well will be connected to VDD or GND. It is divided into back-bias tap-cell and none back-bias tap-cell: there will be

a back-bias issue involved here. The difference lies in whether there is an additional power network VPP. and VBB connected to p/n well. As shown
below, the left side represents a tap-cell with back-bias, and the right side represents a tap-cell without back-bias. It should be noted that when usin
bias tap-cell, do not name other pins VPP and VBB, otherwise they will be short-circuited by default.

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14/11/2023, 14:36 Tap Cell Usage Guidlines Reading Notes-CSDN Blog

back-bias tap-cell none back-bias tap-cell

As the name suggests, tap-less libraries mean that the p/n well is not connected to VDD/GND, and an additional welltap needs to be added to conn
potential to the substrate.

2. What is well tap?

You can understand that the well tap is a cell that specifically connects the circuit p/n well to VDD/GND, but there is no effective circuit in it, just to c
well level.
Generally speaking, tap-less libraries require the insertion of well taps during the placement and routing process to provide voltage to the substrate.
libraries with tap-cell, there is no need to insert a well tap.

When inserting a well tap, you need to carefully consider its location: too far from the circuit will cause latch-up, and too close to the circuit may seiz
resources (the location of the well tap must be considered before wiring).
We say that the addition of tap cells will also reduce the latch-up effect. So what exactly is a latch-up?

3. What is the latch up effect?

Latch-up refers to the gate effect, which refers to the phenomenon of high current damage to the circuit caused by a short circuit between power an
Think it’s One-clic
integrated circuit. In the CMOS process, a parasitic BJT tube is formed between the power electrode and the ground electrode of the good?
pretty NMOS collectio
and PM
which will form an SCR (parasitic silicon-controlled rectifier),
Clara_D resulting
focusin
ona low-impedance path and the possibility of generating large
4 currents. 54
.

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14/11/2023, 14:36 Tap Cell Usage Guidlines Reading Notes-CSDN Blog

Commonly used methods of placing latch-up are:

1. Add some oxide trench and buried oxide layers around NMOS and PMOS for isolation (this is called trench), which will break the interaction be
NMOS and PMOS, destroy the SCR, and thus Reduce the latch-up effect.

2. Changing the substrate doping accelerates the carrier recombination speed, thereby reducing the BJT gain and increasing the impedance of th
supply to ground path.

3. Use guard ring: P+ Ring surrounds NMOS and connects to GND; N+ Ring connects to PMOS and connects to VDD.

4. Keep enough distance between NMOS and PMOS to reduce the possibility of SCR. Sub contact holes and Well contact holes should be as clo
possible to the source area. To reduce the resistance of Rwell and Rsub.

5. Try not to use PMOS at IO. (nwell)

4. How to identify whether it is tap-less through the layout

4.1. Determine the standard unit with tap cell

This section introduces how to determine whether there is a tap cell inside through the layout of a standard unit. It mainly comes from
https://blog.eetop.cn/blog-1592-6947193.html . This section is a guide. The original blog is also very well written, and friends who need it can expan
For example, the layout of the INV cell below. Sometimes it is not easy to judge by looking at it directly. I will share some tips later.

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14/11/2023, 14:36 Tap Cell Usage Guidlines Reading Notes-CSDN Blog

My little trick is to only open NW(NWELL) and NP(N+) and see if there is any overlap. The NWELL and N+ of this INV cell obviously overlap, near th

Open CO (contact) and M1 again, and you can see the complete NWELL->N±>contact->M1 metal forming the NWELL tap. P-sub/PWELL taps can
quickly determined using the same technique.
note: NWELL->N±>contact->M1 metal refers to the path connecting nwell to VDD at the physical level.

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14/11/2023, 14:36 Tap Cell Usage Guidlines Reading Notes-CSDN Blog

At this point, it can be determined that this standard element has its own well tap, and there is no need to add a dedicated well tap cell in the back-e

4.2. Determine standard cells without tap cells

The same technique can also be used to quickly determine whether the standard element is tapless. For example, the NWELL and N+ of the cell be
overlap at all, and it is impossible to construct an NWELL tap. This standard element is tapless.

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By the way, you can take a look at what the dedicated well tap cell in this tapless library looks like. The structure of this dedicated cellgood?
pretty is actually NW
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14/11/2023, 14:36 Tap Cell Usage Guidlines Reading Notes-CSDN Blog

>N±>CONT->M1(VDD), plus p-sub->P±>CONT->M1(GND).

It can be seen that transistors cannot be formed in this well tap, and it is a unit that does not contain circuits.

references:

1. http://blog.sina.com.cn/s/blog_bc93ac450102x6bk.html

2. https://blog.csdn.net/weixin_39619478/article/details/112187875

3. https://blog.eetop.cn/blog-1592-6947193.html

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