A Practical Introduction To Electrical Circuits

A Practical Introduction
to Electrical Circuits
A Practical Introduction to Electrical Circuits represents a fresh approach to the
subject which is compact and easy to use, yet offers a comprehensive description of
the fundamentals, including Kirchhoff’s laws, nodal and mesh analysis, Thevenin
and Norton’s theorems, and maximum power transfer for both DC and AC circuits,
as well as transient analysis of first- and second-order circuits. Advanced topics such
as mutual inductance and transformers, operational amplifier circuits, sequential
switching, and three-phase systems reinforce the fundamentals. Approximately one
hundred solved examples are included within the printed copy. Extra features online
include over two hundred additional problems with detailed, step-by-step solutions,
and 40 self-service quizzes with solutions and feedback.
A Practical Introduction
to Electrical Circuits
John E. Ayers
Cover: Web Large Image (Public).
First edition published 2024

by CRC Press
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© 2024 John E. Ayers
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ISBN: 9781032528151 (hbk)

ISBN: 9781032528168 (pbk)
ISBN: 9781003408529 (ebk)
DOI: 10.1201/9781003408529
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Contents
Preface.......................................................................................................................ix
Author.........................................................................................................................x
Chapter 1 Beginning Concepts and Resistive Circuits..........................................1

1.1 Why Circuit Theory Is Important..............................................1
1.2 Assumptions of Circuit Theory..................................................1
1.3 Charges, Voltages, and Currents................................................2
1.4 Power, Energy, and the Passive Sign Convention.......................4
1.5 Independent and Dependent Sources.........................................5
1.6 The Resistor and Ohm’s Law.....................................................6
1.7 Kirchhoff’s Current Law............................................................6
1.8 Kirchhoff’s Voltage Law............................................................8
1.9 Kirchhoff’s Laws and the Validity of Circuit Connections............9
1.10 Series Resistors and the Voltage-Divider Rule......................... 12
1.11 Parallel Resistors and the Current-Divider Rule...................... 14
1.12 Series–Parallel Combinations of Resistors.............................. 16
1.13 Other Configurations and Delta–Wye and
Wye–Delta Transformations..................................................... 18
1.14 Superposition............................................................................ 22
1.15 Summary..................................................................................24
Chapter 2 Nodal Analysis....................................................................................40

2.1 Introduction and Definitions.....................................................40
2.2 The Basic Node Voltage Method (NVM)................................ 41
2.3 The Node Voltage Method and Alternate Node Numbering........44
2.4 The Node Voltage Method with Four Essential Nodes............46
2.5 The Node Voltage Method with Dependent Sources............... 49
2.6 The Node Voltage Method with a Known Node Voltage......... 51
2.7 The Node Voltage Method with a Supernode.......................... 56
2.8 Summary.................................................................................. 59
Chapter 3 Operational Amplifier Circuits........................................................... 70

3.1 Introduction to Operational Amplifiers.................................... 70
3.2 Analysis of Operational Amplifier Circuits............................. 71
3.3 Analysis of a Saturated Operational Amplifier Circuit............ 73
3.4 Analysis of a Circuit Involving Multiple Op Amps................. 75
3.5 Inverting Amplifier................................................................... 79
3.6 Non-inverting Amplifier...........................................................80
3.7 Summing Amplifier.................................................................. 81
v
vi Contents
3.8 Difference Amplifier................................................................ 82

3.9 Design of Op Amp Circuits......................................................84
3.10 Non-ideal Characteristics of Op Amps.................................... 89
3.11 Summary..................................................................................94
Chapter 4 Mesh Analysis................................................................................... 114

4.1 Introduction and Basic Definitions......................................... 114
4.2 Applicability of the Mesh Current Method............................ 115
4.3 The Basic Mesh Current Method (MCM).............................. 115
4.4 The Mesh Current Method with More Than Two Meshes........ 119
4.5 The Mesh Current Method with a Known Mesh Current......... 122
4.6 The Mesh Current Method with a Supermesh....................... 125
4.7 The Double Supermesh.......................................................... 128
4.8 A Supermesh Containing a Known Mesh Current................ 129
4.9 The Mesh Current Method with a Dependent Source............ 131
4.10 Choosing between the MCM and the NVM.......................... 136
4.11 Summary................................................................................ 139
Chapter 5 Thevenin’s and Norton’s Theorems................................................... 155

5.1 Thevenin’s Theorem............................................................... 155
5.2 Thevenin Equivalent for a Circuit with
Only Independent Sources..................................................... 157
5.3 Thevenin Equivalent for a Circuit with Mixed Sources........... 161
5.4 Thevenin Equivalent for a Circuit Containing Only
Dependent Sources................................................................. 173
5.5 Source Transformations.......................................................... 177
5.6 Norton’s Theorem................................................................... 180
5.7 Maximum Power Transfer Theorem...................................... 180
5.8 Summary................................................................................ 188
Chapter 6 First-Order Circuits........................................................................... 201

6.1 Introduction............................................................................ 201
6.2 The Capacitor......................................................................... 201
6.3 Parallel Capacitors..................................................................203
6.4 Series Capacitors....................................................................204
6.5 Natural Response of an RC Circuit........................................205
6.6 Step Response of an RC Circuit............................................. 210
6.7 General Case of Natural and Step Response
in an RC Circuit...................................................................... 214
6.8 The Inductor........................................................................... 221
6.9 Series Inductors...................................................................... 223
6.10 Parallel Inductors....................................................................224
6.11 Natural Response of an RL Circuit........................................ 225
6.12 Step Response of an RL Circuit............................................. 228
Contents vii
6.13 General Case of the Natural and Step Response

in an RL Circuit...................................................................... 229
6.14 Sequential Switching in First-Order Circuits......................... 238
6.15 Summary................................................................................ 247
Problems............................................................................................ 249
Chapter 7 Second-Order Circuits.......................................................................260

7.1 Introduction............................................................................260
7.2 Natural Response of a Series RLC Circuit.............................260
7.3 Overdamped Natural Response of a Series RLC Circuit.......... 263
7.4 Critically-Damped Natural Response of a
Series RLC Circuit................................................................. 268
7.5 Underdamped Natural Response of a Series RLC Circuit........ 271
7.6 Step and Natural Response of a Series RLC Circuit.............. 273
7.7 Natural Response of a Parallel RLC Circuit.......................... 278
7.8 Step and Natural Response of a Parallel RLC Circuit...........280
7.9 General RLC Circuit.............................................................. 288
7.10 Summary................................................................................ 291
Problems............................................................................................ 295
Chapter 8 Sinusoidal Steady-State Analysis......................................................306

8.1 Introduction............................................................................306
8.2 Review of Complex Numbers.................................................307
8.3 Phasors....................................................................................308
8.4 Impedances.............................................................................309
8.4.1 Impedance of a Resistor............................................ 310
8.4.2 Impedance of an Inductor......................................... 311
8.4.3 Impedance of a Capacitor......................................... 313
8.4.4 Series Impedances..................................................... 315
8.4.5 Parallel Impedances.................................................. 317
8.4.6 Combinations of Series and Parallel Impedances........ 318
8.4.7 Impedance and Admittance...................................... 319
8.5 Sinusoidal Steady-State Analysis........................................... 320
8.6 Nodal Analysis in Circuits with Sinusoidal Excitation.......... 322
8.7 Mesh Analysis in Circuits with Sinusoidal Excitation........... 326
8.8 Thevenin’s and Norton’s Theorems in AC Circuits................ 328
8.8.1 Thevenin’s Theorem.................................................. 328
8.8.2 Source Transformations............................................ 336
8.8.3 Norton’s Theorem...................................................... 337
8.9 Sinusoidal Steady-State Power............................................... 337
8.9.1 Instantaneous Power, Average Power, and
Reactive Power.......................................................... 337
8.9.2 Average Power and Root Mean Square
(rms) Values of Voltage or Current........................... 339
8.9.3 Complex Power S......................................................340
viii Contents
8.10 Maximum Power Transfer in Circuits

with Sinusoidal Excitation...................................................... 342
8.11 Three-Phase Circuits and Systems......................................... 347
8.11.1 Three-Phase Configurations...................................... 349
8.11.2 Balanced Wye–Wye System...................................... 352
8.11.3 Balanced Delta–Delta System................................... 354
8.11.4 Unbalanced Three-Phase System.............................. 358
8.12 Mutual Inductance and Transformers....................................360
8.12.1 Fundamental Considerations.....................................360
8.12.2 The Dot Convention for Polarities............................. 362
8.12.3 The Linear Transformer in the Phasor Domain...........364
8.12.4 The Ideal Transformer............................................... 366
8.13 Summary................................................................................ 369
Chapter 9 Frequency Response.......................................................................... 391

9.1 Introduction............................................................................ 391
9.2 Passive Filters......................................................................... 393
9.3 Active Filters.......................................................................... 397
9.3.1 Sallen and Key Low-Pass Filter................................ 397
9.3.2 Sallen and Key High-Pass Filter............................... 399
9.3.3 Multiple Feedback Bandpass Filter...........................400
9.4 Summary................................................................................403
APPENDIX A: Resistor Color Code..................................................................... 416

APPENDIX B: Standard Values of 5% Resistors................................................. 417
APPENDIX C: Standard Values of 10% Capacitors............................................. 418
APPENDIX D: Ceramic Capacitors...................................................................... 419
APPENDIX E: Electrolytic Capacitors................................................................. 420
APPENDIX F: Complex Numbers........................................................................ 421
APPENDIX G: Cramer’s Method......................................................................... 423
Index....................................................................................................................... 427
Preface
The concept for this book developed over three decades, as I fine-tuned my deliv-
ery of the electrical circuits course at the University of Connecticut. Having talked
with thousands of students taking the course, I learned what they really wanted
and needed to master the subject. They wanted a text that was comprehensive yet
compact, concise, and easy to use. They needed solved examples, with a wide cross-
section of topics, which attacked the problems from start to finish, and which explained
the process in a step-by-step fashion. They needed a source that was practical in its
description of analysis techniques, components, design, and methods of measurement.
A Practical Introduction to Electrical Circuits represents a fresh approach that
delivers on all counts. The printed book is compact and easy to use, yet offers a
comprehensive description of Kirchhoff’s laws, nodal and mesh analysis, Thevenin
and Norton’s theorems, and maximum power transfer for both DC and AC circuits,
as well as transient analysis of first- and second-order circuits. Advanced topics such
as mutual inductance and transformers, operational amplifier circuits, sequential
switching, and three-phase systems reinforce the fundamentals. Approximately one
hundred solved examples are included within the printed copy. Extra features online
(www.routledge.com/9781032528151) include detailed solutions to over two hundred
additional problems and 40 self-service quizzes with solutions and feedback. The
ebook+ version includes multiple additional tools for learning, including 12 labora-
tory exercises, 39 animated presentations on the full range of topics, and 10 example
exams with detailed solutions.
I would like to express my sincere gratitude to the thousands of electrical circuits
students who inspired this project, as well as my many teaching assistants for their
fruitful discussions and suggestions. Most of all, I would like to thank my family for
their unending support and patience throughout this endeavor.
John E. Ayers
July 25, 2023
Storrs, CT
ix
Author
John Ayers has been engaged in teaching and academic research for over three
decades at the University of Connecticut, where he is a University Teaching Fellow.
Ayers considers electrical circuits to be one of his passions. He earned the BSEE
from the University of Maine in 1984 and the MSEE and PhDEE from Rensselaer
Polytechnic Institute in 1987 and 1990, respectively. His industrial experience
includes Fairchild Semiconductor, National Semiconductor, Phillips Laboratories,
and Epitax Engineering. Ayers has authored nine books as well as hundreds of
research papers, and is the recipient of eight awards for excellence and innovation
in teaching.
x
1 Beginning Concepts
and Resistive Circuits
1.1 WHY CIRCUIT THEORY IS IMPORTANT

Circuit theory is an important tool for the design and analysis of electrical systems,
which include digital systems and computers; biomedical instruments such as elec-
trocardiographs and blood glucose monitors; imaging systems such as radars, sonars,
and ultrasound systems; sensor systems including air quality monitors, seismographs,
and strain gauges on transportation systems; communication systems such as the
internet, radio, television, and telephones; power systems including nuclear reactors,
wind turbines, and photovoltaic panels; and vehicle systems including engine moni-
tors and controls, anti-lock braking and traction control systems, and self-driving
systems. Electrical circuit theory is therefore applicable to every subfield of engi-
neering, including the electrical, computer, biomedical, civil, mechanical, automo-
tive, aerospace, and environmental engineering fields.
1.2 ASSUMPTIONS OF CIRCUIT THEORY

Circuit theory is useful for the analysis of devices, circuits, and systems provided that
three assumptions are satisfied.
The first assumption of circuit theory is that of a lumped parameter system.
In engineering terms, this assumption means that the wavelength λ associated with
electrical signals is much greater than the physical size of the system, L.
λ >> L (1.1)
Electrical signals propagate at the speed of light, c, so an electrical signal with fre-
quency f has an associated wavelength:
c
λ= . (1.2)
f
For example, at the frequency of 60 Hz used for power distribution in the United States,
c 3 × 108 m/s
λ= = = 5 × 10 6 m. (1.3)
f 60 s−1
This is equal to 5000 km, or roughly the width of the continental United States. The
first assumption applies for a system with a physical size much smaller than this; if
we use “much smaller” to mean a factor of ten, this would correspond to roughly the
width of Arizona. Clearly, the first assumption is easily satisfied at low frequencies!
DOI: 10.1201/9781003408529-1 1
2 A Practical Introduction to Electrical Circuits
The second assumption is that there is zero net electrical charge on each
c omponent in the system. This is approximately true for all of the situations we will
encounter, although there is one device (the capacitor) which can contain equal and
opposite charges within.
The third assumption is that there is zero magnetic coupling between com-
ponents. Although this will generally hold for the circuits we consider, there are
important devices which have internal magnetic coupling (the inductor and the
transformer).
Going forward, we will assume that these three assumptions apply, so we can use
circuit theory for our analysis, rather than resorting to the more complicated elec-
tromagnetic theory based on Maxwell’s equations. First, though, we will explore the
physical origins of basic electrical phenomena.
1.3 CHARGES, VOLTAGES, AND CURRENTS

Electrical circuit phenomena are associated with electrical charges, which are quan-
tified in Coulombs (abbreviated C). These charges are discrete (any electrical charge
is an integer multiple of the unit charge q, which is the absolute value of the charge
of a single electron, where q = 1.602 × 10 −19 C) and bipolar (charges may be positive
or negative).
The physical separation of charge gives rise to electric fields (measured in volts
per meter, or V/m) and potential differences, measured in volts (V). Figure 1.1 shows
in a qualitative way the electric field lines and equipotential contours in two dimen-
sions for the case of a single positive charge and a single negative charge separated
by some distance. A positive test charge will be repelled by the positive charge on
the left and attracted by the negative charge on the right. Hence, the electric field vec-
tors (shown by arrows) point away from the positive charge and toward the negative
FIGURE 1.1 Separation of charge gives rise to electric fields and potential differences.
Beginning Concepts and Resistive Circuits 3
charge, in the way that a positive test charge would move. At any point, the electric
field is the negative of the gradient of the electric potential.

E = −∇v. (1.4)
The equipotential contours curve around the two charges, everywhere  perpen-
dicular to the electric field lines. Integration of the electric field E between two
points a and b gives the electric potential difference vab between the two points:
b

∫
vab = va − vb = − E dr . This electric potential difference, usually called the potential
a
difference or voltage, between these points may be related to the incremental amount of
work done on an incremental positive test charge to move it from one point to the other:
dW
vab = . (1.5)
dq
Therefore, if the work is measured in Joules (J) and the charge is measured in
Coulombs (C), then the unit of potential difference, Volt (V), can be expressed in
other units as 1 V = 1 J/C. In this example, the positive charge on the left is at a higher
electric potential than the negative charge on the right, because net work must be
done to move a positive test charge from right to left.
The motion of charge gives rise to electrical current. Consider a section of copper
wire carrying an electrical current as shown in Figure 1.2. Negatively-charged elec-
trons flow from right to left, giving rise to a conventional current flowing from left to
right. (Conventional current is defined with respect to the motion of positive charges.)
The electrical current, measured in Amperes (A), is given by the incremental amount
of charge dq passing through a cross section of the wire (for example, the cross sec-
tion shaded in gray) in an incremental amount of time dt:
dq
i= . (1.6)
dt
The unit of electrical current is Ampere (A), and in terms of other units 1 A = 1 C/s.
FIGURE 1.2 Motion of charges (negatively-charged electrons in a copper wire) giving rise
to an electrical current.
1.4 POWER, ENERGY, AND THE PASSIVE SIGN CONVENTION

Power is the rate at which work is done:
dw
p= . (1.7)
dt
For a two-terminal device with a potential difference across the terminals given by
v and an electrical current equal to i flowing into the positive terminal as shown in
Figure 1.3a, we can relate the power to the current and voltage as follows:
dw dw dq
p= = = vi. (1.8)
dt dq dt
The unit of power is Watt (W). In terms of the other units, 1 W = 1 J/s = 1 VA.
The sign of the power is important. Here, we will use the passive sign conven-
tion, so a positive value of power indicates that power is absorbed by the circuit
element, whereas negative power indicates that power is extracted from the circuit
element. Absorbed power could be dissipated (turned into heat) or stored in the cir-
cuit element. Extracted power is either developed (as in a source, such as a battery) or
delivered from previously-stored energy (as from a capacitor or an inductor).
To properly use the passive sign convention, we must observe the following rule:
if the reference direction of the current is entering the terminal with the plus sign
for the voltage reference polarity, we calculate the power by p = iv, whereas if the
reference direction of the current is entering the terminal with the minus sign for the
voltage reference polarity, we should apply p = −iv. This is illustrated in Figure 1.3,
FIGURE 1.3 (a–d) Use of the passive sign convention with assumed reference polarities for
the voltage and current.
FIGURE 1.4 (a and b) Examples of application of the passive sign convention.
which shows the four possible permutations for the reference polarities. When apply-
ing this rule we must also account for the algebraic signs of the current and the volt-
age. If the actual current is flowing opposite to the reference direction, we indicate
that by assigning the current a negative value. Likewise, if the polarity of the actual
voltage is opposite to the reference polarity, we assign a negative value to the voltage.
Both of these situations arise commonly, because we often set up reference polarities
before we know the actual polarities (i.e., before we have solved the circuit). Two
possible situations of this type are illustrated in Figure 1.4.
1.5 INDEPENDENT AND DEPENDENT SOURCES

Sources are two-terminal circuit elements, which supply voltage or current to a cir-
cuit. They may be independent (fixed) sources or dependent sources, which are con-
trolled by a voltage or current elsewhere in the circuit.
An independent source may supply voltage or current, so there are two types of
independent sources as shown in Figure 1.5a and b. In our notation, an independent
source is shown by a circle and the current source is distinguished by an arrow within
the circle. Note that a battery can be modeled as an independent voltage source.
We will assume that these sources are ideal. Therefore, the voltage source will
provide a fixed voltage regardless of the amount of current we draw, and the current
source will output a fixed current regardless of the voltage we apply across its ter-
minals. Any real source has limitations, but we can nonetheless model a real source
using an ideal source along with a resistor.
A dependent source may provide voltage or current, and it may be controlled by
either a voltage or a current elsewhere in the circuit. This results in four types of
dependent sources as shown in Figure 1.5c–f. These are the voltage-controlled volt-
age source (VCVS), current-controlled voltage source (CCVS), voltage-controlled
current source (VCCS), and current-controlled current source (CCCS), respectively.
Dependent sources are important for modeling electronic devices such as transis-
tors and amplifiers. For example, the bipolar junction transistor may be modeled by a
CCCS, whereas a field-effect transistor may be modeled by a VCCS.
In our notation, the dependent source has a diamond shape, and a current source
is distinguished by the inclusion of an arrow within the diamond. The controlling
variable is made clear by the equation of the dependent source, and in Figure 1.5, the
controlling variable is referred to as ix (for a controlling current) or v x (for a control-
ling voltage). The coefficient that multiplies the controlling variable has units which
are determined by the output and controlling variable for the source. For example,
FIGURE 1.5 Independent and dependent sources: (a) independent voltage source, (b) inde-
pendent current source, (c) VSVS, (d) CCVS, (e) VCCS, and (f) CCCS.
a CCVS has a coefficient µ with units of V/A, whereas a CCCS has a unitless coeffi-
cient β (units of A/A). It should be noted that the controlling variable must be labeled
in the circuit with its polarity shown.
1.6 THE RESISTOR AND OHM’S LAW

The resistor is a two-terminal circuit element with the symbol as shown in Figure 1.6.
It exhibits a linear relationship between voltage and current, given by Ohm’s law:
v = iR, (1.9)
where R is the resistance in units of Ohms, shown by the upper case Greek letter
omega (1Ω = 1V/A).
Current always flows into the more positive terminal of the resistor. Therefore,
according to the passive sign convention, the power absorbed by a resistor is always
positive, and the resistor always dissipates power. Referring to the polarity references
given in Figure 1.6, we can say that the voltage and current given in the figure must
have the same algebraic sign (both positive or both negative). If we change either one
of the polarity references, we expect the voltage and current to have opposite signs.
To review, see Presentation 1.1 in ebook+. To test your knowledge, try Quiz 1.1
in ebook+.
1.7 KIRCHHOFF’S CURRENT LAW

Kirchhoff’s current law (KCL) is one of the three most important laws of circuit
analysis (along with Ohm’s law and Kirchhoff’s voltage law). Kirchhoff’s laws may
be understood using some simple circuit definitions. A node is a point in the circuit
where two or more elements are connected. An essential node is one which is con-
nected to more than two elements. A path is a trace of elements, none repeated.
FIGURE 1.6 The resistor.
FIGURE 1.7 A circuit involving sources and resistors for the illustration of KCL.
A branch is a path that connects two essential nodes. A loop is a path that begins and
ends on the same node. A mesh is a loop that does not enclose another loop.
One statement of KCL is that the algebraic sum of the currents leaving a
node is zero. By “algebraic sum,” we mean that we must account for the algebraic
signs of the individual currents, some of which may be negative. A second, equiva-
lent statement of KCL is that the algebraic sum of the currents entering a node is
zero. However, our convention will be to always add the currents leaving a node, and
you are strongly encouraged to use this convention consistently in order to avoid sign
errors.
Some examples of the use of KCL may be developed using the circuit diagram
of Figure 1.7. For node A, there are three branches connected. Adding the currents
leaving this node, we obtain
I1 + I 2 + I 3 = 0. (1.10)
Notice that for this to be true for non-zero currents, at least one of the currents
involved must be positive and at least one of the currents must be negative. Often
we will arbitrarily assign the reference polarities before we know the true direc-
tions of any of the currents. This is fine as long as we use the reference polarities
consistently after they have been chosen. Once we have solved the circuit, we will
find the algebraic signs of the currents and thus discover the true directions of cur-
rent flow.
We can write additional equations by using KCL for the other nodes in the circuit.
For node B,
− I 3 − 2 A + I 4 = 0, (1.11)
and for node C,
− I1 − I 4 + I 5 = 0. (1.12)
An important situation occurs at node E, because whereas the other nodes considered
involve the connection of three elements, node E only joins two elements. The use of
KCL at this node yields
I6 − I5 = 0 (1.13)
or
I6 = I5. (1.14)
This trivial application of KCL leads us to the important conclusion that two ele-
ments connected in series carry the same current. (Two elements are connected in
series if they share a single node, and nothing else is connected to this shared node.)
Finally, notice that for node D, we can apply KCL to obtain
− I 2 + 2 A − I 5 = 0. (1.15)
This is not an independent equation, but rather may be obtained by combining the
equations for nodes A, B, and C.
1.8 KIRCHHOFF’S VOLTAGE LAW

A third important circuit law is Kirchhoff’s voltage law (KVL). A statement of
Kirchhoff’s voltage law is that the algebraic sum of the voltages around a loop
is zero. By “loop,” we mean a connection of elements, none repeated, which starts
and ends at the same point in the circuit. Our convention will be to proceed clock-
wise around a loop and add voltage drops. Operationally, this means that, when
proceeding clockwise, we will add a voltage term if we encounter the plus sign first
but we will subtract a voltage term if we first arrive at the negative sign. It is strongly
recommended that you always use this convention to avoid sign errors. Note that the
order of the terms does not matter, so we can start at any point along the loop as long
as we end at the same point.
We can develop several applications of KVL using the example circuit of Figure 1.8.
For the top loop, proceeding clockwise and adding voltage drops, we obtain
−VA + VB + 15 V − VC = 0. (1.16)
FIGURE 1.8 A circuit with sources and resistors for the demonstration of KVL.
Application of KVL to the loop on the lower left yields
−5 V + VC + VD = 0, (1.17)
and for the loop on the lower right, we obtain
−VD + VF − VE = 0. (1.18)
There are additional loops in the circuit, but each of these encloses at least two
smaller loops and therefore does not yield an additional independent equation. For
example, for the outer loop, we obtain
−5 V − VA + VB + 15 V + VF − VE = 0. (1.19)
However, this is not a fourth independent equation. Because the outer loop encloses
the three smaller loops considered above, its equation may be obtained by simply
adding the three previous equations.
1.9 KIRCHHOFF’S LAWS AND THE VALIDITY

OF CIRCUIT CONNECTIONS
One application of Kirchhoff’s laws is to determine whether a circuit connection is
valid. To do this, we write the KVL equation for each independent loop and we write
the KCL equation for each independent node. In each case, we should consider com-
binations of the resulting equations if we are to make an exhaustive search. If neither
of these exercises reveals a violation of one of Kirchhoff’s laws, then the circuit con-
nection is valid and may be solved.
We can illustrate this analysis using Figure 1.9. This circuit has two independent
loops; these are the loops which do not enclose another loop, and they are also called
meshes. There is one on the top and one on the bottom. For the top loop,
−Vw + Vx − 18 V + 12 V −Vy = 0, (1.20)
and this reveals no violation of KVL because there are values of Vw, Vx, and Vy which
make this true. For the bottom loop, KVL requires
Vy − 12 V + 10 V − Vz + 15 V − 20 V = 0, (1.21)
and here too there is no violation because there are values of Vy and Vz which can
satisfy this equation. Neither adding nor subtracting the two equations reveals a vio-
lation of KVL.
Having exhausted the independent loops, we can consider the equation for each
independent node. To identify independent nodes, we find all of the nodes connected
to three or more elements, called the essential nodes. We must consider KCL for all
but one of these essential nodes. The last essential node will not provide an indepen-
dent equation, and neither will any of the non-essential nodes connected to only two
FIGURE 1.9 An example circuit for the determination of its validity.

elements. In the circuit of Figure 1.9, there are two essential nodes labeled “A” and
“B.” Applying KCL to node A, we obtain
0.2 A + I1 + I 2 = 0, (1.22)
and this reveals no violation because there are values of I1 and I 2 which make it true.
Having eliminated every possible violation of Kirchhoff’s laws, we can say that the
circuit of Figure 1.9 is valid and may be solved.
As another example, consider the circuit of Figure 1.10. Here, there are four
essential nodes, labeled “A,” “B,” “C,” and “D,” and three independent loops, or
meshes. To make an exhaustive search for a violation of Kirchhoff’s laws, we would
write the KCL equation for three of the essential nodes, write the KVL equations
for each of the three independent loops, and consider combinations of the equa-
tions in each case. The circuit can be considered valid only if the exhaustive search
fails to reveal any violation of Kirchhoff’s laws, and a single violation of either of
Kirchhoff’s laws shows that the circuit is not valid. Here, the application of KCL at
node A yields
1.5 A − 1A + 0.5 A = 0, (1.23)
and this is not true. The circuit is not valid, and we don’t need to explore further.
in ebook+.
FIGURE 1.10 A second circuit for the determination of its validity.

FIGURE 1.11 Two series resistors.
1.10 SERIES RESISTORS AND THE VOLTAGE-DIVIDER RULE

If two or more resistors are connected in series, and the total voltage across the
combination is known, we can use the voltage-divider rule (VDR) to determine
the individual voltages. To see this, consider the connection of two series resistors as
shown in Figure 1.11. By KVL,
−Vs + V1 + V2 = 0. (1.24)
Rearranging,
Vs = V1 + V2 . (1.25)
By Ohm’s law,
Vs = I s R1 + I s R2 = 0. (1.26)
Solving for the current,

Vs
Is = . (1.27)
R1 + R2
Therefore, the equivalent resistance for the series combination of resistors is
equal to their sum:
Vs
Req = = R1 + R2 . (1.28)
Is
The use of Ohm’s law then yields the VDR equations:
R1
V1 = Vs (1.29)
R1 + R2
and
R2
V2 = Vs . (1.30)
R1 + R2
FIGURE 1.12 Three series resistors.
Therefore, a statement of the VDR is that: when two resistances are connected in
series, the fraction of the total voltage appearing across one of the resistors is
equal to the fraction of the total resistance contained in this resistor.
We can extend the VDR to three or more resistors as well, and Figure 1.12 shows
the case of three series resistors. In this case,
−Vs + I s R1 + I s R2 + I s R3 = 0, (1.31)
Vs
Is = , (1.32)
R1 + R2 + R3
and the equivalent resistance for the series combination is the sum of the individual
resistances:
Vs
Req = = R1 + R2 + R3 . (1.33)
Is
The use of Ohm’s law then yields the VDR equations:
R1
V1 = Vs , (1.34)
R1 + R2 + R3
R2
V2 = Vs , (1.35)
R1 + R2 + R3
and
R3
V3 = Vs . (1.36)
R1 + R2 + R3
1.11 PARALLEL RESISTORS AND THE CURRENT-DIVIDER RULE

Another important situation involves the parallel connection of two or more resistors,
as shown in Figure 1.13. KCL for the top node dictates that
− I s + I1 + I 2 = 0 (1.37)
or
I s = I1 + I 2 . (1.38)
By Ohm’s law, we find that
Vs Vs
Is = + . (1.39)
R1 R2
The equivalent resistance for the parallel combination is
−1
Vs  1 1
Req = = +  . (1.40)
I s  R1 R2 
In other words, the equivalent resistance for two parallel resistors is equal to the
reciprocal of the sum of their reciprocals. In the particular case of two parallel
resistors, we can rewrite this equation in an equivalent form:
R1R2
Req = . (1.41)
R1 + R2
For two parallel resistors, the equivalent resistance is equal to their product
divided by their sum.
FIGURE 1.13 Two parallel resistors.

When two resistances act in parallel, we can understand how the total current
splits between the two parallel resistors using the current-divider rule (CDR). For
the situation shown in Figure 1.13,
R1R2
Vs = I s Req = I s . (1.42)
R1 + R2
The use of Ohm’s law leads us to the current-divider equations:
R2
I1 = I s (1.43)
R1 + R2
and
R1
I2 = Is . (1.44)
R1 + R2
A statement of the CDR is as follows: when two resistors are connected in paral-
lel, the fraction of the total current flowing through one of the resistors is equal
to the value of the opposite resistor divided by the sum of the two resistances.
We can generalize the CDR to three or more resistors in parallel as well. Consider
the case of four parallel resistors as shown in Figure 1.14a. To find the current, we can
combine three of these resistors (R2, R3, and R4) in parallel as shown in Figure 1.14b.
This yields the current-divider relation
R2  R3  R4
I1 = I s . (1.45)
R1 + R2  R3  R4
FIGURE 1.14 (a) Four resistors connected in parallel and (b) simplified circuit created by
combining three of the resistors.
We can determine the other currents in a similar fashion:
R1  R3  R4
I2 = Is , (1.46)
R2 + R1  R3  R4
R1  R2  R4
I3 = Is , (1.47)
R3 + R1  R2  R4
and
R1  R2  R3
I4 = Is . (1.48)
R4 + R1  R2  R3
1.12 SERIES–PARALLEL COMBINATIONS OF RESISTORS

Often a network involving a single source and a number of resistors may be simpli-
fied by combining parallel- and series-connected resistors. If the network can be
simplified to a single source and a single resistance, it may then be solved completely
by repeated applications of Ohm’s law, the VDR, and the CDR. An example is shown
in Figure 1.15.
Here, the equivalent resistance connected to the source is
Req = 3 Ω  6 Ω + 2.5 Ω  ( 2 Ω + 3 Ω + 5 Ω ) + 1Ω
(1.49)
= 3 Ω  6 Ω + 2.5 Ω  10 Ω + 1Ω = 2 Ω + 2 Ω + 1Ω = 5 Ω.
FIGURE 1.15 Circuit involving parallel and series combinations of resistors with a single
source.
The source current can be found by Ohm’s law:

5V 5V
Is = = = 1A. (1.50)
Req 5 Ω
The currents I1 and I 2 may be found by using the CDR:
6Ω 6Ω
I1 = I S = (1A ) = 0.667 A, (1.51)
6Ω + 3Ω 6Ω + 3Ω
and
3Ω 3Ω
I2 = IS = (1A ) = 0.333 A. (1.52)
6Ω + 3Ω 6Ω + 3Ω
The voltage VA may be found by using Ohm’s law:
VA = I1 ( 3 Ω ) = ( 0.667 A )( 3 Ω ) = 2.00 V. (1.53)
We can find I 3 and I 4 by two more applications of the CDR:

10 Ω 10 Ω
I3 = I S = (1A ) = 0.800 A (1.54)
10 Ω + 2.5 Ω 10 Ω + 2.5 Ω
and
2.5 Ω 2.5 Ω
I4 = IS = (1A ) = 0.200 A. (1.55)
10 Ω + 2.5 Ω 10 Ω + 2.5 Ω
The voltages VB and VC may be found using Ohm’s law:
VB = I 3 ( 2.5 Ω ) = ( 0.800 A )( 2.5 Ω ) = 2.00 V (1.56)
and
VC = − I S (1Ω ) = − (1.000 A )(1Ω ) = −1.00 V. (1.57)
The remaining voltages may be found through the use of the VDR:
2Ω 2Ω
VD = VB = ( 2.00 V ) = 0.40 V, (1.58)
2Ω + 3Ω + 5Ω 2Ω + 3Ω + 5Ω
3Ω 3Ω
VE = VB = ( 2.00 V ) = 0.60 V, (1.59)
2Ω + 3Ω + 5Ω 2Ω + 3Ω + 5Ω
and
5Ω 5Ω
VF = VB = ( 2.00 V ) = 1.00 V. (1.60)
2Ω + 3Ω + 5Ω 2Ω + 3Ω + 5Ω
FIGURE 1.16 Wheatstone bridge circuit.
1.13 OTHER CONFIGURATIONS AND DELTA–WYE AND

WYE–DELTA TRANSFORMATIONS
Some resistive circuits contain connections, which are neither parallel nor series.
They may not be analyzed by simple applications of Ohm’s law, the VDR, and the
CDR, but instead require additional tools. An example is the Wheatstone bridge
circuit as shown in Figure 1.16. This circuit has no pair of resistors, which may be
combined in series; this would require the pair of resistors to share a single node with
nothing else connected to this shared node. For example, the resistors RE and RB may
not be combined in series because of the presence of RC. The circuit also has no pair
of resistors which may be combined in parallel; this would require that the resistors
be connected to the same two nodes. For example, the resistors RE and RD may not be
combined in parallel because they share only one node.
A circuit like the Wheatstone bridge may be analyzed by first using a delta-to-wye
or a wye-to-delta transformation if this renders a transformed circuit, which may
then be analyzed by consideration of series and parallel combinations of resistors. To
illustrate this, we will first consider the basic delta-to-wye and wye-to-delta trans-
formations and then apply the delta-to-wye transformation to a Wheatstone bridge.
Consider three delta-connected resistors and three wye-connected resistors,
shown in Figure 1.17 on the left and right, respectively. If the resistors RA, RB, and RC
are known, we can find values of R1, R2, and R3 such that the delta and wye configu-
rations will be externally equivalent. (By “externally equivalent,” we mean that all
currents and voltages outsider of the terminals A, B, and C will be unchanged if we
FIGURE 1.17 Delta-to-wye and wye-to-delta transformations.
replace the delta with the wye.) Similarly, if we know the values of R1, R2, and R3, we
can find values of RA, RB, and RC such that the delta and wye configurations will be
externally equivalent.
If the delta and wye configurations are externally equivalent, then it must be true
that the resistance measured between any pair of terminals is the same for the delta
and the wye. For the delta, the resistances measured between the pairs of terminals are
RAB = RC  ( RA + RB ) , (1.61)
RBC = RA  ( RB + RC ) , (1.62)
and
RCA = RB  ( RC + RA ) . (1.63)
where RAB is the resistance between the terminals A and B, RBC is the resistance
between the terminals B and C, and RCA is the resistance between the terminals C and
A. Similarly, for the wye connection, the resistances are given by
RAB = R1 + R2 , (1.64)
RBC = R2 + R3 , (1.65)
and
RCA = R3 + R1. (1.66)

If we equate the corresponding resistances of the delta and wye configuration, we

obtain a system of three equations:
RAB = RC  ( RA + RB ) = R1 + R2 , (1.67)
RBC = RA  ( RB + RC ) = R2 + R3 , (1.68)
and
RCA = RB  ( RC + RA ) = R3 + R1. (1.69)
By solving this system of three equations, we can find expressions that relate the val-
ues in the delta and wye. Thus, if we know the values of R1, R2, and R3 in a wye, we
can find the required values of RA, RB, and RC in the equivalent delta. The solution is
R1R2 + R2 R3 + R3 R1
RA = , (1.70)
R1
R1R2 + R2 R3 + R3 R1
RB = , (1.71)
R2
and
R1R2 + R2 R3 + R3 R1
RC = . (1.72)
R3
Similarly, if we know the values of RA, RB, and RC in a delta, we can find the required
values of R1, R2, and R3 in the equivalent wye. They are given by
RB RC
R1 = , (1.73)
RA + RB + RC
RC RA
R2 = , (1.74)
RA + RB + RC
and
RA RB
R3 = . (1.75)
RA + RB + RC
Now we turn to a specific example of a Wheatstone bridge (shown in Figure 1.18) and
show how it can be solved by making use of a delta-to-wye transformation.
To solve this circuit, we will first undertake a delta-to-wye transformation on the delta
comprising RA, RB, and RC. The resistors in the transformed wye section are given by
R1 =
RB RC
=
(175 Ω )(150 Ω ) = 38.9 Ω, (1.76)
RA + RB + RC 350 Ω + 175 Ω + 150 Ω
FIGURE 1.18 Wheatstone bridge circuit.
R2 =
RC RA
=
(150 Ω )(350 Ω ) = 77.8 Ω, (1.77)
RA + RB + RC 350 Ω + 175 Ω + 150 Ω
and
R3 =
RA RB
=
(350 Ω )(175 Ω ) = 90.7 Ω. (1.78)
RA + RB + RC 350 Ω + 175 Ω + 150 Ω
The transformed circuit therefore takes the form as shown in Figure 1.19, and this
circuit may be analyzed readily because it involves only simple combinations of par-
allel and series branches.
The equivalent resistance for the network is given by
Req = ( 200 Ω + 38.9 Ω )  (100 Ω + 77.8 Ω ) + 90.7 Ω = 192.6 Ω. (1.79)
The source current is given by
VS 40 V
IS = = = 0.2077 A. (1.80)
Req 192.6 Ω
We can determine the branch currents and by use of the CDR:
 100 Ω + 77.8 Ω 
I1 = 0.2077 A   = 0.0886 A (1.81)
 200 Ω + 38.9 Ω + 100 Ω + 77.8 Ω 
FIGURE 1.19 Transformed Wheatstone bridge circuit.
and
 200 Ω + 38.9 Ω 
I 2 = 0.2077 A   = 0.1191A. (1.82)
 200 Ω + 38.9 Ω + 100 Ω + 77.8 Ω 
Once we know the three unique branch currents, we can find all of the voltages in the
circuit by use of Ohm’s law.
To review, see Presentation 1.3 in ebook+. To test your knowledge, try Quiz 1.3 in
ebook+. To put your knowledge to practice, try Laboratory Exercise 1.1 in ebook+.
1.14 SUPERPOSITION
A circuit with multiple sources can not always be solved simply by using repeated
applications of the CDR and VDR. Usually, an additional tool must be used, and one
such tool is the principle of superposition.
The principle of superposition states that when a linear system is driven by
multiple independent sources, the overall response is the sum of the individual
responses. In a circuit, the response to be found is a voltage or current. By finding the
contributions to this voltage or current associated with each independent source, and
summing them, we can find the value of the voltage or current in question.
To see how this works, we can consider the determination of I x in the circuit of
Figure 1.20. Here, there are three independent sources, so we should find the con-
tribution to I x from each and sum these together. To determine the contribution I x′
associated with the 10 V source, we disable the 2 A and 20 V sources and apply some
combination of the CDR, VDR, and Ohm’s law. (To disable a voltage source, we set
it to zero volts or a short circuit; to disable a current source, we set it to zero amperes
or an open circuit.) Then, we find the contribution I x′′ associated with the 2 A source
by disabling the other two sources, and finally we find the contribution I x′′′ from the
20 V source by disabling the 10 V and 2 A sources. The value of I x is then found by
adding the three contributions: I x = I x′ + I x′′ + I x′′′ .
To find the contribution from the 10 V source, we open-circuit the 2 A source and
short-circuit the 20 V source, as shown in Figure 1.21.
By the CDR,
 10 V   2Ω + 5Ω + 3Ω 
I x′ = −  × = −0.200 A.
 10 Ω + 20 Ω ( 2 Ω + 5 Ω + 3 Ω ) 
 2 Ω + 5 Ω + 3 Ω + 20 Ω 
 

total current flowing from the 10 V source fraction of total current flowing in 20 Ω resistor
(1.83)
To find the contribution from the 2 A source, we short-circuit the 10 V and 20 V

sources, as shown in Figure 1.22.
FIGURE 1.20 A circuit for the application of the principle of superposition.
FIGURE 1.21 Determination of the contribution I x′ from the 10 V source.
FIGURE 1.22 Determination of the contribution I x′′ from the 2 A source.

FIGURE 1.23 Determination of the contribution I x′′′ from the 20 V source.
Here, it is necessary to apply the CDR twice:
 5Ω   10 Ω 
I x′′ = 2 A ×   ×   = 0.200 A.
 5 Ω + 2 Ω + 20 Ω 10 Ω + 3 Ω   10 Ω + 20 Ω 

fraction of total current flowing in 2 Ω resistor fraction of current in 2 Ω which flows in 20 Ω
(1.84)
To find the contribution from the 20 V source, we short-circuit the 10 V source and
open-circuit the 2 A source, as shown in Figure 1.23.
By the CDR,
 20 V   10 Ω 
′′′=
Ix  ×  10 Ω + 20 Ω  = 0.400 A. (1.85)
 5 Ω + 2 Ω + 20 Ω 10 Ω + 3 Ω   

total current flowing from the 10 V source fraction of total current flowing in 20 Ω
The total current is the sum of these three individual contributions:
I x = I x′ + I x′′ + I x′′′= −0.200 A + 0.200 A + 0.400 A = 0.400 A. (1.86)
In principle, we may also apply superposition to a circuit with mixed (independent

and dependent sources). In such a case, we disable all but one independent source for
the determination of each component of current or voltage. However, we must leave
all dependent sources active, and this process doesn’t lend itself to simple appli-
cations of the VDR and CDR. Instead, it is often better to apply the node voltage
method, described in the next chapter.
in ebook+.
1.15 SUMMARY
Circuit theory is important for the analysis of electrical circuits and is applicable
to every field of engineering. The three starting assumptions of circuit theory are a
lumped parameter system (that the wavelengths associated with electrical signals are
much larger than the physical dimensions of the system), zero net electrical charge on
each element, and zero magnetic coupling between elements. As long as these hold,
we may apply circuit theory instead of resorting to the full electromagnetic theory.
Electrical circuit phenomena are associated with electrical charges, which are dis-
crete (in increments of the electronic charge q) and bipolar (may be positive or nega-
tive). Separation of charge gives rise to electric fields (in V/m) and electric potentials
(in V). Motion of charge gives rise to electrical current (in A).
Power, or the rate at which work is done, may be related to the product of the
voltage and current. Using the passive sign convention, if the current and voltage
reference polarities for a two-terminal element are such that the current reference
direction enters the terminal with the positive voltage reference, then p = iv, where i
is the current and v is the voltage. If we reverse either reference polarity, so the refer-
ence direction for current is entering the terminal with the negative voltage reference,
then p = −iv. We must take into account the algebraic signs of both the voltage and
current as well, either may be negative. Once we find the sign of the power, a positive
value means that the element absorbs power but a negative value means that power is
extracted from the element.
There are independent (fixed) and dependent sources. Independent sources may
supply voltage or current, leading to two types. Dependent sources may supply volt-
age or current and may be controlled by either a voltage or a current, leading to four
basic types; these are the VCVS, CCVS, VCCS, and CCCS.
The three most important laws for circuit analysis are Ohm’s law, KCL, and KVL.
The resistor is a linear element which follows Ohm’s law, which states that v = iR
where R is the resistance in Ω.
Kirchhoff’s laws may be understood using some simple circuit definitions. A node
is a point in the circuit where two or more elements are connected. An essential node
is one which is connected to more than two elements. A path is a trace of elements,
none repeated. A branch is a path that connects two essential nodes. A loop is a
path that begins and ends on the same node. A mesh is a loop that does not enclose
another loop.
KCL states that the sum of the branch currents leaving a node is zero. KVL states
that the sum of the voltages around a closed path (a loop or a mesh) is zero. Our con-
vention is to proceed clockwise around such a closed path and to add voltage drops.
(If we encounter the plus sign first, we add the voltage term.)
For resistors in series, the equivalent resistance is the sum of the individual resis-
tances. The VDR may be used to find how the total voltage across series resistances
splits between the individual resistances. It states that the fraction of the voltage
appearing across a resistor is equal to the fraction of total resistance in that resistor.
For resistors in parallel, the equivalent resistance is the reciprocal of the sum of
the reciprocals of the individual resistances. The CDR may be used to find how a
total current splits among parallel resistances. It states that the fraction of total cur-
rent flowing in one parallel resistor is equal to the equivalent resistance for the other
resistors divided by the sum of the equivalent resistance for the other resistors and the
resistance for the branch in question.
Some configurations or resistors may not be simplified by the use of parallel
and series combinations. These configurations generally contain wye-connected
or delta-connected combinations of resistors, and an example is the Wheatstone
bridge. Circuits of this type may be simplified by using delta–wye or wye–delta
transformations.
The principle of superposition is a useful tool for solving some circuit problems.
It states that when a linear system is driven by more than one independent source, the
total response is the sum of the individual responses associated with each of the inde-
pendent sources. Here, the total response is a voltage or a current, and we can find it
by summing the individual responses, each determined by leaving one independent
source active while deactivating all others.
PROBLEMS
Problem 1.1. Consider the electrical circuit of Figure P1.1 containing a bat-
tery and two resistors.
FIGURE P1.1 Circuit involving a battery and resistors.
a. Does conventional current enter or leave the positive terminal of the

battery?
b. Do electrons enter or leave the positive terminal of the battery?
c. What is the absolute value of the conventional current flowing in the
circuit?
d. What is the power for the battery, and does the battery develop or dis-
sipate power?
Problem 1.2. Consider the three-battery circuit shown in Figure P1.2.
FIGURE P1.2 Circuit involving three batteries and three resistors.
a. Does conventional current enter or leave the top terminal of the upper
1.5 V battery?
b. Do electrons enter or leave the top terminal of the upper 1.5 V battery?
c. Does conventional current enter or leave the positive terminal of the 9 V
battery?
d. Do electrons enter or leave the positive terminal of the 9 V battery?
e. Find the power for each of the 1.5 V batteries.
f. Find the power for the 9 V battery.
Problem 1.3. Consider the two-battery circuit shown in Figure P1.3.
FIGURE P1.3 Circuit involving two batteries and three resistors.
a. Find I A, I B, and IC.

b. Determine the voltages V1, V2, and V3.
c. Determine the power for each of the batteries.
Problem 1.4. Determine if the circuit connection of Figure P1.4 is valid. If it

is valid, solve for the value of I X .
FIGURE P1.4 Circuit with three meshes and four essential nodes to test for validity.
Problem 1.5. Determine if the circuit connection of Figure P1.5 is valid. If

it is valid, solve for the value of VX .
FIGURE P1.5 Circuit with five meshes and five essential nodes to test for validity.
Problem 1.6. Determine if the circuit connection of Figure P1.6 is valid. If

it is valid, solve for the value of VZ .
FIGURE P1.6 Circuit with five meshes and eight essential nodes to test for validity.
Problem 1.7. Use the ad hoc application of Kirchhoff’s laws and Ohm’s law
to solve the circuit shown in Figure P1.7. Thus, determine the currents I A, I B,
IC, I D , I E, I F, and I G , and the voltages VX , VY , and VZ .
FIGURE P1.7 Circuit involving sources and resistors.

Problem 1.8. Use the ad hoc application of Kirchhoff’s laws and Ohm’s law to
solve the circuit of Figure P1.8. Thus, determine the currents I A, I B, IC, I D , I E,
I F, and I G , and the voltages VX , VY , and VZ .
FIGURE P1.8 Complex circuit involving many independent sources and resistors.
Problem 1.9. Determine the currents I1, I 2, and I 3, and the voltage VX in the
network of Figure P1.9.
FIGURE P1.9 Circuit containing a single voltage source and five resistances.
Problem 1.10. Find the voltages V1, V2, and V , and the current I X for the cir-
cuit of Figure P1.10.
FIGURE P1.10 Circuit containing a single current source and seven resistances.
Problem 1.11. Determine the currents I A, I B, and IC, and the voltage VX for
the circuit shown in Figure P1.11.
FIGURE P1.11 Circuit containing a single voltage source and twelve resistances.
Problem 1.12. Find I S , I1, I 2, and V1 in the circuit of Figure P1.12.
FIGURE P1.12 Wheatstone bridge circuit.
Problem 1.13. Find I S , I1, I 2, and V1 in the circuit shown in Figure P1.13.
FIGURE P1.13 Resistive circuit containing a Wheatstone bridge.

Problem 1.14. Determine VA, VB, VC , and the power for the voltage source in
the circuit of Figure P1.14.
FIGURE P1.14 Circuit involving a voltage source and ten resistors.

Problem 1.15. Calculate the four voltages VW , VX , VY , and VZ in the circuit

shown in Figure P1.15.
FIGURE P1.15 Circuit involving a voltage source and seven resistors.

Problem 1.16. Determine I X and the voltages V1, V2, and V3 in the circuit
shown in Figure P1.16.
FIGURE P1.16 Circuit with a voltage source and resistors.
Problem 1.17. Use superposition to find the current I X in the circuit of

Figure P1.17.
FIGURE P1.17 Circuit with independent sources and resistors.

Problem 1.18. Use superposition to find the current I X in the circuit shown
in Figure P1.18.
FIGURE P1.18 Circuit with four essential nodes, three sources, and five resistors.
Problem 1.19. Use superposition to find the voltage VX in the circuit of

Figure P1.19.
FIGURE P1.19 Circuit with three essential nodes.

Problem 1.20. Use superposition to find the current I Z in the circuit shown
in Figure P1.20, and thereby determine the power for the voltage source.
FIGURE P1.20 Circuit with four essential nodes, three sources, and resistors.
Problem 1.21. Use superposition to determine how much the current IY in

the circuit of Figure P1.21 will change if the 3 A source is changed to 2 A.
FIGURE P1.21 Circuit with four essential nodes.

Problem 1.22. Use superposition to determine how much the current IY in

the circuit of Figure P1.22 will change if the voltage source is reversed in
polarity.
FIGURE P1.22 Circuit with four essential nodes, three sources, and four resistors.
Problem 1.23. Use superposition to find VA and VB in the circuit of Figure P1.23.
FIGURE P1.23 Circuit with five essential nodes.

Problem 1.24. Use superposition to determine how much the voltage VQ in

the circuit of Figure P1.24 will change if the current source is reversed in
polarity.
FIGURE P1.24 Circuit with five essential nodes, three sources, and six resistors.
Problem 1.25. Use superposition to calculate how much the voltage VZ in the
circuit of Figure P1.25 will change if the voltage source is changed from 4 V
to 8 V.
FIGURE P1.25 Circuit with four independent sources and resistors.

2 Nodal Analysis
2.1 INTRODUCTION AND DEFINITIONS

Nodal analysis, commonly called the node voltage method (NVM), is a standard
method for solving a circuit with the minimum number of equations. To establish
some definitions and explain the method, we will use the example circuit shown in
Figure 2.1.
First, we will consider basic definitions. A node is a point in the circuit where two
or more elements are joined. Our example circuit contains five nodes, indicated and
labeled A–E in Figure 2.2. An essential node is one connected to more than two
elements. Our circuit contains three essential nodes: B, C, and E. Nodes A and D are
non-essential because each of them is connected to only two elements. (It is impor-
tant to note that node E is a single node, even though it is drawn with two “solder
blobs.” This is because there is only wire between these solder blobs, and the circuit
could be redrawn with wires coming together at a single point on the bottom if we
tilted the 6 Ω and 3 Ω resistors.) A path is a trace of adjoining elements with none
repeated. A branch is a path that connects two essential nodes.
FIGURE 2.1 Circuit for analysis by the NVM.
FIGURE 2.2 Identification of nodes in the example circuit.
40 DOI: 10.1201/9781003408529-2
Nodal Analysis 41
FIGURE 2.3 Identification of essential nodes in the example circuit.
FIGURE 2.4 Choice of a reference node in the example circuit.
2.2 THE BASIC NODE VOLTAGE METHOD (NVM)

To illustrate the node voltage, we will solve the circuit in Figure 2.1. This involves
six steps. The first step is to identify the essential nodes as shown in Figure 2.3, and
as mentioned previously there are three in this circuit.
The second step is to choose one of the essential modes as the reference node,
as shown in Figure 2.4. It can be any of the essential nodes, but it will simplify the
analysis somewhat if we choose the essential node which is connected to the most
elements. Here, we have chosen the bottom node to be the reference node, and this
means that the other node voltages will be determined with respect to this refer-
ence node.
The third step is to number the remaining ( ne − 1) nodes, where ne is the number
of essential nodes. Here we have labeled the top two essential nodes 1 and 2 as shown
in Figure 2.5. The node voltages V1 and V2 represent the minimum set, which we must
determine in order to solve the circuit, and they are both measured with respect to the
reference node as shown. For example, V1 is the voltage across the 6 Ω resistor, with
the voltage reference having the “plus” at node 1.
As a fourth step, we write ( ne − 1) node voltage equations in terms of the ( ne − 1)
node voltages. (In this case, we need to solve two node voltage equations to find two
node voltages. This is the minimum number of equations that must be solved. We
could write additional equations involving the node voltages, but they are not inde-
pendent equations and are not needed.)
FIGURE 2.5 Numbering of remaining essential nodes.
FIGURE 2.6 Branch currents used to write the node equations.
The node equations are written by making use of Kirchhoff’s current law as
shown in Figure 2.6. For node 1, we sum the branch currents leaving node 1 and
set this sum to zero. Thus, I a + I b + I c = 0. In a similar fashion for node 2, we write
I d + I e + I f = 0.
These two node equations must be rewritten in terms of the node voltages and
circuit quantities in order to be useful. The branch current I a is fixed by the current
source so I a = −3 A. Here, the minus sign applies because the reference direction
of I a is opposite to the direction of the current source. The second branch current
I b may be found by the use of Ohm’s law: I b = V1 / 6 Ω. For the determination of the
third branch current I c , we need to apply Kirchhoff’s voltage law and Ohm’s law with
respect to the 4 Ω resistor. The voltage across this resistor, Vx, may be determined by
consideration of KVL: −V1 + Vx + V2 = 0 so Vx = V1 − V2. Therefore, the branch current
I c is given by I c = Vx / 4 Ω = (V1 − V2 ) / 4 Ω. The node 1 equation may be written as
−3 A + V1 / 6 Ω + (V1 − V2 ) / 4 Ω = 0 .
When developing the node 2 equation we can use similar ideas, but we should
note that I d has the opposite reference polarity compared to I c , and therefore
I d = − I c = (V2 − V1 ) / 4 Ω. The determination of I f requires the use of KVL for the
determination of Vy. The basic KVL equation is −V2 + Vy + 8 V = 0, which may be
rewritten as Vy = V2 − 8 V . Then, Ohm’s law can be used to find the branch current:
Nodal Analysis 43
I f = Vx / 2 Ω = (V2 − 8 V ) / 2 Ω. For simplicity, we often state the units as V , A, and Ω,

and then write the node equations with only numerical quantities given. Thus, we
would write the system of two node equations in V , A, and Ω as
V1 V1 − V2
N1 − 3 + + =0 (2.1)
6 4
and
V2 − V1 V2 V2 − 8
N2 + + = 0. (2.2)
4 3 2
The next and fifth step in the process is to solve this system of equations for the node
voltages (two equations, two unknowns). There are a number of approaches which
may be taken, but we will illustrate one of them. For example, we can start by mul-
tiplying each equation by the least common denominator (LCD). Here, the LCD for
each equation is 12, and multiplying by this we obtain
N 1 − 36 + 2V1 + 3V1 − 3V2 = 0 (2.3)
and
N 2 3V2 − 3V1 + 4V2 + 6V2 − 48 = 0. (2.4)
Collecting like terms, we can rewrite the node equations as
N 1 5V1 − 3V2 = 36. (2.5)
N 2 − 3V1 + 13V2 = 48. (2.6)
Next, it is convenient to write this system of equations in matrix form so we can solve
by matrix techniques.
 5 −3   V1   36 
 −3  = . (2.7)
 13   V2   48 
For example, we can solve by use of Cramer’s rule. The node voltages are given by
36 −3
48 13
V1 = = 10.93 V (2.8)
5 −3
−3 13
and
5 36
−3 48
V2 = = 6.21V. (2.9)
5 −3
−3 13
In each case, we take the ratio of two determinants. To find V1, the numerator is the
determinant of the original 2 × 2 matrix modified by replacing the first column with
the 2 × 1 matrix, and the denominator is the determinant of the original 2 × 2 matrix.
To find V2, the numerator is the determinant of the original 2 × 2 matrix modified by
replacing the second column with the 2 × 1 matrix, and the denominator is the deter-
minant of the original 2 × 2 matrix.
The sixth and final step in solving the circuit is to use these node voltages to find
the remaining circuit quantities. All currents, voltages, and power values in the
circuit may be determined once the node voltages have been found, although we
may not need to find each of these quantities. For example, the branch current flow-
ing from top to bottom in the 6 Ω resistor is
V1 10.93 V
Ib = = = 1.822 A (2.10)
6Ω 6Ω
and the power in the 4Ω resistor is
(10.93 V − 6.21V )
2
(V1 − V2 )2
P4 Ω = = = 5.57 W. (2.11)
4Ω 4Ω
2.3 THE NODE VOLTAGE METHOD AND

ALTERNATE NODE NUMBERING
Our choices of reference node and node numbers are arbitrary, but the circuit quanti-
ties are unique and not changed by these choices. To show this, we will reconsider the
circuit in Figure 2.5 with different choices of reference node and node numbering as
shown in Figure 2.7. It should be understood that VA and VB will not be equivalent to
V1 and V2 found in the previous solution; this is because the former are defined differ-
ently than the latter. However, fundamental circuit quantities such as I b and P4 Ω are
invariant with respect to our choices of reference node and node numbering.
The node equations for the alternate node numbering in V , A, and Ω are
VA − VB VA VA + 8
NA 3 + + + =0 (2.12)
6 3 2
and
VB − VA VB
NB − 3 + + = 0. (2.13)
6 4
Nodal Analysis 45
FIGURE 2.7 The electrical circuit of the previous section with the reference node and node
labels chosen differently.
Multiplying each by the LCD (6 and 12, respectively), we obtain
NA 18 + VA − VB + 2VA + 3VA + 24 = 0 (2.14)
and
NB − 36 + 2VB − 2VA + 3VB = 0. (2.15)
Collecting like terms,
NA 6VA − VB = −42 (2.16)
and
NB − 2VA + 5VB = 36. (2.17)
Next, it is convenient to write this system of equations in matrix form so we can solve
by matrix techniques.
 6 −1   VA   −42 
 −2  = . (2.18)
 5   VB   36 
Solving,
−42 −1
36 5
VA = = −6.21V (2.19)
6 −1
−2 5
and
6 −42
−2 36
VB = = 4.71V. (2.20)
6 −1
−2 5
Basic quantities in the circuit are invariant with respect to our choices of refer-
ence node and node numbering. For example, the branch current flowing from top
to bottom in the 6 Ω resistor is
VB − VA 4.71V − ( −6.21V )
Ib = = = 1.820 A (2.21)
6Ω 6Ω
and the power in the 4Ω resistor is
V 2 ( 4.71V )
2
P4 Ω = B = = 5.55 W. (2.22)
4Ω 4Ω
These values are the same as those determined with the original node labeling in the
previous section, apart from round-off differences.
2.4 THE NODE VOLTAGE METHOD WITH

FOUR ESSENTIAL NODES
The method described in the previous section can readily extend to cases with higher
numbers of essential nodes. To illustrate this, we will consider the circuit in Figure 2.8.
FIGURE 2.8 An electrical circuit with four essential nodes.

Nodal Analysis 47
FIGURE 2.9 An electrical circuit with four essential nodes which are labeled.
In Figure 2.9, the four essential nodes have been identified, the reference node has
been chosen, and the remaining nodes have been numbered.
The node voltage equations are the following in units of V , A, and Ω.
V1 V1 − V2 V1 + 30 − V3
N1 + + = 0, (2.23)
15 12 5
V2 − V1 V −V
N2 − 2 + 2 3 = 0, (2.24)
12 10
and
V3 − 30 − V1 V3 − V2 V3 − 20
N3 + + = 0. (2.25)
5 10 4
Multiplying by the LCD in each case, we obtain
N 1 4V1 + 5V1 − 5V2 + 12V1 + 360 − 12V3 = 0, (2.26)
N 2 5V2 − 5V1 − 120 + 16V2 − 6V3 = 0, (2.27)
and
N 3 4V3 − 120 − 4V1 + 2V3 − 2V2 + 5V3 − 100 = 0. (2.28)

N 1 21V1 − 5V2 − 12V3 = −360, (2.29)
N 2 − 5V1 + 11V2 − 6V3 = 120, (2.30)
and
N 3 − 4V1 − 2V2 + 11V3 = 220. (2.31)
It is useful to note that in the node one equation only the V1 term has a positive coef-
ficient while the V2 and V3 terms have negative coefficients. In general, in the nth node
equation, only the Vn term will have a positive coefficient. This will always be true
unless there are dependent sources present. In matrix form, the three node equations are
 11 −5 −12   V1   −360 
 −5 −6  V   .
 21  2  =  120  (2.32)
 −4 −2 11   V3   220
 
This system of equations may be solved by use of Cramer’s rule:
−360 −5 −12
120 11 −6
220 −2 11
V1 = = 4.72 V, (2.33)
21 −5 −12
−5 11 −6
−4 −2 11
21 −360 −12
−5 120 −6
−4 220 11
V2 = = 27.64 V, (2.34)
21 −5 −12
−5 11 −6
−4 −2 11
21 −5 −360
−5 11 120
−4 −2 220
V3 = = 26.74 V, (2.35)
21 −5 −12
−5 11 −6
−4 −2 11
Once the three node voltages are known, we can find all remaining circuit quantities
as needed.
Nodal Analysis 49
and Quiz 2.2 (solving systems of equations) in ebook+. For more on solving systems
of equations, refer to Appendix G. To put your knowledge to practice, try Laboratory
Exercise 2.1 in ebook+
2.5 THE NODE VOLTAGE METHOD WITH DEPENDENT SOURCES

We can apply the NVM to circuits containing dependent sources, and this just
requires us to express the dependent sources in terms of the node voltages. As an
example, we will solve the circuit in Figure 2.10, which contains a voltage-controlled
voltage source, but the same method applies in the case of other types of dependent
sources or even multiple dependent sources.
The essential nodes in the example circuit have been identified and labeled in
Figure 2.11.
The two node voltage equations are the following in units of V , A, and Ω.
V1 − 4 V −V
N1 −1+ 1 2 = 0 (2.36)
2 6
and
V2 − V1 V2 V2 − 3v x
N2 + + = 0. (2.37)
6 12 4
FIGURE 2.10 An electrical circuit containing a dependent source.
FIGURE 2.11 Essential nodes labeled in an electrical circuit containing a dependent source.
Here, we have two equations in three unknowns, so an additional equation is needed.

This is the equation relating the dependent source to the node voltages, which may
be found using KVL:
DS v x = 4 − V1 (2.38)
Substituting the dependent source equation into the node two equation, we obtain the
following system:
V1 − 4 V −V
N1 −1+ 1 2 = 0 (2.39)
2 6
and
V2 − V1 V2 V2 − 3 ( 4 − V1 )
N 2 DS + + = 0. (2.40)
6 12 4
Multiplying each equation by its LCD, we have
N 1 3V1 − 12 − 6 + V1 − V2 = 0, (2.41)
and
N 2 DS 2V2 − 2V1 + V2 + 3V2 − 36 + 9V1 = 0. (2.42)
N 1 4V1 − V2 = 18 ((2.43)
and
N 2 DS 7V1 + 6V2 = 36. (2.44)
The equations in matrix form are
 4 −1   V1   18 
 = . (2.45)
 7
 6   V2   36 
The solution, obtained using Cramer’s rule, is
18 −1
36 6
V1 = = 4.64 V (2.46)
4 −1
7 6
and
4 18
7 36
V2 = = 0.581V. (2.47)
4 −1
7 6
Nodal Analysis 51
All other circuit quantities may be readily determined once the node voltages are
known; for example, the controlling variable v x is
v x = 4 V − V1 = 4 V − 4.64V = −0.64 V. (2.48)
To review, see Presentation 2.2 in ebook+. To test your knowledge, try Quiz 2.3 in ebook+.
2.6 THE NODE VOLTAGE METHOD WITH

A KNOWN NODE VOLTAGE
When applying the NVM, special cases are introduced by voltage sources (indepen-
dent or dependent), which are connected directly between essential nodes. When a
voltage source exists between the reference node and one of the other essential nodes,
this gives rise to a known node voltage. Such a case will be illustrated using the
circuit in Figure 2.12.
Suppose we label the essential nodes as shown in Figure 2.13.
With this choice of reference node, V1 is fixed by the 20 V source and represents a
known node voltage. The node two equation is written in the usual fashion, by apply-
ing KCL. Therefore, the node equations in V, mA, and kΩ are
N 1 V1 = 20 (known node voltage) (2.49)
and
V2 − V1 V2
N2 + + 10 = 0. (2.50)
5 4
FIGURE 2.12 An electrical circuit containing a known node voltage.
FIGURE 2.13 An electrical circuit containing a known node voltage with the nodes labeled.
Substitution of the node one equation into the node two equation results in
V2 − 20 V2
N 1N 2 + + 10 = 0. (2.51)
5 4
Multiplying by the LCD,
N 1N 2 4V2 − 80 + 5V2 + 200 = 0 (2.52)
or
N 1N 2 9V2 = −120. (2.53)
Solving,
N 1N 2 V2 = −13.33 V. (2.54)
Having solved for the node voltages we can find all other circuit quantities. For
example, we can determine the power for the 20 V source. Referring to the currents
defined in Figure 2.14,
P20 V = ( ix ) ( 20 V ) = ( ia + ib ) ( 20 V )
 40 V − V1 V2 − V1  (2.55)
=
 10 kΩ
+
5 kΩ 
( 20 V ) = −93.3 mW.
The negative value indicates that this source is developing power.
Notice that, for this example with three essential nodes, we expected to solve two
equations, but the presence of a special case (the known node voltage) reduced the
system of equations to one. In general, each special case will allow us to eliminate
one equation from the number to be solved.
FIGURE 2.14 Consideration of the power for the 20 V source in the example circuit with
a known node voltage.
Nodal Analysis 53
Also noteworthy is our choice of V, mA, and kΩ units to solve this problem. We
could have used units of V, A, and Ω, but this would have given rise to an equivalent
yet cumbersome node two equation:
V2 − V1 V
N2 + 2 + 0.01 = 0. (2.56)
5000 4000
Therefore, we will generally use units of V, mA, and kΩ whenever the resistances
are all of the order of kΩ.
In the NVM, a special case can arise from any voltage source, independent or
dependent. To show this, we will consider the circuit in Figure 2.15. Here, there
are four essential nodes, leading to three equations. The dependent source (current-
controlled voltage source) gives rise to a known node voltage and provides an oppor-
tunity to reduce to two equations, although this is less straightforward than in the
case of an independent source so we may opt to solve the system of three equations
instead. In Figure 2.16, the essential nodes have been identified and labeled.
FIGURE 2.15 A circuit containing a dependent source giving rise to a known node voltage.
FIGURE 2.16 A circuit containing a dependent source arising from a known node voltage.
The three node voltage equations in units of V, A, and Ω are
N 1 V1 = 4ix (known node voltage), (2.57)
V2 − V1 V2 V2 − V3
N2 + + = 0, (2.58)
8 12 6
and
V3 − V2
N 3 0.5 + − 1 = 0. (2.59)
6
The equation governing the dependent source is
V3 − V2
DS ix = . (2.60)
6
Substituting the dependent source equation into the node one equation, we obtain the
following system:
V −V
N 1DS V1 = 4  3 2  . (2.61)
 6 
V2 − V1 V2 V2 − V3
N2 + + = 0, (2.62)
8 12 6
and
V3 − V2
N 3 0.5 + − 1 = 0. (2.63)
6
N 1DS 6V1 + 4V2 − 4V3 = 0 (2.64)
and
N 2 3V2 − 3V1 + 2V2 + 4V2 − 4V3 = 0. (2.65)
N 3 3 + V3 − V2 − 6 = 0. (2.66)
N 1DS 6V1 + 4V2 − 4V3 = 0 (2.67)
and
N 2 − 3V1 + 9V2 − 4V3 = 0. (2.68)

Nodal Analysis 55
N 3 − V2 + V3 = 3. (2.69)
 6 4 −4   V1   0 
 −3 −4  V   
 9  2  =  0 . (2.70)
 0 −1 1   V3   3 

Solving,
0 4 −4
0 9 −4
3 −1 1
V1 = = 2.00 V, (2.71)
6 4 −4
−3 9 −4
0 −1 1
6 0 −4
−3 0 −4
0 3 1
V2 = = 3.60 V, (2.72)
6 4 −4
−3 9 −4
0 −1 1
and
6 4 0
−3 9 0
0 −1 3
V3 = = 6.60 V. (2.73)
6 4 −4
−3 9 −4
0 −1 1
Once the three node voltages are known, we can find all remaining circuit quantities.
As examples,
V3 − V2 6.60 V − 3.60 V
ix = = = 0.500 A, (2.74)
6Ω 6Ω
and the power for the dependent source is
 V −V   3.6 V − 2.0 V 
P4 ix = (V1 )  0.5 A + 2 1  = ( 2.0 V )   = 0.400 W. (2.75)
 8Ω   8Ω 
2.7 THE NODE VOLTAGE METHOD WITH A SUPERNODE

Another special case that arises in the NVM is the supernode. This refers to a voltage
source directly between two essential nodes, neither of which is the reference node. This
means that our choice of reference node determines whether a voltage source gives rise
to a known node voltage or a supernode. However, sometimes a circuit will contain a
supernode no matter where we choose to place the reference node, and it is therefore
necessary to understand how to solve problems containing supernodes. To see this, we
can consider the circuit in Figure 2.17. This network contains two voltage sources, which
are connected directly between essential nodes, and it therefore gives rise to two special
cases. If we choose the bottom node as the reference, then the 12 V source gives rise to
a known node voltage while the 6 V source gives rise to a supernode. There is no place-
ment of the reference node which will avoid a supernode, and in fact placing the refer-
ence on the right-hand side of the circuit will result in two supernodes!
For our NVM analysis, we will choose the reference node and node numbers as
shown in Figure 2.18. With this choice, there is a known node voltage at node one
while nodes two and three form a supernode.
FIGURE 2.17 An electrical circuit with five essential nodes. This circuit contains at least
one supernode for any choice of reference node.
FIGURE 2.18 An electrical circuit containing a supernode.

Nodal Analysis 57
When writing the node equations here, it is not possible to directly determine the
branch current between nodes two and three by the use of Ohm’s law because there
is no resistor in series with the voltage source. If we invoke this branch current and
define it as ix , the node two and node three equations are, in units of V, A, and Ω:
V2 − V1 V2
N2 + + ix = 0, (2.76)
6 10
and
V3 V3 − V4
N 3 − ix + + = 0. (2.77)
15 5
These equations are not as useful as written because they invoke a new unknown (the
current ix ). However, if we add these two equations together we obtain a single equa-
tion for the supernode, which does not require us to invoke the current ix :
V2 − V1 V2 V3 V3 − V4
N 23 + + + = 0. (2.78)
6 10 15 5
This is the supernode equation, and it can be written directly by adding the branch
currents leaving the supernode. Usually, we will do so directly, without the extra step
of first writing the two node equations and adding them. Thus, the node equations for
this example would be directly written, in units of V , A, and Ω, as
N 1 V1 = 12 (known node voltage), (2.79)
V2 − V1 V2 V3 V3 − V4
N 23 + + + = 0 (supernode), (2.80)
6 10 15 5
and
V4 − V1 V4 − V3
N4 + − 0.3 = 0. (2.81)
30 5
Because we wrote a single equation for the supernode we have three equations with
four unknowns. One more equation is needed, and this is the equation of the voltage
source involved in the supernode, developed using KVL:
VS V2 = V3 + 6. (2.82)
Substituting the voltage source equation into the supernode equation, we obtain
N 1 V1 = 12, (2.83)
V3 + 6 − V1 V3 + 6 V3 V3 − V4
N 23VS + + + = 0, (2.84)
6 10 15 5
and
V4 − V1 V4 − V3
N4 + − 0.3 = 0. (2.85)
30 5
We can substitute the node one equation into each of the others to obtain a system of
two equations:
V3 + 6 − 12 V3 + 6 V3 V3 − V4
N 23VS + + + =0 (2.86)
6 10 15 5
and
V4 − 12 V4 − V3
N4 + − 0.3 = 0 (2.87)
30 5
N 123 DS 5V3 − 30 + 3V3 + 18 + 2V3 + 6V3 − 6V4 = 0 (2.88)
and
N 14 V4 − 12 + 6V4 − 6V3 − 9 = 0. (2.89)
N 123 DS 16V3 − 6V4 = 12 (2.90)
and
N 14 − 6V3 + 7V4 = 21. (2.91)
 16 −6   V3   12 
 −6  = . (2.92)
 7   V4   21 
The solution is
12 −6
21 7
V3 = = 2.76 V (2.93)
16 −6
−6 7
and
16 12
−6 21
V4 = = 5.37 V (2.94)
16 −6
−6 7
Nodal Analysis 59
Therefore,
V2 = V3 + 6V = 8.76V (2.95)
ebook+.
2.8 SUMMARY
In this chapter, we considered the NVM, which is a general-purpose tool for solving
electrical circuits. By the NVM, we determine the voltages at the essential nodes
(“node voltages”) with respect to a reference node, and all remaining circuit quanti-
ties may be readily found once these node voltages are known.
The basic NVM involves six steps. First, we identify all ne essential nodes (nodes
connected to more than two elements). Second, we choose one of these to be the
reference node. Third, we number the remaining ( ne − 1) essential nodes. Fourth, we
write ( ne − 1) node equations based on Kirchhoff’s current law. In each node equa-
tion, the sum of the branch currents leaving the node is set to zero. Fifth, we solve this
set of equations using algebraic methods. Sixth, we use the node voltages to solve for
other circuit quantities (voltages, currents, and power values).
If one or more dependent sources appear in the circuit, the controlling variable for
each dependent source must be expressed in terms of the node voltages.
Special cases arise in the NVM when a voltage source (independent or dependent)
is placed between essential nodes. If a voltage source is placed between the reference
node and one of the other essential nodes, then a known node voltage results. If a
voltage source appears between two essential nodes, neither of which is the reference
node, a supernode results. Therefore, the choice of reference node can affect the
character of individual special cases.
To evaluate your mastery of Chapters 1 and 2, solve Example Exam 2.1 in ebook+
or Example Exam 2.2 in ebook+.
PROBLEMS
Problem 2.1. Solve for V1, I x, and the power of the 3 Ω resistor in Figure P2.1.
FIGURE P2.1 Circuit with seven elements and two essential nodes.
Problem 2.2. Determine I1, I 2, and VS of the circuit in Figure P2.2.
FIGURE P2.2 Circuit with three sources and two essential nodes.
Problem 2.3. Find VA and VB for the circuit in Figure P2.3.
FIGURE P2.3 Circuit with seven elements and three essential nodes.
Nodal Analysis 61
Problem 2.4. Determine the values of VX and VY for the network in Figure P2.4.
FIGURE P2.4 Circuit with eight elements and three essential nodes.
Problem 2.5. Find V1, V2, and V3, and the power for the current source in
Figure P2.5.
FIGURE P2.5 Circuit with nine elements, three sources, and four essential nodes.
Problem 2.6. Calculate the values of the voltages VA, VB, and VC in Figure
P2.6. Find the power for each of the current sources.
FIGURE P2.6 Circuit with nine elements, four sources, and four essential nodes.
Problem 2.7. Determine I A, I B, and IC, and the power for the current source
in the circuit in Figure P2.7.
FIGURE P2.7 Circuit with ten elements, four sources, and four essential nodes.
Nodal Analysis 63
Problem 2.8. Solve for I A, I B, IC, and the power of the current source in
Figure P2.8.
FIGURE P2.8 Circuit with six elements, four essential nodes, and one special case.
Problem 2.9. Determine the values of VA and VB of the circuit in Figure P2.9.
FIGURE P2.9 Circuit with eight elements, four essential nodes, and one special case.
Problem 2.10. Calculate VA, VB, and power of the current source in Figure P2.10.
FIGURE P2.10 Circuit with seven elements, four essential nodes, and two special cases.
Problem 2.11. Find the currents I1, I 2, and I 3, and the power for each of the
current sources for the circuit in Figure P2.11.
FIGURE P2.11 Circuit with eleven elements, five sources, and six essential nodes.
Nodal Analysis 65
Problem 2.12. Calculate VA, VB, and VC for the network in Figure P2.12.
FIGURE P2.12 Circuit with ten elements, four sources, and six essential nodes.
Problem 2.13. Calculate ix and the power for the dependent source of the
circuit in Figure P2.13.
FIGURE P2.13 Circuit with eight elements, including a CCCS, and four essential nodes.
Problem 2.14. Determine v x , v y , and the power for each of the sources in
Figure P2.14.
FIGURE P2.14 Circuit with eight elements, including a VCVS, and four essential nodes.
Problem 2.15. Find and the power for each of the resistors for the circuit in
Figure P2.15.
FIGURE P2.15 Circuit with eight elements, including a CCVS, and three essential nodes.
Nodal Analysis 67
Problem 2.16. Determine v x , v y , and vz for the circuit in Figure P2.16.
FIGURE P2.16 Circuit with nine elements, including a VCCS, and five essential nodes.
Problem 2.17. Find ix for the network in Figure P2.17.
FIGURE P2.17 Circuit with seven elements, including a CCCS, and four essential nodes.
Problem 2.18. Determine the currents I X , IY , and I Z ; find the voltage va and
the power for the dependent source in Figure P2.18.
FIGURE P2.18 Circuit with eight elements, including a VCVS, and five essential nodes.
Problem 2.19. For the circuit of Figure P2.19, determine I1, I 2, I 3, and I 4;
show that their sum is zero.
FIGURE P2.19 Circuit with eleven elements, four sources, and seven essential nodes.
Nodal Analysis 69
Problem 2.20. Find ix , v x , and the power for each of the sources for the
FIGURE P2.20 Circuit with thirteen elements, including two dependent sources, and seven
essential nodes.
3 Operational
Amplifier Circuits
3.1 INTRODUCTION TO OPERATIONAL AMPLIFIERS

The operational amplifier (op amp) is an electronic differential amplifier with two
inputs and one output as shown in Figure 3.1. Although a typical op amp contains
a large number of transistors and resistors, our focus will be on the external circuit
behavior. This external behavior may be readily understood by the use of Kirchhoff’s
and Ohm’s laws because commercially available op amps have nearly ideal behavior
in many respects.
The op amp is a differential amplifier and therefore amplifies the difference
between two input voltages. Referring to Figure 3.1, the input terminal marked with
a plus sign is the non-inverting input with the voltage v p applied, and the input ter-
minal marked with a minus sign is the inverting input with the voltage vn applied.
The input currents i p and in flow into the non-inverting and inverting terminals,
respectively. For a real op amp, these currents are so small that they may usually be
neglected. The output terminal emanates from the point of the triangular symbol,
and the voltage at this terminal is Vout . The other two terminals shown on the op amp
are the power terminals; the positive supply is +VCC and the negative supply is −VEE .
The power supplies must be connected to an op amp for it to function; therefore,
these connections are always present even if they are omitted from some circuit
diagrams for simplicity.
The voltage transfer characteristic for a typical op amp is shown in Figure 3.2. In
the linear region of operation, the output voltage is proportional to the difference in
the input voltages:
Vout = A ( v p − vn ) , (3.1)
FIGURE 3.1 Operational amplifier symbol with power connections.
70 DOI: 10.1201/9781003408529-3
Operational Amplifier Circuits 71
FIGURE 3.2 Operational amplifier voltage transfer characteristic.
where A is the open-loop gain of the op amp. Typically, the open-loop gain is
100,000 or more, so for any typical value of the output voltage the difference in
the input voltages ( v p − vn ) = Vout / A is exceedingly small. Therefore, for linear
operation of the op amp, we will usually assume that the two input terminals are at
the same voltage. However, the output voltages are limited by the supply voltages:
even for an ideal op amp, Vout may not be more positive than +VCC or more negative
than −VEE . This gives rise to positive saturation at +VCC and negative saturation
at −VEE . It is important to realize that the open-loop gain does not apply in either
case of saturation, so it is no longer true that the input voltages are approximately
equal.
3.2 ANALYSIS OF OPERATIONAL AMPLIFIER CIRCUITS

For the analysis of op amp circuits, we usually assume that the op amps exhibit ideal
behavior and apply three concepts: the assumption of infinite input impedance (I3),
the virtual short (VS), and a check for saturation.
The assumption of infinite input impedance causes us to consider that the
currents flowing in the inputs of the op amp (both the non-inverting and invert-
ing terminals) are zero. Because the real input currents are typically on the order of
nA, it is reasonable to neglect them as long as the resistances in the circuit are ≤ 1MΩ,
resulting in circuit branch currents ≥ 1µA. The concept of infinite input impedance
applies to linear or saturated operations.
The concept of the virtual short applies to linear operation only, for which the
open-loop gain is operational. The large open-loop gain A of the op amp ensures that
the difference in the input voltages, ( v p − vn ) = Vout / A, is very small (on the order of
µV). Therefore, we will assume that there is a “virtual short” between the inputs
and that v p = vn , for linear operation. It is a “virtual” short because no current can
flow directly between the input nodes even though they are maintained at the same
electric potential. A special case of the virtual short is the “virtual ground”; this
refers to the situation in which one input terminal is grounded and a virtual ground
exists at the other input terminal.
When analyzing an op amp circuit, we always start by assuming linear oper-
ation, but we must then check for saturation. Using the linear assumption, we
make a tentative calculation of the output voltage. If the tentative output voltage is
outside of the range of the supply voltages, we conclude that the op amp is saturated.
Specifically, if the tentative output voltage is more positive than +VCC, we infer posi-
tive saturation and set the output voltage to +VCC. Likewise, if the tentative output
voltage is more negative than −VEE , we infer negative saturation and set the output
voltage to −VEE . In the case of saturation, the virtual short does not apply, so we
must reconsider the value of the voltage at the inverting input. We should also recon-
sider any other quantities that were based on the tentative output voltage, including
currents.
To illustrate the use of these three concepts (the infinite input impedance, virtual
short, and saturation check), we will consider the op amp circuit in Figure 3.3.
We start by assuming linear operation so we can find the tentative output voltage.
The non-inverting input is connected to the ground so
v p = 0. (3.2)
Making use of the virtual short,
vn = v p = 0. (3.3)
FIGURE 3.3 An op amp circuit for analysis.

We can apply Kirchhoff’s current law (KCL) at the inverting input node (units of V,
mA, and kΩ) with the assumption of in = 0 (infinite input impedance):
0 − 5 0 − Vout
′
2+ + = 0, (3.4)
4 2
′ is the tentative output voltage. Multiplying by the least common

where Vout
denominator,
8 − 5 − 2Vout
′ = 0. (3.5)
Solving, we obtain
′ = 1.50 V.
Vout (3.6)
The tentative output voltage is less positive than +VCC = +5V so the op amp is not
saturated, and we conclude that the tentative output voltage is the actual output volt-
age. Having solved for Vout and having verified the value of vn , we can determine all
other circuit quantities. For example,
Vout − vn 1.5V − 0
iout = = = 0.75mA. (3.7)
2 kΩ 2 kΩ
It is important to note that, although the currents flowing in the inputs of the op amp
are zero (infinite input impedance), the output current is generally not zero.
Another important point involves the orientation of the non-inverting and
inverting input terminals. It is tempting to think that the op amp will behave in a
similar fashion, though with a change in the sign of the output voltage, if we inter-
change the non-inverting and inverting terminals in this circuit. This is not true,
however, because although we have made the assumption of the virtual short, there
is actually an infinitesimally small difference between the input voltages, and this
is amplified to create the output voltage. The resistor connected between the output
and the inverting input terminal provides negative feedback, which stabilizes the
output voltage. If we instead connect a feedback resistor between the output and
the non-inverting input, positive feedback results, and the output will be driven to
saturation. As such the feedback resistor must always be connected between the
output and the inverting terminal to provide negative feedback and stabilize
the output.
3.3 ANALYSIS OF A SATURATED OPERATIONAL

AMPLIFIER CIRCUIT
The three concepts introduced in the previous section may be used to analyze any
op amp circuit, including one in which the op amp is saturated. As in the previous
example, we will start by assuming linear operation in order to find a tentative output
voltage. If this tentative output voltage is outside the range of the supply voltages, we
will adjust it accordingly and revisit the voltage at the inverting input. To illustrate
this process, we will use the circuit in Figure 3.4.
We start by assuming linear operation so we can find the tentative output volt-
age. The voltage at the non-inverting input is determined by the independent voltage
source:
v p = 2 V. (3.8)
Making use of the virtual short, the tentative voltage at the inverting input vn′ is
vn′ = v p = 2 V. (3.9)
We can apply KCL at the inverting input node (units of V, mA, and kΩ) with the
assumption of in = 0 (infinite input impedance):
2 − 4 2 − 8 2 − Vout
′
−1 + + + = 0. (3.10)
1 6 3
Multiplying by the least common denominator,
−6 − 12 − 6 + 4 − 2Vout
′ = 0. (3.11)
FIGURE 3.4 An op amp circuit with four independent sources.

Solving, we obtain the tentative output voltage:
′ = −10 V.
Vout (3.12)
The tentative output voltage is more negative than −VEE = −5V so the op amp is satu-
rated, and we need to set the output voltage to the saturated voltage with the same
sign as the tentative output voltage:
Vout = −5V. (3.13)
Because the op amp is saturated, the virtual short does not apply and we must recon-
sider the value of the voltage at the inverting input. This can be done using the node
voltage method at this node. In units of V, mA, and kΩ,
vn − 4 vn − 8 vn − Vout
−1 + + + = 0. (3.14)
1 6 3
−6 + 6 vn − 24 + vn − 8 + 2 vn − 2Vout = 0. (3.15)
Solving,
38 + 2Vout
vn = = 3.11V. (3.16)
9
Having found the true values of Vout and vn , we must use these true values (not tenta-
tive values) to calculate the other voltages and currents in the circuit.
To review, see Presentation 3.1 in ebook+. To test your knowledge, try Quiz
3.1 in ebook+. To put your knowledge to practice, try Laboratory Exercise 3.1 in
ebook+
3.4 ANALYSIS OF A CIRCUIT INVOLVING MULTIPLE OP AMPS

We may analyze circuits containing multiple op amps using the three concepts
of the infinite input impedance, virtual short, and saturation check. However, we
must start the analysis upstream and work our way downstream. To show this, we
will consider the circuit in Figure 3.5, which contains three op amps. Op amps
OA1 and OA2 provide the inputs to OA3; therefore, we must analyze OA1 and
OA2 before OA3.
We will start by analyzing OA1 with the assumption of linear operation. The non-
inverting input is grounded, so assuming a virtual short exists between the inputs we
find the tentative voltage at the inverting input:
V1′ = 0. (3.17)
FIGURE 3.5 A circuit involving multiple op amps.
We can apply KCL at the inverting input node (units of V, mA, and kΩ) with the
assumption that zero current flows into the inverting input terminal (infinite input
impedance):
0 − 2 0 − V2′
−0.5 + 3 + + = 0. (3.18)
4 8
−4 + 24 − 4 − V2′ = 0. (3.19)
V2′ = 16 V. (3.20)
The tentative output voltage is more positive than +VCC = +12 V so the op amp is
saturated, and we need to set the output voltage to +VCC:
V2 = 12 V. (3.21)
Because the op amp is saturated, the virtual short does not apply and we must recon-
sider the value of the voltage at the inverting input. This can be done using the node
voltage method. In units of V, mA, and kΩ,
V1 − 2 V1 − (12 )
−0.5 + 3 + + = 0. (3.22)
4 8
−4 + 24 + 2V1 − 4 + V1 − 12 = 0. (3.23)
4 + 3V1 = 0. (3.24)
Solving,
V1 = −1.333V. (3.25)
Thus, we have solved for the voltages surrounding OA1. We are not ready to find the
current I B because it depends on V5, which is not yet known, and we will save the
calculation of currents for last.
For OA2, we begin by assuming linear operation. Making use of the virtual short,
we consider the tentative voltage at the inverting input to be the same as the voltage
at the non-inverting input:
V3′ = 1V. (3.26)
To find the tentative output voltage for OA2, we can apply KCL at the inverting input
node (units of V, mA, and kΩ) with the assumption that zero current flows into the
inverting input terminal (infinite input impedance):
1 − V4′
−2.5 + = 0. (3.27)
2
−5 + 1 − V4′ = 0. (3.28)
V4′ = −4 V. (3.29)
The tentative output voltage is within the range of the supply voltages, so OA2 is not
saturated and the actual voltages are equal to the tentative voltages:
V3 = 1V (3.30)
and
V4 = −4 V. (3.31)
Next, we consider OA3, starting with the assumption of linear operation. The virtual
short gives rise to a tentative voltage at the inverting input:
V5′ = 0. (3.32)
Making use of the infinite input impedance, the KCL equation for the inverting input
node is (units of V, mA, and kΩ)
0 − V2 0 − V4 0 − V6′
+ + = 0. (3.33)
5 2.5 10
−2V2 − 4V4 − V6′ = 0. (3.34)
The tentative output voltage is
V6′ = −2V2 − 4V4 = −2 (12 V ) − 4 ( −4 V ) = −16 V. (3.35)
The tentative output voltage is more negative than −VEE = −12 V so OA3 is saturated
and the actual output voltage is equal to −VEE :
V6 = −12 V. (3.36)
This causes us to reconsider the voltage at the inverting input, because the virtual
short does not apply in the case of saturation. Using the node voltage method with
units of V, mA, and kΩ,
V5 − V2 V5 − V4 V5 − V6
+ + = 0. (3.37)
5 2.5 10
2V5 − 2V2 + 4V5 − 4V4 + V5 − V6 = 0. (3.38)
Solving,
2V2 + 4V4 + V6 2 (12 V ) + 4 ( −4 V ) + ( −12 V )

V5 = = = −0.571V. (3.39)
7 7
Finally, now that all of the node voltages are known, we can calculate the current
values.
2 V − V1 2 V − ( −1.333 V )
IA = = = 0.833 mA, (3.40)
4 kΩ 4 kΩ
V2 V −V V −V
IB = + 2 1+ 2 5
1kΩ 8 kΩ 5 kΩ
(3.41)
12 V 12 V − ( −1.333 V ) 12 V − ( −0.571V )
= + + = 16.18 mA,
1kΩ 8 kΩ 5 kΩ
V2 − V5 12 V − ( −0.571V )
IC = = = 3.14 mA, (3.42)
5 kΩ 4 kΩ
and
V4 − V3 V4 − V5 −4 V − 1V −4 V − ( −0.571V )
ID = + = + = −4.33 mA. (3.43)
2 kΩ 2.5 kΩ 2 kΩ 2.5 kΩ
This same general process may be used to analyze any circuit involving multiple op
amps with cascading involved.
3.5 INVERTING AMPLIFIER

The three general principles applied to op amp analysis allow us to design op amp
circuits as well. As an example, we will consider the inverting amplifier, which is a
general-purpose building block for op amp design. The inverting amplifier has the
layout shown in Figure 3.6. The non-inverting terminal is grounded. An input voltage
is connected to the inverting input through an input resistor R1 and there is a feedback
resistor RF .
FIGURE 3.6 Inverting amplifier.

If we assume linear operation, the virtual short fixes the voltage at the inverting
input:
vn = v p = 0. (3.44)
If we apply KCL at the inverting input, making use of the infinite input impedance
(in = 0), then
0 − VIN 0 − VOUT
I1 + I F = + = 0. (3.45)
R1 RF
Solving for VOUT ,
R 
VOUT = −  F  VIN . (3.46)
 R1 
The voltage gain VOUT / VIN of this amplifier is − ( RF / R1 ), in which the minus sign
indicates an inverting amplifier and can be interpreted as a phase shift of 180° for
sinusoidal signals. This gain can be set by the ratio of two resistors. Moreover, vari-
able gain may be achieved by making one of the resistors adjustable.
3.6 NON-INVERTING AMPLIFIER

Another general-purpose building block for op amp design is the non-inverting
amplifier shown in Figure 3.7. An input voltage is connected directly to the non-
inverting input. There is a resistor R1 connected between the inverting input and
ground, and there is a feedback resistor RF .
If we assume linear operation, the virtual short fixes the voltage at the inverting input:
vn = v p = VIN . (3.47)
FIGURE 3.7 Non-inverting amplifier.

(in = 0), then
VIN VIN − VOUT

I1 + I F = + = 0. (3.48)
R1 RF
Solving for VOUT ,
 R 
VOUT =  1 + F  VIN . (3.49)
 R1 
The voltage gain VOUT / VIN of this amplifier is (1 + RF / R1 ). The positive gain indi-
cates non-inverting operation. For sinusoidal signals, this means the output voltage
will be in phase with the input voltage. Also, it should be noted that the minimum
absolute value of gain is unity, occurring in the limit as RF / R1 → 0. In this limit,
with RF replaced by a wire and R1 replaced by an open circuit, we obtain a practi-
cal circuit which is a unity-gain buffer. This circuit, shown in Figure 3.8, allows us
to reproduce a voltage from a source node to a target node without drawing current
from the source node. For this reason, it is called a “buffer amplifier” or a “unity-gain
buffer.”
3.7 SUMMING AMPLIFIER

A summing amplifier allows us to scale and add two or more voltage signals. A two-
input summing amplifier is illustrated in Figure 3.9. Each input voltage is applied to
the inverting input terminal through a resistor. The non-inverting input is grounded
and there is a feedback resistor RF .
If we assume linear operation, the virtual short fixes the voltage at the inverting
input:
vn = v p = 0. (3.50)
FIGURE 3.8 Buffer amplifier.

FIGURE 3.9 Summing amplifier.
(in = 0), then
0 − V1 0 − V2 0 − VOUT
I1 + I 2 + I F = + + = 0. (3.51)
R1 R1 RF
Solving for VOUT ,
 R  R  
VOUT = −  F  V1 +  F  V2  . (3.52)

 1R   R2  
The input signals have voltage gain values which may be designed independently,
because although RF is common to both ratios, R1 and R2 may be chosen indepen-
dently. Both terms are negative, indicating inverting behavior. The summing ampli-
fier may be scaled up to three or more inputs by simply connecting additional input
resistors to the inverting input.
3.8 DIFFERENCE AMPLIFIER

A difference amplifier produces the difference in two scaled voltage signals and is
shown in Figure 3.10.
Applying KCL at the inverting input, and making use of the infinite input imped-
ance (in = 0),
vn − V1 vn − VOUT
I A + IB = + = 0. (3.53)
RA RB
Solving,
 R  R 
VOUT =  1 + B  vn −  B  V1. (3.54)
 RA   RA 
FIGURE 3.10 Difference amplifier.
Similarly, at the non-inverting input (i p = 0):
v p − V2 v p − VOUT
IC + I D = + =0 (3.55)
RC RD
Solving for v p,
 RD 
v p = V2  . (3.56)
 RC + RD 
Making use of the virtual short (vn = v p), and substituting this value of into the equa-
tion for VOUT , we obtain
 R   RD  R 
VOUT =  1 + B    V2 −  B  V1. (3.57)
 RA   RC + RD   RA 
Therefore, the output is the difference in the scaled input voltages, and the two scale
factors may be set as desired by choice of the four resistors.
in ebook+.
3.9 DESIGN OF OP AMP CIRCUITS

An op amp circuit may be designed to sum n inputs V1 , V2 , , Vn with gain coefficients
A1 , A2 , , An, such that
VOUT = A1V1 + A2V2 +  + AnVn . (3.58)
Such a design may be achieved by combining inverting, non-inverting, summing, and

difference amplifiers, so the gain coefficients may be positive or negative and may be
fixed by ratios of resistors. It is even possible to make some or all of the gain coef-
ficients adjustable, by introducing potentiometers as variable resistances or variable
voltage dividers.
A potentiometer is a three-terminal device as shown in Figure 3.11. There is a fixed
resistance RP between terminals a and c; there is a third terminal b (the wiper), which
can be physically moved from one end of the resistance to the other by pushing a
slider or rotating a knob. The position of the wiper can be expressed by the parameter
x, where 0 ≤ x ≤ 1. A value of x = 0 corresponds to a wiper position at one end (for
example, at c) while a value of x = 1 corresponds to a wiper position at the other end
(point a). The resistance between terminals b and c is given by xRP , while the resis-
tance between a and b is given by (1 − x ) RP. A potentiometer can be used as a simple
variable resistance by tying the wiper (terminal b) to either of the other terminals.
A variable-gain inverting amplifier can be constructed by using a potentiometer
as a variable feedback resistor as shown in Figure 3.12. For this circuit, the voltage
gain is
VOUT xR
AV = =− P, (3.59)
VIN R1
FIGURE 3.11 Potentiometer.

FIGURE 3.12 Variable-gain inverting amplifier.
where 0 ≤ x ≤ 1, so the gain may be adjusted all the way to zero. As a matter of good
practice, op amp circuits use resistances between 1kΩ and 1MΩ, because smaller
resistances result in excessive current loading and larger resistances result in designs
which are noisy and contain voltage offsets. Thus, if a 10 kΩ potentiometer is used
for the feedback resistor, the maximum absolute value of voltage gain will be 10, cor-
responding to R1 = 1kΩ.
If a non-zero minimum gain (minimum absolute value) is desired in a variable-
gain inverting amplifier, this can be achieved by placing a fixed resistor in series with
the variable resistance as shown in Figure 3.13. The voltage gain is
VOUT xR + R2
AV = =− P , (3.60)
VIN R1
where 0 ≤ x ≤ 1. The maximum value of AV is ( R2 + RP ) / R1, whereas the mini-

mum value is R2 / R1. Therefore, the ratio of maximum gain to minimum gain is
( R2 + RP ) / R2.
A variable-gain non-inverting amplifier may be constructed by using a potentiom-
eter as a variable voltage divider as shown in Figure 3.14. For this circuit, the voltage
gain is
VOUT  R 
AV = = x 1 + F  , (3.61)
VIN  R1 
where 0 ≤ x ≤ 1, so the gain may be adjusted to zero.

If a non-zero minimum gain is desired in a variable-gain non-inverting amplifier,
this can be achieved by placing a fixed resistor in series with the variable resistance
as shown in Figure 3.15. The voltage gain is
VOUT  R2 + xRP   R 
AV = = 1+ F  , (3.62)
VIN  R2 + RP   R1 
FIGURE 3.13 Variable-gain inverting amplifier with non-zero minimum voltage gain.
FIGURE 3.14 Variable-gain non-inverting amplifier.
FIGURE 3.15 Variable-gain non-inverting amplifier with non-zero minimum voltage gain.
where 0 ≤ x ≤ 1. The maximum value of AV is (1 + RF / R1 ) whereas the minimum

value is [ R2 / ( R2 + RP )](1 + RF / R1 ). Therefore, the ratio of maximum gain to mini-
mum gain is ( R2 + RP ) / R2.
A summing amplifier with independent gain adjustment of two voltage signals

may be implemented as shown in Figure 3.16. The output voltage of this adjustable
inverting summer is given by
 R + xRP1   RF   R + xRP 2   RF  
VOUT ≈ −  S1   V1 +  S 2 V2  . (3.63)
 
 RS1 + RP1  R1   RS 2 + RP 2   R2  
This expression is approximate because it does not take into account the loading of
the variable voltage dividers by the input resistors (R1, R2). However, we may neglect
this loading with good accuracy if R1 and R2 are made sufficiently large (R1  RS1,
R1  RP1, R2  RS 2 , and R2  RP 2).
As an example design, we can consider an op amp circuit to produce an output
VOUT with three inputs V1, V2, and V3 as follows:
VOUT = − A1V1 − A2V2 + A3V3 , (3.64)
with A1 fixed ( A1 = 2), with A2 variable from zero to a maximum value ( 0 ≤ A2 ≤ 10 ),

and with A3 adjustable by a factor of ten ( 2 ≤ A3 ≤ 20 ). To combine the signals, we
will need a three-input summing amplifier. The summing amplifier is inherently
inverting, so this will provide the minus signs for the V1 and V2 terms. For the V1
channel, we can use a simple input resistor to the summing amplifier. For the V2
channel, we can use a potentiometer as a variable voltage divider and feed this to an
input resistor to the summing amplifier. For the V3 channel, we can use a variable-
gain inverting amplifier with non-zero minimum gain. The cascade of two inverting
amplifiers will produce a positive coefficient for V3. Combining these ideas, we arrive
at a design layout as shown in Figure 3.17.
FIGURE 3.16 Variable-gain summing amplifier with independent gain adjustment of two
voltage signals.
FIGURE 3.17 Three-input amplifier system with independent gain adjustment for two volt-
age signals.
Next, we need to choose the resistor values, keeping all resistors in the prac-
tical range of 1kΩ − 1MΩ. We will assume that we are using 5% resistors with
standard values, and we will use potentiometers from the set of most common
values (1kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 50 kΩ, and 100 kΩ). We will first choose the feed-
back resistor to be RF = 100 kΩ. Now to achieve a gain of 2.0 for the V1 channel
we can choose
RF 100 kΩ
R1 = = = 50 kΩ. (3.65)
A1 2
We will choose the closest standard value: R1 = 51kΩ. For the V2 channel, we need to
choose R2 in order to provide the maximum required gain:
RF 100 kΩ
R2 = = = 10 kΩ. (3.66)
A2 ( maximum ) 10
The potentiometer RP2 should be chosen to be much smaller than R2 in order to mini-
mize loading, so we will choose RP 2 = 1kΩ . (A small amount of loading here will
affect the linearity of the gain adjustment but will not impact the minimum or maxi-
mum values of gain.) For the V3 channel, we will choose R3 such that the maximum
required gain is achieved in the summing stage:
RF 100 kΩ
R3 = = = 5 kΩ. (3.67)
A3 ( maximum ) 20
We will choose the closest standard value: R3 = 5.1kΩ. The inverting stage must
therefore have gain adjustment in the range of 0.1 − 1.0. Considering the minimum
gain requirement,
RS 3
0.1 = , (3.68)
RA 3
and considering the maximum gain requirement,
RS 3 + RP 3
1.0 = . (3.69)
RA 3
This requires RP 3 / RA3 = 0.9 . If we choose a 10 kΩ potentiometer (RP 3 = 10 kΩ), then

RA3 ≈ 11kΩ. (This is a standard value.) This requires RS 3 ≈ 1.1kΩ (also a standard
value). The completed design is shown in Figure 3.18.
3.10 NON-IDEAL CHARACTERISTICS OF OP AMPS

So far we have assumed ideal op amp behavior. This simplifies the analysis and
design of op amp circuits, and it is also appropriate for most purposes given that
practical op amps approximate ideal ones in many ways. However, it is important
to be aware of non-ideal op amp behavior when designing for high precision or high
frequencies.
FIGURE 3.18 Completed example design.

We would not expect an op amp to respond to arbitrarily high frequencies. A real

op amp has a gain-bandwidth (GBW) product, which limits its response at higher
frequencies. If the op amp is configured in a circuit with a voltage gain of AV , the
expected upper cutoff frequency is
GBW
fc = . (3.70)
AV
For example, if we use an op amp with GBW = 10 MHz to build a circuit with a volt-
age gain of AV = 100, we expect the upper cutoff frequency to be fc = 100 kHz.
For switching applications, in which the op amp output is supposed to take on a
rectangular waveform, another limitation comes into play, and this is the slew rate s.
The rise and fall time for a rectangular wave output are equal to the peak-to-peak
output amplitude divided by the slew rate:
VPP
t R , tF = . (3.71)
s
For example, with a peak-to-peak output amplitude of VPP = 10 V and slew rate
s = 0.5 V/µs, the rise time will be t R = 20 µs.
There are several non-ideal op amp characteristics, which affect DC operation as
well. These include the input bias current, input offset current, input offset voltage,
open-loop gain, input resistance, and output resistance. These are shown in the op
amp model of Figure 3.19. The input bias current I B is the average current, which
flows into each input terminal of the op amp with zero voltage difference applied.
FIGURE 3.19 Model for op amp including some important non-ideal characteristics.
If the input current to the inverting terminal is I B− and the input current to the non-
inverting terminal is I B+, the input bias current is
I B = ( I B + + I B − ) / 2. (3.72)
The input offset current I IO is the difference between the two input currents
I IO = I B + − I B − . (3.73)
When a voltage difference is applied between the input terminals, there is another
current proportional to this voltage difference because of the presence of a finite
input resistance Ri . The output voltage of the op amp is not exactly zero when
there is a zero voltage difference between the input terminals. The input voltage
that must be applied to make the output voltage zero is called the input offset
voltage VIO . The open-loop gain of a real op amp is not infinite but takes on a
very large number. Finally, there is a finite output resistance Ro. Table 3.1 sum-
marizes some ideal characteristics and compares them to typical values for an
LM741 op amp.
To see how these non-ideal characteristics could affect circuit performance, we
can consider a prototypical inverting amplifier with an expected voltage gain of −2.0
as shown in Figure 3.20. If we assume ideal behavior then in = i p = 0, vn = v p = 0,
Vout = −2.000 V, and I out = Vout / RF + Vout / RL = −3.000 mA . For comparison, we can
also consider the circuit of Figure 3.21, which includes a more realistic model for the
op amp including the effects of the finite input bias current, input offset current, input
resistance, output resistance, and open-loop gain.
The node equations for the inverting input node (node Nn) and the output node
(node Nout) are
vn − Vin I v + VIO vn − Vout

Nn + I B + IO + n + =0 (3.74)
R1 2 Ri RF
TABLE 3.1
Ideal and Typical Values of Some Op Amp Characteristics
Parameter Ideal value Typical value for LM741
Gain-bandwidth (GBW) product ∞ 3 MHz
Slew rate (s) ∞ 0.5 MV/s
Input bias current (I B ) 0 30 nA
Input offset current (I IO ) 0 3 nA
Input offset voltage (VIO) 0 0.8 mV
Input resistance (Ri) ∞ 6MΩ
Open-loop gain (A) ∞ 2 × 105
Output resistance (Ro ) 0 50Ω
The LM741 op amp is used as an example for typical characteristics.

FIGURE 3.20 Inverting op amp circuit built with an ideal op amp.
FIGURE 3.21 Inverting op amp circuit constructed with a non-ideal op amp.
and
Vout − vn Vout Vout − A ( −VIO − vn )

Nout + + = 0. (3.75)
RF RL Ro
1 1 1   1   Vin I IO VIO 
Nn vn  + +  + Vout  − R  =  R − I B − 2 − R  (3.76)
R
 1 Ri RF   F  1 i 
and
 1 A  1 1 1   AVIO 
Nout vn  − +  + Vout  + +  = − . (3.77)
 RF Ro   RF RL Ro  Ro 
In matrix form,
 1 1 1 1   Vin I V 
 + + −  − I B − IO − IO
 R R R RF   vn   R1 2 Ri

= 
1 i F
 1 A 1 1 1   Vout   AVIO 
 − + + +   − 
 R F Ro RF RL Ro   Ro 
(3.78)
Solving,
Vin I V 1
− I B − IO − IO −
R1 2 Ri RF
AVIO 1 1 1
− + +
Ro RF RL Ro
vn = (3.79)
1 1 1 1
+ + −
R1 Ri RF RF
1 A 1 1 1
− + + +
RF Ro RF RL Ro
 Vin I IO VIO   1 1 1   1   AVIO 

 R − I B − 2 − R   R + R + R  −  − R   − R 
1 i F L o F o
= , (3.80)
 1 1 1  1 1 1   1  1 A
+ + + + − − − +
 R R R   R
1 i F F RL Ro   RF   RF Ro 
and
1 1 1 Vin I V
+ + − I B − IO − IO
R1 Ri RF R1 2 Ri
1 A AVIO
− + −
RF Ro Ro
Vout = , (3.81)
1 1 1 1
+ + −
R1 Ri RF RF
1 A 1 1 1
− + + +
RF Ro RF RL Ro
and
 1 1 1   AVIO   Vin I IO VIO   1 A

 R + R + R   − R  −  R − I B − 2 − R   − R + R 
1 i F o 1 i F o
= . (3.82)
 1 1 1  1 1 1   1  1 A
+ + + + − − − +
 R R R   R
1 i F F RL Ro   RF   RF Ro 
For example, using Vin = 1V, R1 = 1kΩ, RF = 2 kΩ, RL = 1kΩ, and with the typical
parameters given in Table 3.1, we obtain vn = −0.000789 V and Vout = −2.0023 V .
These values are both within a millivolt of the values obtained using the ideal op
amp model. This is consistent with the fact that the ideal op amp model will almost
always provide adequate accuracy, unless we desire high voltage precision and use
precision resistors with tight tolerances.
3.11 SUMMARY
An operational amplifier (op amp) is a high-gain electronic differential amplifier
having two inputs and a single output. One of the inputs is called the inverting
input and is marked by a minus sign; the other input is the non-inverting input and
is marked by a plus sign. The voltages at the inverting and non-inverting inputs are
called vn and v p, respectively. For linear operation, the output voltage is equal to the
difference of the input voltages multiplied by the open-loop gain for the amplifier:
VOUT = A ( v p − vn ), where A is the open-loop gain and typically has a very high
value of 10 5 − 10 6. The output voltage of the op amp is limited to be in the range
of the power supply voltages. For an ideal op amp, the output will exhibit positive
saturation limited by the positive supply [VOUT ( maximum ) = +VCC ] and negative
saturation limited by the negative supply [VOUT ( minimum ) = −VEE ]. To achieve use-
ful values of voltage gain which are much less than the open-loop gain, negative
feedback is employed by connecting a resistor between the output and the inverting
input of the op amp.
Analysis of an arbitrary op amp circuit can be done by standard circuit analysis
techniques with the use of three concepts specific to op amps. These are the vir-
tual short, infinite input impedance, and the check for saturation. The virtual
short applies to linear operation only; this requires us to start our analysis by first
assuming linear operation so that v p = vn because of the high open-loop gain; by so
doing we can find a tentative value of the voltage at the inverting terminal (vn′). The
infinite input impedance leads us to assume that the currents flowing into the two
input terminals are both zero. This applies to linear and saturation operation. After
starting by assuming linear operation, we calculate the tentative output voltage
′ ). If this tentative output voltage is in the range of the supply voltages, then the
(VOUT
actual output voltage will be equal to the tentative value. If not, then the output will
saturate at the supply voltage having the same sign as the tentative output voltage.
If the output voltage is saturated, we must reconsider the value of vn and any other
circuit quantities which are affected by VOUT . When analyzing a circuit that involves
multiple op amps, some of which feed downstream to others, we must first analyze
the upstream op amps.
Design of op amp circuits can be done to provide scaled sums or differences of

multiple inputs. The scale factors (gain coefficients) are set by ratios of resistors and
may be adjustable if potentiometers are used to achieve variable resistances or vari-
able voltage dividers. Important building blocks for design of op amp circuits include
the inverting amplifier, the non-inverting amplifier, the summing amplifier, and the
difference amplifier.
To put your knowledge to practice, try Laboratory Exercise 3.3 in ebook+.
PROBLEMS
Problem 3.1. Find the currents I A, I B, and IC; find the voltages V1 and V2 with
respect to ground for the circuit in Figure P3.1. Assume that the op amp is
ideal.
FIGURE P3.1 Op amp circuit.

Problem 3.2. For the op amp circuit in Figure P3.2, determine the currents
I A, I B, and IC; find the voltages V1 and V2 with respect to ground. Assume that
the op amp is ideal.
FIGURE P3.2 Op amp circuit involving a single source and three resistors.
Problem 3.3. For the circuit in Figure P3.3, determine the currents I A, I B, IC,
and I D ; find the voltages V1 and V2 with respect to ground. Assume that the
op amp is ideal.
FIGURE P3.3 Op amp circuit involving a single source and four resistors.
Problem 3.4. Determine the currents I A, I B, IC, and I D and find the voltages
V1 and V2 with respect to ground for the circuit in Figure P3.4. Assume that
the op amp is ideal.
FIGURE P3.4 Op amp circuit with a fixed voltage source connected to the noninverting
input and four resistors.
Problem 3.5. For the op amp circuit in Figure P3.5, determine the relation-
ship between Vout and Vin for the case of linear operation, and using this find
the range of Vin for linear operation of the op amp. Assume that the op amp
is ideal.
FIGURE P3.5 Op amp circuit with a variable input voltage connected to the inverting input.
Problem 3.6. Determine the relationship between Vout and Vin for the circuit
of Figure P3.6 for the case of linear operation, and using this find the range
of Vin for linear operation of the op amp. Assume that the op amp is ideal.
FIGURE P3.6 Op amp circuit with a variable input voltage connected to the noninverting
input.
Problem 3.7. For the op amp circuit of Figure P3.7, find the relationship
between Vout and Vin for linear operation, and using this determine the range
of Vin for linear operation of the op amp. Assume that the op amp is ideal.
FIGURE P3.7 Op amp circuit involving a fixed voltage source, a variable input voltage, and
four resistors.
Problem 3.8. For the circuit in Figure P3.8, determine the currents I A, I B,
IC, I D , I E, and I F; find the voltages V1, V2, V3, and V4 with respect to ground.
Assume that the op amps are ideal.
FIGURE P3.8 A circuit involving two op amps.
Problem 3.9. Determine the currents I A, I B, IC, I D , I E, and I F and find the
voltages V1, V2, V3, and V4 with respect to ground for the circuit in Figure
P3.9. Assume that the op amps are ideal.
FIGURE P3.9 A circuit involving two op amps and three voltage sources.
IC, I D , I E, and I F; find the voltages V1, V2, V3, and V4 with respect to ground.
FIGURE P3.10 A circuit involving two op amps, three voltage sources, and six resistors.
voltages V1, V2, V3, and V4 with respect to ground for the circuit in Figure P3.11.
FIGURE P3.11 A circuit involving two op amps, three voltage sources, two current sources,
and six resistors.
Problem 3.12. Considering the circuit in Figure P3.12, is there a range of

values of Vin for which OA1 will be linear? If so determine this range. Is
there a range of values of Vin for which OA2 will be linear? If so, determine
this range. If there is a range of values of Vin for which both op amps are
linear, find this range and the equation relating Vout to Vin .
FIGURE P3.12 A circuit involving two op amps, three voltage sources, and six resistors.
Problem 3.13. Considering the circuit in Figure P3.13, is there a range of val-
ues of Vin for which OA1 will be linear? If so determine this range. Is there
a range of values of Vin for which OA2 will be linear? If so, determine this
range. If there is a range of values of Vin for which both op amps are linear,
find this range and the equation relating Vout to Vin .
FIGURE P3.13 A circuit involving two op amps, two fixed voltage sources, a variable input
voltage, and six resistors.
Problem 3.14. For the circuit in Figure P3.14, choose the values of the resis-
tors so that Vout = −4VA − 10VB. Use standard resistor values. The nominal
voltage gains, before taking into account resistor tolerances, should be
within 10% of the desired values. Assume that the op amps are ideal.
FIGURE P3.14 Op amp circuit with two input voltages and three unspecified resistors.
Problem 3.15. Choose values of the resistors in the circuit in Figure P3.15 so
that Vout = 20 (VB − VA ). Use standard resistor values. The nominal voltage
gains, before taking into account resistor tolerances, should be within 10%
of the desired values. Assume that the op amps are ideal (Figure P3.15).
FIGURE P3.15 Op amp circuit with two input voltages and four unspecified resistors.
Problem 3.16. Choose values of the resistors of the circuit in Figure P3.16
so that Vout = −12VA − 8VB + 4VC. Use standard resistor values. The nomi-
nal voltage gains, before taking into account resistor tolerances, should be
within 10% of the desired values. Assume that the op amps are ideal.
FIGURE P3.16 Op amp circuit with three input voltages and five unspecified resistors.
Problem 3.17. Choose values of the unspecified resistors of the circuit in

Figure P3.17 so that the absolute value of voltage gain for V1 is adjustable
from 0 to 20 and the absolute value of voltage gain for V2 is adjustable from
0 to 40. Use standard 5% resistor values. The nominal voltage gains, before
taking into account resistor tolerances, should be within 10% of the desired
values. Assume that the op amps are ideal.
FIGURE P3.17 Circuit involving three op amps and two potentiometers for gain adjustment.
Problem 3.18. Choose values of the unspecified resistors of the circuit in

Figure P3.18 so that the absolute value of voltage gain for V1 is adjustable
from 5 to 20 and the absolue value of voltage gain for V2 is adjustable from
10 to 40. Use standard 5% resistor values. The nominal voltage gains, before
taking into account resistor tolerances, should be within 10% of the desired
values. Assume that the op amps are ideal.
FIGURE P3.18 Circuit involving three op amps and two potentiometers for gain adjustment.
Problem 3.19. Choose values of the potentiometers and resistors of the cir-
cuit shown in Figure P3.19 so that the absolute value of the voltage gain for
VA is adjustable from 0 to 15 and the absolute value of the voltage gain for VB
is adjustable from 10 to 100. You may use potentiometers with any of the fol-
lowing values: 5 kΩ, 10 kΩ, and 20 kΩ. For the fixed resistors, use standard
5% values. The nominal voltage gains, before taking into account resistor
and potentiometer tolerances, should be within 10% of the desired values.
FIGURE P3.19 Op amp circuit with two potentiometers for gain adjustment.
Problem 3.20. Design an op amp circuit based on the diagram of figure

P3.20 so that Vout = − aVA − bVB , where VA and VB are the input voltages and
the gain coefficients are adjustable according to the following: 0 ≤ a ≤ 50
and 10 ≤ b ≤ 100. Potentiometers of values 5 kΩ, 10 kΩ, or 20 kΩ may be
used. Use standard 5% fixed resistor values. The nominal voltage gains,
before taking into account resistor tolerances, should be within 10% of the
desired values. Assume that the op amps are ideal.
FIGURE P3.20 Op amp circuit with two input voltages, each with adjustable gain
Problem 3.21. For the op amp circuit in Figure P3.21, determine the currents
I A, I B, IC, I D , I E, and I F; find the voltages V1, V2, V3, V4, V5, and V6 with respect
to ground. Assume that the op amps are ideal.
FIGURE P3.21 Circuit involving three op amps and two voltage sources.
IC, I D , I E, and I F; find the voltages V1, V2, V3, V4, V5, and V6 with respect to
ground. Assume that the op amps are ideal.
FIGURE P3.22 Circuit involving three op amps, two voltage sources, and eight resistors.
voltages V1, V2, V3, V4, V5, and V6 with respect to ground of the circuit in
Figure P3.23. Assume that the op amps are ideal.
FIGURE P3.23 Circuit involving three op amps, five voltage sources, two current sources,
and ten resistors.
IC, I D , I E, and I F; find the voltages V1, V2, V3, V4, V5, and V6 with respect to
ground. Assume that the op amps are ideal.
FIGURE P3.24 Circuit involving three op amps, four voltage sources, two current sources,
and twelve resistors.
IC, I D , I E, I F, I G , and I H ; find the voltages V1, V2, V3, V4, V5, V6, V7, and V8 with
respect to ground. Assume that the op amps are ideal.
FIGURE P3.25 Circuit involving four op amps.

4 Mesh Analysis
4.1 INTRODUCTION AND BASIC DEFINITIONS

The mesh current method (MCM), also known as mesh analysis, is an important
circuit analysis technique, which complements the node voltage method (NVM).
Like the NVM, it is intended to allow the solution of a circuit with the minimum
number of equations. However, some circuits lend themselves to easier analysis
with the MCM; this is especially true for circuits containing transformers. On
the other hand, some circuits especially those involving op amps are more easily
analyzed by the NVM. It is therefore important to master both NVM and MCM.
In many cases, you may want to first consider both methods before settling on one
over the other.
To describe the MCM, it is necessary to first give some basic definitions. A path
is a trace of adjoining elements with none repeated. A loop is a path that begins and
ends at the same point. A mesh is a loop that does not enclose another loop. The
circuit in Figure 4.1 contains three meshes: these are ABED, BCFE, and DEFHG.
The loop ABCFED is not a mesh because it encloses the loops ABED and BCFE.
The outer loop ABCFHGD is not a mesh because it encloses ABED, BCFE, and
DEFHG.
FIGURE 4.1 A circuit with three meshes.
114 DOI: 10.1201/9781003408529-4

Mesh Analysis 115
4.2 APPLICABILITY OF THE MESH CURRENT METHOD

The MCM is applicable only to planar circuits. A planar circuit is one which may
be drawn on a flat piece of paper without the use of crossovers. In the case of a non-
planar circuit, we are unable to define mesh currents without ambiguities or contra-
dictions, and therefore the NVM must be used for non-planar circuits.
The circuit shown in Figure 4.2 is non-planar because it cannot be drawn without
crossovers. Therefore, the MCM is not applicable to this circuit, and we would need
to use the NVM instead.
The circuit shown in Figure 4.3 initially appears to be non-planar, because it
includes two crossovers. However, it may be redrawn without the use of crossovers
as shown in Figure 4.4, and therefore, we could analyze this circuit using the MCM.
(This circuit includes five meshes.)
4.3 THE BASIC MESH CURRENT METHOD (MCM)

To illustrate the basic MCM, we will use the circuit in Figure 4.5 as an example.
There are five steps in the MCM. First, we identify the meshes; the example circuit
has two.
The second step is to label and number the mesh currents as shown in Figure 4.6.
As a matter of convention, we define all mesh currents to flow clockwise. Although
it is possible to define counterclockwise mesh currents or even mix clockwise and
counterclockwise currents, it is strongly recommended that you adhere to the clock-
wise convention in order to avoid sign errors. The numbering is arbitrary and may be
chosen for convenience; the basic quantities in the circuit are invariant with respect
to our chosen numbering of the mesh currents.
FIGURE 4.2 A non-planar circuit.

FIGURE 4.3 A planar circuit that uses unnecessary crossovers.
FIGURE 4.4 The circuit of the previous figure redrawn without the use of crossovers, show-
ing that it is planar.
The third step is to write an equation for each mesh using Kirchhoff’s voltage law
(KVL). Each mesh equation is developed by moving clockwise around the mesh and
adding the voltage drops. This means that, when moving clockwise, we add a term if
we arrive at the plus sign first but subtract the term if we arrive at the minus sign first.
With reference to Figure 4.7, the two mesh equations are therefore (with numerical
quantities in units of V)
M 1 − 5 + VA + VB + VC = 0 (4.1)
Mesh Analysis 117
FIGURE 4.5 Example circuit with two meshes.
FIGURE 4.6 Example circuit with the mesh currents labeled.
FIGURE 4.7 Example circuit with branch currents and voltage drops labeled.
and
M 2 − VB + VD + VE + 12 = 0. (4.2)
The mesh equations are not too useful in this form, because we have six unknowns but
only two equations. We therefore must express the individual voltage drops in terms of
the mesh currents. This requires us to relate branch currents to the mesh currents and
use these to find the voltage drops around each mesh. Referring to Figure 4.7, it can
be seen that the mesh current I1 flows clockwise in the 3 Ω resistor, the 5 V source, and
the 2 Ω resistor. However, the 5 Ω resistor is common to both meshes and the current
( I1 − I 2 ) flows from top to bottom. (This can be confirmed by the use of Kirchhoff’s
current law (KCL) at the bottom node.) Using Ohm’s law, with units of V, A, and Ω,
we can find the voltage drops in mesh one to be VA = 2 I1, VB = 5 ( I1 − I 2 ), and VC = 3I1.
Similarly, the voltage drops in mesh two are VD = 4 I 2 and VE = 1I 2 .
The two mesh equations may therefore be written with units of V, A, and Ω as
M 1 − 5 + 2 I1 + 5 ( I1 − I 2 ) + 3 I1 = 0 (4.3)
and
M 2 5 ( I 2 − I1 ) + 4 I 2 + 1I 2 + 12 = 0. (4.4)
Collecting like terms, we obtain
M 1 10 I1 − 5I 2 = 5 (4.5)
and
M 2 − 5I1 + 10 I 2 = −12. (4.6)
It should be noted that in the M1 equation the I1 coefficient is positive but the I 2 coef-
ficient is negative. The opposite is true in the M2 equation. In general, when writing
the nth mesh equation, the coefficient for the nth mesh current will be positive while
all others will be negative, and this is sometimes helpful when checking for sign
errors. The exception to this rule occurs when the circuit contains dependent sources.
In matrix form, the mesh equations are
 10 −5   I1   5 
 −5  = . (4.7)
 10   I 2   −12 
The fourth step in the MCM is to solve for the mesh currents:
5 −5
−12 10
I1 = = −0.1333 A (4.8)
10 −5
−5 10
Mesh Analysis 119
and
10 5
−5 −12
I2 = = −1.267 A (4.9)
10 −5
−5 10
The fifth step in application of the MCM is to determine other circuit quantities as
needed by using the mesh current values. As an example, the power in the 5 Ω resis-
tor is
P5Ω = 5 Ω ( I1 − I 2 ) = 5 Ω  −0.1333 A − ( −1.267 A )  = 6.43 W.

2 2
(4.10)
4.4 THE MESH CURRENT METHOD WITH

MORE THAN TWO MESHES
The MCM may be readily extended to more than two meshes. When solving a circuit
with nm meshes, we will have nm mesh equations to solve for nm mesh currents (unless
there are special cases, to be described in the next two sections). To illustrate this, we
will solve the circuit in Figure 4.8, which contains four meshes.
We will use the mesh numbering scheme shown in Figure 4.9. (We could use a
different choice of mesh numbers if we prefer. This would change the definition of
the mesh currents and therefore the values of I1, I 2, I 3, and I 4, but it would not change
basic circuit quantities such as I X .)
The mesh equations with units of V, A, and Ω are
M 1 15 + 5I1 + 7 ( I1 − I 3 ) + 4 ( I1 − I 2 ) = 0, (4.11)
FIGURE 4.8 Example circuit with four meshes.

FIGURE 4.9 Example circuit with four meshes labeled.
M 2 − 10 + 4 ( I 2 − I1 ) + 9 ( I 2 − I 3 ) + 2 I 2 = 0, (4.12)
M 3 9 ( I 3 − I 2 ) + 7 ( I 3 − I1 ) + 12 ( I 3 − I 4 ) + 6 I 3 = 0, (4.13)
and
M 4 12 ( I 4 − I 3 ) − 20 + 8 I 4 = 0. (4.14)
M 1 16 I1 − 4 I 2 − 7 I 3 = −15, (4.15)
M 2 − 4 I1 + 15I 2 − 9 I 3 = 10, (4.16)
M 3 − 7 I1 − 9 I 2 + 34 I 3 − 12 I 4 = 0, (4.17)
and
M 4 − 12 I 3 + 20 I 4 = 20. (4.18)
In matrix form,
 16 −4 −7 0  I1  
−15 
    
 −4 15 −9 0  I2   10 
  = . (4.19)
 −7 −9 34 −12  I3   0 
 0 0 −12 20  I4   20 
     
Mesh Analysis 121
It should be noted that the zero coefficients must be entered into the matrix. Solving,
−15 −4 −7 0
10 15 −9 0
0 −9 34 −12
20 0 −12 20
I1 = = −0.410 A, (4.20)
16 −4 −7 0
−4 15 −9 0
−7 −9 34 −12
0 0 −12 20
16 −15 −7 0
−4 10 −9 0
−7 0 34 −12
0 20 −12 20
I2 = = 0.954 A, (4.21)
16 −4 −7 0
−4 15 −9 0
−7 −9 34 −12
0 0 −12 20
16 −4 −15 0
−4 15 10 0
−7 −9 0 −12
0 0 20 20
I3 = = 0.661A, (4.22)
16 −4 −7 0
−4 15 −9 0
−7 −9 34 −12
0 0 −12 20
and
16 −4 −7 −15
−4 15 −9 10
−7 −9 34 0
0 0 −12 20
I4 = = 1.397 A. (4.23)
16 −4 −7 0
−4 15 −9 0
−7 −9 34 −12
0 0 −12 20
Having found the mesh currents, we can easily determine all other circuit quantities.
For example,
I X = I 3 − I 2 = 0.661A − 0.954 A = −0.293 A. (4.24)
The MCM is especially convenient when we need to find the power for voltage
sources. In this example,
P10 V = ( −1) (10 V ) I 2 = ( −1) (10 V )( 0.954 A ) = −9.54 W. (4.25)
P15V = (15 V ) I1 = (15 V )( −0.410 A ) = −6.15 W. (4.26)
P20 V = ( −1) ( 20 V ) I 4 = ( −1) ( 20 V )(1.397 A ) = −27.9 W. (4.27)
Multiplication by −1 was necessary in the power calculations for the 10 and 20 V

sources according to the passive sign convention, because in both cases the reference
direction for the electrical current was entering the negative terminal for the voltage
source. All three power values are negative, indicating that all three voltage sources
are developing power.
4.5 THE MESH CURRENT METHOD WITH

A KNOWN MESH CURRENT
In the MCM, special cases arise whenever there is a current source (independent or
dependent) in the circuit. If the current source appears on the periphery of the circuit,
and only in one mesh, it gives rise to a known mesh current (KMC). If the current
Mesh Analysis 123
source is on the interior of the circuit, and shared by two meshes, it gives rise to a
supermesh. (The supermesh will be described in more detail in the next section.)
An example of a circuit with a KMC is shown in Figure 4.10. Here, there are three
meshes, and we would generally expect to set up and solve three mesh equations.
However, the presence of a special case allows us to reduce the system to two equa-
tions. In general, if there are nm meshes and ns special cases, the system will reduce
to ( nm − ns ) equations.
We will use the mesh numbering scheme shown in Figure 4.11. Here, there is a
current source in mesh one, so I1 is a KMC: I1 = −1A. The minus sign results from
the fact that the direction for the current source (counterclockwise) is opposite to the
FIGURE 4.10 A circuit having a KMC.
FIGURE 4.11 A circuit having a KMC with the mesh currents labeled.
reference direction for the mesh current (clockwise). The other two mesh equations
can be written in the normal fashion, using KVL. Therefore, the three mesh equa-
tions with units of V, A, and Ω are
M 1 I1 = −1, (4.28)
M 2 2 ( I 2 − I1 ) + 4 I 2 + 25 + 6 ( I 2 − I 3 ) = 0, (4.29)
and
M 3 7 ( I 3 − I1 ) + 6 ( I 3 − I 2 ) + 9 I 3 + 4 I 3 = 0. (4.30)

M 1 I1 = −1, (4.31)
M 2 − 2 I1 + 12 I 2 − 6 I 3 = −25, (4.32)
and
M 3 − 7 I1 − 6 I 2 + 26 I 3 = 0. (4.33)
Substituting M1 into M2 and M3,
M 1M 2 12 I 2 − 6 I 3 = −27, (4.34)
and
M 1M 3 − 6 I 2 + 26 I 3 = −7. (4.35)
In matrix form,
 12 −6   I 2   −27 
 −6  = . (4.36)
 26   I 3   −7 
Solving,
−27 −6
−7 26
I2 = = −2.70 A (4.37)
12 −6
−6 26
Mesh Analysis 125
and
12 −27
−6 −7
I3 = = −0.891A. (4.38)
12 −6
−6 26
Other circuit quantities may be determined as needed. For example,
VZ = ( 9 Ω ) I 3 = ( 9 Ω )( −0.891A ) = −8.02 V (4.39)
and
P25V = ( 25 V ) I 2 = ( 25 V )( −2.70 A ) = −67.5 W (4.40)
Whereas the MCM allows very convenient determination of power for voltage
sources, power determination for a current source is somewhat cumbersome because
we have to apply KVL to find the voltage across the current source. For example,
P1A = (1A ) ( 3 Ω ) ( I1 ) + ( 2 Ω ) ( I1 − I 2 ) + ( 7 Ω ) ( I1 − I 3 ) + (1 Ω ) ( I1 )

(4.41)
= −1.363 W.
4.6 THE MESH CURRENT METHOD WITH A SUPERMESH

Another special case in the MCM is the supermesh; this is introduced by a current
source (independent or dependent) which is on the interior of the circuit, and shared
by two meshes. An example is shown in Figure 4.12.
If we use the mesh numbering shown in Figure 4.13, then meshes two and three
together constitute a supermesh. If we attempt to write mesh equations for each of the
individual meshes, we have to invoke a new variable v x , which represents the voltage
drop across the current source in the supermesh. In units of V, A, and Ω,
M 1 − 12 + 6I1 + 1I1 + 4 + 8 ( I1 − I 3 ) + 3 ( I1 − I 2 ) = 0, (4.42)
M 2 − 10 + 3 ( I 2 − I1 ) + v x + 4 I 2 = 0, (4.43)
and
M 3 − v x + 8 ( I 3 − I1 ) + 3I 3 + 2 I 3 = 0. (4.44)
As it stands, the previous set of equations may not be solved because there are four
unknowns but only three equations. It is therefore more useful to write a single equa-
tion for the supermesh. This could be found by adding the M2 and M3 equations, but
FIGURE 4.12 A circuit containing a supermesh.
FIGURE 4.13 A circuit having a supermesh with the mesh currents labeled.
usually we will write the supermesh equation directly by use of KVL. Therefore, the
mesh equations are
M 1 − 12 + 6I1 + 1I1 + 4 + 8 ( I1 − I 3 ) + 3 ( I1 − I 2 ) = 0 (4.45)

Mesh Analysis 127
and
M 23 − 10 + 3 ( I 2 − I1 ) + 8 ( I 3 − I1 ) + 3I 3 + 2 I 3 + 4 I 2 = 0. (4.46)
One more equation is needed and this is the equation of the current source:
CS I3 − I2 = 2 (4.47)
or
CS I 3 = I 2 + 2. (4.48)
This equation may be obtained by use of KCL at the bottom node. If we substitute
this current source equation into the M1 and M23 equations, we obtain a set of two
equations with two unknowns:
M 1CS − 12 + 6 I1 + 1I1 + 4 + 8 ( I1 − I 2 − 2 ) + 3 ( I1 − I 2 ) = 0 (4.49)
and
M 23CS − 10 + 3 ( I 2 − I1 ) + 8 ( I 2 + 2 − I1 ) + 3 ( I 2 + 2 ) + 2 ( I 2 + 2 ) + 4 I 2 = 0. (4.50)

M 1CS 18 I1 − 11I 2 = 24 (4.51)
and
M 23CS − 11I1 + 20 I 2 = −16. (4.52)
In matrix form,
 18 −11   I1   24 
 −11  = (4.53)
 20   I 2   −16 
Solving,
24 −11
−16 20
I1 = = 1.272 A (4.54)
18 −11
−11 20
and
18 24
−11 −16
I2 = = −0.1004 A. (4.55)
18 −11
−11 20
Using the current source equation,
I 3 = I 2 + 2 = 1.900 A. (4.56)
To review, see Presentation 4.2 in ebook+.To test your knowledge, try Quiz 4.2 in
ebook+.
4.7 THE DOUBLE SUPERMESH

As another example, consider the case of the double supermesh shown in Figure 4.14.
The meshes are labeled in Figure 4.15, and we see that mesh two contains two cur-
rent sources, each shared by an adjacent mesh. Therefore, meshes one, two, and three
together constitute a double supermesh.
In units of V, A, and Ω, the double supermesh equation is
M 123 − 9 + 3I1 + 1.5I 2 − 6 + 1I 3 + 4 I 3 + 2 I 2 + 2.5I1 = 0. (4.57)
In addition to this, we need to write the equation for each of the two current sources.
We will refer to the left-hand source as current source one (CS1) and the right-hand
source as current source two (CS2).
CS1 2 = I 2 − I1 , or I1 = I 2 − 2 (4.58)
FIGURE 4.14 A circuit containing a double supermesh.
FIGURE 4.15 A circuit containing a double supermesh with the meshes labeled.
Mesh Analysis 129
and
CS 2 3 = I 2 − I 3 , or I 3 = I 2 − 3. (4.59)
Collecting like terms in the double supermesh equation,
M 123 5.5I1 + 3.5I 2 + 5I 3 = 15. (4.60)
Substituting the CS1 and CS2 equations into the double supermesh equation,
M 123CS1CS 2 5.5 ( I 2 − 2 ) + 3.5I 2 + 5 ( I 2 − 3) = 15. (4.61)
Simplifying,
M 123CS1CS 2 14 I 2 = 41. (4.62)
Solving,
I 2 = 2.929 A, (4.63)
I1 = I 2 − 2 A = 0.929 A, (4.64)
and
I 2 = I 2 − 3 A = −0.071A. (4.65)
Of course, it would be possible to have triple supermeshes, quadruple supermeshes,

and so on, but we do not expect higher-order supermeshes to be common in practical
circuits.
4.8 A SUPERMESH CONTAINING A KNOWN MESH CURRENT

In the previous section, we illustrated one combination of two special cases in the
MCM: it was the combination of two supermeshes into a double supermesh. Here, we
consider a second possibility of combining two special cases, which is a supermesh
containing a KMC. Such a situation is shown in Figure 4.16, and with the meshes
labeled in Figure 4.17.
The right-hand current source is on the periphery and within a single mesh so it
gives rise to a KMC: I 3 = −25 mA . The 10 mA current source is shared by meshes
two and three and therefore creates a supermesh. We will not write the supermesh
equation in this case, because to do so we would need to invoke a new unknown vari-
able to represent the voltage across the 25 mA current source. However, because I 3
FIGURE 4.16 A circuit having a supermesh that contains a KMC.
FIGURE 4.17 A circuit having a supermesh that contains a KMC with the meshes labeled.
is known we can use the equation of the 10 mA current source to find I 2. The set of
three equations in units of V, mA, and kΩ is
M 1 − 40 + 2.5I1 + 3 ( I1 − I 2 ) + 1I1 = 0, (4.66)
CS1 10 = I 3 − I 2 , or I 2 = I 3 − 10, (4.67)
and
M 3 I 3 = −25 mA. (4.68)
Substituting the M3 equation into the CS1 equation,
CS1M 3 I 2 = I 3 − 10 mA = −35 mA. (4.69)
Substituting the value of I 2 into the M1 equation,
M 1CS1M 3 − 40 + 2.5I1 + 3 ( I1 − ( −35)) + 1I1 = 0. (4.70)
Simplifying,
M 1CS1M 3 6.5I1 = 145. (4.71)

Mesh Analysis 131
Solving,
I1 = 22.3 mA. (4.72)
4.9 THE MESH CURRENT METHOD WITH A DEPENDENT SOURCE

When a dependent source appears in a circuit, the value of the controlling variable
(and therefore the value of the source) must be expressed in terms of the mesh cur-
rents. If the dependent source is a current source, it will give rise to a special case –
either a KMC or a supermesh. To illustrate these ideas, we can consider the circuit
in Figure 4.18, which contains a current-controlled voltage source. The meshes are
labeled in Figure 4.19.
This circuit has three meshes and no special cases, so we will solve a system of
three mesh equations. In units of V, A, and Ω,
M 1 − 4 + 2.5I1 + 1( I1 − I 3 ) + 3 ( I1 − I 2 ) = 0, (4.73)
M 2 3ix + 3 ( I 2 − I1 ) + 2 ( I 2 − I 3 ) + 1.5I 2 = 0, (4.74)
and
M 3 2 ( I 3 − I 2 ) + 1( I 3 − I1 ) + 0.5I 3 + 2 = 0. (4.75)
The equation of the dependent source is
DS ix = I 3 . (4.76)
FIGURE 4.18 A circuit containing a dependent source (a current-controlled voltage source).

FIGURE 4.19 A circuit containing a dependent source (current-controlled voltage source)

with the mesh currents labeled.
Substituting this into the M2 equation,
M 1 − 4 + 2.5I1 + 1( I1 − I 3 ) + 3 ( I1 − I 2 ) = 0, (4.77)
M 2 DS 3I 3 + 3 ( I 2 − I1 ) + 2 ( I 2 − I 3 ) + 1.5I 2 = 0, (4.78)
and
M 3 2 ( I 3 − I 2 ) + 1( I 3 − I1 ) + 0.5I 3 + 2 = 0. (4.79)
M 1 6.5I1 − 3I 2 − I 3 = 4, (4.80)
M 2 DS − 3I1 + 6.5I 2 + I 3 = 0, (4.81)
and
M 3 − I1 − 2 I 2 + 3.5I 3 = −2. (4.82)
In matrix form,
 6.5 −3 −1   I1   4 
 −3  I   .
 6.5 1  2 = 0  (4.83)
 −1 −2 3.5   I 3   −2
 
Mesh Analysis 133
Solving,
4 −3 −1
0 6.5 1
−2 −2 3.5
I1 = = 0.768 A, (4.84)
6.5 −3 −1
−3 6.5 1
−1 −2 3.5
6.5 4 −1
−3 0 1
−1 −2 3.5
I2 = = 0.375 A, (4.85)
6.5 −3 −1
−3 6.5 1
−1 −2 3.5
and
6.5 −3 4
−3 6.5 0
−1 −2 −2
I3 = = −0.1376 A. (4.86)
6.5 −3 −1
−3 6.5 1
−1 −2 3.5
As another example, consider the circuit in Figure 4.20. Here, the dependent source
is a voltage-controlled current source (VCCS), and it gives rise to a special case
because it is a current source.
We will use the mesh numbering shown in Figure 4.21. There are three meshes.
The dependent source is a current source shared by two meshes so it gives rise to a
supermesh.
The mesh equations in units of V, mA, and kΩ are
M 12 − 10 + 2 I1 + 4 I 2 + 1I 2 + 6 ( I 2 − I 3 ) + 1.5 ( I1 − I 3 ) = 0 (4.87)
and
M 3 1.5 ( I 3 − I1 ) + 6 ( I 3 − I 2 ) + 5I 3 − 20 = 0. (4.88)
DS I 2 − I1 = 2 v x = 3 ( I 3 − I1 ) = 0 (4.89)
FIGURE 4.20 A circuit containing a dependent source.
FIGURE 4.21 A circuit containing a dependent source with the mesh currents labeled.
or
DS I1 = 1.5I 3 − 0.5I 2 . (4.90)
Collecting like terms in the mesh equations,
M 12 3.5I1 + 11I 2 − 7.5I 3 = 10 (4.91)

Mesh Analysis 135
and
M 3 − 1.5I1 − 6 I 2 + 12.5I 3 = 20. (4.92)
Substituting the dependent source equation into the supermesh equation and the
mesh three equation,
M 12 DS 3.5 (1.5I 3 − 0.5I 2 ) + 11I 2 − 7.5I 3 = 10 (4.93)
and
M 3 DS − 1.5 (1.5I 3 − 0.5I 2 ) − 6 I 2 + 12.5I 3 = 20. (4.94)
Simplifying,
M 12 DS 9.25I 2 − 2.25I 3 = 10 (4.95)
and
M 3 DS − 5.25I 2 + 10.25I 3 = 20. (4.96)
In matrix form,
 9.25 −2.25   I 2   10 
 −5.25  = . (4.97)
 10.25   I 3   20 
Solving,
10 −2.25
20 10.25
I2 = = 1.777 mA (4.98)
9.25 −2.25
−5.25 10.25
and
9.25 10
−5.25 20
I3 = = 2.86 mA. (4.99)
9.25 −2.25
−5.25 10.25
Using the dependent source equation,
I1 = 1.5I 3 − 0.5I 2 = 1.5 ( 2.86 mA ) − 0.5 (1.777 mA ) = 3.40 mA. (4.100)
ebook+.
4.10 CHOOSING BETWEEN THE MCM AND THE NVM

Before solving a problem, we will generally consider both the MCM and the NVM
to determine which method will require fewer equations. A solution using fewer
equations is not only more efficient but also less prone to errors. To illustrate
this, we will consider several example circuits, starting with the one shown in
Figure 4.22.
This circuit has six meshes, as indicated in Figure 4.23. There is a single special
case; the current source in mesh two gives rise to a KMC. Therefore, the number of
equations that must be solved in the MCM reduces to nm − nsm = 6 − 1 = 5, where nm
is the number of meshes and nsm is the number of special cases for the MCM.
FIGURE 4.22 A circuit with six meshes and six essential nodes.
FIGURE 4.23 A circuit with six meshes and six essential nodes, with the meshes labeled.
Mesh Analysis 137
This circuit also has six essential nodes, as shown in Figure 4.24, but there are four
voltage sources resulting in four special cases for the NVM. If we make the bottom
node the reference node, then we have known node voltages at node three and node
five. Nodes one and three together constitute a supernode, but this involves a known
node voltage so the voltage at node one can be determined immediately. Nodes two
and four together constitute another supernode. Accounting for these special cases,
the number of equations that must be solved when using the NVM will reduce to
ne − nsn − 1 = 6 − 4 − 1 = 1, where ne is the number of essential nodes and nsn is the
number of special cases for the NVM. Therefore, we would clearly choose the NVM,
requiring one equation, over the MCM, requiring five equations, for this circuit.
Now consider the circuit of Figure 4.25.
This circuit has six meshes, as indicated in Figure 4.26. There are two special
cases: meshes one and two make up a supermesh while mesh six has a KMC. The
number of equations that must be solved in the MCM reduces to nm − nsm = 6 − 2 = 4 .
This circuit has only three essential nodes, as indicated in Figure 4.27. There
are no special cases for the NVM because none of the voltage sources is connected
directly between essential nodes. (There is a series resistor involved in each case.)
Hence, the number of equations to be solved is ne − nsn − 1 = 3 − 0 − 1 = 2. Once again,
we would choose the NVM as the more efficient approach.
As a third example consider the circuit in Figure 4.28. This circuit is non-planar
and cannot be solved using the MCM. Hence, we need to use the NVM. In this case,
there are 16 essential nodes, with one supernode involving nodes two and three, so
we will need to solve 14 equations (Figure 4.29).
By now you may feel that we will never use the MCM. This is not true; although
we tend to use the NVM more often, we will not use it exclusively. For example,
FIGURE 4.24 A circuit with six meshes and six essential nodes, with the essential nodes
labeled.
FIGURE 4.25 A circuit with six meshes and three essential nodes.
FIGURE 4.26 A circuit with six meshes and three essential nodes, with the meshes labeled.
consider the circuit in Figure 4.30. This circuit contains five meshes, as labeled in
Figure 4.31. There are four special cases introduced by four current sources, so we
would need to solve one equation when using the MCM. There are seven essential
nodes, as indicated in Figure 4.32, but no special cases for the NVM. Therefore, we
would have to solve six equations when using the NVM. Clearly, the MCM is the
better choice here. In Chapter 8, we will see that the MCM is the best approach for
transformer circuits. Therefore, although we will use the NVM more often, it is nec-
essary to be fluent with both the NVM and the MCM.
Mesh Analysis 139
FIGURE 4.27 A circuit with six meshes and three essential nodes, with the essential nodes
labeled.
FIGURE 4.28 A non-planar circuit.
4.11 SUMMARY
The MCM is a general-purpose tool for solving planar circuits. (It is not appli-
cable to non-planar circuits, which cannot be drawn on a flat piece of paper without
the use of crossovers.) There are five steps in the basic MCM. First, we identify
the meshes in the circuit. A mesh is a loop that does not enclose any other loops.
Second, we label and number the meshes. As a convention, we define each mesh
current as flowing clockwise around its mesh. Third, we write an equation for each
mesh using KVL. As a convention, we travel clockwise around the mesh and add
FIGURE 4.29 A non-planar circuit with the 16 essential nodes labeled.
FIGURE 4.30 A circuit with five meshes and seven essential nodes.
Mesh Analysis 141
FIGURE 4.31 A circuit with five meshes and seven essential nodes labeled for implementa-
tion of the MCM.
the voltage drops. While doing this we must recognize that a branch shared by two
meshes carries the difference in the individual mesh currents. Fourth, we solve the
system of mesh equations using algebraic methods. Fifth, we use the mesh currents
to determine all other circuit quantities as needed.
Special cases are introduced by the presence of current sources, either inde-
pendent or dependent. A current source on the periphery of the circuit, which is
contained in a single mesh, gives rise to a KMC. A current source on the interior
of a circuit, shared by two meshes, gives rise to a supermesh. Each special case
can be used to reduce the number of equations which must be solved by one.
Therefore, the number of equations that must be solved is equal to nm − nsm , where
nm is the number of meshes and nsm is the number of special cases (current sources)
for the MCM.
FIGURE 4.32 A circuit with five meshes and seven essential nodes labeled for the imple-
mentation of the NVM.
When using the MCM to solve a circuit containing a dependent source, we must
express the value of the controlling variable, and therefore the dependent source,
in terms of the mesh currents. If the dependent source is a current source, either
a VCCS or a current-controlled current source, it will result in a special case as
described in the previous paragraph.
Before solving a circuit, we should first evaluate the applicability and complex-
ity (number of equations required) for the NVM and the MCM. Only the NVM is
applicable to non-planar circuits, but the MCM is strongly preferred for transformer
circuits, as we will see in Chapter 8. If either method is applicable, we will choose
the method that results in fewer equations.
Mesh Analysis 143
PROBLEMS
Problem 4.1. Is the circuit in Figure P4.1 planar? If it is, redraw the circuit
without crossovers and determine the number of meshes. Determine the
number of essential nodes.
FIGURE P4.1 Complex circuit drawn in the form of a cube.
Problem 4.2. Determine if the circuit shown in Figure P4.2 is planar. If it is,
determine the number of meshes. Also determine the number of essential
nodes.
FIGURE P4.2 Complex circuit drawn using two crossovers.

Problem 4.3. Try to draw the circuit in Figure P4.3 without crossovers and
thus determine if it is planar. If it is, find the number of meshes. Also find
the number of essential nodes. Determine the number of essential nodes.
FIGURE P4.3 Complex circuit drawn in the form of two adjacent cubes with a diagonal
voltage source.
Problem 4.4. Determine the two mesh currents I1 and I 2 for the circuit in
Figure P4.4.
FIGURE P4.4 Circuit with two meshes.

Mesh Analysis 145
Problem 4.5. Find the mesh currents I1, I 2, and I 3 for the circuit in Figure
P4.5. Determine the power for each of the voltage sources.
FIGURE P4.5 Circuit with three meshes.
Problem 4.6. For the circuit in Figure P4.6, determine the mesh currents I A,
I B, and IC. Find the power in the 8 Ω and 15 Ω resistors.
FIGURE P4.6 Circuit with three meshes involving three sources and six resistors.
Problem 4.7. Find the mesh currents I1, I 2, and I 3 and the branch currents I X ,
IY , and I Z for the circuit in Figure P4.7.
FIGURE P4.7 Circuit with three meshes involving two voltage sources and eight resistors.
Problem 4.8. For the circuit in Figure P4.8, determine the currents I A, I B, IC,
and I D and show that their sum is zero.
FIGURE P4.8 Circuit with four meshes.

Mesh Analysis 147
Problem 4.9. Calculate the mesh currents I1, I 2, I 3, and I 4 for the circuit in
Figure P4.9. Find the power for each of the voltage sources.
FIGURE P4.9 Circuit with four meshes, three sources, and eleven resistors.
Problem 4.10. Determine the currents I X and IY for the circuit in Figure P4.10.
FIGURE P4.10 Circuit with two meshes and one known mesh current.
Problem 4.11. Determine the currents I A and I B for the circuit in Figure P4.11.
FIGURE P4.11 Circuit with two meshes making up one supermesh.
Problem 4.12. Determine the currents I A and I B for the circuit in Figure P4.12.
FIGURE P4.12 Circuit with three meshes and one known mesh current.
Mesh Analysis 149
Problem 4.13. For the circuit in Figure P4.13, find the mesh currents I1, I 2,
and I 3. Determine the power for each of the sources.
FIGURE P4.13 Circuit with three meshes including one supermesh.
Problem 4.14. For the circuit in Figure P4.14, find the currents I A, I B, IC, and
I D . Calculate the power for the 8 Ω resistor.
FIGURE P4.14 Circuit with four meshes including two special cases.
Problem 4.15. For the circuit in Figure P4.15, find the currents I A and I B.
Determine the power for the voltage source.
FIGURE P4.15 Circuit with three meshes including two special cases.
Problem 4.16. Find the currents I A, I B, IC, and I D for the circuit in Figure P4.16.
Determine the power for the voltage source.
FIGURE P4.16 Circuit with three meshes including a known mesh current and a supermesh.
Problem 4.17. Find the currents I A, I B, and IC for the circuit in Figure P4.17.
FIGURE P4.17 Circuit with four meshes including a known mesh current and a supermesh.
Mesh Analysis 151
Problem 4.18. For the circuit in Figure P4.18, find the voltages V1, V2, V3, and V4.
FIGURE P4.18 Circuit with four meshes including two current sources.
Problem 4.19. Determine the power for each of the voltage sources in
Figure P4.19.
FIGURE P4.19 Circuit with three meshes which make up a double supermesh.
Problem 4.20. Determine the power for each of the voltage sources for the
FIGURE P4.20 Circuit with four meshes including a double supermesh.
Problem 4.21. Find ix and the power for the dependent source of the circuit
in Figure P4.21.

Mesh Analysis 153
Problem 4.22. Find v x and the power for the dependent source in Figure P4.22.
Problem 4.23. Find v x and ix for the circuit in Figure P4.23.

Problem 4.24. Find v x and ix for the circuit in Figure P4.24.
Problem 4.25. For the circuit in Figure P4.25, find ix and iy .

5 Thevenin’s and
Norton’s Theorems
5.1 THEVENIN’S THEOREM

Thevenin’s theorem is a useful tool for solving certain types of problems. It states
that for any two-terminal network involving resistors and sources, there is a Thevenin
equivalent network involving a single voltage source VTh and a single resistance RTh, as
shown in Figure 5.1. The Thevenin circuit is externally equivalent to the original cir-
cuit, in the sense that if we connect additional circuitry to the two terminals a and b, the
voltages and currents in this external circuitry will be the same for the Thevenin equiv-
alent as the original circuit, regardless of the complexity of the original circuit. They
are not internally equivalent, however. This means that we cannot use the Thevenin
equivalent circuit to directly find voltages and currents inside the original circuit.
Because the Thevenin circuit is externally equivalent to the original circuit, we
can analyze the behavior with simple external connections to find VTh and RTh. One
such connection involves a short circuit as shown in Figure 5.2. If we place a wire
directly between the terminals a and b to create a short circuit, the same current
FIGURE 5.1 A network containing resistors and sources and its Thevenin equivalent.
FIGURE 5.2 The short-circuit condition for a network containing resistors and sources and
its Thevenin equivalent.
DOI: 10.1201/9781003408529-5 155

FIGURE 5.3 The open-circuit condition for a network containing resistors and sources and
its Thevenin equivalent.
should flow in either case. The short-circuit current for the Thevenin equivalent is
VTh / RTh . Therefore, the short-circuit current for the original circuit on the left should
be equal to the short-circuit current for the Thevenin equivalent:
I SC = VTh / RTh . (5.1)
Another simple external condition of importance is the open-circuit condition shown

in Figure 5.3. The open-circuit voltage for the Thevenin equivalent is VTh , and if the
two circuits are externally equivalent, the open-circuit voltage for the original circuit
on the left should be equal to the open-circuit voltage for the Thevenin equivalent:
VOC = VTh . (5.2)
If the original circuit contains at least one independent source, then its open-circuit
voltage and short-circuit current will both be nonzero so we may determine the
Thevenin resistance from their ratio:
RTh = VOC / I SC (5.3)
Occasionally, the original circuit may contain no independent sources, either because
it contains only resistors or because the sources within it are all dependent sources. If
this is the case, both the open-circuit voltage and the short-circuit current will be zero
and we may not use their ratio to find the Thevenin resistance. Instead, we can apply
a test source as shown in Figure 5.4. It should be noted that we can use either a volt-
age test source or a current test source, in case one is more convenient than the other.
In Figure 5.4, we show the application of a voltage test source of value VTest , and the
resulting current I Test is to be determined. We could also apply a current test source
of value I Test , and then find the resulting voltage VTest . Either way, simple application
of KVL and Ohm’s law reveals that
RTh = (VTest − VTh ) / I Test . (5.4)
In a case for which the Thevenin voltage is zero, this simplifies to
RTh = VTest / I Test . (5.5)

Thevenin’s and Norton’s Theorems 157
FIGURE 5.4 The application of a test source to a circuit containing resistors and sources as
well as its Thevenin equivalent.
In the following sections, we will make use of these concepts to determine the
Thevenin equivalent circuit for several two-terminal networks.
5.2 THEVENIN EQUIVALENT FOR A CIRCUIT

WITH ONLY INDEPENDENT SOURCES
For a two-terminal circuit with only independent sources and resistors, we may use
a combination of the open-circuit analysis and the short-circuit analysis to determine
the Thevenin equivalent circuit. It turns out there is a third analysis, the resistance
shortcut analysis, which may also be used to determine the Thevenin resistance. In
light of this, we may use the combination of any two of the open-circuit analy-
sis, the short-circuit analysis, and the resistance shortcut analysis to find the
Thevenin equivalent. To illustrate this, we will find the Thevenin equivalent with
respect to the terminals a and b for the circuit in Figure 5.5.
We will start by doing the open-circuit analysis by the node voltage method as
In units of V, A, and Ω, the node voltage equations are
N 1 V1 = 15, (5.6)
V2 − V3
N 2 − 1 − 0.5 + = 0, (5.7)
2
and
V3 − V1 V3 − V2 V3
N3 + + = 0. (5.8)
5 2 20
Substituting the N1 known node voltage into the N3 equation,
V2 − V3
N 2 − 1 − 0.5 + =0 (5.9)
2
and
V3 − 15 V3 − V2 V3
N3 + + = 0. (5.10)
5 2 20
FIGURE 5.5 A two-terminal network containing four independent sources and resistors.
FIGURE 5.6 Open-circuit analysis of a two-terminal network containing three independent

sources and resistors.
Multiplying by the least common denominators,
N 2 − 2 − 1 + V2 − V3 = 0, (5.11)
N 3 4V3 − 60 + 10V3 − 10V2 + V3 = 0. (5.12)
N 2 V2 − V3 = 3, (5.13)
N 3 − 10V2 + 15V3 = 60. (5.14)

In matrix form,
 1 −1   V2   3 
 = . (5.15)
 −10
 15   V3   60 
Solving,
3 −1
60 15
V2 = = 21.0 V (5.16)
1 −1
−10 15
and
1 3
−10 60
V3 = = 18.0 V. (5.17)
1 −1
−10 15
The open-circuit voltage is the same as the node three voltage:
VOC = V3 = 18.0 V . (5.18)
Next, we will do the short-circuit analysis, also by the node voltage method, as shown
in Figure 5.7. Notice that shorting between terminals a and b eliminates one essential
node (node three is combined with the reference node).
FIGURE 5.7 Short-circuit analysis of a two-terminal network containing only independent

N 1 V1 = 15 (5.19)
and
V2
N 2 − 1 − 0.5 + = 0. (5.20)
2
Simplifying,
N 2 − 2 − 1 + V2 = 0 (5.21)
or
V2 = 3 V. (5.22)
It is important to note that the value of V2 under short-circuit conditions is not the
same as the value of V2 under open-circuit conditions! Having solved for the node
voltages, we can use Kirchhoff’s current law (KCL) to find the short-circuit current.
V1 V
I SC = + 2 = 4.5 A. (5.23)
5Ω 2Ω
Now, we can determine the Thevenin equivalent circuit:
VTh = VOC = 18.0 V (5.24)
and
VOC
RTh = = 4.0 Ω. (5.25)
I SC
In a circuit with only independent sources and resistors, we can also use the resis-
tance shortcut analysis to find the Thevenin resistance. To apply the resistance short-
cut, we disable all of the independent sources and find the equivalent resistance for the
remaining network with respect to the terminals a and b. When we disable a voltage
source we set it to zero volts, which corresponds to a short circuit. To disable a current
source, we set it to zero amperes, which is an open circuit. Disabling the independent
sources in the circuit of Figure 5.5 results in the circuit of Figure 5.8. The 2 Ω resistor
has no effect on the Thevenin resistance because it is disconnected from the rest of the
circuit on the left-hand side, and no current can flow in it. The Thevenin resistance is
the equivalent resistance seen looking into the terminals a and b; it is
RTh = 5 Ω  20 Ω = 4.0 Ω. (5.26)
This result was already obtained by combining the open-circuit and short-circuit
analyses. We could choose to do any two of the three analyses and obtain the
Thevenin equivalent circuit. If we do all three, we can check the results for consis-
tency and this may help to find small errors.
FIGURE 5.8 Resistance shortcut analysis of a two-terminal network containing only inde-
pendent sources and resistors.

WITH MIXED SOURCES
If a two-terminal network contains mixed dependent and independent sources, as
well as resistors, we may still use the open-circuit and short-circuit analyses. The
resistance shortcut is not applicable, but we can use a test-source analysis. We will
make these points using the circuit in Figure 5.9.
N 1 V1 = 8, (5.27)
V2 − 16 V −V
N2 − 4ix + 2 3 = 0, (5.28)
12 8
and
V3 − V1 V3 − V2
N3 + − 0.5 = 0. (5.29)
4 8
16 − V2
DS ix = . (5.30)
12
FIGURE 5.9 A two-terminal network containing mixed (independent and dependent)

FIGURE 5.10 Open-circuit analysis of a two-terminal network containing only indepen-

dent sources and resistors.
Substituting the DS equation into the N2 equation, and substituting the N1 known
node voltage into the N3 equation,
V2 − 16  16 − V2  V2 − V3
N 2 DS − 4 + =0 (5.31)
12  12  8
and
V3 − 8 V3 − V2
N 1N 3 + − 0.5 = 0. (5.32)
4 8
N 2 DS 2V2 − 32 − 128 + 8V2 + 3V2 − 3V3 = 0 (5.33)
and
N 1N 3 2V3 − 16 + V3 − V2 − 4 = 0. (5.34)
N 2 DS 13V2 − 3V3 = 160 (5.35)
and
N 1N 3 − V2 + 3V3 = 20. (5.36)
In matrix form,
 13 −3   V2   160 
 −1  = . (5.37)
 3   V3   20 
Solving,
160 −3
20 3
V2 = = 15.00 V (5.38)
13 −3
−1 3
and
13 160
−1 20
V3 = = 11.67 V. (5.39)
13 −3
−1 3
The open-circuit voltage is not directly equal to any of the node voltages in this case,
because node B is not the reference node. (In fact, it is not even an essential node!)
The open-circuit voltage is
VOC = VA − VB , (5.40)
where
VA = V3 = 11.67 V (5.41)
and
VB = − ( 0.5 A )( 6 Ω ) = −3.00 V. (5.42)

FIGURE 5.11 Short-circuit analysis of a two-terminal network containing mixed (indepen-

dent and dependent) sources and resistors.
The open-circuit voltage is therefore
VOC = VA − VB = 11.67 V − ( −3.00 V ) = 14.67 V. (5.43)
Next, we will do the short-circuit analysis, also by the node voltage method, as shown
in Figure 5.11.
In units of V , A, and Ω, the node voltage equations are
N 1 V1 = 8, (5.44)
V2 − 16 V −V
N2 − 4ix + 2 3 = 0, (5.45)
12 8
and
V3 − V1 V3 − V2 V
N3 + − 0.5 + 0.5 + 3 = 0. (5.46)
4 8 6
Notice that the independent current source flows between two points on node three
so the net contribution is zero when writing the node equation. (However, we will see
that this current source contributes to the short-circuit current.)
16 − V2
DS ix = . (5.47)
12
Substituting the DS equation into the N2 equation, and substituting the N1 known
node voltage into the N3 equation,
V2 − 16  16 − V2  V2 − V3
N 2 DS − 4 + =0 (5.48)
12  12  8
and
V3 − 8 V3 − V2 V3
N 1N 3 + + = 0. (5.49)
4 8 6
N 2 DS 2V2 − 32 − 128 + 8V2 + 3V2 − 3V3 = 0 (5.50)
and
N 1N 3 6V3 − 48 + 3V3 − 3V2 + 4V3 = 0. (5.51)
N 2 DS 13V2 − 3V3 = 160 (5.52)
and
N 1N 3 − 3V2 + 13V3 = 48. (5.53)
In matrix form,
 13 −3   V2   160 
 −3  = . (5.54)
 13   V3   48 
Solving,
160 −3
48 13
V2 = = 13.90 V (5.55)
13 −3
−3 13
and
13 160
−3 48
V3 = = 6.90V. (5.56)
13 −3
−3 13
Once again it is important to note that the node voltages under short-circuit condi-
tions are generally different from the node voltages under open-circuit conditions.
The short-circuit current may be found by using KCL with the short-circuit node
voltages. Referring to Figure 5.11, we see that this is a somewhat unusual use of KCL
because the short-circuit current flows between two points on the same essential
node.
V1 − V3 V2 − V3
I SC = iy + iz + 0.5 A = + + 0.5 A = 1.650 A. (5.57)
4Ω 8Ω
The Thevenin resistance is therefore
VOC 14.67 V
RTh = = = 8.89 Ω. (5.58)
I SC 1.650 A
The resistance shortcut is not applicable to circuits containing mixed independent

and dependent sources. This is because dependent sources contribute to the Thevenin
resistance, so disabling them alters the apparent Thevenin resistance. To see this, con-
sider the circuit of Figure 5.9 with all sources disabled (voltage sources replaced by
shorts and current sources replaced by opens). The resulting circuit appears in Figure
5.12, and the equivalent resistance with respect to the nodes a and b is
Rab = (8 Ω + 12 Ω )  ( 4 Ω + 6 Ω ) = 6.59 Ω ≠ VTh . (5.59)
Therefore, we cannot use the resistance shortcut in a network containing dependent

sources.
FIGURE 5.12 A two-terminal network containing mixed (independent and dependent)

sources and resistors, after the sources have all been disabled to show that the resistance
shortcut is not valid in the case of mixed sources.
FIGURE 5.13 Test-source analysis of a two-terminal network containing mixed (indepen-

dent and dependent) sources and resistors. The independent sources have been disabled but
the dependent source has been left active.
On the other hand, we can use a test-source analysis for a network containing
mixed sources. For this analysis, we disable only the independent sources and apply a
test source to the terminals a and b. The test source may be a current source or a volt-
age source – and sometimes one may be more convenient than the other. Also, the
test source can take a specific value (1V, for example) or it can have an abstract value
(such as VTest ). We will use a test source with the unspecified value of VTest , as shown
in Figure 5.13, but the value of the test source will cancel out in the final analysis.
Notice that in this particular circuit, the number of essential nodes has been reduced
to two by disabling the independent sources. This is because the node which was for-
merly called N1 has been joined with the reference node by disabling the 8 V source.
V1 − VTest V1 V1 − V2
N1 + + =0 (5.60)
6 4 8
and
V2 V −V
N2 − 4ix + 2 1 = 0. (5.61)
12 8
−V2
DS ix = . (5.62)
12
Substituting the DS equations into the N2 equation, we obtain
V1 − VTest V1 V1 − V2
N1 + + =0 (5.63)
6 4 8
and
V2 −V V −V
N 2 DS − 4  2  + 2 1 = 0. (5.64)
12  12  8
N 1 4V1 − 4VTest + 6V1 + 3V1 − 3V2 = 0 (5.65)
and
N 2 DS 2V2 + 8V2 + 3V2 − 3V1 = 0. (5.66)
N 1 13V1 − 3V2 = 4VTest (5.67)
and
N 2 DS − 3V1 + 13V2 = 0. (5.68)
In matrix form,
 13 −3   V1   4VTest 
 −3  = . (5.69)
 13   V2   0 
Solving,
4VTest −3
0 13 52VTest 13VTest
V1 = = = (5.70)
13 −3 160 40
−3 13
and
13 4VTest
−3 0 12VTest 3VTest
V2 = = = . (5.71)
13 −3 160 40
−3 13
Now, we can find the resulting value of test current:
VTest − V1 VTest − 13VTest / 40

I Test = = . (5.72)
6Ω 6Ω
The Thevenin resistance is then

−1
VTest  1 − 13 / 40 
RTh = =  = 8.89 Ω, (5.73)
I Test  6 Ω 
which is the same as the value found by use of the open-circuit and short-circuit
analyses.
As previously mentioned, we can choose to use a specific value of the test source
if it is more convenient; sometimes this simplifies the mathematics. As an example,
we will solve the present example using a test source of 1 V, as shown in Figure 5.14.
V1 − 1 V1 V1 − V2
N1 + + =0 (5.74)
6 4 8
and
V2 V −V
N2 − 4ix + 2 1 = 0. (5.75)
12 8
−V2
DS ix = . (5.76)
12
V1 − 1 V1 V1 − V2
N1 + + =0 (5.77)
6 4 8
FIGURE 5.14 Use of a test source with a specific value (1V) with a two-terminal net-
work containing mixed (independent and dependent) sources and resistors. The independent
sources have been disabled but the dependent source has been left active.
and
V2 −V V −V
N 2 DS − 4  2  + 2 1 = 0. (5.78)
12  12  8
N 1 4V1 − 4 + 6V1 + 3V1 − 3V2 = 0 (5.79)
and
N 2 DS 2V2 + 8V2 + 3V2 − 3V1 = 0. (5.80)
N 1 13V1 − 3V2 = 4 (5.81)
and
N 2 DS − 3V1 + 13V2 = 0. (5.82)
In matrix form,
 13 −3   V1   4 
 −3  = . (5.83)
 13   V2   0 
Solving,
4 −3
0 13
V1 = = 0.325 V (5.84)
13 −3
−3 13
and
13 4
−3 0
V2 = = 0.0750 V. (5.85)
13 −3
−3 13
Now, we can find the resulting value of test current:
1V − V1 1V − 0.325 V
I Test = = = 0.1125 A. (5.86)
6Ω 6Ω
VTest 1V
RTh = = = 8.89 Ω, (5.87)
I Test 0.1125 A
The same as before.

Finally, we could choose to use a test current source as shown in Figure 5.15.
In units of V , A, and Ω, the node voltage equations are
V1 V1 − V2
N 1 − I Test + + =0 (5.88)
4 8
and
V2 V −V
N2 − 4ix + 2 1 = 0. (5.89)
12 8
−V2
DS ix = . (5.90)
12
V1 V1 − V2
N 1 − I Test + + =0 (5.91)
4 8
and
V2 −V V −V
N 2 DS − 4  2  + 2 1 = 0. (5.92)
12  12  8
FIGURE 5.15 Use of a test current source with a two-terminal network containing mixed
(independent and dependent) sources and resistors. The independent sources have been dis-
abled but the dependent source has been left active.
N 1 − 8 I Test + 2V1 + V1 − V2 = 0 (5.93)
and
N 2 DS 2V2 + 8V2 + 3V2 − 3V1 = 0. (5.94)
N 1 3V1 − V2 = 8 I Test (5.95)
and
N 2 DS − 3V1 + 13V2 = 0. (5.96)
In matrix form,
 3 −1   V1   8 I Test 
 −3  = . (5.97)
 13   V2   0 
Solving,
8 I Test −1
0 13 104 I Test 26 I Test
V1 = = = (5.98)
3 −1 36 9
−3 13
and
3 8 I Test
−3 0 24 I Test 2 I Test
V2 = = = . (5.99)
3 −1 36 3
−3 13
Now, we can find the resulting value of test voltage:
VTest = Va − Vb = V1 −  − ( 6 Ω ) I Test  = ( 26 Ω / 9 ) I Test −  − ( 6 Ω ) I Test  . (5.100)
VTest 26
RTh = = Ω + 6 Ω = 8.89 Ω, (5.101)
I Test 9
same as before. When using a current source, we could also assume a specific value
for I Test , such as 1A, if desired.
in ebook+.

CONTAINING ONLY DEPENDENT SOURCES
If a two-terminal network contains only dependent sources, along with resistors,
the open-circuit voltage is zero (and therefore the Thevenin voltage is zero). This
is known without performing the open-circuit analysis, so the open-circuit analysis
provides no new useful information. The short-circuit current is also zero, and the
Thevenin resistance cannot be found from the ratio VOC / I SC . The resistance shortcut
method is not applicable because of the presence of dependent sources. Only the
test-source analysis is applicable.
Consider the circuit in Figure 5.16, which contains only dependent sources and
resistors.
First, we will show that the open-circuit voltage is zero for this circuit, using the
node voltage method as shown in Figure 5.17.
In units of V, mA, and kΩ , the node voltage equations are
V1 − V2 V1 + 2ix − V2
N 1 − 4 ix + + =0 (5.102)
1 10
and
V2 − V1 V2 V2 V2 − 2ix − V1
N2 + + + = 0. (5.103)
1 10 2 10
The equation of the current controlling the dependent sources is
V2
DS ix = − . (5.104)
10
FIGURE 5.16 A two-terminal network containing only dependent sources and resistors.
FIGURE 5.17 Open-circuit analysis of a two-terminal network containing only dependent

Substituting the DS equation into the N1 and N2 equations,
V V − V V − 2V2 / 10 − V2
N 1DS − 4  − 2  + 1 2 + 1 =0 (5.105)
 10  1 10
and
V2 − V1 V2 V2 V2 + 2V2 / 10 − V1
N 2 DS + + + = 0. (5.106)
1 10 2 10
N 2 DS 40V2 + 100V1 − 100V2 + 10V1 − 2V2 − 10V2 = 0 (5.107)
and
N 1DS 100V2 − 100V1 + 10V2 + 50V2 + 10V2 + 2V2 − 10V1 = 0. (5.108)
N 2 DS 110V1 − 72V2 = 0 (5.109)
and
N 1DS − 110V1 + 172V2 = 0. (5.110)
In matrix form,
 110 −72   V2   0 
 −110  = . (5.111)
 172   V3   0 
Solving,
0 −72
0 172
V1 = =0 (5.112)
110 −72
−110 172
and
110 0
−110 0
V2 = = 0. (5.113)
110 −72
−110 172
The open-circuit voltage is equal to the node two voltage and is therefore zero:
VOC = V2 = 0. (5.114)
In general, we can show that both the open-circuit voltage and the short-circuit
current will be zero for any two-terminal network containing only dependent
sources and resistors. Therefore, the Thevenin voltage is zero for such a net-
work, and the Thevenin equivalent circuit comprises only a resistor RTh.
The Thevenin resistance may be determined for such a network by a test-source
analysis. This may be done using a voltage test source (either generic or of a specific
value) or a current test source (either generic or of a specific value). In Figure 5.18,
we apply a generic voltage source to the network in Figure 5.16.
FIGURE 5.18 Use of a test voltage source with a two-terminal network containing only
dependent sources and resistors.
In units of V, mA, and kΩ, the node voltage equations are
V1 − V2 V1 + 2ix − V2
N 1 − 4 ix + + =0 (5.115)
1 10
and
N 2 V2 = VTest . (5.116)
The equation for the current controlling the dependent sources is
V2
DS ix = − . (5.117)
10
Substituting the DS and N2 equations into the N1 equation,
V V −V V − 2VTest / 10 − VTest
N 1N 2 DS − 4  − Test  + 1 Test + 1 = 0. (5.118)
 10  1 10
N 1N 2 DS 40VTest + 100V1 − 100VTest + 10V1 − 2VTest − 10VTest = 0. (5.119)
N 1N 2 DS 110V1 − 72VTest = 0 (5.120)
or
V1 = 72VTest / 110. (5.121)
Next, we can find the test current by using KCL:
VTest V V − V VTest − ( 2 kΩ ) ix − V1
I Test = + Test + Test 1 + . (5.122)
2 kΩ 10 kΩ 1kΩ 10 kΩ
Substituting in the equations for V1 and iTest ,
VTest V V − 72VTest / 110 VTest + 0.4VTest − 72VTest / 110

I Test = + Test + Test + .
2 kΩ 10 kΩ 1kΩ 10 kΩ
(5.123)
The Thevenin resistance is

−1
V  1 1 1 − 72 / 110 1 + 0.4 − 72 / 110 
RTh = Test =  + + +  = 0.980 kΩ.
I Test  2 kΩ 10 kΩ 1kΩ 10 kΩ 
(5.124)
It should be noted that the Thevenin equivalent circuit comprises only this resis-
tance because the Thevenin voltage is zero and there is no need to include a volt-
age source. It should also be noted that the resistance shortcut may not be used
in this circuit due to the presence of dependent sources, which contribute to the
Thevenin resistance. (The resistance shortcut would yield an equivalent resistance of
Rab = 10 kΩ  2 kΩ = 1.667 kΩ, which is not valid.)
in ebook+.
5.5 SOURCE TRANSFORMATIONS

A two-terminal network comprising a voltage source and a series resistance may be
transformed to a two-terminal network comprising a current source and a parallel
resistor, and these two will be externally equivalent as long as the open-circuit volt-
age and short-circuit current are preserved by the transformation. This has broad
applicability because we have seen that any two-terminal network involving resis-
tors and sources may be represented by its Thevenin equivalent involving a voltage
source and series resistance.
Referring to the top two networks in Figure 5.19, the open-circuit voltages of the
two are equal provided that VTh = I N RN . The two short-circuit currents are equal if
VTh / RTh = I N . These two conditions are satisfied if
VTh
IN = (5.125)
RTh
and
RN = RTh . (5.126)
These equations allow us to transform from the circuit on the left (with the voltage
source) to the one on the right (containing the current source). By rearranging the
FIGURE 5.19 Source transformations.

FIGURE 5.20 A circuit containing four meshes and five essential nodes.
first equation, we can transform in the other direction as illustrated on the bottom of
Figure 5.19. As long as the two networks behave equivalently for the open-circuit and
short-circuit conditions, they will behave equivalently when connected to a general
network of sources and resistors. The two are externally equivalent; that is, all exter-
nal voltages and currents will be unchanged by transforming from one to the other.
The use of source transformations can sometimes aid in the analysis of a circuit
if it allows us to reduce the number of essential nodes or meshes or both. Consider
the determination of IQ for the circuit in Figure 5.20, which contains four meshes and
five essential nodes. We can simplify this circuit without obscuring the current IQ if
we perform two source transformations on the right-hand side.
First, we will transform the 3 A in parallel with 10 Ω to 30 V in series with 10 Ω,
resulting in the circuit of Figure 5.21. This has reduced the meshes to three and the
essential nodes to four.
Next, we will transform the 1A in parallel with 5 Ω to 5 V in series with 5 Ω, result-
ing in the circuit of Figure 5.22. Notice that the 5 V source has the plus sign on the
bottom. This is because the original current source pointed downward, and we need
to preserve the sign of the open-circuit voltage for this two-terminal combination.
The second source transformation rendered a circuit with two meshes and two
essential nodes. We can further simplify by combining series resistances and series
voltage sources, giving us the simplified circuit in Figure 5.23.
Now, we can easily apply the node voltage method with a single equation:
V1 − 60 V V V1 − 25 V
N1 + 1 + = 0; (5.127)
15 Ω 24 Ω 43 Ω
60 V / 15 Ω + 25 V / 43 Ω
V1 = = 34.82 V (5.128)
1 / 15 Ω + 1 / 24 Ω + 1 / 43 Ω
and
V1
IQ = = 1.451A. (5.129)
24 Ω
FIGURE 5.21 The previous circuit simplified by one source transformation.
FIGURE 5.22 The previous circuit simplified by a second source transformation.
FIGURE 5.23 The previous circuit simplified by combining series resistors and series volt-
age sources.
FIGURE 5.24 Any two-terminal network involving sources and resistances may be repre-
sented by its Norton equivalent.
It is important to realize that the transformed pieces of the circuit are externally
equivalent, but not internally equivalent. The simplified circuit obscures certain
quantities in the original circuit, such as the power in the 3 A source or the current in
the 5 Ω resistor. If we required quantities such as these, we might choose to solve the
original circuit, even though more equations would be needed.
5.6 NORTON’S THEOREM

Norton’s theorem states that any two-terminal network comprising sources and resis-
tances may be represented by its Norton equivalent, which involves a single current
source and a parallel resistor as shown in Figure 5.24. The original network and its
Norton representation are externally equivalent, so all currents and voltages external
to the two terminals are unchanged when we replace the original network with its
Norton equivalent.
Norton’s theorem follows from Thevenin’s theorem and a source transforma-
tion. Hence, the Norton equivalent may be found using the same methods used to
find a Thevenin equivalent. For a network involving only independent sources and
resistances, we can use any two of the open-circuit analysis, short-circuit analysis,
and resistance shortcut. For a network involving mixed (independent and dependent)
sources, we may use any two of the open-circuit, short-circuit, and test-source analy-
ses. For a network involving only dependent sources and resistances, we need to use
a test-source analysis.
in ebook+.
5.7 MAXIMUM POWER TRANSFER THEOREM

An important application of Thevenin’s theorem (or Norton’s theorem) is in solving
maximum power transfer problems. Suppose a load resistor is connected to a two-
terminal network involving sources and resistors as shown on the left-hand side of
Figure 5.25. We can represent the two-terminal network by its Thevenin equivalent
as shown on the right-hand side of this figure.
We want to know the maximum amount of electrical power which can be deliv-
ered to the load from this network, and what value of load resistance will give rise to
this maximum power transfer. This problem can be easily solved using the Thevenin
representation for the original circuit.
FIGURE 5.25 A load resistor connected to a two-terminal network for consideration of

maximum power transfer.
The load voltage may be found using the voltage divider rule:
VTh RL
VL = . (5.130)
RTh + RL
The load current may be determined using Ohm’s law:
VTh
IL = . (5.131)
RTh + RL
The load power is
VTh2 RL
PL = VL I L = . (5.132)
( RTh + RL )2
To find the value of load resistance that will maximize this power, we can differenti-
ate the power expression with respect to the load resistance, set the derivative to zero,
and solve. We can use the quotient rule to find the partial derivative of the power with
respect to the load resistance:
∂ PL VTh2 ( RTh + RL ) − VTh2 RL 2 ( RTh + RL )

2
= . (5.133)
∂ RL ( RTh + RL )4
We set this partial derivative to zero in order to maximize the power:
VTh2 ( RTh + RL ) − VTh2 RL 2 ( RTh + RL )

2
= 0. (5.134)
( RTh + RL )4
We may multiply both sides by ( RTh + RL ) :
3
VTh2 ( RTh + RL ) − VTh2 RL 2 = 0. (5.135)
It is assumed that the Thevenin voltage is nonzero, so we may divide both sides by
VTh2 :
( RTh + RL ) − 2 RL = 0. (5.136)
Solving, we find that maximum power will be delivered when the load resistance is
matched to the Thevenin resistance for the network delivering the power:
RL = RTh . (5.137)
Substituting this result into the power equation, we find the maximum power that can
be delivered to the load (corresponding to RL = RTh ):
VTh2
PL ,max = . (5.138)
4 RTh
The maximum power that can be delivered to a resistive load RL by a two-
terminal network with Thevenin voltage VTh and Thevenin resistance RTh is
equal to VTh2 / ( 4 RTh ), and this maximum power is delivered to the load when its
resistance is matched to the Thevenin resistance: RL = RTh .
As an example, we can find the maximum power PL,max , which may be delivered to
the load resistor RL in Figure 5.26, and the corresponding value of this load resistor.
The most efficient approach to this problem is to find the Thevenin equivalent with
respect to the terminals where the load resistor is connected.
In Figure 5.27, the load resistor is removed so we can perform the open-circuit
analysis with respect to the terminals where this load had been applied.
Using the node voltage method with units of V, A, and Ω,
V1 − V2 V −V
N1 + 3iα + 1 4 = 0, (5.139)
1 3
V2 − 8 V2 − V1 V2 − V3
N2 + + = 0, (5.140)
2 1 6
V3 − V2 V −V
N3 − 3iα − 0.5 + 3 4 = 0, (5.141)
6 4
FIGURE 5.26 A two-terminal network with a load resistor RL connected.

FIGURE 5.27 Open-circuit analysis of the previous circuit.
N 4 V4 = 12. (5.142)
The equation controlling the dependent source is
V4 − V1
DS iα = . (5.143)
3
Substituting the DS equation into the N1 and N3 equations,
V1 − V2 V −V V −V
N 1DS + 3  4 1  + 1 4 = 0, (5.144)
1  3  3
V2 − 8 V2 − V1 V2 − V3
N2 + + = 0, (5.145)
2 1 6
V3 − V2 V −V V −V
N 3 DS − 3  4 1  − 0.5 + 3 4 = 0, (5.146)
6  3  4
and
N 4 V4 = 12. (5.147)
Substituting the N4 equation into the N1 and N3 equations,
V1 − V2  12 − V1  V1 − 12
N 1N 4 DS + 3 + = 0, (5.148)
1  3  3
V2 − 8 V2 − V1 V2 − V3
N2 + + = 0, (5.149)
2 1 6
and
V3 − V2  12 − V1  V3 − 12
N 3 N 4 DS − 3  − 0.5 + = 0. (5.150)
6  3 4
N 1N 4 DS 3V1 − 3V2 + 36 − 3V1 + V1 − 12 = 0, (5.151)
N 2 3V2 − 24 + 6V2 − 6V1 + V2 − V3 = 0, (5.152)
and
N 3 N 4 DS 2V3 − 2V2 − 144 + 12V1 − 6 + 3V3 − 36 = 0. (5.153)
N 1N 4 DS V1 − 3V2 = −24, (5.154)
N 2 − 6V1 + 10V2 − V3 = 24, (5.155)
and
N 3 N 4 DS 12V1 − 2V2 + 5V3 = 186. (5.156)
In matrix form,
 1 −3 0   V1   −24 
 −6 −1  V   .
 10  2  =  24  (5.157)
 12 −2 5   V3   186 

Solving,
−24 −3 0
24 10 −1
186 −2 5
V1 = = 39.0 V, (5.158)
1 −3 0
−6 10 −1
12 −2 5
1 −24 0
−6 24 −1
12 186 5
V2 = = 21.0 V, (5.159)
1 −3 0
−6 10 −1
12 −2 5
and
1 −3 −24
−6 10 24
12 −2 186
V3 = = −48.0 V. (5.160)
1 −3 0
−6 10 −1
12 −2 5
The open-circuit voltage is equal to the node three voltage:
VOC = V3 = −48.0 V. (5.161)
Next, we can consider the short-circuit analysis. Referring to Figure 5.28, we see that
the short eliminates one essential node.
Using the node voltage method with units of V, A, and Ω,
V1 − V2 V −V
N1 + 3iα + 1 3 = 0, (5.162)
1 3
FIGURE 5.28 Short-circuit analysis of the previous circuit.

V2 − 8 V2 − V1 V2
N2 + + = 0, (5.163)
2 1 6
and
N 3 V3 = 12. (5.164)
The equation controlling the dependent source is
V3 − V1
DS iα = . (5.165)
3
Substituting the DS equation into the N1 equations,
V1 − V2 V −V V −V
N 1DS + 3  3 1  + 1 3 = 0, (5.166)
1  3  3
V2 − 8 V2 − V1 V2
N2 + + = 0, (5.167)
2 1 6
and
N 3 V3 = 12. (5.168)
Substituting the N3 equation into the N1 equation,
V1 − V2  12 − V1  V1 − 12
N 1DSN 3 + 3 + =0 (5.169)
1  3  3
and
V2 − 8 V2 − V1 V2
N2 + + = 0. (5.170)
2 1 6
N 1DSN 3 3V1 − 3V2 + 36 − 3V1 + V1 − 12 = 0 (5.171)
and
N 2 3V2 − 24 + 6V2 − 6V1 + V2 = 0. (5.172)
N 1DSN 4 V1 − 3V2 = −24 (5.173)
and
N 2 − 6V1 + 10V2 = 24. (5.174)

In matrix form,
 1 −3   V1   −24 
 −6  = . (5.175)
 10   V2   24 
Solving,
1 −3
−6 10
V1 = = 21.0 V (5.176)
1 −3
−6 10
and
1 −3
−6 10
V2 = = 15.0 V. (5.177)
1 −3
−6 10
The short-circuit current may be found using KCL:
V2 V
I SC = + 3iα + 0.5 A + 3
6Ω 4Ω
(5.178)
15.0 V  12.0 V − 21.0 V  12.0 V
= + 3  + 0.5 A + = −3.00 A.
6Ω  3Ω  4Ω
The Thevenin resistance is

VOC −48.0 V
RTh = = = 16.0 Ω. (5.179)
I SC −3.0 A
Notice that the usual sign conventions resulted in negative values for both the open-
circuit voltage and short-circuit current, and this yielded a positive value of Thevenin
resistance. Mixed signs for VOC and I SC (one positive and one negative) would indicate
a sign error.
Knowing the Thevenin equivalent for the two-terminal network connected to the
load resistor allows us to easily solve the maximum power transfer problem. The
maximum power that may be delivered to the load is
VTh2
PL ,max = = 36.0 W, (5.180)
4 RTh
and this corresponds to a load resistor which is matched to the Thevenin resistance:
RL = RTh = 16.0 Ω. (5.181)

FIGURE 5.29 Load power as a function of load resistance for the example considered above.
Another advantage of the Thevenin approach is that we can easily determine the
power delivered to an arbitrary load resistor even if does not correspond to the maxi-
mum power condition. In this more general case, the power delivered to the load is
VTh2 RL
PL = , (5.182)
( RTh + RL )2
as previously determined. Using VTh and RTh from the example just considered, we can
plot the load power as a function of the load resistance and this is shown in Figure 5.29. As
expected, the load power peaks at VTh2 / ( 4 RTh ) = 36.0 W and this corresponds to a load
resistance of RL = RTh = 16.0 Ω . If the load resistance is halved, the load power is reduced
to VTh2 ( 0.5 RTh ) / ( RTh + 0.5 RTh ) = (8 / 9 )VTh2 / ( 4 RTh ) = 32.0 W , which is reduced by a
2
factor of 8 / 9 compared to the maximum power. If the load resistance is doubled,

the load power is reduced to VTh2 ( 2 RTh ) / ( RTh + 2 RTh ) = (8 / 9 )VTh2 / ( 4 RTh ) = 32.0 W,
2
which is also reduced by a factor of 8 / 9 compared to the maximum power!

in ebook+.
5.8 SUMMARY
Thevenin’s theorem states that any two-terminal network made up of sources and
resistors may be represented by its Thevenin equivalent, which comprises a single
voltage source VTh and a series resistance RTh . The Thevenin model and the origi-
nal circuit are externally equivalent; that is, they produce identical responses in
external circuitry connected to the two terminals. Norton’s theorem states that
any two-terminal network including sources and resistors may be represented by
its Norton equivalent, which comprises a current source I N and a parallel resistance
RN . In a two-terminal circuit containing only independent sources with resistors,
we may find the Thevenin (or Norton) equivalent by performing any two of the
open-circuit, short-circuit, and resistance shortcut analyses. In a two-terminal
network involving mixed (independent and dependent) sources as well as resistors,
we may use any two of the short-circuit, open-circuit, and test-source analyses
to find the Thevenin (or Norton equivalent). For a two-terminal network involving
only dependent sources and resistors (no independent sources), the Thevenin voltage
is zero and the Thevenin equivalent reduces to a single resistance. This resistance
may be found using a test-source analysis. The Norton current also vanishes in this
case, so the Norton equivalent reduces to a single resistance and is identical to the
Thevenin equivalent in this case!
We may translate between the Thevenin and Norton equivalent circuits by using
source transformations. More generally, a source transformation allows us to find
a voltage source in series with a resistance, which is externally equivalent to a cur-
rent source with a parallel resistance, or vice versa. This can be very useful in circuit
analysis because it may allow us to simplify a circuit, this reducing the number of
essential nodes or the number of meshes. We must be careful when simplifying a
circuit this way, because it is possible to obscure some of the quantities (currents or
voltages) which need to be determined. In principle, source transformations may be
done with dependent sources, but extreme care must be exercised so the controlling
variable for a dependent source is not obscured.
Thevenin’s and Norton’s theorems are extremely helpful when solving a complex
circuit for a number of values of a single parameter. An example is a maximum
power transfer problem, in which we want to find the maximum amount of power
which may be delivered to a load resistor by a two-terminal circuit, as well as the cor-
responding value of the load resistor. If we find the Thevenin equivalent for the cir-
cuitry connected to the two terminals of the load resistor, then the maximum power
that may be delivered to the load is VTh2 / ( 4 RTh ) and this corresponds to a load which
is matched to the Thevenin resistance (RL = RTh ). In the next two chapters, we will
see other important applications for Thevenin and Norton equivalents in first-order
and second-order circuits.
To evaluate your mastery of Chapters 3–5, solve Example Exam 5.1 in ebook+ or
Example Exam 5.2 in ebook+.
PROBLEMS
Problem 5.1. For the network in Figure P5.1, find the Thevenin equivalent
with respect to the terminals a and b.
FIGURE P5.1 A two-terminal network containing only independent sources and resistors.
Problem 5.2. Find the Thevenin equivalent for the network in Figure P5.2
FIGURE P5.2 A two-terminal network containing two independent sources and three
resistors.
Problem 5.3. For the two-terminal network in Figure P5.3, find the Norton
equivalent with respect to the terminals a and b.
FIGURE P5.3 A two-terminal network containing two independent sources and four resistors.
Problem 5.4. For the network in Figure P5.4, determine the Thevenin equiv-
alent with respect to the terminals a and b.
FIGURE P5.4 A two-terminal network containing two independent sources and five resistors.
Problem 5.5. For the circuit in Figure P5.5, find the Norton equivalent with
respect to the terminals a and b.
FIGURE P5.5 A two-terminal network containing four independent sources and five resistors.
Problem 5.6. Find the Thevenin equivalent with respect to the terminals a
and b for the two-terminal network in Figure P5.6.
FIGURE P5.6 A two-terminal network containing only independent sources and resistors.
Problem 5.7. For the circuit in Figure P5.7, use source transformations to
solve for the current I X .
FIGURE P5.7 Circuit with five meshes.
Problem 5.8. For the circuit in Figure P5.8, use the number of source trans-
formations to find the Thevenin equivalent with respect to the terminals
where the load resistor RL is connected. Using this Thevenin equivalent,
find and plot I L as a function of RL , VL as a function of RL , and PL as a func-
tion of RL , for a range of load resistance 0.1RTh ≤ RL ≤ 10 RTh.
FIGURE P5.8 Complex circuit involving independent sources and resistors, including an
unspecified load resistor R L .
FIGURE P5.9 A two-terminal network containing mixed sources and resistors.
Problem 5.10. Find the Thevenin equivalent with respect to the terminals a
and b for the network in Figure P5.10.
FIGURE P5.10 A two-terminal network containing two independent sources, a dependent

source, and three resistors.
Problem 5.11. For the circuit in Figure P5.11, find the Thevenin equivalent
FIGURE P5.11 A two-terminal network containing two independent sources, two depen-
dent sources and six resistors.
Problem 5.12. For the circuit in Figure P5.12, find the Thevenin equivalent
FIGURE P5.12 A two-terminal network containing only dependent sources and resistors.
Problem 5.13. Determine the value of load resistance RL which will dissipate
maximum power of the circuit in Figure P5.13. Find the values of I L , VL , and
PL corresponding to this value of the load resistance.
FIGURE P5.13 Circuit including independent sources and resistors with an unspecified
load resistance R L .
Problem 5.14. Find the value of the load resistance RL which will dissipate
maximum power in Figure P5.14. Find the power delivered to the load resis-
tance when it is set to this value.
FIGURE P5.14 Circuit involving mixed sources and resistors, including an unspecified load
resistance R L .
Problem 5.15. For the circuit in Figure P5.15, find the value of the load resis-
tance RL which will dissipate maximum power. Find the power delivered to
the load resistance when it is set to this value.
FIGURE P5.15 Circuit including three independent sources, a dependent source, and ten
resistors, one of which is an unspecified load resistance R L .
Problem 5.16. Find the value of the load resistance RL in Figure P5.16 which
will dissipate maximum power. Find the power delivered to the load resis-
tance when it is set to this value.
FIGURE P5.16 Circuit including mixed sources and an unspecified load resistance R L .
Problem 5.17. For the circuit in Figure P5.17, find the current I S in the volt-
age source VS as a function of its value, by determination of the Thevenin
equivalent for the rest of the circuit.
FIGURE P5.17 Circuit with an unspecified voltage source VS.

Problem 5.18. For the circuit in Figure P5.18, calculate the value of Vx for
each of the following values of Rx: 1kΩ, 2 kΩ, 4 kΩ, 8 kΩ, and 16 kΩ.
FIGURE P5.18 Circuit with an unspecified resistance R X.
Problem 5.19. For the circuit in Figure P5.19, calculate the value of IQ for
each of the following values of RQ : 0.3 Ω, 1Ω, 3 Ω, 10 Ω, and 30 Ω.
FIGURE P5.19 Circuit with an unspecified resistance RQ.

Problem 5.20. Refer to the circuit in Figure P5.20. Find the voltage VZ
that exists between the terminals a and b in the circuit below. (This is the
Thevenin voltage with respect to these two terminals.) Now suppose that
the voltage VZ is to be measured by a voltmeter with a finite input resistance.
Find the voltage which will be measured, and the percent error, for each of
the following three cases of the voltmeter input resistance: 2 MΩ, 5 MΩ, and
10 MΩ. (This can be determined by use of the Thevenin equivalent with
respect to terminals a and b, if the voltage divider rule is utilized.)
FIGURE P5.20 A two-terminal network containing three independent sources and five
resistors.
6 First-Order Circuits
6.1 INTRODUCTION
Up to this point, we have considered only circuits with constant (not time-varying)
voltages and currents. In this chapter, we forge ahead to first-order circuits that have
time-varying circuit quantities. The voltages and currents in these circuits are solu-
tions to first-order homogeneous linear differential equations, and end up being
exponential in nature.
There are two important types of first-order circuits; these are the RC circuit and
the RL circuit. The RC circuit involves a capacitor connected to a resistance (which
may be part of a Thevenin equivalent), whereas an RL circuit involves an inductor
connected with a resistance (which may also be part of a Thevenin equivalent). In
this chapter, we will therefore need to consider two new circuit elements, the capaci-
tor and inductor, to set up our discussions of first-order circuits.
6.2 THE CAPACITOR

The capacitor is a two-terminal element comprising two metal plates separated by an
insulating material, or dielectric, as shown in Figure 6.1.
The application of a voltage across the capacitor with the polarity given in the fig-
ure places positive charges on the top plate and negative charges on the bottom plate.
The positive and negative charges are equal in number, so the capacitor as a whole is
charge neutral, but the separation of charge supports the voltage applied across the
plates. As a consequence of Gauss’ law, the charge on either plate is directly propor-
tional to the applied voltage,
Q = Cv, (6.1)
where Q is the electrical charge on the top plate in Coulombs, v is the applied voltage
in Volts, and C is the capacitance in Farads (in basic units, Farad = Coulomb/Volt).
FIGURE 6.1 The capacitor: (a) physical structure and (b) circuit symbol.
DOI: 10.1201/9781003408529-6 201

The capacitance depends on the geometry of the structure (the area A and separa-
tion of the plates d ) as well as the permittivity εi of the insulating material between
the plates: C = Aε i / d . It is important to recognize that the Farad is a very large
quantity; although supercapacitors of 1 Farad or more have become available, we
will commonly use capacitors measured in microfarads (1µF = 10 −6 F ), nanofarads
(1nF = 10 −9 F ), or even picofarads (1pF = 10 −12 F ).
In an ideal capacitor, no electrical current may flow from one plate to the other
through the insulating material. Nonetheless, an external current in the leads is
necessary to charge and discharge the plates, and this is referred to as a displace-
ment current. Combining the defining relation for electrical current with equa-
tion (6.1),
dQ dv
i= =C . (6.2)
dt dt
Here, we have assumed that the capacitance is constant and not a function of applied
voltage. (This is generally a good assumption but may not hold for some special-
purpose capacitive devices.) Therefore, the above relationship allows us to find the
displacement current if we know the time variation of the voltage. An important
consequence of this equation is that the voltage across a capacitor cannot change
instantaneously in time, because this would require infinite current.
In some cases, we may know the time dependence of the current and desire to
find the resulting voltage. To analyze this situation, we can rearrange the current
equation:
i
dv = dt. (6.3)
C
Integrating both sides, with x as a variable of integration for voltage and y as a vari-
able of integration for time,
v t
1
∫
V0
dx =
C ∫
idy,
0
(6.4)
where V0 is the initial value of the voltage: V0 = v ( 0 ). Evaluating the left-hand integral
at the limits,
t
1
v = V0 +
C
idy.
∫
0
(6.5)
This expression allows us to determine the voltage if the current is known as a func-
tion of time. The current equation (6.2) and the voltage equation (6.5) are two of the
most important relationships for a capacitor.
A third important relationship quantifies the energy stored in the capacitor (by
way of the electric field which exists in the dielectric). To find this relationship, we
start by considering the instantaneous power of the capacitor:
p = vi. (6.6)
First-Order Circuits 203
Using the current equation (6.2), we may write this as

dv
p = vC . (6.7)
dt
Rearranging,
pdt = Cvdv. (6.8)
Integrating both sides, with x as a variable of integration for voltage and y as a vari-
t v
∫0
∫
pdy = C xdx.
0
(6.9)
The expression on the left is the definition of work, so the energy stored in the capacitor is
 x2 v 1 2
w=C = Cv . (6.10)
 2 0 2
Notice that, because we are squaring the voltage, the energy stored in the capacitor
depends only on the absolute value of the voltage and not on its algebraic sign.
6.3 PARALLEL CAPACITORS

When two or more capacitors are connected in parallel, as shown in Figure 6.2, we
may find the equivalent capacitance for the combination, and thereby simplify the
overall circuit.
The total current i may be found by applying KCL, with the recognition that the
three parallel capacitors share the same voltage:
dv dv dv dv
i = i1 + i2 + i3 = C1 + C2 + C3 = (C1 + C2 + C3 ) . (6.11)
dt dt dt dt
The equivalent capacitance for the parallel combination may be found as follows:
dv dv
i = Ceq = (C1 + C2 + C3 ) ; (6.12)
dt dt
FIGURE 6.2 Parallel capacitors.

therefore,
Ceq = C1 + C2 + C3 . (6.13)
Thus, the equivalent capacitance for parallel capacitors is equal to the sum of
the individual capacitors. Although we considered three parallel capacitors here,
this rule applies to any number of parallel capacitors. Moreover, because paral-
lel capacitors share the same voltage, they share the same initial voltage for any
integration.
6.4 SERIES CAPACITORS

Sometimes, we may have series combinations of capacitors, as shown in Figure 6.3.
The current i is common to the series capacitors, but they have different voltages.
By KVL,
v = v1 + v2 + v3
t t t
1 1 1
= V01 +
C1 ∫
idy + V02 +
0
C2 ∫
idy + V03 +
0
C3
idy
∫
0
t
 1 1 1 (6.14)
= (V01 + V02 + V03 ) +  + +  idy
 C1 C2 C3  ∫
0
t
1
= V0eq +
Ceq
idy.
∫
0
FIGURE 6.3 Series capacitors.

Therefore, the initial voltage for the combination is the sum of the individual initial
voltages:
V0eq = V01 + V02 + V03 , (6.15)
and the equivalent capacitance is the reciprocal of the sum of the reciprocals of the
individual capacitances:
−1
 1 1 1
Ceq =  + + . (6.16)
 C1 C2 C3 
In terms of the equivalent capacitance, parallel capacitors combine like series resis-
tors but series capacitors combine like parallel resistors.
To review, see Presentation 6.1 in ebook+.
To test your knowledge, try Quiz 6.1 in ebook+.
6.5 NATURAL RESPONSE OF AN RC CIRCUIT

Suppose that the switch in Figure 6.4 has been in position a for a “long time” before
instantaneously moving to position b at t = 0. The circuitry on the left could repre-
sent any two-terminal network, which has been replaced by its Thevenin equivalent.
Although we are considering a simple resistor on the right for now, we will later
generalize to the case of a Thevenin circuit on the right as well.
When we say that the switch has been in position a for a “long time,” we mean
that the circuit has settled, and therefore all time derivatives have vanished to zero.
Therefore, the capacitor current Cdv / dt will have settled to zero. If we apply KVL at
t = 0 −, the point in time right before the switch moves
−VTh0 + i ( 0 − ) RTh0 + v ( 0 − ) = 0. (6.17)
Because the capacitor current (and therefore the middle term) will have settled to
zero,
v ( 0 − ) = VTh0 . (6.18)
FIGURE 6.4 A switched RC circuit for the consideration of the natural response.
Therefore, the capacitor voltage will have settled to the Thevenin voltage for the
circuitry connected prior to the switch movement. Because the capacitor voltage can-
not change instantaneously, it will still have this value immediately after the switch
movement:
v ( 0 + ) = v ( 0 − ) = VTh0 . (6.19)
If we consider KCL for node b after the switch has moved, then
dv v
C + = 0. (6.20)
dt RTh1
This is a first-order linear homogeneous differential equation. Rearranging,
dv dt
=− . (6.21)
v RTh1C
We can solve this by integrating both sides. Using x as a variable of integration for
voltage and y as a variable of integration for time,
v( t ) t
dx 1
∫
VTh 0
x
=−
RTh1C
dy.
∫
0
(6.22)
Integrating,
v( t ) 1  t
[ln ( x ) VTh 0 = − y (6.23)
RTh1C  0
Applying the limits,
t
ln [ v ( t )] − ln [VTh0 ] = − . (6.24)
RTh1C
The difference of two logarithms is the logarithm of the quotient:
 v (t )  t
ln   =− . (6.25)
 VTh0  RTh1C
Taking the antilogarithm of each side,
v (t )  −t 
= exp  . (6.26)
VTh0  RTh1C 
Therefore, the voltage is given by the exponential function of time:
 −t 
v ( t ) = VTh0 exp  ; t ≥ 0 +. (6.27)
 RTh1C 
The exponential function may also be expressed as
v ( t ) = V0 exp ( −t / τ ); t ≥ 0 + , (6.28)
where V0 is the initial voltage across the capacitor and τ is the “time constant” for
the circuit, given by τ = RTh1C . Figure 6.5 shows the normalized natural response for
an RC circuit; the voltage is normalized by dividing by the initial value and time is
normalized by dividing by the time constant. We can see that the normalized value is
0.05 (95% settled to zero) after three time constants and 0.007 (99.3% settled to zero)
after five time constants. As a practical rule of thumb, we often say that a circuit is
settled after 3–5 time constants, although the actual characteristic reaches its limit-
ing value asymptotically. Therefore, if we require that the switch was in position a
for a “long time” before moving at t = 0, a practical interpretation of this is that the
switch was in its starting position for at least five time constants. When applying this
requirement, we must consider the time constant which existed for t < 0, or RTh0C .
It should be noted that all voltages and currents in an RC circuit will be given
by exponential functions with the same time constant as the capacitor voltage. For
example, the capacitor current may be found by using the capacitor–current relationship:
dv d   −t  
i (t ) = C = C VTh0 exp 
dt dt   RTh1C  
(6.29)
V  −t 
= Th0 exp  ; t ≥ 0 +.
RTh1  RTh1C 
FIGURE 6.5 Normalized natural response for an RC circuit.

As an example, we will find v ( t ) and i ( t ) for t > 0 + of the circuit in Figure 6.6. Here,
the 2 kΩ resistor is connected both before and after the movement of the switch, so
it affects both RTh0 and RTh1. However, the exact value of RTh0 is unimportant if we
are to determine v ( t ) and i ( t ) for t > 0 +, just as long as the switch was in its original
position for a long time. In order to solve this problem, we will first find v ( t ) and then
differentiate to determine i ( t ). This might be more convenient than first finding i ( t )
and then integrating to obtain v ( t ).
In order to find VTh0, we will perform the open-circuit analysis for t < 0 (switch
closed) with respect to the terminals where the capacitor had been connected as
We can apply the node voltage method with a single equation:
VTh0 − 60 V V V
N1 − 24 mA + Th0 + Th0 = 0; (6.30)
5 kΩ 20 kΩ 2 kΩ
60 V / 5 kΩ + 24 mA
VTh0 = = 48.0 V. (6.31)
1 / 5 kΩ + 1 / 20 kΩ + 1 / 2 kΩ
FIGURE 6.6 RC circuit example for consideration of the natural response.
FIGURE 6.7 Open-circuit analysis of the previous circuit for t < 0 with respect to the ter-
minals where the capacitor had been connected.
For t > 0, with the switch open, there are no sources connected to the capacitor
so we are considering a natural response. By inspection, RTh1 = 2 kΩ . Therefore,
V0 = VTh0 = 48.0 V , τ = RTh1C = ( 2 kΩ )( 5 µF ) = 10 ms , and
v ( t ) = 48.0 V exp ( −t / 10 ms ); t ≥ 0 +. (6.32)
The capacitor current may be found by differentiating
dv d   −t  
i (t ) = C = ( 5 µF )  48.0 V exp   
dt dt   10 ms  
(6.33)
=
(5 µF )( 48.0 V )  −t   −t 
= −24.0 mA exp  +
−10 ms
exp 
10 ms  10 ms ; t ≥ 0 .
   
The voltage response is shown in Figure 6.8 and the current response is shown
in Figure 6.9. It can be seen that both settle in approximately five time constants,
which is 50 ms in this case. As stated previously, the voltage across the capacitor
cannot change instantaneously so v ( 0 + ) = v ( 0 − ) = 48.0 V . The same is not true for
the capacitor current, which is proportional to the time derivative of the voltage and
may change instantaneously. Therefore, although the current will have settled to zero
before the switch is moved t ( 0 − )  = 0, the value of current right after the switch
movement is non-zero t ( 0 + ) = −24 mA .
FIGURE 6.8 Natural response (voltage) for the previous example.

FIGURE 6.9 Natural response (current) for the previous example.
FIGURE 6.10 A switched RC circuit for the consideration of the step response.
6.6 STEP RESPONSE OF AN RC CIRCUIT

Now consider the situation depicted in Figure 6.10, in which a capacitor has been
discharged for a “long time” with the switch in position a, and then the switch moves
to position b at t = 0, causing the capacitor to charge asymptotically to VTh1 through
the resistance RTh1.
Therefore, the capacitor current Cdv / dt will have settled to zero. If we apply KVL at
t = 0 −, the point in time right before the switch moves,
i ( 0 − ) RTh0 + v ( 0 − ) = 0. (6.34)
Because the capacitor current (and therefore the left-hand term) will have settled to
zero,
v ( 0 − ) = 0. (6.35)
Because the capacitor voltage cannot change instantaneously, it will still have this
value immediately after the switch movement:
v ( 0 + ) = v ( 0 − ) = 0. (6.36)
dv v − VTh1
C + = 0. (6.37)
dt RTh1
This is a first-order linear differential equation. Rearranging,
dv dt
= . (6.38)
VTh1 − v RTh1C
We can solve by integrating both sides. Using x as a variable of integration for volt-
age and y as a variable of integration for time,
v( t ) t
dx 1
∫
0
=
VTh1 − x RTh1C
dy.
∫ 0
(6.39)
Integrating,
v( t ) 1
[ln (VTh1 − x ) 0 = − y t . (6.40)
RTh1C  0
t
ln [VTh1 − v ( t )] − ln [VTh1 ] = − . (6.41)
RTh1C
 V − v (t )  t
ln  Th1 =− . (6.42)
 VTh1  RTh1C
VTh1 − v ( t )  −t 
= exp  . (6.43)
VTh1  RTh1C 
  −t  
v ( t ) = VTh1 1 − exp  +
  ; t ≥ 0 . (6.44)
  RTh1C 
v ( t ) = VF [1 − exp ( −t / τ )]; t ≥ 0 + , (6.45)
where VF is the final voltage across the capacitor and τ is the “time constant” for the
circuit, given by τ = RTh1C . Figure 6.11 shows the normalized step response for an
RC circuit. Similar to the case of the natural response, the value is 95% settled after
three constants and 99.3% settled after five time constants; the difference is that the
normalized step response asymptotically approaches unity rather than zero.
As an example, consider the circuit in Figure 6.12. This circuit is almost exactly
the same as the one considered in the previous section; the only difference is that the
FIGURE 6.11 Normalized step response for an RC circuit.
FIGURE 6.12 RC circuit example for consideration of the step response.

switch closes rather than opening at t = 0, and this produces a step response. There
is no source connected to the capacitor for t < 0 so VTh0 = 0 . The value of RTh0 is
unimportant provided that the switch has been in its starting position for a long time,
allowing the circuit to have settled before we move the switch.
There is no source connected to the capacitor for t < 0 so VTh0 = 0 . In order to find
VTh1, we will perform the open-circuit analysis for t > 0 (switch closed) with respect
to the terminals where the capacitor had been connected as shown in Figure 6.13.
We can apply the node voltage method with a single equation:
VTh1 − 60 V V V
N1 − 24 mA + Th1 + Th1 = 0 (6.46)
5 kΩ 20 kΩ 2 kΩ
and
60 V / 5 kΩ + 24 mA
VTh1 = = 48.0 V. (6.47)
1 / 5 kΩ + 1 / 20 kΩ + 1 / 2 kΩ
Next, we will perform the short-circuit analysis for t > 0 with respect to the terminals
where the capacitor had been connected, as shown in Figure 6.14. There is only one
FIGURE 6.13 Open-circuit analysis of the previous circuit for t > 0 with respect to the
terminals where the capacitor had been connected.
FIGURE 6.14 Short-circuit analysis of the previous circuit for t > 0 with respect to the
essential node (the reference node) so it is unnecessary to solve for any node voltages.
Also, under short-circuit conditions, no current flows in either the 20 kΩ resistor or
the 2 kΩ resistor, because there is zero voltage applied across both of them.
The short-circuit current is given by
60 V
I SC1 = + 24 mA = 36.0 mA. (6.48)
5 kΩ
The Thevenin resistance RTh1 for t > 0 is therefore
VOC1 VTh1 48.0 V

RTh1 = = = = 1.333 kΩ. (6.49)
I SC1 I SC1 36.0 mA
The final voltage is VF = VTh1 = 48.0 V and the time constant is

τ = RTh1C = (1.333 kΩ )( 5 µF ) = 6.66 ms so the capacitor voltage is therefore
v ( t ) = 48.0 V 1 − exp ( −t / 6.66 ms )  , t ≥ 0 +. (6.50)
The capacitor current is
i (t ) = C
dv
dt
= ( 5 µF )
d
dt
{48.0 V 1 − exp ( −t / 6.66 ms )  }
(6.51)
=
(5 µF )( −48.0 V ) exp  −t   −t  +
−6.66 ms  6.66 ms  = 36.0 mA exp  6.66 ms  , t ≥ 0 .
   
So although the voltage has a non-zero final value, the current decays to zero. (It is
always true that the capacitor current will approach zero as the circuit settles and all
time derivatives decay to zero.)
6.7 GENERAL CASE OF NATURAL AND STEP

RESPONSE IN AN RC CIRCUIT
In the general case of a switched RC circuit, the initial and final values for the capaci-
tor voltage may both be non-zero. Then, the total response is the sum of the natural
response (associated with the initial voltage) and the step response (associated with
the final value of voltage). This corresponds to a circuit of the type shown in Figure
6.15. Here, the capacitor has been connected for a long time to a two-terminal net-
work with Thevenin voltage VTh0 and Thevenin resistance RTh0, and after t = 0 is con-
nected to a two-terminal network with Thevenin voltage VTh1 and Thevenin resistance
RTh1. Keep in mind that the overall circuit configuration may not look exactly like the
one shown in Figure 6.15, because other switch configurations may be used and it
is possible that some circuit elements may be common to the two Thevenin circuits.
Considering the configuration in Figure 6.15, if we apply KVL at t = 0 −, the point
in time right before the switch moves,
FIGURE 6.15 A switched RC circuit for the consideration of the general case of the natural
and step response.
−VTh0 + i ( 0 − ) RTh0 + v ( 0 − ) = 0. (6.52)
Because the capacitor current (and therefore the middle term) will have settled to
zero,
v ( 0 − ) = VTh0 . (6.53)
Because the capacitor voltage cannot change instantaneously, it will still have this
v ( 0 + ) = v ( 0 − ) = VTh0 . (6.54)
dv v − VTh1
C + = 0. (6.55)
dt RTh1
dv dt
=− . (6.56)
v − VTh1 RTh1C
We can solve by integrating both sides. Using x as a variable of integration for volt-
age and y as a variable of integration for time,
v( t ) t
dx 1
∫
VTh 0
x − VTh1
=−
RTh1C
dy.
∫
0
(6.57)
Integrating,
v( t ) 1
[ln ( x − VTh1 ) V =− y t . (6.58)
Th 0 RTh1C  0
t
ln [ v ( t ) − VTh1 ) ] − ln [VTh0 − VTh1 ] = − . (6.59)
RTh1C
 v ( t ) − VTh1  t
ln   =− . (6.60)
 VTh0 − VTh1  RTh1C
v ( t ) − VTh1  −t 
= exp  . (6.61)
VTh0 − VTh1  RTh1C 
 −t 
v ( t ) = VTh1 + (VTh0 − VTh1 ) exp  ; t ≥ 0 +. (6.62)
 RTh1C 
This function may also be expressed as
v ( t ) = VF + (V0 − VF ) exp ( −t / τ ); t ≥ 0 + , (6.63)
where V0 is the initial voltage (V0 = VTh0 ), VF is the final voltage (VF = VTh1 ), and τ is
the “time constant” given by τ = RTh1C . The same form is applicable to any voltage
or current in an RC circuit. This is extremely useful because it allows us to imme-
diately write the solution for any such voltage or current as long as the initial value,
final value, and time constant are known. For example, the current in the capacitor
may be written as
i ( t ) = I F + ( I 0 − I F ) exp ( −t / τ ); t ≥ 0 + , (6.64)
where I 0 is the initial current, I F is the final current, and τ is the “time constant.” (The
time constant takes on the same value for any voltage or current in an RC circuit.)
Lastly, we should note that the overall response can be considered to be the sum
of the natural and step response:
v ( t ) = V0 exp ( −t / τ ) + VF [1 − exp ( −t / τ )]; t ≥ 0 +. (6.65)

natural response step response
Here, the natural response is associated with the initial value term while the step
response is associated with the final value terms.
As an example, consider the RC circuit in Figure 6.16. The switch has been in its
starting position for a “long time” before moving at t = 0, and we want to determine
v ( t ) and i ( t ) for t > 0 +. By inspection, VTh0 = 15V and RTh0 = 2 kΩ.
FIGURE 6.16 RC circuit example for consideration of the natural and step response.
With the switch closed, we may use the open-circuit and short-circuit analyses to
find VTh1 and RTh1. Figure 6.17 shows the labeling of nodes for use of the node voltage
method with the open-circuit analysis.
Using units of V, mA, and kΩ,
V1 − V2 V −V
N1 − 10 + 1 3 = 0, (6.66)
6 1
V2 − V1 V
N2 + 10 + 2 = 0, (6.67)
6 0.5
and
V3 − V1 V − 15
N3 − 2iβ + 3 = 0. (6.68)
1 2
The equation of the current controlling the dependent source is
V2 − V1
DS iβ = . (6.69)
6
Substituting the DS equation into the N3 equation,
V1 − V2 V −V
N1 − 10 + 1 3 = 0, (6.70)
6 1
V2 − V1 V
N2 + 10 + 2 = 0, (6.71)
6 0.5
V3 − V1 V −V V − 15
N 3 DS − 2  2 1  + 3 = 0. (6.72)
1  6  2
N 1 V1 − V2 − 60 + 6V1 − 6V3 = 0, (6.73)
N 2 V2 − V1 + 60 + 12V2 = 0, (6.74)
and
N 3 DS 6V3 − 6V1 − 2V2 + 2V1 + 3V3 − 45 = 0. (6.75)
N 1 7V1 − V2 − 6V3 = 60, (6.76)
N 2 − V1 + 13V2 = −60, (6.77)
and
N 3 DS − 4V1 − 2V2 + 9V3 = 45. (6.78)
In matrix form,
 7 −1 −6   V1   60 
 −1  V   .
 13 0  2  =  −60  (6.79)
 −4 −2 9   V3   45
 
Solving,
60 −1 −6
−60 13 0
45 −2 9
V1 = = −19.07 V, (6.80)
7 −1 −6
−1 13 0
−4 −2 9
7 60 −6
−1 −60 0
−4 45 9
V2 = = −3.15V, (6.81)
7 −1 −6
−1 13 0
−4 −2 9
and
7 −1 60
−1 13 −60
−4 −2 45
V3 = = 12.78 V. (6.82)
7 −1 −6
−1 13 0
−4 −2 9
Therefore,
VTh1 = VOC1 = V3 = 12.78 V. (6.83)
where the capacitor had been connected, as shown in Figure 6.18.
Using units of V, mA, and kΩ,
V1 − V2 V
N1 − 10 + 1 = 0 (6.84)
6 1
and
V2 − V1 V
N2 + 10 + 2 = 0. (6.85)
6 0.5
N 1 V1 − V2 − 60 + 6V1 = 0 (6.86)
and
N 2 V2 − V1 + 60 + 12V2 = 0. (6.87)
N 1 7V1 − V2 = 60 (6.88)
and
N 2 − V1 + 13V2 = −60. (6.89)
In matrix form,
 7 −1   V1   60 
 −1  = . (6.90)
 13   V2   −60 
Solving,
60 −1
−60 13
V1 = = 8.00 V (6.91)
7 −1
−1 13
and
7 60
−1 −60
V2 = = −4.00 V. (6.92)
7 −1
−1 13
The short-circuit current is given by
V1 15V V  V − V  15V
I SC1 = + 2iβ + = 1 + 2 2 1  + = 11.50 mA. (6.93)
1kΩ 2 kΩ 1kΩ  6 kΩ  2 kΩ
The Thevenin resistance RTh1 for t > 0 is therefore
VOC1 VTh1 12.78 V

RTh1 = = = = 1.111kΩ. (6.94)
I SC1 I SC1 11.50 mA
The initial voltage is V0 = VTh0 = 15V, the final voltage is VF = VTh1 = 12.78 V and the time
constant is τ = RTh1C = (1.111kΩ )( 2 µF ) = 2.22 ms so the capacitor voltage is therefore
v ( t ) = VF + (V0 − VF ) exp ( −t / τ )
(6.95)
= 12.78 V + 2.22 V exp ( −t / 2.22 ms ); t ≥ 0 +
The capacitor current is
i (t ) = C
dv
dt
= ( 2 µF )
d
dt
{
12.78 V + 2.22 V exp ( −t / 2.22 ms ) }
(6.96)
=
( 2 µF )( 2.22 V ) exp  −t   −t  +
−2.22 ms  2.22 ms  = −2.00 mA exp  2.22 ms  . t ≥ 0 .
   
It should be noted that the general form of the solution for the step plus natural
response is always applicable, although either VF or V0 may be zero in the special
cases of the natural response or step response, respectively.
To test your knowledge, try Quiz 6.3 in ebook+. To put your knowledge to prac-
tice, try Laboratory Exercise 6.1 in ebook+.
6.8 THE INDUCTOR

The inductor is a two-terminal element which involves a coil of wire wrapped around
a core which could be air or some magnetic material shown in Figure 6.19. Flowing
a current through the coil gives rise to magnetic flux, which links the coil and is in a
direction determined by the “right-hand rule.”
FIGURE 6.19 The inductor; (a) physical structure and (b) circuit symbol.
Quantitatively, the magnetic flux density B in a linear magnetic medium is

given by
B = µ H = µ Ni, (6.97)
where µ is the permeability of the medium (Wb m −2 A −1), H is the magnetic field
intensity (A), N is the number of turns in the coil, and i is the electrical current
(A). The magnetic flux φ is the product of the flux density B and the cross-sectional
area A:
φ = AB = Aµ Ni. (6.98)
By the Faraday law, the voltage developed across the coil is proportional to the time
rate of change of the magnetic flux linkage:
dλ dNφ di di
v= = = Aµ N 2 = L , (6.99)
dt dt dt dt
where λ = Nφ is the magnetic flux linkage (Wb) and L is the inductance in units of
Henries (H). It is clear from this equation that the inductance depends on the device
geometry as well as the magnetic medium. Like the Farad, the Henry is a very large
quantity. In most practical applications, we will use inductors measured in millihen-
ries (1mH = 10 −3 H) or microhenries (1µH = 10 −6 H).
The voltage equation, v = Ldi / dt , is one of the three most important equations for
the inductor, and it allows us to find the voltage if the current is known as a function
of time. It also reveals that the inductor current may not change instantaneously in
time, because that would require infinite voltage. We can derive an equation for the
current as follows. First, we rearrange the voltage equation:
v
di = dt. (6.100)
L
Integrating both sides, with x as a variable of integration for current and y as a vari-
i t
1
∫
I0
dx =
L∫vdy,
0
(6.101)
where I 0 is the initial value of the current: I 0 = i ( 0 ). Evaluating the left-hand integral
at the limits,
t
1
i = I0 +
L ∫
vdy.
0
(6.102)
This expression allows us to determine the current if the voltage is known as a func-
tion of time.
A third important relationship quantifies the energy stored in the inductor (by way
of the magnetic field). To find this relationship, we start by considering the instanta-
neous power of the inductor:
p = iv. (6.103)
Using the voltage equation, we may write this as
di
p = iL . (6.104)
dt
Rearranging,
pdt = Lidi. (6.105)
Integrating both sides, with x as a variable of integration for current and y as a vari-
t i
∫ pdy = L ∫xdx.
0 0
(6.106)
The expression on the left is the definition of work, so the energy stored in the capacitor is
 x2 i 1 2
w = L = Li . (6.107)
 2 0 2
Because we are squaring the current, the energy stored in the inductor depends only
on the absolute value of the current and not on its algebraic sign. This is approxi-
mately true for a real inductor if it is approximately linear and free from saturation
and residual magnetization effects.
6.9 SERIES INDUCTORS

When two or more inductors are connected in series, as shown in Figure 6.20, we can
find the equivalent inductance for the combination and this may allow us to simplify
the overall circuit.
The total voltage v may be found by applying KVL, with the recognition that the
three series inductors share the same current:
di di di di
v = v1 + v2 + v3 = L1 + L2 + L3 = ( L1 + L2 + L3 ) . (6.108)
dt dt dt dt
The equivalent inductance for the series combination may then be found.
di di
v = Leq = ( L1 + L2 + L3 ) ; (6.109)
dt dt
therefore,
Leq = L1 + L2 + L3 . (6.110)
FIGURE 6.20 Series inductors.
Thus, the equivalent inductance for series inductors is equal to the sum of the indi-
vidual inductances. Although we considered three series inductors here, this rule
applies to any number. Moreover, because series inductors share the same current,
they share the same initial current for any integration.
6.10 PARALLEL INDUCTORS

Sometimes, we may have parallel combinations of inductors, as shown in Figure 6.21.
The voltage v is common to the parallel inductors, but they have distinct currents.
By KCL,
i = i1 + i2 + i3
t t t
1 1 1
= I 01 +
L1 ∫
vdy + I 02 +
0
L2 ∫
vdy + I 03 +
0
L3
vdy
∫
0
t
 1 1 1 (6.111)
= ( I 01 + I 02 + I 03 ) +  + +
∫
 L1 L2 L3 
0
vdy
t
1
= I 0eq +
Leq ∫
vdy.
0
FIGURE 6.21 Parallel inductors.
Therefore, the initial current for the combination is the sum of the individual initial
voltages:
I 0eq = I 01 + I 02 + I 03 , (6.112)
and the equivalent inductance is the reciprocal of the sum of the reciprocals of the
individual inductances:
−1
 1 1 1
Leq =  + + . (6.113)
 L1 L2 L3 
In terms of the equivalent value, series and parallel inductances combine in a manner
like resistors.
6.11 NATURAL RESPONSE OF AN RL CIRCUIT

Suppose that the switch in Figure 6.22 has been in position a for a “long time” before
instantaneously moving to position b at t = 0 . Prior to the switch movement, the
inductor is connected to a two-terminal network represented by its Norton equiva-
lent comprising a current source I N 0 and a parallel resistance RN 0 . (This is com-
pletely general; any two-terminal circuit containing sources and resistors may be
represented by its Norton equivalent.) After movement of the switch, the inductor is
connected to a simple resistance RN1.
The switch used here is a special type, known as a “make-before-break” switch
because it makes contact with b before breaking contact with a. The configuration
shown requires a make-before-break switch to avoid a momentary interruption of the
inductor current, which would give rise to a large induced voltage (Ldi / dt ) and cause
arcing across the physical contacts. We will see that in some circuit configurations
it is possible to use a simple single-pole, single-throw switch as long as a path for
inductor current exists for both positions of the switch.
FIGURE 6.22 A switched RL circuit for the consideration of the natural response.
Therefore, the inductor voltage Ldi / dt will have settled to zero. If we apply KCL at
t = 0 − , the point in time right before the switch moves,
v ( 0− )
−IN 0 + + i ( 0 − ) = 0. (6.114)
RN 0
Because the inductor voltage (and therefore the middle term) will have settled to zero,
i ( 0− ) = I N 0 . (6.115)
Therefore, the inductor current will have settled to the Norton current for the cir-
cuitry connected prior to the switch movement. Because the inductor current can-
not change instantaneously, it will still have this value immediately after the switch
movement:
i ( 0+ ) = i ( 0− ) = I N 0 . (6.116)
If we consider KVL for the right-hand mesh after the switch has moved, then
di
−L − iRN 1 = 0. (6.117)
dt
This is a first-order linear homogeneous differential equation. Rearranging,
di dt
=− . (6.118)
i L / RN 1
We can solve by integrating, with x as a variable of integration for current and y as a

variable of integration for time,
i( t ) t
dx 1
∫
IN 0
x
=−
L / RN 1
dy.
∫
0
(6.119)
Integrating,
i (t ) 1  t
[ln ( x ) I N 0 = − y . (6.120)
L / RN 1  0
t
ln [ i ( t )] − ln [ I N 0 ] = − . (6.121)
L / RN 1
 i (t )  t
ln  =− . (6.122)
 I N 0  L / RN 1
i (t )  −t 
= exp  . (6.123)
IN0  L / RN 1 
Therefore, the inductor current is described by the exponential function of time:
 −t 
i ( t ) = I N 0 exp  ; t ≥ 0 +. (6.124)
 L / RN 1 
i ( t ) = I 0 exp ( −t / τ ); t ≥ 0 + , (6.125)
where I 0 = I N 0 is the initial current in the inductor and τ is the “time constant” for
the circuit, given by τ = L / RN 1. As in the case of the RC circuit, all voltages and
currents are exponential functions of time, exhibit the same time constant, and
settle after about five time constants. For example, the inductor voltage may be
found by using the inductor voltage relationship:
di d   −t  
v (t ) = L = L  I N 0 exp 
dt dt   L / RN 1  
(6.126)
 −t 
= I N 0 RN 1 exp  ; t ≥ 0 +.
 L / RN 1 
FIGURE 6.23 A switched RL circuit for the consideration of the step response.
6.12 STEP RESPONSE OF AN RL CIRCUIT

Now consider the situation depicted in Figure 6.23, in which an inductor has been
connected to a resistor for a long time with the make-before-break switch in position
a, and then the switch moves to position b at t = 0 , causing the inductor current to
increase asymptotically to I N1 with a parallel resistance RN1.
Therefore, the inductor voltage Ldi / dt will have settled to zero. If we apply KCL
with respect to node a at t = 0 − , the point in time right before the switch moves,
i ( 0 − ) RN 0 + Ldi / dt = 0. (6.127)
Because the inductor voltage (and therefore the right-hand term) will have settled to zero,
i ( 0− ) = 0 (6.128)
Because the inductor current cannot change instantaneously, it will still have this
i ( 0 + ) = i ( 0 − ) = 0. (6.129)
Ldi / dt
i − I N1 + = 0. (6.130)
RN 1
di dt
− =− . (6.131)
I N1 − i L / RN 1
We can solve by integrating both sides. Using x as a variable of integration for current
and y as a variable of integration for time,
i (t ) t
dx 1
∫
0
=
I N 1 − i L / RN 1 ∫
dy.
0
(6.132)
Integrating,
i (t ) 1  t
−[ln ( I N 1 − x ) 0 = y . (6.133)
L / RN 1  0
t
ln [ I N 1 − i ( t )] + ln [ I N 1 ] = − . (6.134)
L / RN 1
 I − i (t )  t
ln  N 1 =− . (6.135)
 I N 1  L / RN 1
I N1 − i (t )  −t 
= exp  . (6.136)
I N1  L / RN 1 
  −t  
i ( t ) = I N 1 1 − exp  +
  ; t ≥ 0 . (6.137)
  L / RN 1 
i ( t ) = I F [1 − exp ( −t / τ )]; t ≥ 0 +. (6.138)
where I F is the final current in the inductor and τ is the “time constant” for the cir-
cuit, given by τ = L / RN 1.
6.13 GENERAL CASE OF THE NATURAL AND

STEP RESPONSE IN AN RL CIRCUIT
In the general case of a switched RL circuit, the initial and final values for the induc-
tor current may both be non-zero. Then, the total response is the sum of the natural
response (associated with the initial current) and the step response (associated with the
final value of current). This corresponds to a circuit of the type shown in Figure 6.24.
Here, the inductor has been connected for a long time to a two-terminal network with
FIGURE 6.24 A switched RL circuit for the consideration of the general case of the natural
and step response.
Norton current I N 0 and Norton resistance RN 0 , and after t = 0 is connected to a two-

terminal network with Norton current I N1 and Norton resistance RN1. Keep in mind that
the overall circuit configuration may not look exactly like the one shown in Figure 6.24,
because other switch configurations may be used and it is possible that some circuit
elements may be common to the two Norton circuits.
Considering the configuration in Figure 6.24, if we apply KCL to node a at t = 0 − ,
the point in time right before the switch moves,
Ldi / dt
−IN 0 + + i ( 0 − ) = 0. (6.139)
RN 0
Because the inductor voltage (and therefore the middle term) will have settled to zero,
i ( 0− ) = I N 0 . (6.140)
Because the inductor current cannot change instantaneously, it will still have this
i ( 0+ ) = i ( 0− ) = I N 0 . (6.141)
Ldi / dt
i − I N1 + = 0. (6.142)
RN 1
Rearranging,
di dt
=− . (6.143)
i − I N1 L / RN 1
We can solve by integrating both sides. Using x as a variable of integration for current
and y as a variable of integration for time,
i (t ) t
dx 1
∫
IN 0
i − I N1
=−
L / RN 1
dy.
∫
0
(6.144)
Integrating,
i (t ) 1  t
[ln ( i − I N 1 ) I =− y . (6.145)
N0 L / RN 1  0
t
ln [ i ( t ) − I N 1 ) ] − ln [ I N 0 − I N 1 ] = − . (6.146)
L / RN 1
 i (t ) − I N1  t
ln  =− . (6.147)
 I N 0 − I N 1  L / RN 1
i (t ) − I N1  −t 
= exp  . (6.148)
I N 0 − I N1  L / RN 1 
Therefore, the current is given by the exponential function of time:
 −t 
i ( t ) = I N 1 + ( I N 0 − I N 1 ) exp  ; t ≥ 0 +. (6.149)
 L / RN 1 
This function may also be expressed as
i ( t ) = I F + ( I 0 − I F ) exp ( −t / τ ); t ≥ 0 +. (6.150)
where I 0 is the initial current ( I 0 = I N 0 ), I F is the final current ( I F = I N1 ), and τ is the

“time constant” given by τ = L / RN 1. The same form is applicable to any voltage or
current in an RL circuit. This is extremely useful because it allows us to immediately
write the solution for any such voltage or current as long as the initial value, final
value, and time constant are known. For example, the voltage across the inductor
may be written as
v ( t ) = VF + (V0 − VF ) exp ( −t / τ ); t ≥ 0 + , (6.151)
where V0 is the initial voltage, VF is the final voltage, and τ is the “time constant.” It
should be noted that the final value of the inductor voltage will always be zero (all
time derivatives will settle to zero). Also, the time constant takes on the same value
for any voltage or current in an RL circuit.
As in the RC circuit, the overall response can be considered to be the sum of the
natural and step response:
i ( t ) = I 0 exp ( −t / τ ) + I F [1 − exp ( −t / τ )]; t ≥ 0 +. (6.152)

natural response step response
Here, the natural response is associated with the initial value term while the step
response is associated with the final value terms.
As an example, consider the RL circuit in Figure 6.25. The switch has been in its
starting position for a “long time” before moving at t = 0 , and we want to determine
v ( t ) and i ( t ) for t > 0 + .
We can use a short-circuit analysis for t < 0 (switch open) to find I SC0 as shown in
Figure 6.26.
FIGURE 6.25 RL circuit example for consideration of the natural and step response.
FIGURE 6.26 Short-circuit analysis of the previous circuit for t < 0 with respect to the
terminals where the inductor had been connected.
Using units of V, A, and Ω,
V1 − V2 V V +5
N1 −2+ 1 + 1 =0 (6.153)
4 20 5
and
V2 − V1 V
N2 + 2 + 2 = 0. (6.154)
4 2
N 1 5V1 − 5V2 − 40 + V1 + 4V1 + 20 = 0 (6.155)
and
V2 − V1 + 8 + 2V2 = 0. (6.156)
N 1 10V1 − 5V2 = 20 (6.157)
and
N 2 − V1 + 3V2 = −8. (6.158)
In matrix form,
 10 −5   V1   20 
 −1  = . (6.159)
 3   V2   −8 
Solving,
20 −5
−8 3
V1 = = 0.800 V (6.160)
10 −5
−1 3
and
10 20
−1 −8
V2 = = −2.40 V. (6.161)
10 −5
−1 3
Therefore,
V1 V1 + 5 V
I N 0 = I SC0 = + = 1.200 A. (6.162)
20 Ω 5Ω
where the inductor is connected, as shown in Figure 6.27.
V1 − V2 V V +5
N1 −2+ 1 + 1 =0 (6.163)
4 20 5
and
V2 − V1 V
N2 + 2 + 2 = 0. (6.164)
4 2
N 1 5V1 − 5V2 − 40 + V1 + 4V1 + 20 = 0 (6.165)
and
N 2 V2 − V1 + 8 + 2V2 = 0. (6.166)
N 1 10V1 − 5V2 = 20 (6.167)
and
N 2 − V1 + 3V2 = −8. (6.168)
terminals where the inductor is connected.
In matrix form,
 10 −5   V1   20 
 −1  = . (6.169)
 3   V2   −8 
Solving,
20 −5
−8 3
V1 = = 0.800 V (6.170)
10 −5
−1 3
and
10 20
−1 −8
V2 = = −2.40 V. (6.171)
10 −5
−1 3
Therefore,
V1 V1 + 5 V
I N 1 = I SC1 = + + 1.00 A = 2.200 A. (6.172)
20 Ω 5Ω
Finally, we will perform the open-circuit analysis for t > 0 with respect to the termi-
nals where the inductor is connected, as shown in Figure 6.28. This will enable the
determination of RN1 and the time constant.
terminals where the inductor is connected.
V1 − V2 V − V V + 5 − V3
N1 −2+ 1 3 + 1 = 0, (6.173)
4 20 5
V2 − V1 V
N2 + 2 + 2 = 0, (6.174)
4 2
and
V3 − V1 V3 − 5 − V1 V3 V
N3 + + − 1 + 3 = 0. (6.175)
20 5 10 5
N 1 5V1 − 5V2 − 40 + V1 − V3 + 4V1 + 20 − 4V3 = 0, (6.176)
N 2 V2 − V1 + 8 + 2V2 = 0, (6.177)
and
N 3 V3 − V1 + 4V3 − 20 − 4V1 + 2V3 − 20 + 4V3 = 0. (6.178)
N 1 10V1 − 5V2 − 5V3 = 20, (6.179)
N 2 − V1 + 3V2 = −8, (6.180)
and
N 3 − 5V1 + 11V3 = 40. (6.181)
In matrix form,
 10 −5 −5   V1   20 
 −1  V   
 3 0  2  =  −8 . (6.182)
 −5 0 11   V3   40 

Solving,
20 −5 −5
−8 3 0
40 0 11
V1 = = 4.10 V, (6.183)
10 −5 −5
−1 3 0
−5 0 11
10 20 −5
−1 −8 0
−5 40 11
V2 = = −1.300 V, (6.184)
10 −5 −5
−1 3 0
−5 0 11
and
10 −5 20
−1 3 −8
−5 0 40
V3 = = 5.50 V. (6.185)
10 −5 −5
−1 3 0
−5 0 11
Therefore, after movement of the switch,
VOC1 = V3 = 5.50 V (6.186)
and
VOC1 5.50 V
RN 1 = = = 2.50 Ω. (6.187)
I SC1 2.20 A
The initial current is I 0 = I N 0 = 1.200 A , the final current is I F = I N 1 = 2.20 A , and

the time constant is τ = L / RN 1 = 0.1H / 2.50 Ω = 40 ms so the inductor current is
therefore
i ( t ) = I F + ( I 0 − I F ) exp ( −t / τ )
(6.188)
= 2.20 A − 1.00 A exp ( −t / 40 ms ) ; t ≥ 0 +.
The inductor voltage is
v (t ) = L
di
dt
= ( 0.1H )
d
dt
{
2.20 A − 1.00 A exp ( −t / 40 ms ) }
(6.189)
=
( 0.1H )( −1.00 A ) exp  −t   −t  +
−40 ms  40 ms  = 2.50 V exp  40 ms  . t ≥ 0 .
   
As expected for the inductor, the final value of the voltage is zero.
6.14 SEQUENTIAL SWITCHING IN FIRST-ORDER CIRCUITS

The general principles presented in the previous sections may be extended to first-
order circuits in which there are two or more switching events occurring at different
times. In such a case, the initial condition for the second or later switching event is
determined by considering the solution for the previous switching event. To illustrate
this, we will consider two sequential switching examples: one involving an RL cir-
cuit and one involving an RC circuit.
Consider the RL circuit in Figure 6.29. Here, there are two switches: switch one
closes at t = 0 and then switch two closes at t = 10 ms.
For t < 0 , with both switches open as shown in Figure 6.30, there are no sources
connected to the inductor, and
I SC0 = 0. (6.190)
Next, we will consider 0 + ≤ t ≤ 10 ms− , for which switch one is closed but switch two
is still open as shown in Figure 6.31.
The short-circuit current with respect to the terminals where the inductor is con-
nected is
8V
I SC1 = = 0.2 A. (6.191)
40 Ω
FIGURE 6.29 An RL circuit with two sequential switching events.
FIGURE 6.30 The previous RL circuit for t < 0 (both switches open).
FIGURE 6.31 The previous RL circuit for 0 + ≤ t ≤ 10 ms − (switch one closed, switch two
open).
By the resistance shortcut analysis,
RN 1 = 40 Ω  10 Ω  8 Ω = 4 Ω. (6.192)
For this time interval (which we will refer to as time interval one), the initial cur-
rent is I 01 = I N 0 = 0 , the final current is I F 1 = I N 1 = 0.2 A , and the time constant is
τ 1 = L / RN 1 = 50 mH / 4 Ω = 12.5 ms. The solution for the inductor current during this
time interval is therefore
i ( t ) = I F 1 + ( I 01 − I F 1 ) exp ( −t / τ 1 )
(6.193)
=  0.2 − 0.2 exp ( −t / 12.5 ms )  A; 0 + ≤ t ≤ 10 ms−
We can also solve for the inductor voltage by differentiating
di d
v (t ) = L = ( 50 mH )  0.2 − 0.2 exp ( −t / 12.5 ms )  A
dt dt
=
(50 mH )( −0.2 A ) exp  −t   −t  + −
−12.5 ms  12.5 ms  = 0.8 V exp  40 ms  ; 0 ≤ t ≤ 10 ms .
   
(6.194)
Before we move on to the second switching event, it is worth noting that the circuit
will never settle to the “final values” for time interval one. This is because the sec-
ond switch will move at t = 10 ms whereas it would take about five time constants, or
62.5 ms, for the circuit to settle.
For consideration of the second time interval after the second switching event,
t ≥ 10 ms+ , we will use the solution for the first switching event, evaluated at t = 10 ms
to find the initial condition:
I 02 = i (10 ms+ ) = i (10 ms− )

(6.195)
=  0.2 − 0.2 exp ( −10 ms / 12.5 ms )  A = 0.110 A.
FIGURE 6.32 The previous RL circuit for t ≥ 10 ms + (both switches closed).
To find the final value of the current for time interval two, we need to find the short-
circuit current with respect to the terminals where the inductor is connected, for
the situation in which both switches have moved to their final positions as shown in
Figure 6.32.
The short-circuit current with respect to the terminals where the inductor is con-
nected is
8V
I SC2 = + 100 mA = 0.3 A. (6.196)
40 Ω
RN 2 = 40 Ω  10 Ω  8 Ω  6 Ω = 2.4 Ω. (6.197)
For the second time interval (t ≥ 10 ms+ ), the initial current is I 01 = 0.110 A
as found above, the final current is I F 2 = I N 2 = 0.3 A , and the time constant is
τ 2 = L / RN 2 = 50 mH / 2.4 Ω = 20.83 ms . The solution for the inductor current dur-
ing this time interval is therefore
i ( t ) = I F 2 + ( I 02 − I F 2 ) exp ( −(t − t1 ) / τ 2 )
(6.198)
=  0.3 − 0.190 exp ( −(t − 10 ms) / 20.83 ms )  A; t ≥ 10 ms + ,
where t1 is the time of the second switching event, which corresponds to the initial
value calculated for time interval two.
We can also solve for the inductor voltage by differentiating
di d
v (t ) = L = ( 50 mH )  0.3 − 0.190 exp ( −(t − 10 ms) / 20.83 ms )  A
dt dt
=
(50 mH )( −0.190 A ) exp  − (t − 10 ms)  = 0.456 V exp  − (t − 10 ms)  ;
   
−20.83 ms  20.83 ms   20.83 ms 
t ≥ 10 ms+ .
(6.199)
The overall solution for the current may be expressed in a piecewise fashion:
  0.2 − 0.2 exp ( −t / 12.5 ms )  A;

   0 + ≤ t ≤ 10 ms− ;
i (t ) = 
  0.3 − 0.190 exp ( −(t − 10 ms) / 20.83 ms )  A; t ≥ 10 ms + .

(6.200)
Similarly, the overall voltage solution is
  0.8 exp ( −t / 12.5 ms )  V;

   0 + ≤ t ≤ 10 ms− ;
v (t ) =  (6.201)
  0.456 exp ( −(t − 10 ms) / 20.83 ms )  V; t ≥ 10 ms + .

A similar approach may be applied to solve an RC circuit with sequential switching.
Consider the circuit in Figure 6.33, which involves three switching events: switch one
moves at t = 0 , switch two moves at t = 20 ms , and switch three moves at t = 40 ms .
Notice that switch two opens whereas the other two switches close; in general, we
could have any mix of openings and closures so this must be observed carefully.
For t ≤ 0 − , all switches are in their starting positions as shown in Figure 6.34
(switch one is open, switch two is closed, and switch three is open). We can perform
the open-circuit analysis to find the initial capacitor voltage.
Performing the open-circuit analysis with units of V, mA, and kΩ , there are two
essential nodes and a single node equation:
V1
N1 − 10 = 0. (6.202)
2
Solving,
V1 = 20 V. (6.203)
FIGURE 6.33 An RC circuit with three sequential switching events.

FIGURE 6.34 Open-circuit analysis of the previous RC circuit for t ≤ 0 − (switch one open,
switch two closed, switch three open) with respect to the terminals where the capacitor had
been connected.
By KVL,
VTh0 = VOC0 = V1 + 30 V = 50 V. (6.204)
Next, we will consider the time interval 0 + ≤ t ≤ 20 ms − , which we will refer to as

“time interval one.” For this time interval, switches one and two are closed but switch
three is open as shown in Figure 6.35.
Using units of V, mA, and kΩ ,
V1 + 30 − V2 V1 V1 + 12 − V2
N1 + + =0 (6.205)
6 2 4
and
V2 − 12 − V1 V − 30 − V1
N2 − 10 + 2 = 0. (6.206)
4 6
N 1 2V1 + 60 − 2V2 + 6V1 + 3V1 + 36 − 3V2 = 0 (6.207)
and
N 2 3V2 − 36 − 3V1 − 120 + 2V2 − 60 − 2V1 = 0. (6.208)
N 1 11V1 − 5V2 = −96 (6.209)

FIGURE 6.35 Open-circuit analysis of the previous RC circuit for 0 + ≤ t ≤ 20 ms − (switch

one closed, switch two closed, switch three open) with respect to the terminals where the
capacitor had been connected.
and
N 2 − 5V1 + 5V2 = 216. (6.210)
In matrix form,
 11 −5   V1   −96 
 −5  = . (6.211)
 5   V2   216 
Solving,
−96 −5
216 5
V1 = = 20.0 V, (6.212)
11 −5
−5 5
11 −96
−5 216
V2 = = 63.2 V. (6.213)
11 −5
−5 5
Therefore,
VTh1 = VOC1 = V2 = 63.2 V. (6.214)

RTh1 = 6 kΩ  4 kΩ + 2 kΩ = 4.4 kΩ. (6.215)
For this time interval (which we will refer to as time interval one), the initial voltage
is V01 = VTh0 = 50.0 V, the final voltage is VF 1 = VTh1 = 63.2 V, and the time constant is
τ 1 = RTh1C = ( 4.4 kΩ )(12 µF ) = 52.8 ms . The solution for the capacitor voltage during
this time interval is therefore
v ( t ) = VF 1 + (V01 − VF 1 ) exp ( −t / τ 1 )
(6.216)
= 63.2 − 13.2 exp ( −t / 52.8 ms )  V; 0 + ≤ t ≤ 20 ms− .
We can also solve for the capacitor current by differentiating
dv d
i (t ) = C = (12 µF ) 63.2 − 13.2 exp ( −t / 52.8 ms )  V
dt dt
=
(12 µF )( −13.2 V ) exp ( −t / 52.8 ms) (6.217)
−52.8 ms
= 3.00 exp ( −t / 52.8 ms ) mA; 0 + ≤ t ≤ 20 ms − .
For consideration of the second time interval, after the second switching event but
before the third switching event, 20 ms+ ≤ t ≤ 40 ms− , we will use the solution for the
first switching event, evaluated at t = 20 ms to find the initial condition:
v ( t ) = 63.2 − 13.2 exp ( −20 ms / 52.8 ms )  V = 54.2 V. (6.218)
To find the final value of the voltage for time interval two, we need to find the open-
circuit voltage with respect to the terminals where the capacitor had been connected
as shown in Figure 6.36.
Performing the open-circuit analysis with units of V, mA, and kΩ, there are two
essential nodes and a single node equation, because the opening of switch two elimi-
nates one essential node:
V1
N1 − 10 = 0. (6.219)
2
Solving,
V1 = 20 V, (6.220)
and by KVL,
VTh2 = VOC2 = V1 + 24 V + (10 mA )( 4 kΩ ) = 84 V. (6.221)

FIGURE 6.36 Open-circuit analysis of the previous RC circuit for 20 ms + ≤ t ≤ 40 ms −

(switch one closed, switch two open, switch three open) with respect to the terminals where
the capacitor had been connected.
RTh2 = 4 kΩ + 2 kΩ = 6 kΩ. (6.222)
For time interval two, the initial voltage is V02 = 54.2 V as found above, the final volt-
age is VF 2 = VTh2 = 84 V, and the time constant is τ 2 = RTh2C = ( 6 kΩ )(12 µF ) = 72 ms.
The solution for the capacitor voltage during this time interval is therefore
v ( t ) = VF 1 + (V01 − VF 1 ) exp ( −(t − t1 ) / τ 1 )

(6.223)
= 84 − 29.8 exp ( −(t − 20 ms) / 72 ms )  V; 20 ms+ ≤ t ≤ 40 ms − .

dv d
i (t ) = C = (12 µF ) 63.2 − 29.8 exp ( −(t − 20 ms) / 72 ms )  V
dt dt
=
(12 µF )( −29.8 V ) exp ( −(t − 20 ms) / 72 ms ) (6.224)
−72 ms
= 5.00 exp ( −(t − 20 ms) / 72 ms ) mA; 20 ms + ≤ t ≤ 40 ms − .
For consideration of the third time interval, after the third switching event, t ≥ 40 ms+,
we will use the solution for the second switching event, evaluated at t = 40 ms to find
the initial condition:
V03 = v ( 40 ms+ ) = v ( 40 ms− )

(6.225)
= 84 − 29.8 exp ( −(40 ms − 20 ms) / 72 ms )  V = 61.4 V.
To find the final value of the voltage for time interval three, we need to find the open-
circuit voltage with respect to the terminals where the capacitor had been connected
as shown in Figure 6.37.
With this switch configuration, there are two essential nodes and one node equa-
tion. Using units of V, mA, and kΩ,
V1 − 12 V + 20
N1 − 10 + 1 = 0. (6.226)
6 2
N 1 V1 − 12 − 60 + 3V1 + 60 = 0. (6.227)
N 1 4V1 = 12. (6.228)
Solving,
V1 = 3.0 V. (6.229)
Therefore,
VTh3 = VOC3 = V1 = 3.0 V. (6.230)
RTh3 = ( 4 kΩ + 2 kΩ )  2 kΩ = 1.5 kΩ. (6.231)
FIGURE 6.37 Open-circuit analysis of the previous RC circuit for t ≥ 40 ms − (switch one
closed, switch two open, switch three closed) with respect to the terminals where the capaci-
tor had been connected.
For time interval three, the initial voltage is V03 = 61.4 V as found above, the final voltage
is VF3 = VTh3 = 3.0 V, and the time constant is τ 3 = RTh3C = (1.5 kΩ )(12 µF ) = 18.0 ms.
The solution for the capacitor voltage during this time interval is therefore
v ( t ) = VF 1 + (V01 − VF 1 ) exp ( −(t − t3 ) / τ 1 )

(6.232)
= 3.0 + 58.4 exp ( −(t − 40 ms) / 18.0 ms )  V; t ≥ 40 ms+ .
i (t ) = C
dv
dt
d
(
= (12 µF ) 3.0 + 58.4 exp − ( t − 40 ms ) / 18.0 ms  V
dt   )
=
(12 µF)(58.4 V ) exp ( −(t − 40 ms) / 18.0 ms) (6.233)
−18.0 ms
= 38.9 exp ( −(t − 40 ms) / 18.0 ms ) mA; t ≥ 40 ms+ .
The overall solution for the current may be expressed in a piecewise fashion:
 63.2 − 13.2 exp ( −t / 52.8 ms )  V;

   0 + ≤ t ≤ 20 ms − ;

v ( t ) =  84 − 29.8 exp ( −(t − 20 ms) / 72 ms )  V; 20 ms+ ≤ t ≤ 40 ms − ;

 3.0 + 58.4 exp ( −(t − 40 ms) / 18.0 ms )  V; t ≥ 40 ms+ .

(6.234)
Similarly, the overall current solution is
 3.00 exp ( −t / 52.8 ms ) mA; 0 + ≤ t ≤ 20 ms− ;



i ( t ) =  5.00 exp ( −(t − 20 ms) / 72 ms ) mA; 20 ms+ ≤ t ≤ 40 ms− ;

 41.5 exp ( −(t − 40 ms) / 18.0 ms ) mA; t ≥ 40 ms+ .

(6.235)
To review, see Presentation 6.6 in ebook+

6.15 SUMMARY
The capacitor is a two-terminal device comprising two metal plates separated by
an insulating material. As a consequence of Gauss’ law, an external current, called
the displacement current, flows to charge and discharge the plates and is given by
i = Cdv / dt , where i is the capacitor current, v is the capacitor voltage, and C is the
capacitance in Farads. Hence, the capacitor voltage may not change instantaneously.
t
1
The capacitor voltage may be found by integrating the current: v = V0 +
C
0
idy, where
∫
V0 is the initial voltage across the capacitor. The energy w stored in a capacitor is pro-
1
portional to the square of the voltage: w = Cv 2. When two or more capacitors are
2
connected in parallel, the equivalent capacitance is the sum of the individual capaci-
tances. When two or more capacitors are connected in series, the equivalent capaci-
tance is the reciprocal of the sum of the reciprocals of the individual capacitances.
The inductor is a two-terminal device comprising a coil of wire wrapped around
a magnetic medium (which may be air). According to the Faraday law, the voltage
across an inductor is given by v = Ldi / dt , where v is the voltage, i is the current, and
L is the inductance in Henries. Hence, the inductor current may not change instanta-
t
1
neously. The inductor current may be found by integrating the voltage: i = I 0 +
L
vdy,
∫0
where I 0 is the initial voltage across the capacitor. The energy w stored in an inductor
1
is proportional to the square of the current: w = Li 2 . When inductors are connected
2
in series, the equivalent inductance is the sum of the individual inductances. When
inductors are connected in parallel, the equivalent inductance is the reciprocal of the
sum of the reciprocals of the individual inductances.
An RC circuit is a first-order circuit containing a capacitor, a switch, and sources and
resistances. Determination of the capacitor voltage or current as a function of time after
movement of the switch requires solution of a first-order differential equation. The solu-
tion for the capacitor voltage is of the form v ( t ) = VF + (V0 − VF ) exp ( −t / τ ). The initial
voltage V0 is determined by the Thevenin voltage for the circuitry connected prior to the
movement of the switch: V0 = VTh0 . The final voltage VF is determined by the Thevenin
voltage for the circuitry connected after the movement of the switch: VF = VTh1. The time
constant is given by τ = RTh1C , where RTh1 is the Thevenin resistance of the circuitry
connected after movement of the switch and C is the capacitance. Once the capacitor
voltage is known, the current can be readily found by differentiation: i ( t ) = Cdv ( t ) / dt .
An RL circuit is a first-order circuit containing an inductor, a switch, sources, and
resistances. Determination of the inductor current or voltage as a function of time after
movement of the switch requires solution of a first-order differential equation. The
solution for the inductor current is of the form i ( t ) = I F + ( I 0 − I F ) exp ( −t / τ ). The ini-
tial current I 0 is determined by the Norton current for the circuitry connected prior to
the movement of the switch: I 0 = I N 0. The final current I F is determined by the Norton
current for the circuitry connected after the movement of the switch: I F = I N1. The time
constant is given by τ = L / RN 1, where RN1 is the Norton resistance of the circuitry
connected after movement of the switch and L is the inductance. Once the inductor
current is known, the voltage can be readily found by differentiation: v ( t ) = Ldi ( t ) / dt .
The concepts developed above may be applied to sequential switching prob-
lems, in which an RC or RL circuit contains two or more switches which move at dif-
ferent times. The solution for the first switching event may be found in the same way
as described above. For any subsequent switching event, the solution is of the general
form v ( t ) = VF + (V0 − VF ) exp ( −(t − tn ) / τ ) or i ( t ) = I F + ( I 0 − I F ) exp ( −(t − tn ) / τ ),
in which the initial condition is found by evaluating the solution for the previous
switching event at the time of the present switching event (t = tn), the final condition
is evaluated by determination of the Thevenin voltage or the Norton current which
exists after the present switching event, and the time constant is found as τ = RThnC
or τ = L / RNn , using the Thevenin or Norton resistance which exists after the current
switching event.
PROBLEMS
Problem 6.1. For the circuit shown in Figure P6.1, find vC ( 0 − ), vC ( 0 + ),
vC ( ∞ ), iC ( 0 − ), iC ( 0 + ), iC ( ∞ ), vC ( t ) for t ≥ 0 + and iC ( t ) for t ≥ 0 +. Determine
the initial and final energy stored in the capacitor. The switch has been in its
starting position for a long time before moving at the time indicated.
FIGURE P6.1 Switched RC circuit.
Problem 6.2. For the circuit shown in Figure P6.2, find vC ( 0 − ), vC ( 0 + ), vC ( ∞ ),

iC ( 0 − ), iC ( 0 + ), iC ( ∞ ), vC ( t ) for t ≥ 0 + and iC ( t ) for t ≥ 0 +. Determine the
initial and final energy stored in the capacitor. The switch has been in its
FIGURE P6.2 Switched RC circuit containing two sources and two resistors.
Problem 6.3. For the circuit shown in Figure P6.3, find v L ( 0 − ), v L ( 0 + ),

v L ( ∞ ), iL ( 0 − ), iL ( 0 + ), iL ( ∞ ), v L ( t ) for t ≥ 0 + and iL ( t ) for t ≥ 0 +. Determine
the initial and final energy stored in the inductor. The switch has been in its
FIGURE P6.3 Switched RL circuit.

v L ( ∞ ), iL ( 0 − ), iL ( 0 + ), iL ( ∞ ), v L ( t ) for t ≥ 0 + and iL ( t ) for t ≥ 0 +. Determine
the initial and final energy stored in the inductor. The switch has been in its
FIGURE P6.4 Switched RL circuit containing two sources and three resistors.
Problem 6.5. For the circuit shown in Figure P6.5, find vC ( t ), iC ( t ), ix ( t ),

and v y ( t ) for t ≥ 0 +. The switch has been in its starting position for a long
time before moving at the time indicated.
FIGURE P6.5 Switched RC circuit containing three sources and three resistors.
Problem 6.6. For the circuit shown in Figure P6.6, find vC ( t ), iC ( t ), and ix ( t )
for t ≥ 0 +. The switch has been in its starting position for a long time before
moving at the time indicated.
FIGURE P6.6 Switched RC circuit containing three sources, five resistors, and a single-
pole, double-throw switch.
Problem 6.7. For the circuit shown in Figure P6.7, determine vC ( t ) and iC ( t )
for t ≥ 0 +. The switch has been in its starting position for a long time before
moving at the time indicated.
FIGURE P6.7 Switched RC circuit containing mixed sources and six resistors.
Problem 6.8. For the circuit shown in Figure P6.8, find vC ( t ), iC ( t ), and ix ( t ) for
t ≥ 0 +. The switch has been in its starting position for a long time before moving
at the time indicated.
FIGURE P6.8 Switched RC circuit containing an independent source, a CCCS, and three
resistors.
Problem 6.9. For the circuit shown in Figure P6.9, find v L ( t ), iL ( t ), and iR ( t ) for
t ≥ 0 +. The switch has been in its starting position for a long time before moving
at the time indicated.
FIGURE P6.9 Switched RL circuit containing three sources and two resistors.
Problem 6.10. For the circuit shown in Figure P6.10, find v L ( t ), iL ( t ), and
ix ( t ) for t ≥ 0 +. The switch has been in its starting position for a long time
before moving at the time indicated.
FIGURE P6.10 Switched RL circuit containing four sources, two resistors, and a make-
before-break switch.
Problem 6.11. For the circuit of Figure P6.11, determine v L ( t ), iL ( t ), and

ix ( t ) for t ≥ 0 +. The switch has been in its starting position for a long time
before moving at the time indicated.
FIGURE P6.11 Switched RL circuit containing mixed sources and three resistors.
Problem 6.12. The circuit shown in Figure P6.12 has zero initial stored
energy. Determine v1 ( t ), v2 ( t ), i1 ( t ), i2 ( t ), and i3 ( t ) for t ≥ 0 +. The switch
has been in its starting position for a long time before moving at the time
indicated.
FIGURE P6.12 Switched RC circuit involving three capacitors.

Problem 6.13. For the circuit of Figure P6.13, determine v1 ( t ), v2 ( t ), and

iR ( t ) for t ≥ 0 +. The switches have been in their starting positions for a long
time before moving at the time indicated.
FIGURE P6.13 Switched RC circuit involving three switches which move simultaneously.
Problem 6.14. The circuit shown in Figure P6.14 has zero initial stored energy.
Determine v1 ( t ), v2 ( t ), i1 ( t ), i2 ( t ), and i3 ( t ) for t ≥ 0 +. The switch has been in
its starting position for a long time before moving at the time indicated.
FIGURE P6.14 Switched RL circuit involving three inductors.
Problem 6.15. Find v ( t ), i1 ( t ), and i2 ( t ) for t ≥ 0 + in the circuit of Figure

P6.15. Is there energy trapped in the circuit after it settles? If so, how much?
The switch has been in its starting position for a long time before moving at
the time indicated.
FIGURE P6.15 Switched RL circuit involving two inductors.

Problem 6.16. For the circuit shown in Figure P6.16, find vC ( t ) and iC ( t )
for t ≥ 0 +. The switches have been in their starting positions for a long time
before moving at the times indicated.
FIGURE P6.16 Sequentially-switched RC circuit.
FIGURE P6.17 Sequentially-switched RC circuit involving two sources, three resistors, and
two switches.
Problem 6.18. For the circuit shown in Figure P6.18, find v L ( t ) and iL ( t )
FIGURE P6.18 Sequentially-switched RL circuit.
FIGURE P6.19 Sequentially-switched RC circuit involving three switching events.

Problem 6.20. For the circuit shown in Figure P6.20, find v L ( t ) and iL ( t )
for t ≥ 0 +. The switches have been in their starting position for a long time
FIGURE P6.20 Sequentially-switched RL circuit involving mixed sources, three resistors,

and three switches.
7 Second-Order Circuits
7.1 INTRODUCTION
A second-order circuit is one which contains two energy-storage elements so that
its behavior is governed by a second-order differential equation. Energy-storage ele-
ments include capacitors and inductors, and here our focus will be on the transient
response of resistor-inductor-capacitor (RLC) second-order circuits containing one
capacitor and one inductor. We will first consider the series RLC circuit, in which
the capacitor and the inductor are in series; then we will consider the parallel RLC
circuit, in which the capacitor and the inductor are in parallel, and finally we will
briefly visit the general case in which the inductor and the capacitor are neither in
parallel nor in series.
7.2 NATURAL RESPONSE OF A SERIES RLC CIRCUIT

Consider the series RLC circuit in Figure 7.1. We will assume that the initial cur-
rent in the inductor is I 0 and the initial voltage across the capacitor is V0 . (There
are numerous switching configurations capable of establishing these initial condi-
tions, and we will consider some of these, but we omit them here for simplicity.)
We want to determine i ( t ) and v ( t ) for t ≥ 0 + . If we allow the circuit to settle, both
the inductor current and the capacitor voltage will settle to zero: i ( ∞ ) = 0 and
v ( ∞ ) = 0.
To determine the transient response of this circuit while it is settling, we need to
set up and solve a second-order homogeneous linear differential equation. To do this,
we start by using Kirchhoff’s voltage law (KVL):
t
di 1
Ri + L
dt
+ V0 +
C ∫
idy = 0.
0
(7.1)
FIGURE 7.1 A series RLC circuit for consideration of the natural response.
260 DOI: 10.1201/9781003408529-7

Second-Order Circuits 261
Differentiating with respect to time,
di d 2i i
R + L 2 + = 0. (7.2)
dt dt C
Rearranging and normalizing with respect to the second-order term,
d 2i R di 1
+ + i = 0. (7.3)
dt 2 L dt LC
We will assume solutions of the form i ( t ) = Ae st . (This should seem plausible, given
that a linear combination of the function and its first two derivatives is equal to zero,
but we defer to a course on differential equations for a more rigorous justification.)
Using our assumed form for the solution,
R 1
s 2 Ae st + sAe st + Ae st = 0. (7.4)
L LC
Dividing by Ae st we obtain a quadratic in s, which we call the characteristic equa-

tion for the series RLC circuit:
R 1
s2 + s+ = 0. (7.5)
L LC
Applying the quadratic formula, we can find the two roots of the characteristic
equation:
2
R R 1
s1 , s2 = − ±  − . (7.6)
2L  2L  LC
This may be rewritten as
s1 , s2 = −α ± α 2 − ω 02 , (7.7)
where α = R / ( 2 L ) is the neper frequency and ω 0 = 1 / LC is the resonant fre-

quency for the series RLC circuit.
There are three important cases with regard to the nature of the roots and the
response of the circuit. If α > ω 0 , the roots are real and distinct, and the solution is
given by a linear combination of two exponentials. This is the overdamped case:
i ( t ) = A1e s1t + A2e s2t , t ≥ 0 + , (7.8)
where A1 and A2 are coefficients determined by applying the initial conditions. If α = ω 0 ,

the roots are real and equal, s1 = s2 = α , and one of the exponentials must be multiplied
by t to render two independent solutions. This is the critically-damped case:
i ( t ) = D1te −α t + D2e −α t , t ≥ 0 +. (7.9)

where D1 and D2 are coefficients determined by applying initial conditions.
Finally, if ω 0 > α then the roots are complex conjugates:

s1 , s2 = −α ± j ω 02 − α 2 = −α ± jω d . This is the underdamped case. We could treat
the solution as a linear combination of two exponentials having complex exponents
and complex coefficients, but it will be more useful to rewrite the form of the solution
with real exponents and real coefficients. We start by rewriting the expression for i ( t )
by using the properties of exponents.
i ( t ) = A1e s1t + A2e s2t
= A1e( −α + jω d )t + A2e( −α − jω d )t
= A1e −α t e jω d t + A2e −α t e − jω d t , t ≥ 0 +. (7.10)
Now, we can make use of Euler’s identity: e jθ = cos θ + j sin θ , yielding
i ( t ) = A1e −α t  cos (ω d t ) + j sin (ω d t ) + A2e −α t  cos (ω d t ) + j sin (ω d t )
= ( A1 + A2 ) e −α t cos (ω d t ) + j ( A1 − A2 ) e −α t sin (ω d t )
= B1e −α t cos (ω d t ) + B2e −α t sin (ω d t ) , t ≥ 0 +. (7.11)
In the final step, we have assumed that A1 and A2 are complex conjugates so that
( A1 + A2 ) and j ( A1 − A2 ) are both real quantities; this is necessarily true because
the currents and voltages in real circuits are real, not complex. Therefore we have
simplified the final expression by using the real coefficients B1 = ( A1 + A2 ) and
B2 = j ( A1 − A2 ). Thus, the underdamped solution is a linear combination of two
damped sinusoids:
i ( t ) = B1e −α t cos (ω d t ) + B2e −α t sin (ω d t ) , t ≥ 0 + , (7.12)
where ω d = ω 02 − α 2 is the damped radian frequency.

The three cases of the solution for i ( t ) are summarized in Table 7.1; the solutions
for v L ( t ) and vC ( t ) have the same general forms but with different coefficients. These
general results will be further explained with examples in the following sections.
TABLE 7.1
Three Cases of Natural Response for a Series RLC Circuit
Series RLC Circuit: α = R / ( 2 L ) , ω 0 = 1 / LC .

α > ω0 i ( t ) = A1e s1t + A2e s2t , t ≥ 0 + s1 , s2 = −α ± α 2 − ω 02
Overdamped
α = ω0 i ( t ) = D1te −α t + D2e −α t , t ≥ 0 + s1 , s2 = −α
Critically-damped
α < ω0 i ( t ) = B1e −α t cos (ω d t ) + B2e −α t sin (ω d t ) , t ≥ 0 + s1 , s2 = −α ± jω d
Underdamped ω d = ω 02 − α 2
7.3 OVERDAMPED NATURAL RESPONSE OF A SERIES RLC CIRCUIT

Consider the natural response of the series RLC circuit in Figure 7.2. Suppose that
the initial conditions given in the figure have been established by switched circuitry
which is omitted from the diagram for simplicity. Whereas the inductor current can-
not change instantaneously, i ( 0 + ) = i ( 0 − ) = i ( 0 ). Similarly, the capacitor voltage may
not change instantaneously so vC ( 0 + ) = vC ( 0 − ) = vC ( 0 ).
For this series circuit, the neper frequency is
R 500 Ω
α= = = 5, 000 rad/s, (7.13)
2 L 2 ( 50 mH )
and the resonant frequency is
1
ω0 = = 4, 000 rad/s. (7.14)
(1.25 µF )(50 mH )
Because α > ω 0 , the roots of the characteristic equation are real and distinct:
s1 , s2 = −α ± α 2 − ω 02
(7.15)
( )
= −5, 000 ± 5, 000 2 − 4, 000 2 rad/s = −2, 000, −8, 000 rad/s.
This is an overdamped circuit and the solution is given by a linear combination of

two exponentials:
i ( t ) = A1e s1t + A2e s2t = A1e −2,000 t + A2e −8,000 t ; t ≥ 0 +. (7.16)
The units of s1 and s2 have not been shown explicitly, but it should be remembered
that each has units of rad/s and therefore the argument of the exponent is unitless if
time is expressed in s.
FIGURE 7.2 An overdamped series RLC circuit for consideration of the natural response.
To find the coefficients, we need to apply the initial conditions. The numerical
value of the initial inductor current is i ( 0 + ) = I 0 = 20 mA . From the general form of
the solution, evaluated at t = 0 + , i ( 0 + ) = A1 + A2 . Equating these two,
A1 + A2 = 20 mA. (7.17)
The initial value of the derivative of the current may be found by consideration of
the inductor voltage, and this can be found by using KVL and the knowledge of the
initial capacitor voltage:
di v L ( 0 + ) − vC ( 0 + ) − Ri ( 0 + ) −6 V − ( 500 Ω )( 20 mA )
= = = = −320 A/s.
dt t = 0+ L L 50 mH
(7.18)
From the general form of the solution,
di
= s1 A1 + s2 A1 = −2, 000 A1 − 8, 000 A2 . (7.19)
dt t = 0+
Equating these two,

−2, 000 A1 − 8, 000 A2 = −320 A/s. (7.20)
Now, we can solve for the coefficients using equations (7.17) and (7.20):
 1 1   A1   0.02 A 
 −2, 000 rad/s −8, 000 rad/s   A2 = . (7.21)
    −320 A/s 
Solving,
1 1
−2, 000 −8, 000
A1 = = −0.0267 A (7.22)
1 1
−2, 000 −8, 000
and
1 1
−2, 000 −8, 000
A2 = = 0.0467 A. (7.23)
1 1
−2, 000 −8, 000
Therefore,
i ( t ) =  −0.0267e −2,000 t + 0.0467e −8,000 t  A; t ≥ 0 +. (7.24)

Once we have solved for the current, which is common to the resistor, inductor, and
capacitor, we may find the voltage for each element. For example, the inductor volt-
age may be found by
di d
vL (t ) = L = ( 50 mH )  −0.0267e −2,000 t + 0.0467e −8,000 t  A
dt dt (7.25)
−2,000 t −8,000 t +
=  2.67e − 18.68e  V; t ≥ 0 .
The capacitor voltage could be found by integrating the current but it can also be
found using KVL, which may be more convenient:
di
vC ( t ) = −iR − L
dt
= − ( 500 Ω )  −0.0267e −2,000 t + 0.0467e −8,000 t  A

(7.26)
d
− ( 50 mH )  −0.0267e −2,000 t + 0.0467e −8,000 t  A
dt
= 10.68e −2,000 t − 4.67e −8,000 t  V; t ≥ 0 +.
The transient response (current and capacitor voltage) is plotted in Figure 7.3.
As another example, consider the natural response of the series RLC circuit in
Figure 7.4. The make-before-break switch has been in position a for a long time
and moves to position b at t = 0. Prior to the movement of the switch, all time deriv-
atives would have settled to zero, and therefore the capacitor current would have
settled to zero. Because the inductor is in series with the capacitor, its current will
also have settled to zero. This means that in a circuit with this configuration, the
FIGURE 7.3 Transient response (current and capacitor voltage) in the overdamped series
RLC circuit of Figure 7.2.
FIGURE 7.4 A switched series RLC circuit for consideration of the natural response.
initial condition for the inductor will always be zero. On the other hand, the voltage
across the capacitor will have settled to the value of the Thevenin voltage for the
circuitry connected prior to the switch movement, because with the current settled
to zero there will be zero voltage across the resistor and zero voltage across the
inductor. This same capacitor voltage will exist immediately after the movement
of the switch because the capacitor voltage may not change instantaneously. Thus,
vC ( 0 + ) = vC ( 0 − ) = VTh0 = 10 V.
This is a series RLC circuit because the inductor and the capacitor are in series.
The neper frequency is
R 500 Ω
α= = = 10, 000 rad/s, (7.27)
2 L 2 ( 25 mH )

1
ω0 = = 8, 000 rad/s. (7.28)
( 0.625 µF )( 25 mH )
s1 , s2 = −α ± α 2 − ω 02
(7.29)
( )
= −10, 000 ± 10, 000 2 − 8, 000 2 rad/s = −4, 000, −16, 000 rad/s.
This is an overdamped circuit and the solution is given by a linear combination of

two exponentials:
i ( t ) = A1e s1t + A2e s2t = A1e −4,000 t + A2e −16,000 t ; t ≥ 0 +. (7.30)

To find the coefficients, we need to apply the initial conditions. The numerical value
of the initial inductor current is zero: i ( 0 + ) = 0. From the general form of the solu-
tion, evaluated at t = 0 + , i ( 0 + ) = A1 + A2 . Equating these two,
A1 + A2 = 0. (7.31)
di v L ( 0 + ) − vC ( 0 + ) − Ri ( 0 + ) −10 V − ( 500 Ω ) ( 0 )
= = = = −400 A/s. (7.32)
dt t = 0+ L L 25 mH
di
= s1 A1 + s2 A1 = −4, 000 A1 − 16,000 A2 . (7.33)
dt t = 0+
Equating these two,
−4, 000 A1 − 16,000 A2 = −400 A/s. (7.34)
Now, we can solve for the coefficients using the two equations involving A1 and A2:
 1 1   A1   0 
 −4, 000 rad/s −16, 000 rad/s   A2  =  −400 A/s . (7.35)
    
Solving,
0 1
−400 A/s −16, 000 rad/s
A1 = = −0.0333 A (7.36)
1 1
−4, 000 rad/s −16, 000 rad/s
and
1 0
−4, 000 rad/s −400 A/s
A2 = = 0.0333 A. (7.37)
1 1
−4, 000 rad/s −16, 000 rad/s
Therefore,
i ( t ) =  −0.0333e −4,000 t + 0.0333e −16,000 t  A; t ≥ 0 +. (7.38)

The inductor voltage also exhibits an overdamped form:
di d
vL (t ) = L = ( 25 mH )  −0.0333e −4,000 t + 0.0333e −16,000 t  A
dt dt
= 3.33e −4,000 t − 13.33e −16,000 t  V; t ≥ 0 +. (7.39)
By KVL, the capacitor voltage is
di
vC ( t ) = −iR − L
dt
= − ( 500 Ω )  −0.0333e −4,000 t + 0.0333e −16,000 t  A
d
− ( 25 mH )  −0.0333e −4,000 t + 0.0333e −16,000 t  A
dt 
= 13.33e −4,000 t − 3.33e −16,000 t  V; t ≥ 0 +. (7.40)
The current and capacitor voltage are plotted in Figure 7.5.
7.4 CRITICALLY-DAMPED NATURAL RESPONSE

OF A SERIES RLC CIRCUIT
Now, consider the circuit of Figure 7.6, it is similar to the previous example except
that the resistor value RTh1 has been changed. Once again i ( 0 + ) = i ( 0 − ) = 0 but
vC ( 0 + ) = vC ( 0 − ) = VTh0 = 10 V.
FIGURE 7.5 Transient response (current and capacitor voltage) in the overdamped series
FIGURE 7.6 A critically-damped series RLC circuit for consideration of the natural
response.
This is a series RLC circuit; the neper frequency is
R 400 Ω
α= = = 8, 000 rad/s, (7.41)
2 L 2 ( 25 mH )
1
ω0 = = 8, 000 rad/s. (7.42)
( 0.625 µF )( 25 mH )
Because α = ω 0 , the roots of the characteristic equation are real and equal:
s1 , s2 = −α ± α 2 − ω 02
(
= −8, 000 ± 8, 000 2 − 8, 000 2 rad/s )
= −8, 000, −8, 000 rad/s. (7.43)
This is therefore a critically-damped circuit and the solution is given by
i ( t ) = D1te −α t + D2e −α t = D1te −8,000 t + D2e −8,000 t ; t ≥ 0 +. (7.44)

To find the coefficients, we must apply the initial conditions. The numerical value
of the initial inductor current is zero: i ( 0 + ) = 0. From the general form of the
solution, evaluated at t = 0 + , i ( 0 + ) = D2. Equating these two,
D2 = 0. (7.45)
di v L ( 0 + ) − vC ( 0 + ) − Ri ( 0 + ) −10 V − ( 400 Ω ) ( 0 )
= = = = −400 A/s. (7.46)
dt t = 0+ L L 25 mH
di
= D1 − α D2 = D1. (7.47)
dt t = 0+
Equating these two,
D1 = −400 A/s. (7.48)
Therefore,
i ( t ) = ( −400 A/s ) te −8,000 t ; t ≥ 0 +. (7.49)
The inductor voltage also exhibits a critically-damped form:
di d
vL (t ) = L = ( 25 mH ) ( −400 A/s ) te −8,000 t 
dt dt
= (80, 000 V/s ) te −8,000 t − 10 Ve −8,000 t  ; t ≥ 0 +. (7.50)
di
vC ( t ) = −iR − L
dt
= − ( 400 Ω )( −400 A/s ) te −8,000 t
d
− ( 25mH ) ( −400 A/s ) te −8,000 t 
dt  
= (80,000 V/s ) te −8,000 t + 10 Ve −8,000 t  ; t ≥ 0 +. (7.51)

It is interesting to note that, although the second coefficient is zero in the current
expression, the inductor voltage and capacitor voltage expressions both have two non-
zero coefficients.
The transient response (current and capacitor voltage) is plotted in Figure 7.7.
Visually, it is difficult to distinguish the critically-damped and overdamped responses.
7.5 UNDERDAMPED NATURAL RESPONSE

OF A SERIES RLC CIRCUIT
Now consider the circuit in Figure 7.8; it is similar to the circuit of the previous exam-
ple except that the resistor value RTh1 has been changed. Once again i ( 0 + ) = i ( 0 − ) = 0
but vC ( 0 + ) = vC ( 0 − ) = VTh0 = 10 V.
For this series RLC circuit, the neper frequency is
R 50 Ω
α= = = 1, 000 rad/s (7.52)
2 L 2 ( 25 mH )
1
ω0 = = 8, 000 rad/s. (7.53)
( 0.625 µF )( 25 mH )
Because α < ω 0 , the roots of the characteristic equation are complex conjugates and
the solution has an underdamped form with
ω d = 8, 000 2 − 1, 000 2 rad/s = 7,937 rad/s. (7.54)
FIGURE 7.7 Transient response (current and capacitor voltage) in the critically-damped
series RLC circuit of Figure 7.6.
FIGURE 7.8 An underdamped series RLC circuit for consideration of the natural response.
The solution is of the form:
i ( t ) = B1e −α t cos (ω d t ) + B2e −α t sin (ω d t )

(7.55)
= B1e −1,000 t cos ( 7,937t ) + B2e −1,000 t sin ( 7,937t ); t ≥ 0 +.
To find the coefficients, we will apply the initial conditions. The numerical value of
the initial inductor current is zero: i ( 0 + ) = 0. From the general form of the solution,
evaluated at t = 0 + , i ( 0 + ) = B1. Equating these two,
B1 = 0. (7.56)
di v L ( 0 + ) − vC ( 0 + ) − Ri ( 0 + ) −10 V − ( 50 Ω ) ( 0 )
= = = = −400 A/s. (7.57)
dt t = 0+ L L 25 mH
di
= −α B1 + ω d B2 . (7.58)
dt t = 0+
Equating these two,
−α B1 + ω d B2 = −400 A/s, (7.59)

so
−400 A/s + α B1 −400 A/s + (1, 000 rad/s ) ( 0 )

B2 = = = −0.0504 A. (7.60)
ωd 7,937 rad/s
Therefore,
i ( t ) = −0.0504 A e −1,000 t sin ( 7,937t ); t ≥ 0 +. (7.61)
The inductor voltage also exhibits an underdamped form:
di d
vL (t ) = L = ( 25 mH )  −0.0504 A e −1,000 t sin ( 7,937t )
dt dt
(7.62)
=  −10.0e −1,000 t cos ( 7,937t ) + 1.26e −1,000 t sin ( 7,937t ) V; t ≥ 0 +.
di
vC ( t ) = −iR − L
dt
= − ( 50 Ω ) (−0.0504 A)e −1,000 t sin ( 7,937t )
(7.63)
d
− ( 25 mH ) ( −0.0504 ) A e −1,000 t sin ( 7,937t )
dt
=  −10.0e −1,000 t cos ( 7,937t ) + 1.26e −1,000 t sin ( 7,937t ) V; t ≥ 0 +.
It is interesting to note that, although the first coefficient is zero in the current expres-
sion, the inductor voltage and capacitor voltage expressions both have two non-zero
coefficients.
The current and capacitor voltage are plotted in Figure 7.9, and it can be seen that
each exhibits the form of a decaying sinusoid. This is further illustrated in Figure 7.10,
which shows the current transient along with its envelope ±0.0504 A exp ( −α t ) .
7.6 STEP AND NATURAL RESPONSE OF A SERIES RLC CIRCUIT

Consider the series RLC circuit in Figure 7.11. We will assume that the switch has
been in position a for a “long time” before moving to position b. If the circuit has
been allowed to settle before the movement of the switch, all time derivatives will
have settled to zero. Therefore, the current will have settled to zero, and because
of the inductor this current may not change instantaneously when the switch is
moved. Hence, i ( 0 + ) = i ( 0 − ) = 0. It follows that the capacitor voltage will have
settled to the Thevenin voltage for the circuit connected prior to the movement of
the switch, and the capacitor voltage may not change instantaneously. Therefore,
vC ( 0 + ) = vC ( 0 − ) = VTh0 .
FIGURE 7.9 Transient response (current and capacitor voltage) in the underdamped series
FIGURE 7.10 Current in the underdamped series RLC circuit of Figure 7.8 along with its
exponential envelope ±0.0504 A exp ( −α t ).
To determine the transient response of this circuit after the movement of the
switch, we need to set up and solve a second-order homogeneous linear differential
equation. To do this, we start by using KVL:
t
di 1
Ri + L
dt
+ V0 +
C∫idy − VTh1 = 0.
0
(7.64)
FIGURE 7.11 A series RLC circuit for consideration of the step and natural response.
di d 2i i
R + L 2 + = 0. (7.65)
dt dt C
d 2i R di 1
+ + i = 0. (7.66)
dt 2 L dt LC
This is identical to the differential equation we obtained when considering the natu-
ral response. Hence, the solution for i ( t ) will have one of the same forms (over-
damped, critically-damped, or underdamped) as found when considering the natural
response. On the other hand, the solution for the capacitor voltage will have one of
the same forms plus a constant to account for a non-zero final value. These forms of
the solution are summarized in Table 7.2.
As an example, consider the circuit in Figure 7.12.
For this series RLC circuit, the neper frequency is
R 12 Ω
α= = = 600 rad/s (7.67)
2 L 2 (10 mH )
1
ω0 = = 2, 000 rad/s. (7.68)
( 25 µF )(10 mH )
TABLE 7.2
Three Cases of Step and Natural Response for a Series RLC Circuit
Series RLC circuit: α = R / ( 2 L ), ω 0 = 1 / LC .
α > ω0 Overdamped i ( t ) = A1e s1t + A2e s2t ; s1 , s2 = −α ± α 2 − ω 02
vC ( t ) = VF + E1e s1t + E2e s2t ;
t ≥ 0+
α = ω0 Critically- i ( t ) = D1te −α t + D2e −α t ; s1 , s2 = −α
damped vC ( t ) = VF + F1te −α t + F2e −α t
t ≥ 0+
α < ω0 Underdamped i ( t ) = B1e −α t cos (ω d t ) + B2e −α t sin (ω d t ) ; s1 , s2 = −α ± jω d
vC ( t ) = VF + G1e− α t cos ( ωd t ) + G2e− α t sin ( ωd t ) ω d = ω 02 − α 2
t ≥ 0+
FIGURE 7.12 An underdamped series RLC circuit for consideration of the step and natural
response.
Because α < ω 0 , the roots of the characteristic equation are complex conjugates and
the solution has an underdamped form with
ω d = 2,000 2 − 600 2 rad/s = 1,908 rad/s. (7.69)
The solution for the capacitor voltage is of the form:
vC ( t ) = VF + E1e −α t cos (ω d t ) + E2e −α t sin (ω d t )

(7.70)
= VF + E1e −600 t cos (1,908t ) + E2e −600 t sin (1,908t ); t ≥ 0 + ,
where VF = VTh1 = 15 V. To find the coefficients E1 and E2, we will apply the
initial conditions. We have established that the initial capacitor voltage is
vC ( 0 + ) = vC ( 0 − ) = VTh0 = 10 V . From the general form of the solution, evaluated at
t = 0 + , vC ( 0 + ) = VF + E1. Equating these two and solving,
E1 = VTh0 − VF = VTh0 − VTh1 = 10 V − 15 V = −5 V. (7.71)
The initial value of the derivative of the capacitor voltage may be found by consider-
ation of the initial current:
dvC i ( 0+ ) 0
= = = 0. (7.72)
dt t=0 + C 25 µF
dvC
= −α E1 + ω d E2 . (7.73)
dt t = 0+
Equating these two,
−α E1 + ω d E2 = 0, (7.74)
so
0 + α E1 0 + ( 600 rad/s )( −5V )

E2 = = = −1.572 V. (7.75)
ωd 1,908 rad/s
Therefore,
vC ( t ) = VF + E1e −600 t cos (1,908t ) + E2e −600 t sin (1,908t )

(7.76)
15 − 5e −600 t cos (1,908t ) + 1.572e −600 t sin (1,908t ) V; t ≥ 0 +.
The current may be found by differentiation:
dvC d
i (t ) = C = ( 25 µF ) 15 − 5e −600 t cos (1,908t ) + 1.572e −600 t sin (1,908t ) V
dt dt (7.77)
=  +0.262e −600 t sin (1,908t ) A; t ≥ 0 +.
So whereas the capacitor voltage exhibits a non-zero final value, the current does not.
The current and capacitor voltage are plotted in Figure 7.13.
FIGURE 7.13 Step and natural response (current and capacitor voltage) for the under-
damped series RLC circuit in Figure 7.12.
7.7 NATURAL RESPONSE OF A PARALLEL RLC CIRCUIT

Now, we will shift our focus to parallel RLC circuits, in which the inductor and the
capacitor are connected in parallel. We will find that many of the considerations
are similar to those for series circuits, but with key differences in the determina-
tion of α , initial conditions, and final conditions. Suppose that the parallel RLC
circuit in Figure 7.14 exhibits an initial inductor current of I 0 and an initial capaci-
tor voltage of V0. (There are switching configurations capable of establishing these
initial conditions, but the switching circuitry is omitted here for simplicity.) We
want to determine iL ( t ) and v ( t ) for t ≥ 0 + . If we allow the circuit to settle, both
the inductor current and the capacitor voltage will settle to zero: iL ( ∞ ) = 0 and
v ( ∞ ) = 0.
FIGURE 7.14 A parallel RLC circuit for consideration of the natural response.
To determine the transient response of this circuit while it is settling, we need to

set up and solve a second-order homogeneous linear differential equation. To do this,
we start by using Kirchhoff’s current law (KCL):
t
v 1 dv
R
+ I0 +
L ∫
vdy + C
0
dt
= 0. (7.78)
1 dv v d 2v
+ + C 2 = 0. (7.79)
R dt L dt
d 2v 1 dv 1
2
+ + v = 0. (7.80)
dt RC dt LC
As before, we will assume solutions of the form v ( t ) = Ae st . Using this assumed

form,
1 1
s 2 Ae st + sAe st + Ae st = 0. (7.81)
RC LC
Dividing by Ae st , we obtain the characteristic equation for the parallel RLC circuit:
1 1
s2 + s+ = 0. (7.82)
RC LC
Applying the quadratic formula, we can find the two roots of the characteristic
equation:
2
1  1  1
s1 , s2 = − ±  − . (7.83)
2 RC  2 RC  LC
s1 , s2 = −α ± α 2 − ω 02 , (7.84)
where α = 1 / ( 2 RC ) is the neper frequency and ω 0 = 1 / LC is the resonant fre-

quency for the parallel RLC circuit. Whereas the resonant frequency equation is
given by the same expression as the series case, the neper frequency is not.
Once again there are three cases with regard to the nature of the roots and the
response of the circuit. These are the overdamped, critically-damped, and under-
damped cases summarized in Table 7.3. Although the table gives the forms of the
solution for the voltage, which is common to all three elements and therefore a fun-
damental quantity, it should be recognized that the individual currents in the circuit
will exhibit the same general forms.
TABLE 7.3
Three Cases of Natural Response for a Parallel RLC Circuit
Parallel RLC circuit: α = 1 / ( 2 RC ), ω 0 = 1 / LC .
α > ω0 Overdamped v ( t ) = A1e s1t + A2e s2t , t ≥ 0 + s1 , s2 = −α ± α 2 − ω 02
α = ω0 Critically- v ( t ) = D1te + D2e , t ≥ 0
−α t −α t + s1 , s2 = −α
damped
α < ω0 Underdamped v ( t ) = B1e −α t cos (ω d t ) + B2e −α t sin (ω d t ) , t ≥ 0 + s , s = −α ± jω
1 2 d
ω d = ω 02 − α 2
7.8 STEP AND NATURAL RESPONSE OF A PARALLEL RLC CIRCUIT

Now consider the parallel RLC circuit in Figure 7.15, and suppose the switch has
been in position a for a long time before moving to position b. If the circuit settled
with the switch in position a, all time derivatives will have settled to zero. This
implies that v = LdiL / dt will have settled to zero before the movement of the
switch, and the voltage may not change instantaneously because of the capaci-
tor, so v ( 0 + ) = v ( 0 − ) = 0. Also, iC = Cdv / dt will have settled to zero before the
movement of the switch so iC ( 0 − ) = 0. However, the capacitor current may change
instantaneously so the value of iC ( 0 + ) may not be zero and must be determined
by using KCL. Given these considerations, the inductor current will have settled
to the value of the Norton current source connected prior to the switch movement,
and the inductor current may not change instantaneously so the same value of
current will exist right after the switch moves: iL ( 0 + ) = iL ( 0 − ) = I N 0 . If we allow
the circuit to resettle with the switch in position b, similar considerations apply
and iL ( ∞ ) = I N1.
FIGURE 7.15 A parallel RLC circuit for consideration of the step and natural response.
To determine the transient response of this circuit after the switch has moved to
position b, we need to set up and solve a second-order homogeneous linear differen-
tial equation. To do this, we start by using KCL:
t
1 dv v
IN0 +
L ∫
vdy + C
0
dt
− I N1 +
RN 1
= 0. (7.85)
1 dv v d 2v
+ + C 2 = 0. (7.86)
R dt L dt
d 2v 1 dv 1
+ + v = 0. (7.87)
dt 2 RC dt LC
As before, we will assume solutions of the form v ( t ) = Ae st . Using this assumed form,
1 1
s 2 Ae st + sAe st + Ae st = 0. (7.88)
RC LC
Dividing by Ae st , we obtain the characteristic equation:
1 1
s2 + s+ = 0. (7.89)
RC LC
This is the same as the characteristic equation we obtained when solving for the natu-
ral response. Therefore, the solutions will have the same forms, apart from a constant
to account for the final value of the inductor current. The three forms of the solution
are summarized in Table 7.4.
TABLE 7.4
Three Cases of Step and Natural Response for a Parallel RLC Circuit
Series RLC circuit: α = 1 / ( 2 RC ), ω 0 = 1 / LC .
α > ω0 Overdamped v ( t ) = A1e s1t + A2e s2t ; s1 , s2 = −α ± α 2 − ω 02
iL ( t ) = I F + E1e + E2e ;
s1t s 2t
t ≥ 0+
α = ω0 Critically-damped v ( t ) = D1te −α t + D2e −α t ; s1 , s2 = −α
iL ( t ) = I F + F1te −α t + F2e −α t ;
t ≥ 0+
α < ω0 Underdamped v ( t ) = B1e −α t cos (ω d t ) + B2e −α t sin (ω d t ) ; s1 , s2 = −α ± jω d
iL ( t ) = I F + G1e −α t cos (ω d t ) + G2e −α t sin (ω d t ) ; ω d = ω 02 − α 2
t ≥ 0+
FIGURE 7.16 An overdamped parallel RLC circuit for consideration of the step and natural
response.
As an example, consider the circuit in Figure 7.16. The initial value of inductor
current is iL ( 0 + ) = iL ( 0 − ) = I N 0 = 0.2 A , and the final value of inductor current will
be iL ( ∞ ) = I N 1 = 0.1A. The initial voltage will be zero, because the inductor will
settle to zero voltage prior to the switch movement and the parallel capacitor pre-
vents the voltage from changing instantaneously. The final voltage will also be zero
because the inductor will resettle to zero volts after the switch has been moved.
1 1
α= = = 1, 000 rad/s (7.90)
2 RN 1C 2 ( 40 Ω )(12.5 µF )
1
ω0 = = 800 rad/s. (7.91)
(125 mH )(12.5 µF )
s1 , s2 = −α ± α 2 − ω 02
( )
= −1, 000 ± 1, 000 2 − 800 2 rad/s = −400, −1,600 rad/s. (7.92)
This is an overdamped circuit and the solution is of the form:
iL ( t ) = I F + E1e s2t + E2e s2t = 0.1 A + E1e −400 t + E2e −1,600 t ; t > 0 +. (7.93)
of the initial inductor current is iL ( 0 + ) = 0.2 A. From the general form of the solution,
evaluated at t = 0 + , i ( 0 + ) = I F + E1 + E2. Equating these two,
E1 + E2 = iL ( 0 + ) − I F = 0.2 A − 0.1A = 0.1A. (7.94)

diL vL ( 0+ ) 0
= = = 0. (7.95)
dt t=0 + L L
diL
= s1E1 + s2 E2 = −400 E1 − 1,600 E2 . (7.96)
dt t = 0+
Equating these two,

−400 E1 − 1,600 E2 = 0 . (7.97)
Now, we can solve for the coefficients using the two equations involving A1 and A2:
 1 1   E1   0.1A 
=
 −400 rad/s −1,600 rad/s   E2  
 . (7.98)
    0 
Solving,
0.1A 1
0 −1,600 rad/s
E1 = = 0.1333 A (7.99)
1 1
−400 rad/s −1,600 rad/s
and
1 0.1A
−400 rad/s 0
E2 = = −0.0333 A. (7.100)
1 1
−400 rad/s −1,600 rad/s
Therefore,
iL ( t ) =  0.1 + 0.1333e −400 t − 0.0333e −1,600 t  A; t ≥ 0 +. (7.101)
The inductor voltage also exhibits an overdamped form:
diL d
v (t ) = L = (125 mH )  0.1 + 0.1333e −400 t − 0.0333e −1,600 t  A
dt dt
=  −6.665e −400 t + 6.665e −1,600 t  V; t ≥ 0 +. (7.102)
The inductor current and voltage are plotted in Figure 7.17.

FIGURE 7.17 Inductor current and voltage for the overdamped parallel RLC circuit in
Figure 7.16.
FIGURE 7.18 A critically-damped parallel RLC circuit for consideration of the step and
natural response.
As a second example, consider the circuit in Figure 7.18. This is similar to the
previous example except that the value of RN1 has been modified.
1 1
α= = = 800 rad/s (7.103)
2 RN 1C 2 ( 50 Ω )(12.5 µF )

1
ω0 = = 800 rad/s. (7.104)
(125 mH )(12.5 µF )
Because α = ω 0 , the roots of the characteristic equation are real and equal:
s1 , s2 = −α ± α 2 − ω 02
(7.105)
( )
= −800 ± 800 2 − 800 2 rad/s = −800 − 800 rad/s.
This is therefore a critically-damped circuit and the solution is of the form:
iL ( t ) = I F + F1te −α t + F2e −α t
(7.106)
= 0.1A + F1te −800 t + F2e −800 t ; t ≥ 0 +.
evaluated at t = 0 + , i ( 0 + ) = I F + F2 . Equating these two and solving,
F2 = iL ( 0 + ) − I F = 0.2 A − 0.1A = 0.1A. (7.107)
The initial value of the derivative of the inductor current may be found by consider-
ation of the inductor voltage:
diL vL ( 0+ ) 0
= = = 0. (7.108)
dt t=0 + L L
diL
= F1 − α F2 = F1 − (800 rad/s )( 0.1A ) . (7.109)
dt t = 0+
Solving,
F1 = 80 A/s. (7.110)
Therefore,
iL ( t ) =  0.1A + (80 A/s ) te −800 t + ( 0.1A ) e −800 t  ; t ≥ 0 +. (7.111)
The inductor voltage also exhibits a critically-damped form:
di d
v (t ) = L = (125 mH )  0.1A + (80 A/s ) te −800 t + ( 0.1A ) e −800 t 
dt dt
(7.112)
= ( −8, 000 V/s ) te −800 t  ; t ≥ 0 +.
The inductor current and voltage are shown in Figure 7.19.

As a third example, consider the circuit in Figure 7.20. Here, the value of RN1
has been further modified to render an underdamped circuit. (Notice that in the
FIGURE 7.19 Inductor current and voltage transients for the critically-damped parallel
RLC circuit in Figure 7.18.
FIGURE 7.20 An underdamped parallel RLC circuit for consideration of the step and natu-
ral response.
parallel RLC circuit, an underdamped response corresponds to larger values of RN1.

This contrasts with the case of the series RLC circuit.) The initial inductor cur-
rent will be I 0 = iL ( 0 + ) = iL ( 0 − ) = I N 0 = 0.2 A, and the final inductor current will be
I F = iL ( ∞ ) = I N 1 = 0.1A.
1 1
α= = = 100 rad/s, (7.113)
2 RN 1C 2 ( 400 Ω )(12.5 µF )
1
ω0 = = 800 rad/s. (7.114)
(125 mH )(12.5 µF )
Because α < ω 0 , the roots of the characteristic equation are complex conjugates.
s1 , s2 = −α ± j ω 02 − α 2 = −α ± jω d ,
where
ω d = 800 2 − 100 2 rad/s = 794 rad/s. (7.115)
This is therefore an underdamped circuit and the solution is of the form:
iL ( t ) = I F + G1e −α t cos (ω d t ) + G2e −α t sin (ω d t );

(7.116)
= 0.1A + G1e −100 t cos ( 794t ) + G2e −100 t sin ( 794t ); t ≥ 0 +.
evaluated at t = 0 + , i ( 0 + ) = I F + G1. Equating these two and solving,
G1 = iL ( 0 + ) − I F = 0.2 A − 0.1A = 0.1A. (7.117)
The initial value of the derivative of the inductor current may be found by consider-
ation of the inductor voltage:
diL vL ( 0+ ) 0
= = = 0. (7.118)
dt t = 0+ L L
diL
= −α G1 + ω d G2 = − (100 rad/s )( 0.1A ) + ( 794 rad/s ) G2 . (7.119)
dt t = 0+
Solving,
G2 = 0.0125 A. (7.120)
Therefore,
iL ( t ) =  0.1 + 0.1e −100 t cos ( 794t ) + 0.0125e −100 t sin ( 794t ) A; t ≥ 0 +. (7.121)
The inductor voltage also exhibits an underdamped form:
di d
v (t ) = L = (125 mH )  0.1 + 0.1e −100 t cos ( 794t ) + 0.0125e −100 t sin ( 794t ) A
dt dt
=  −10.16e −100 t sin ( 794t ) V; t ≥ 0 +.

(7.122)
The inductor current and voltage are plotted in Figure 7.21.

To review, see Presentations 7.2, 7.3, and 7.4 in ebook+.
To test your knowledge, try Quizzes 7.2, 7.3, and 7.4 in ebook+. To put your
knowledge to practice, try Laboratory Exercise 7.1 in ebook+.
7.9 GENERAL RLC CIRCUIT

Some second-order RLC circuits may be neither parallel nor series in character; that
is, the inductor and the capacitor are neither in parallel nor in series. One example
is shown in Figure 7.22. Here, the switch has been open for a long time and closes
at t = 0. In order to solve for i and v for t ≥ 0 + , it is necessary to derive and solve the
second-order differential equation.
In order to derive the differential equation, we disable the independent sources
and consider the position of the switch for t ≥ 0 + . Here, there is only one independent
voltage source to disable, and we disable it by setting it to zero volts or a short. (If
there had been an independent current source, we would disable it by setting it to zero
amperes or an open circuit.) This results in the circuit of Figure 7.23.
FIGURE 7.21 Inductor current and voltage transients for the underdamped parallel RLC
circuit of Figure 7.20.
FIGURE 7.22 A general RLC circuit which is neither parallel and series in character.
FIGURE 7.23 A general RLC circuit which has been simplified.
By KVL,
di
iR1 + L + v = 0. (7.123)
dt
By KCL,
v dv
i= +C . (7.124)
R2 dt
Differentiating the equation for i,
di 1 dv d 2v
= +C 2 . (7.125)
dt R2 dt dt
Substituting equations (7.123) and (7.124) into equation (7.122),
 v dv   1 dv d 2v 
R1  + C  + L  + C 2  + v = 0. (7.126)
 R2 dt   R2 dt dt 
d 2v  L  dv  R 
( LC ) + R1C +  + 1 + 1  v = 0. (7.127)
dt 2  R2  dt  R2 
Normalizing with respect to the highest-order term,
d 2 v  R1 1  dv  1 + R1 / R2 
+ + +  v = 0. (7.128)
dt 2
 L R2C  dt  LC 
Like before we will assume solutions of the form i ( t ) = Ae st , so that
R 1   1 + R1 / R2  st
s 2 Ae st +  1 + sAe st +   Ae = 0. (7.129)
 L R2C   LC 
Dividing by Ae st , we obtain the characteristic equation:
R 1   1 + R1 / R2 
s2 +  1 + s+  = 0. (7.130)
 L R2C   LC 
Applying the quadratic formula, we can find the two roots of the characteristic equation:
2
 R 1   R 1   1 + R1 / R2 
s1 , s2 = −  1 + ±  1 + − . (7.131)
 2 L 2 R2C   2 L 2 R2C   LC 
s1 , s2 = −α ± α 2 − ω 02 , (7.132)
where the neper frequency is
 R 1 
α = 1 + (7.133)
 2 L 2 R2C 

1 + R1 / R2 
ω 0 =  . (7.134)
 LC 
There are three cases of the solution (overdamped, critically-damped, and under-
damped) which have similar forms to those found before except that the neper fre-
quency and resonant frequency are calculated differently.
It is interesting to consider two limiting cases of this circuit. First, consider what
happens if R1 approaches zero:
 R 1  1
lim α = lim  1 +  = (7.135)
R1 → 0 R1 → 0  2 L 2 R2C  2 R2C
and
 1 + R1 / R2  1
lim ω 0 = lim   = . (7.136)
R1 → 0 R1 → 0  LC  LC
This corresponds to a simple parallel RLC circuit as expected for the case in which
R1 has been replaced by a short. On the other hand, if we consider the limiting case
in which R2 approaches infinity,
 R 1  R1
lim α = lim  1 + = (7.137)
R2 →∞ R2 →∞  2 L 2 R2C  2 L
and
 1 + R1 / R2  1
lim ω 0 = lim   = . (7.138)
R2 →∞ R2 →∞ LC  LC
This corresponds to a simple series RLC circuit as expected for the case in which R2
has been replaced by an open circuit.
7.10 SUMMARY
In this chapter, we considered the transient response for switched second-order
circuits. A second-order circuit contains two energy-storage elements, such as an
inductor and a capacitor, two capacitors, or two inductors, and its transient behav-
ior is described by a second-order differential equation. We considered some
important cases of second-order circuits here, including the series RLC circuit,
the parallel RLC circuit, and the general RLC circuit which may be neither series
nor parallel.
First, we analyzed the natural response of a series RLC circuit as shown in
Figure 7.24.
The initial inductor current is assumed to be I 0 and the initial capacitor voltage is
assumed to be V0. Both final values will be zero. The differential equation describing
the behavior for t ≥ 0 + is
d 2i R di 1
+ + i = 0. (7.139)
dt 2 L dt LC
We assume solutions of the form i ( t ) = Ae st , leading to the characteristic equation:
R 1
s2 + s+ = 0. (7.140)
L LC
FIGURE 7.24 A simple series RLC circuit without sources.
The roots are

s1 , s2 = −α ± α 2 − ω 02 , (7.141)
where α = R / ( 2 L ) is the neper frequency and ω 0 = 1 / LC is the resonant fre-

quency for the series RLC circuit. There are three cases of the solution for t ≥ 0 + :
 A1e s1t + A2e s2t , (overdamped, α > ω 0 ) ;



i ( t ) =  D1te −α t + D2e −α t , ( critically-damped, α = ω 0 ) ;

 B1e −α t cos (ω d t ) + B2e −α t sin (ω d t ) , ( underdamped, α < ω 0 ) .
(7.142)
In each case, the two coefficients are found by consideration of the initial conditions,
and in the underdamped case the damped radian frequency is ω d = ω 02 − α 2 .
Next, we considered the step and natural response of the series RLC circuit
using the switched network in Figure 7.25.
In this circuit configuration, the initial capacitor voltage is V0 = VTh0 and the final
capacitor voltage is VF = VTh1, but the initial and final inductor current are both zero.
When solving for the current, the differential equation and the characteristic equa-
tion are the same as in the case of the natural response, so the forms of the solution
are the same. The solutions for the capacitor voltage are similar but with an added
constant representing the final value. For t ≥ 0 + :
 VF + E1e s1t + E2e s2t , ( overdamped, α > ω0 ) ;




vC ( t ) =  VF + F1te− α t + F2e− α t ( critically-damped, α = ω0 ) ;


 VF + G1e− α t cos ( ωd t ) + G2e− α t sin ( ωd t ) , ( underdamped, α < ω0 ) .

(7.143)
FIGURE 7.25 A switched series RLC circuit for consideration of the step and natural
response.
Third, we analyzed the natural response of a parallel RLC circuit as shown in

Figure 7.26.
The initial inductor current is assumed to be I 0 and the initial capacitor voltage is
assumed to be V0. Both final values will be zero. The differential equation describing
the behavior for t ≥ 0 + is
d 2v 1 dv 1
+ + v = 0. (7.144)
dt 2 RC dt LC
We assume solutions of the form v ( t ) = Ae st , leading to the characteristic equation:
1 1
s2 + s+ = 0. (7.145)
RC LC
The roots are
s1 , s2 = −α ± α 2 − ω 02 , (7.146)
where α = 1 / ( 2 RC ) is the neper frequency and ω 0 = 1 / LC is the resonant fre-

quency for the parallel RLC circuit. There are three cases of the solution for t ≥ 0 + :
 s1t ( overdamped, α > ω0 ) ;

 A1e + A2e ,
s2 t


v ( t ) =  D1te− α t + D2e− α t , ( critically-damped, α = ω0 ) ;

 −α t
 B1e cos ( ωd t ) + B2e− α t sin ( ωd t ) , ( underdamped, α < ω0 ) .

(7.147)
FIGURE 7.26 A parallel RLC circuit for consideration of the natural response.
FIGURE 7.27 A parallel RLC circuit for consideration of the step and natural response.
Fourth, we considered the step and natural response of the parallel RLC cir-
cuit using the switched network in Figure 7.27.
In this circuit configuration, the initial inductor current is I 0 = I N 0 and the final
inductor current is I F = I N1, but the initial and final capacitor voltage are both zero.
When solving for the voltage v ( t ), the differential equation and the characteristic
equation are the same as in the case of the natural response, so the forms of the solu-
tion are the same. The solutions for the inductor current are similar but with an added
constant representing the final value. For t ≥ 0 + :
 I F + E1e s1t + E2e s2t , ( overdamped, α > ω0 ) ;




iL ( t ) =  I F + F1te− α t + F2e− α t , ( critically-damped, α = ω0 ) ;


 I F + G1e− α t cos ( ωd t ) + G2e− α t sin ( ωd t ) , ( underdamped, α < ω0 ) .

(7.148)
More generally, the initial conditions must be found by consideration of the par-
ticular switching configuration, which may be different from those shown in Figures
7.25 and 7.27. Also, some RLC circuits are neither parallel nor series in character, so
it becomes necessary to derive and solve the differential equation rather than use one
of the predetermined solutions obtained above.
To evaluate your mastery of Chapters 6 and 7, solve Example Exam 7.1 in ebook+
or Example Exam 7.2 in ebook+.
PROBLEMS
v L ( ∞ ) , vC ( 0 − ), vC ( 0 + ), vC ( ∞ ), i ( 0 − ), i ( 0 + ), i ( ∞ ), and di / dt t = 0+ .
Determine v L ( t ), vC ( t ), and i ( t ) for t ≥ 0 + . Calculate the initial and final
energy stored in the capacitor. Assume that the switch has been in its start-
ing position for a long time before moving at t = 0.
FIGURE P7.1 Switched series RLC circuit.


v L ( ∞ ) , vC ( 0 − ), vC ( 0 + ), vC ( ∞ ), i ( 0 − ), i ( 0 + ), i ( ∞ ), and di / dt + .
t=0
Determine v L ( t ), vC ( t ), and i ( t ) for t ≥ 0 + . Assume that the switch has been
in its starting position for a long time before moving at t = 0.
FIGURE P7.2 Switched RLC circuit including a voltage source and two resistors.
Problem 7.3. For the circuit shown in Figure P7.3, determine v L ( t ), vC ( t ),

and i ( t ) for t ≥ 0 + . Assume that the switch has been in its starting position
for a long time before moving at t = 0.
FIGURE P7.3 Switched RLC circuit including a current source and four resistors.
Problem 7.4. For the circuit shown in Figure P7.4, determine v L ( t ), vC ( t ),

and i ( t ) for t ≥ 0 + . Assume that the switch has been in its starting position
FIGURE P7.4 Switched RLC circuit including mixed sources.

Problem 7.5. For the circuit shown in Figure P7.5, find iL ( 0 − ), iL ( 0 + ), iL ( ∞ ),

iC ( 0 − ) , iC ( 0 + ), iC ( ∞ ), v ( 0 − ), v ( 0 + ), v ( ∞ ), and dv / dt + . Determine
t=0
iL ( t ), iC ( t ), and v ( t ) for t ≥ 0 + . Calculate the initial and final energy stored
in the inductor. Assume that the switch has been in its starting position for
a long time before moving at t = 0.
FIGURE P7.5 Switched parallel RLC circuit.
Problem 7.6 For the circuit shown in Figure P7.6, find iL ( 0 − ), iL ( 0 + ), iL ( ∞ ),

iC ( 0 − ), iC ( 0 + ), iC ( ∞ ), v ( 0 − ), v ( 0 + ), v ( ∞ ), and dv / dt t = 0+ . Determine iL ( t ),
iC ( t ), and v ( t ) for t ≥ 0 + . Calculate the initial and final energy stored in the
inductor. Assume that the switch has been in its starting position for a long
time before moving at t = 0.
FIGURE P7.6 Switched RLC circuit which includes a voltage source and two resistors.
Problem 7.7. For the circuit shown in Figure P7.7, find iL ( 0 − ), iL ( 0 + ), iL ( ∞ ),

iC ( 0 − ), iC ( 0 + ), iC ( ∞ ) , v ( 0 − ), v ( 0 + ), v ( ∞ ), and dv / dt t = 0+ . Determine
iL ( t ), iC ( t ), and v ( t ) for t ≥ 0 + . Calculate the initial and final energy stored
in the inductor. Assume that the switch has been in its starting position for
FIGURE P7.7 Switched parallel RLC circuit which includes mixed sources and resistors.
Problem 7.8. For the circuit shown in Figure P7.8, find iL ( t ), iC ( t ), and v ( t )
for t ≥ 0 + . Assume that the switch has been in its starting position for a long
time before moving at t = 0.
FIGURE P7.8 Switched parallel RLC circuit which includes a voltage source and three
resistors.

v L ( ∞ ), vC ( 0 − ), vC ( 0 + ), vC ( ∞ ), i ( 0 − ), i ( 0 + ), i ( ∞ ), and di / dt t = 0+ .
Determine v L ( t ), vC ( t ), and i ( t ) for t ≥ 0 + . Assume that the switch has been
in its starting position for a long time before moving at t = 0.
FIGURE P7.9 Switched series RLC circuit which includes a current source and three resistors.

v L ( ∞ ), vC ( 0 − ), vC ( 0 + ), vC ( ∞ ), i ( 0 − ), i ( 0 + ), i ( ∞ ), and di / dt t = 0+ .
Determine v L ( t ), vC ( t ), and i ( t ) for t ≥ 0 + . Calculate the initial and final
energy stored in the capacitor. Assume that the switch has been in its start-
ing position for a long time before moving at t = 0.
FIGURE P7.10 Switched series RLC circuit which includes a voltage source and a resistor.
Problem 7.11. For the circuit shown in Figure P7.11, determine iL ( t ) , iC ( t ),

and v ( t ) for t ≥ 0 + . Assume that the switch has been in its starting position
FIGURE P7.11 Switched parallel RLC circuit which includes a current source and two
resistors.
Problem 7.12. For the circuit shown in Figure P7.12, find iL ( t ), iC ( t ), and
v ( t ) for t ≥ 0 + . Calculate the initial and final energy stored in the inductor
and in the capacitor. Assume that the switch has been in its starting position
FIGURE P7.12 Parallel RLC circuit involving a single-pole, double-throw switch.


v L ( ∞ ), vC ( 0 − ) , vC ( 0 + ) , vC ( ∞ ) , i ( 0 − ) , i ( 0 + ) , i ( ∞ ) , and di / dt t = 0+ .
Determine v L ( t ) , vC ( t ) , and i ( t ) for t ≥ 0 +. Assume that the switch has
been in its starting position for a long time before moving at t = 0 .
FIGURE P7.13 RLC circuit which becomes series in character after the movement of a
switch.
Problem 7.14. For the circuit shown in Figure P7.14, find v L ( 0 − ) , v L ( 0 + ) ,

v L ( ∞ ) , vC ( 0 − ) , vC ( 0 + ) , vC ( ∞ ) , i ( 0 − ) , i ( 0 + ) , i ( ∞ ) , and di / dt t = 0+ .
been in its starting position for a long time before moving at t = 0.
FIGURE P7.14 Switched RLC circuit which changes in character after the movement of
the switch.
Problem 7.15. For the circuit shown in Figure P7.15, find v L ( 0 − ) , v L ( 0 + ) ,

v L ( ∞ ) , vC ( 0 − ) , vC ( 0 + ) , vC ( ∞ ) , i ( 0 − ) , i ( 0 + ) , i ( ∞ ) , and di / dt t = 0+ .
been in its starting position for a long time before moving at t = 0.
FIGURE P7.15 Switched series RLC circuit involving mixed sources.
Problem 7.16. For the circuit shown in Figure P7.16, find v L ( t ) , vC ( t ) , and
i ( t ) for t ≥ 0 +. Assume that the switch has been in its starting position for
FIGURE P7.16 Switched RLC circuit involving two sources and four resistors, which
becomes series in character after the movement of a switch.
Problem 7.17. For the circuit shown in Figure P7.17, find iL ( t ) , iC ( t ) , and
v ( t ) for t ≥ 0 +. Assume that the switch has been in its starting position for
FIGURE P7.17 Switched parallel RLC circuit involving three independent sources and
three resistors.
a long time before moving at t = 0
FIGURE P7.18 Switched RLC circuit which becomes parallel in character after closure of
a switch.
FIGURE P7.19 Switched RLC circuit which changes character after movement of a switch.
FIGURE P7.20 Switched parallel RLC circuit involving a single-pole, double-throw switch.
8 Sinusoidal Steady-
State Analysis
8.1 INTRODUCTION
Up to this point, the independent sources we considered provided constant, unchang-
ing voltages or currents; these are referred to as direct current (DC) sources. Now, we
turn our analysis to the important case of sinusoidal sources, which are also referred
to as alternating current (AC) sources. This is the field of sinusoidal steady-state
analysis, which is important for two reasons: first, electrical power distribution is
usually done using sinusoidal voltages, and second, sinusoidal steady-state analysis
allows us to analyze the frequency response of signal-processing circuitry.
A sinusoidal voltage source may be specified in the time domain as
v ( t ) = Vm cos (ω t + φ ) , (8.1)
where Vm is the amplitude of the sinusoid in V, ω is the radial frequency in rad/s, and
φ is the phase angle in rad. Other quantities of interest are the frequency f in Hz,
where f = ω / ( 2π ), and the period T in s, given by T = 1 / f .
Consider the switched application of a sinusoidal voltage source to the resistor-
inductor (RL) circuit shown in Figure 8.1.
The solution is
−Vm
i (t ) = cos (φ − θ ) exp {( − R / L ) t }
R 2
+ ω 2 L2

transient response
Vm
+ cos (ω t + φ − θ ) ; t ≥ 0 +. (8.2)
R + ω L
2

2 2
sinusoidal steady − state response
This solution comprises two parts. The transient response may be determined by
the methods illustrated in Chapter 6, but it decays exponentially after the switch has
moved. We are often more interested in the sinusoidal steady-state response, which
is sinusoidal with the same frequency as the source in the circuit. This chap-
ter will describe phasor and impedance methods used to determine the sinusoidal
steady-state response. We will see that this approach simplifies the solution by allow-
ing us to solve algebraic equations instead of differential equations.
306 DOI: 10.1201/9781003408529-8

Sinusoidal Steady-State Analysis 307
FIGURE 8.1 Switched application of a sinusoidal voltage source to an RL circuit.
8.2 REVIEW OF COMPLEX NUMBERS

In order to solve AC circuits algebraically, without the need for differential equa-
tions, we will make extensive use of complex numbers and complex mathematics. It
should be understood that this represents a system of shortcuts and that we are using
complex quantities to represent real circuit elements, real currents, and real voltages.
Nonetheless, working with complex quantities is a critical part of sinusoidal steady-
state analysis so we will review the mathematics of complex numbers.
A complex number A + jB involves a real component A and an imaginary com-
ponent, jB, where j is the imaginary unit,1 j = −1. This complex number may be
shown on the complex plane using Cartesian (rectangular) coordinates or polar coor-
dinates of the form R∠θ , as shown in Figure 8.2.
Using Euler’s relationship,2 we can convert from rectangular coordinates to polar
coordinates3:
( )
1/2 −1
A + jB → A2 + B 2 e tan ( B / A) = Re jθ . (8.3)

rectangular coordinates polar coordinates
We can also convert from polar coordinates to rectangular coordinates:
Re jθ
→ R cos θ + jR sin θ = A + jB . (8.4)
polar coordinates

rectangular coordinates
Often, we will express complex numbers in polar form using the shorthand notation
R∠θ ; it should be recognized that this means the same thing as Re jθ .
When adding complex quantities,
( A + jB ) + (C + jD ) = ( A + C ) + j ( B + D ) (8.5)
and
A∠α + B∠β = ( A cos α + B cos β ) + j ( A sin α + B sin β ) . (8.6)
When multiplying complex quantities,
( A + jB )(C + jD ) = ( AC − BD ) + j ( BC + AD ) (8.7)
FIGURE 8.2 A complex quantity A + jB shown in the complex plane.
and
( A∠α ) ( B∠β ) = AB∠ (α + β ) . (8.8)
When dividing complex quantities,

A + jB ( A + jB ) (C − jD ) ( AC + BD ) + j ( BC − AD )
= = (8.9)
C + jD (C + jD ) (C − jD ) C 2 + D2
and
A∠α
= ( A / B ) ∠ (α − β ) . (8.10)
B∠β
Finally, we note that 1 / j = − j , because
1  1  j j
= = = − j. (8.11)
j  j   j  −1
8.3 PHASORS
Consider a sinusoidal voltage in the time domain given by
v ( t ) = Vm cos (ω t + φ ) . (8.12)
If we imagine a vector of length Vm emanating from the origin of the complex

plane4 with a starting angle of φ with respect to the horizontal axis and spinning
counterclockwise at an angular velocity ω , then v ( t ) may be considered to be the

projection of this spinning vector on the real axis. If we freeze this spinning vector at
t = 0, this results in a phasor representation of the sinusoid in the complex plane. For
example, consider the following three sinusoidal voltages:
va ( t ) = 12 V cos ( 400 rad/s ) t + π / 6  ,
vb ( t ) = 10 V cos ( 400 rad/s ) t + π / 4  , (8.13)
vc ( t ) = 8 V cos ( 400 rad/s ) t + π / 3  .
These time-domain voltages are plotted in Figure 8.3.

These same three sinusoids may be represented as complex phasors, which can
be shown in the complex plane. The complex phasors, denoted as bold uppercase
letters, are
Va = 12 V exp ( jπ / 6 ) = 12 V [ cos ( π / 6 ) + j sin ( π / 6 )] = (10.39 + j6.00 ) V,
Vb = 10 V exp ( jπ / 4 ) = 10 V [ cos ( π / 4 ) + j sin ( π / 4 )] = ( 7.07 + j 7.07 ) V, (8.14)
Vc = 8 V exp ( jπ / 3) = 8 V [ cos ( π / 3) + j sin ( π / 3)] = ( 4.00 + j6.92 ) V.
In shorthand polar notation, we can represent these phasors as
Va = 12 V∠π / 6,
Vb = 10 V∠π / 4, (8.15)
Vc = 8 V∠π / 3.
It is important to be familiar with all of these equivalent ways for expressing a pha-
sor, and to be equally comfortable with rectangular forms and polar forms. The three
phasors described above may be plotted in the complex plane as shown in Figure 8.4.
We can represent sinusoidal currents as phasors in much the same way. However, it
must be emphasized that voltages and currents are real, not complex, and the com-
plex phasor is simply a convenient way to represent the amplitude and phase of a real
sinusoid!
8.4 IMPEDANCES
When solving for the sinusoidal steady-state response of a circuit, we first transform
the circuit from the time domain to the phasor domain (also referred to as the
frequency domain). To do this, we represent sources using complex phasors while
passive components (resistors, inductors, and capacitors and their combinations) are
represented by complex impedances.
FIGURE 8.3 Three sinusoidal voltages represented in the time domain.
FIGURE 8.4 Three sinusoidal voltages represented as phasors.
8.4.1 Impedance of a Resistor

First, consider the case of a resistor with an applied sinusoidal voltage as shown in
Figure 8.5a.
Suppose the time-domain voltage is given by
v ( t ) = Vm cos (ω t + φ ) . (8.16)
FIGURE 8.5 A resistor with a sinusoidal voltage applied: (a) time domain and (b) phasor
domain.
By Ohm’s law, the time-domain current is
i ( t ) = v ( t ) / R = (Vm / R ) cos (ω t + φ ) . (8.17)
As shown in Figure 8.5b, the phasor quantities are
V = Vm ∠φ (8.18)
and
I = (Vm / R ) ∠φ . (8.19)
The impedance of the resistor is the ratio of the phasor voltage to the phasor current:
Z R = V / I = [Vm ∠φ ] / (Vm / R ) ∠φ  = R∠0 = R. (8.20)
The impedance of a resistor is equal to its resistance and has zero phase angle;
therefore, the current and voltage for a resistor are in phase (at the same phase
angle).
Figure 8.6 shows the time-domain voltage and current for a resistor in the case
of v ( t ) = 10 V cos ( 400t + π / 12 ) and R = 1.5 Ω . It can be seen that the voltage and
current are in phase. Figure 8.7 shows the phasor voltage and current for this case,
showing that the two phasors have the same angle or phase.
8.4.2 Impedance of an Inductor

Next, consider an inductor with an applied sinusoidal current as shown in Figure 8.8a.
Suppose the time-domain current is given by
i ( t ) = I m cos (ω t + φ ) . (8.21)
The time-domain voltage is
di
v (t ) = L = − ω LI m sin (ω t + φ ) . (8.22)
dt
FIGURE 8.6 Example time-domain voltage and current for a resistor. The time-domain
voltage is v ( t ) = 10Vcos ( 400t + π / 12 ) and the resistance is R = 1 .5Ω .
FIGURE 8.7 Example phasor-domain voltage and current for a resistor. The phasor voltage
is V = 10V∠π / 12, and the impedance of the resistor is Z R = 1 .5Ω.
It is customary to describe sinusoidal voltages and currents in terms of cosines, not

sines, and the phase angles are always given with respect to the cosine function.
In order to express the voltage using a cosine, we use the trigonometric identity
sin (α ) = − cos (α + π / 2 ) resulting in
v ( t ) = ω LI m cos (ω t + φ + π / 2 ). (8.23)
FIGURE 8.8 An inductor with a sinusoidal current applied: (a) time domain and (b) phasor
domain.
Thus, the phasor quantities (see Figure 8.8b) are
I = I m ∠φ (8.24)
and
V = ω LI m ∠(φ + π / 2). (8.25)
The impedance of the inductor is the ratio of the phasor voltage to the phasor current:
Z L = V / I = [ω LI m ∠(φ + π / 2) ] / [ I m ∠φ ] = ω L∠π / 2 = jω L. (8.26)
The impedance of an inductor is equal to jωL; it has a phase angle of π/2 so the
current lags the voltage by π/2 radians.
Figure 8.9 shows the time-domain voltage and current for an inductor in the case
of v ( t ) = 10 V cos ( 400t + π / 12 ) and L = 3.75 mH. It can be seen that the current
lags the voltage by a phase angle of π / 2. (In the time domain, the current peaks
one-quarter period after the voltage.) Figure 8.10 shows the phasor voltage and cur-
rent for this case. Recognizing that increasing angle represents counterclockwise
rotation of a phasor, we see that the current phasor lags the voltage phasor by π / 2.
8.4.3 Impedance of a Capacitor

Finally, we can consider a capacitor with an applied sinusoidal voltage as shown in
Figure 8.11a.
Suppose the time-domain voltage is given by
v ( t ) = Vm cos (ω t + φ ) . (8.27)
The time-domain current is

dv
i (t ) = C = − ω CVm sin (ω t + φ ) . (8.28)
dt
In order to express the current using a cosine function, we note that
sin (α ) = − cos (α + π / 2 ) so
i ( t ) = ω CVm cos (ω t + φ + π / 2 ) . (8.29)

FIGURE 8.9 Example time-domain voltage and current for an inductor. The time-domain
voltage is v ( t ) = 10Vcos ( 400t + π / 12 ), and the inductance is L = 3.75 mH .
FIGURE 8.10 Example phasor-domain voltage and current for an inductor. The phasor volt-
age is V = 10V∠π / 12, and the impedance of the inductor is Z L = j1.5Ω .
Thus, the phasor quantities (see Figure 8.11b) are
I = ω CVm ∠(φ + π / 2) (8.30)
and
V = Vm ∠φ . (8.31)
FIGURE 8.11 A capacitor with a sinusoidal voltage applied: (a) time domain and (b) phasor
domain.
The impedance of the capacitor is the ratio of the phasor voltage to the phasor current:
ZC = V / I = [Vm ∠φ ] / [ω CVm ∠(φ + π / 2) ]
(8.32)
= 1 / (ω C ) ∠ − π / 2 = 1 / ( jω C ) .
The impedance of a capacitor is equal to 1/(jωC); it has a phase angle of −π/2

so the current leads the voltage by π/2 radians.
Figure 8.12 shows the time-domain voltage and current for a capacitor in the case
of v ( t ) = 10 V cos ( 400t + π / 12 ) and C = 5 / 3 mF. It can be seen that the current
leads the voltage by a phase angle of π / 2. (In the time domain, the current peaks
one-quarter period before the voltage.) Figure 8.13 shows the phasor voltage and
current for this case. Recognizing that increasing angle represents counterclockwise
rotation of a phasor, we see that the current phasor leads the voltage phasor by π / 2.
8.4.4 Series Impedances
Kirchhoff’s laws and Ohm’s law apply in the phasor domain, and we can analyze
the case of series impedances in a manner analogous to that used for series resistors.
Consider the case of three series impedances shown in Figure 8.14.
By Kirchhoff’s voltage law,
−Vs + I Z1 + I Z 2 + I Z3 = 0. (8.33)
Solving for the phasor current,

Vs
I= , (8.34)
Z1 + Z 2 + Z3
and the equivalent impedance for the series combination is
Vs
Z eq = = Z1 + Z 2 + Z3 . (8.35)
I
We can extend this to any number of series impedances, showing that series imped-
ances combine like series resistances, and the equivalent impedance for the series
combination is the sum of the individual impedances. Because Kirchhoff’s laws and
FIGURE 8.12 Example time-domain voltage and current for a capacitor. The time-domain
voltage is v ( t ) = 10Vcos ( 400t + π / 12 ), and the capacitance is C = 5 / 3mF .
FIGURE 8.13 Example phasor-domain voltage and current for a capacitor. The phasor volt-
age is V = 10V∠π / 12, and the impedance of the capacitor is ZC = − j1.5Ω .
Ohm’s law apply in the phasor domain, the same is true of the voltage-divider rule.
In the case of three series impedances shown here, the use of the voltage-divider rule
yields
Z1
V1 = Vs , (8.36)
Z1 + Z 2 + Z3
Z2
V2 = Vs , (8.37)
Z1 + Z 2 + Z3
FIGURE 8.14 Three impedances in series.
and
Z3
V3 = Vs . (8.38)
Z1 + Z 2 + Z3
8.4.5 Parallel Impedances
Another important situation involves the parallel connection of two or more imped-
ances, as shown in Figure 8.15.
Applying Kirchhoff’s current law to the top node,
− I s + I1 + I 2 = 0 (8.39)
or
I s = I1 + I 2 . (8.40)
By Ohm’s law,
Vs Vs
Is = + . (8.41)
Z1 Z 2
The equivalent impedance for the parallel combination is
−1
Vs  1 1
Z eq = = + . (8.42)
I s  Z1 Z 2 
In other words, parallel impedances combine like parallel resistors. The equivalent
impedance for two parallel impedances is equal to the reciprocal of the sum of
their reciprocals. In the particular case of two parallel impedances, the equivalent
impedance is equal to the product divided by the sum:
Z1Z 2
Z eq = . (8.43)
Z1 + Z 2
FIGURE 8.15 Two parallel impedances.
We can apply the current-divider rule to parallel impedances in a phasor-domain

circuit. For the circuit in Figure 8.15,
Z1Z 2
Vs = I s Z eq = I s . (8.44)
Z1 + Z 2
The use of Ohm’s law leads us to the current-divider equations:
Z2
I1 = I s (8.45)
Z1 + Z 2
and
Z1
I2 = Is . (8.46)
Z1 + Z 2
A statement of the current-divider rule is as follows: when two impedances are

connected in parallel, the phasor current in one of the impedances is equal to
the total current phasor multiplied by the impedance in the other branch and
divided by the sum of the impedances.
We can generalize the current-divider rule to three or more impedances in parallel
by combining all of the impedances but one, rendering a system with two parallel
impedances.
8.4.6 Combinations of Series and Parallel Impedances

We can extend the concepts of the previous two sections to more complex situations
involving series and parallel combinations of impedances. Consider the circuit in
Figure 8.16, shown both in the time domain (8.16a) and in the phasor domain (8.16b).
Here, C and R1 are in parallel, R2 and L are in parallel, and these two combinations
are then connected in series. The equivalent impedance is therefore
R1 / jω C jω LR2
Z eq = + . (8.47)
R1 + 1 / jω C jω L + R2
Both the real and imaginary parts of the equivalent impedance are seen to be strong
functions of frequency in Figure 8.17. The real component of the impedance plateaus
at 10 Ω in the middle range of frequencies. Moreover, the imaginary part exhibits
a zero crossing at ~ 50, 000 rad/s, so the impedance is real (purely resistive) at this
radial frequency.
FIGURE 8.16 A series/parallel connection of four impedances: (a) time domain and
(b) phasor domain.
FIGURE 8.17 Real and imaginary parts of the equivalent impedance for the series/parallel
connection of Figure 8.16.
8.4.7 Impedance and Admittance

In general, a complex impedance can be expressed as
Z = R + jX , (8.48)
where R is the resistance and X is the reactance, both in units of Ω. Table 8.1 shows
the impedance, resistance, and reactance of the resistor, capacitor, and inductor.
Sometimes, it is convenient to use the admittance Y , which is the reciprocal of
impedance:
Y = 1 / Z = G + jB, (8.49)
where G is the conductance and B is the susceptance. All three parameters have units
of Ω −1. We will use impedances for most purposes, but the admittance may be par-
ticularly convenient in parallel connections. The reason is that, as shown in equation
(8.42), the admittance for several elements in parallel is the sum of the individual
admittances.
8.5 SINUSOIDAL STEADY-STATE ANALYSIS

We now return to the circuit introduced in Figure 8.1; this circuit is reproduced in
Figure 8.18 in both the time domain (8.18a) and the phasor domain (8.18b). The imped-
ance of the inductor in the phasor domain is Z L = jω L = j ( 200 rad/s )( 40 mH ) = j8 Ω.
After conversion to the phasor domain, we can find the phasor current by Ohm’s
law:
Vs 100 V∠π / 4 ( 70.7 + j 70.7 ) V
I= = = = ( 7.76 + j 0.862 ) A (8.50)
R + jω L (10 + j8) Ω (10 + j8) Ω
By the voltage-divider rule, we can find the phasor voltages:
R  10 
V1 = Vs = ( 70.7 + j 70.7 ) V  = ( 77.6 + j8.62 ) V (8.51)
R + jω L  10 + j8 
and
jω L  j8 
V2 = Vs = ( 70.7 + j 70.7 ) V  = ( −6.90 + j62.1) V. (8.52)
R + jω L  10 + j8 
We can then transform back to the time domain, but first we must convert the phasor
quantities from rectangular to polar coordinates, in order to reveal their magnitudes
and phases:
I = ( 7.76 + j 0.862 ) A = 7.81A∠0.11rad, (8.53)
TABLE 8.1
Impedance, Resistance, and Reactance for the Passive Components
Impedance Resistance Reactance
Resistor R + j0 R 0
Inductor 0 + jωL 0 ωL
Capacitor 0 + 1/(jωC) 0 −1/(ωC)
FIGURE 8.18 Example circuit for sinusoidal steady-state analysis: (a) time domain and
(b) phasor domain.
V1 = ( 77.6 + j8.62 ) V = 78.1V∠0.11rad, (8.54)

and
V2 = ( −6.90 + j62.1) V = 62.5 V∠1.68 rad. (8.55)
Now, we can transform back to the time domain:
i ( t ) = 7.81A cos ( 200t + 0.11) , (8.56)
v1 ( t ) = 78.1V cos ( 200t + 0.11) , (8.57)

and
v2 ( t ) = 62.5 V cos ( 200t + 1.68 ) . (8.58)
Thus, by transforming to the phasor domain, we were able to solve algebraically and
then transform back to the time domain. If we had solved this circuit directly in the
time domain, it would have involved the solution of a differential equation. Whereas
we can scale the phasor approach to very complicated circuits by use of the node
voltage or mesh current method, a time-domain solution becomes cumbersome for a
circuit of even modest complexity.
8.6 NODAL ANALYSIS IN CIRCUITS WITH

SINUSOIDAL EXCITATION
Because Kirchhoff’s laws and Ohm’s law apply to circuits with sinusoidal excitation
in the phasor domain, it is also true that we can apply the node voltage method, the
mesh current method, and Thevenin’s and Norton’s theorems to them. As an example
of the use of the node voltage method, consider the circuit in Figure 8.19.
This circuit has been redrawn in the phasor domain in Figure 8.20. To do this, we note that
the radial frequency for all sources is ω = 500 rad/s, and j ( 500 rad/s )(12 mH ) = j6 Ω ,
j ( 500 rad/s )(8 mH ) = j 4 Ω , and 1 /  j ( 500 rad/s )( 250 µF )  = − j8 Ω. For the repre-
sentation of the sources in rectangular form, we note that ( 25 V ) ∠0 = ( 25 + j 0 ) V,
( 2 A ) ∠ π4 =  2 cos  π4  + j2 sin  π4   A = 2 + j 2 A, and (6 A ) ∠0 = (6 + j0 ) A.

( )
These phasor-domain quantities are shown in Figure 8.20, along with the labeling
of the nodes for use of the node voltage method.
The node voltage equations in units of V, A, and Ω are
V1 − V2 V1 + 25 − V3
N1 2+ j 2+ + = 0, (8.59)
7 5 + j10
V2 − V1 V2
N2 + + 6 = 0, (8.60)
7 − j8
and
V3 − 25 − V1 V
N3 − 6 + 3 = 0. (8.61)
5 + j10 9
FIGURE 8.19 Example AC circuit for application of the node voltage method, represented
in the time domain.
in the phasor domain with the nodes labeled.
It will not be helpful to use the least common denominator here; doing so would
actually complicate the calculations. Instead, we retain the fractions as they appear
when collecting like terms.
1 1   −1   −1  25
N 1 V1  +  + V2  7  + V3  5 + j10  = − 2 − j 2 − 5 + j10 , (8.62)
 7 5 + j10     
−1 1 1 
N 2 V1   + V2  +  = −6, (8.63)
7  7 − j8 
and
 −1   1 1 25
N 3 V1   + V3  + = + 6. (8.64)
 5 + j10   5 + j10 9  5 + j10
In matrix form,
 1 1 −1 −1 
 +   25 
 7 5 + j10 7 5 + j10   V   − 2 − j 2 − 5 + j10 
 −1 1 1  1   
 + 0 V
 2  =  − 6 .
 7 7 − j8   V3   
 25 
 −1 1 1    + 6
 0 +   5 + j10 
5 + j10 5 + j10 9   
 
(8.65)
Solving,
 ( −26.6 + j14.33) V 
 V1   
  
 V2 = ( −31.7 + j 42.1) V . (8.66)

 V3   (34.7 + j 23.0 ) V 
   
These phasor voltages are indicated in the complex plane using the phasor diagram
in Figure 8.21.
Similar to the case of a DC circuit, all other circuit quantities may be found once
the node voltages have been determined. As two examples,
V2
IX = = ( −5.27 − j3.97 ) A (8.67)
− j8 Ω
and
V
IY = 3 = ( 3.85 + j 2.58 ) A. (8.68)
9Ω
If needed, we can also convert these phasors to polar form and transform to the time
domain, as shown in the previous section.
We can analyze special cases of the node voltage method in AC circuits in the
same manner as in DC circuits. As an example, consider the circuit in Figure 8.22.
This circuit has been redrawn in the phasor domain in Figure 8.23.
To do this, we note that the radial frequency of both sources is
ω = 800 rad/s, and j (800 rad/s )(10 mH ) = j8 Ω , j (800 rad/s )( 2 mH ) = j1.6 Ω, and
1 /  j (800 rad/s )(100 µF )  = − j12.5 Ω. For the representation of the sources in rect-
angular form, we note that ( 20 V ) ∠π / 2 = ( 0 + j 20 ) V and ( 50 V ) ∠0 = ( 50 + j 0 ) V.
FIGURE 8.21 Phasor diagram showing the node voltages of the circuit in Figure 8.19.
in the time domain.
in the phasor domain with the nodes labeled.
These phasor-domain quantities are shown in Figure 8.23, along with the labeling of
the nodes for use of the node voltage method. It can be seen that there are four essen-
tial nodes and two special cases: one known node voltage and one supernode. (Here,
this is true for any choice of the reference node!)
The node voltage equations in units of V, A, and Ω are
N 2 V2 = 50 + j 0; (known node voltage) (8.69)
and
V1 V − V2 V3 − V2 V3
N 13 + 1 + + = 0; (supernode). (8.70)
6 + j8 4 j1.6 2 − j12.5
The equation of the voltage source contained in the supernode is

VS V3 = V1 + j 20. (8.71)
Substituting the VS and N2 equations into the supernode equation,
V1 V − 50 V1 + j 20 − 50 V1 + j 20
N 2 N 13VS + 1 + + = 0. (8.72)
6 + j8 4 j1.6 2 − j12.5
 1 1 1 1   50 − j 20 + 50 − j 20 
N 2 N 13VS V1  + + +  = + + .
 6 + j8 4 j1.6 2 − j12.5   4 j1.6 2 − j12.5 
(8.73)
Solving,
V1 = ( 40.7 − j18.5) V (8.74)
and
V3 = V1 + j 20 V = ( 40.7 + j1.5) V. (8.75)
Similar to the case of a DC circuit, all other circuit quantities may be found once the
node voltages have been determined. As two examples,
V1 − V2
IA = = ( −2.31 − j 4.62 ) A (8.76)
4Ω
and
V3
IB = = ( 0.39 + j3.20 ) A. (8.77)
( 2 − j12.5) Ω
8.7 MESH ANALYSIS IN CIRCUITS WITH SINUSOIDAL EXCITATION

The mesh current method may be applied to AC circuits as well. Consider the circuit
in Figure 8.24, already rendered in the phasor domain, and with the meshes labeled
and numbered.
The mesh current equations in units of V, A, and Ω are
M 13 5 I1 + j3 I1 − j18 I1 + j 4 ( I1 − I 4 ) + 5 ( I 3 − I 4 )
(8.78)
+ 4 I 3 − j9 ( I 3 − I 2 ) + 7 ( I1 − I 2 ) = 0; (supermesh);
M2 I 2 = −1 − j 2 (known mesh current); (8.79)

FIGURE 8.24 Example AC circuit for application of the mesh current method, represented
in the phasor domain and with the meshes labeled.
and
M 4 5 ( I 4 − I 3 ) + j 4 ( I 4 − I1 ) − 25 + 3 I 4 − j12 I 4 = 0. (8.80)
The equation of the current source contained in the supermesh is
CS I 3 − I1 = 6. (8.81)
Substituting the CS and M2 equations into the others,
M 13 M 2CS 5 I1 + j3 I1 − j18 I1 + j 4 ( I1 − I 4 ) + 5 ( I1 + 6 − I 4 )
+ 4 ( I1 + 6 ) − j9 ( I1 + 6 ) − ( −1 − j 2 )  + 7  I1 − ( −1 − j 2 )  = 0;
(8.82)
M 4CS 5 [ I 4 − ( I1 + 6 )] + j 4 ( I 4 − I1 ) − 25 + 3 I 4 − j12 I 4 = 0. (8.83)
M 13 M 2CS I1 ( 21 − j 20 ) + I 4 ( −5 − j 4 ) = −79 + j 49 (8.84)
and
M 4CS I1 ( −5 − j 4 ) + I 4 (8 − j8 ) = 55 + j 0. (8.85)
In matrix form,
 21 − j 20 −5 − j 4   I1   −79 + j 49 
  = . (8.86)
 −5 − j 4 8 − j8   I 4   55 + j 0 
  
Solving,
I1 = ( −3.38 − j 0.0859 ) A; (8.87)
I 4 = ( 3.18 + j1.541) A; (8.88)

and
I 3 = I1 + 6 = ( 2.62 − j 0.0859 ) A. (8.89)
If needed, other phasor-domain and time-domain quantities may be determined from

these mesh currents using the methods previously shown.
To test your knowledge, try Quiz 8.2 in ebook+. To put your knowledge to prac-
tice, try Laboratory Exercise 8.1 in ebook+.
8.8 THEVENIN’S AND NORTON’S THEOREMS IN AC CIRCUITS

In this section, we will consider the use of Thevenin’s theorem, source transforma-
tions, and Norton’s theorem in circuits with sinusoidal excitation. It should become
clear that many of the considerations are the same as in DC circuits, although it is
necessary to use complex quantities; in an AC circuit, the Thevenin voltage is a com-
plex phasor and the Thevenin impedance is generally complex as well.
8.8.1 Thevenin’s Theorem
With respect to an AC circuit, Thevenin’s theorem states that for any two-terminal
network involving impedances and sources, there is a Thevenin equivalent network
involving a single voltage source VTh and a single impedance Z Th, as shown in Figure
8.25. Generally, both VTh and Z Th will be complex. The Thevenin circuit is externally
equivalent to the original circuit, in the sense that if we connect additional circuitry
to the two terminals a and b, the voltages and currents in this external circuitry will
be the same for the Thevenin equivalent as the original circuit. They are not inter-
nally equivalent, however. This means that we cannot use the Thevenin equivalent
circuit to directly find voltages and currents inside the original circuit.
If the two-terminal network contains independent sources, we may use the open-
circuit and short-circuit conditions to find the Thevenin equivalent circuit. The exter-
nally-equivalent networks should exhibit the same open-circuit voltage as shown in
Figure 8.26.
Therefore, the Thevenin voltage is equal to the open-circuit voltage for the origi-
nal circuit.
FIGURE 8.25 A network containing impedances and sources along with its Thevenin
equivalent.
FIGURE 8.26 The open-circuit condition for a network containing impedances and sources
along with its Thevenin equivalent.
VTh = VOC . (8.90)

The short-circuit current will also be equal for the two circuits as shown in
Figure 8.27, so
I SC = VTh / Z Th , (8.91)
and the Thevenin impedance may be found from
Z Th = VTh / I SC = VOC / I SC . (8.92)
We will see below that, in a two-terminal network containing only independent
sources, we may also find the Thevenin impedance by disabling the sources and
determining the equivalent impedance with respect to the terminals a and b. (We
will refer to this method as the “impedance shortcut.”)
Occasionally, the original circuit may contain no independent sources, either
because it contains only impedances or because the sources within it are all depen-
dent sources. If this is the case, both the open-circuit voltage and the short-circuit
current will be zero so we may not use their ratio to find the Thevenin resistance.
Instead, we can apply a test source as shown in Figure 8.28. We can use either a volt-
age test source or a current test source, if one is more convenient than the other. In
Figure 8.28, we show the application of a voltage test source of value VTest , and the
resulting current I Test is to be determined. We could also apply a current test source
of value I Test, and then find the resulting voltage VTest . Either way, a simple applica-
tion of KVL and Ohm’s law reveals that
Z Th = (VTest − VTh ) / I Test . (8.93)
FIGURE 8.27 The short-circuit condition for a network containing impedances and sources
along with its Thevenin equivalent.
FIGURE 8.28 The application of a test source to a circuit containing resistors and sources
as well as its Thevenin equivalent.
In a case for which the Thevenin voltage is zero, this simplifies to

Z Th = VTest / I Test . (8.94)
As an example, consider the two-terminal circuit in Figure 8.29. It contains only
independent sources, and we may use any two of the open-circuit, short-circuit, and
impedance shortcut analyses.
For the open-circuit analysis, we will use the labeling of nodes shown in Figure
8.30. Note that although the bottom node is not an essential node for the open-circuit
analysis, it will be an essential node for the short-circuit analysis. Hence, we use it as
the reference so we can keep the same labeling of nodes for both analyses.
V1 − V2 V1 − V2
N1 − 4 + + =0 (8.95)
j2 3 + j4
and
N2 +
(
V2 − V1 V2 − V1 V2 − 20 + j 20 3
+ = 0.
) (8.96)
j2 3 + j4 3

1 1   −1 −1 
N 1 V1  +  + V2  j 2 + 3 + j 4  = 4 (8.97)
 j 2 3 + j 4   
FIGURE 8.29 A two-terminal network containing only independent sources and impedances.
FIGURE 8.30 Open-circuit analysis of a two-terminal network containing only indepen-

dent sources and impedances.
and
 −1
N 2 V1  +
−1  1
+ V2  +
1 1
+ =
(
20 + j 20 3
.
) (8.98)

 j2 3 + j4   j2 3 + j4 3  3
In matrix form,
 1 1 −1 −1 
 + +   4 
j 2 3 + j4 j2 3 + j4   V1  =  

 −1 −1 1 1 1   V2   ( 20 + j20 3 ) . (8.99)
 + + +    3 
 j 2 3 + j4 j2 3 + j4 3   
Solving,
V1 = ( 33.1 + j 40.5) V (8.100)
and
V2 = ( 32.0 + j34.6 ) V. (8.101)
The open-circuit voltage may be found by the voltage-divider rule:
 3 
VOC = V1 +  (V2 − V1 ) = ( 29.9 + j38.9 ) V. (8.102)
 3 + j 4 
The short-circuit analysis can be done using the same labeling of nodes as shown in
Figure 8.31.
V1 − V2 V1
N1 − 4 + + =0 (8.103)
j2 3
and
N2 +
(
V2 − V1 V2 V2 − 20 + j 20 3
+ = 0.
) (8.104)
j2 j4 3
 1 1  −1 
N 1 V1  +  + V2   = 4 (8.105)
 j 2 3   j2 
FIGURE 8.31 Short-circuit analysis of a two-terminal network containing only indepen-

dent sources and impedances.
and
 −1  1
N 2 V1   + V2  +
1 1
+ =
20 + j 20 3
.
( ) (8.106)
 j2   j2 j4 3  3
In matrix form,
 1 1 −1 
 +   4 
j2 3 j2   V1  =  

 −1 1 1 1   V2   ( 20 + j20 3 ) . (8.107)
 + +    3 
 j2 j2 j4 3   
Solving,
V1 = (14.62 + j17.54 ) V (8.108)
and
V2 = ( 2.92 + j19.29 ) V. (8.109)
The short-circuit current may be found using KCL:
V1 V
I SC = + 2 = ( 9.69 + j5.12 ) A. (8.110)
3Ω j 4 Ω
Now, we can determine the Thevenin equivalent circuit:
VTh = VOC = ( 29.9 + j38.9 ) V (8.111)
and
VOC
Z Th = = ( 4.07 + j1.867 ) Ω. (8.112)
I SC
It is important to realize that the impedances for the reactive components ( j2 Ω and
j4 Ω) have been determined for a particular frequency; therefore, this Thevenin
equivalent circuit is only applicable at that frequency. In general, the impedances of
inductors and capacitors are frequency dependent so the Thevenin equivalent circuit
is frequency dependent.
Because the circuit contains no dependent sources, we may also use the
impedance shortcut analysis. To apply this, we disable the independent sources and
find the resulting equivalent impedance with respect to the terminals a and b. To dis-
able the sources, we replace the current source with an open and replace the voltage
source with a short, as shown in Figure 8.32.
The Thevenin impedance is the equivalent impedance “seen” looking into the
terminals a and b; it is
Z Th = 3 Ω + ( 3 + j 2 ) Ω  j 4 Ω = ( 4.07 + j1.867 ) Ω. (8.113)

FIGURE 8.32 Impedance shortcut analysis of a two-terminal network containing only

independent sources and impedances.
It should be noted that the impedance shortcut may not be used for a circuit contain-
ing mixed (dependent and independent) sources; this is because a dependent source
contributes to the Thevenin impedance. Fortunately, the open-circuit and short-cir-
cuit analyses may be used with mixed sources.
As a second example, consider the circuit in Figure 8.33, which contains a depen-
dent source but no independent sources.
The Thevenin voltage is necessarily zero, but to find the Thevenin impedance we
can apply a test source as shown in Figure 8.34. (The same approach is applicable
with two or more dependent sources, although the analysis may be more complicated.)
In units of V, A, and Ω, the node voltage equation is
V1 − VTest V1 V − 3v x
N1 + + 1 = 0, (8.114)
3 + j1 4 − j6 3
and the equation of the dependent source is
 4 
DS v x = V1  . (8.115)
 4 − j6 
Combining equations,
V1 − VTest V1 V  4 
N 1DS + + 1 − V1  = 0. (8.116)
3 + j1 4 − j6 3  4 − j6 
 1 1 1 4  VTest
N 1DS V1  + + − = . (8.117)
 3 + j1 4 − j6 3 4 − j6  3 + j1
FIGURE 8.33 Two-terminal circuit containing only a dependent source and impedances.
FIGURE 8.34 Test-source analysis of a two-terminal network containing only independent

sources and impedances.
Solving,
−1
VTest  1 3 1
N 1DS V1 =  − +  . (8.118)
3 + j1  3 + j1 4 − j6 3 
Now, we can find the test current:

−1
VTest − V1 VTest  1  1 3 1  
I Test = = 1 − − + . (8.119)
3 + j1 3 + j1  3 + j1  3 + j1 4 − j6 3  
 
The Thevenin impedance is therefore
−1 −1
V  1  1 3 1  
Z Th = Test = ( 3 + j1) 1 − − + 
I Test 3 + j1  3 + j1 4 − j6 3  
  (8.120)
= ( 3.79 + j3.66 ) Ω.
It should be recognized that the value of VTest cancels out in the final analysis; there-
fore, we may leave its value unspecified (as was done here), or we may choose a spe-
cific value in volts if it is convenient. Although the test-source analysis is not directly
applicable to a circuit containing mixed sources, we could disable the independent
sources and then apply a test source to the remaining network to find its Thevenin
impedance. Generally, though, this will be less convenient than the use of the open-
circuit and short-circuit analyses in such a case.
8.8.2 Source Transformations
A two-terminal network comprising a voltage source and a series impedance may be
transformed to a two-terminal network comprising a current source and a parallel
impedance, and these two will be externally equivalent as long as the open-circuit
voltage and short-circuit current are preserved by the transformation.
Referring to the top two networks in Figure 8.35, the open-circuit voltages of the
two are equal provided that VTh = I N Z N . The two short-circuit currents are equal if
VTh / Z Th = I N . These two conditions are satisfied if
VTh
IN = (8.121)
Z Th
and
Z N = Z Th . (8.122)
These equations allow us to transform from the circuit on the left (with the voltage
source) to the one on the right (containing the current source). By rearranging the
first equation, we can transform in the other direction as illustrated on the bottom of
Figure 8.35. As long as the two networks behave equivalently for the open-circuit and
short-circuit conditions, they will behave equivalently when connected to a network
of sources and impedances. The two are externally equivalent; that is, all external
voltages and currents will be unchanged by transforming from one to the other.
FIGURE 8.35 Source transformations.

8.8.3 Norton’s Theorem
With respect to an AC circuit, Norton’s theorem states that for any two-terminal net-
work involving impedances and sources, there is a Norton equivalent network involv-
ing a single current source I N and a parallel impedance Z N , as shown in Figure 8.36.
This follows directly from the use of Thevenin’s theorem and a source transforma-
tion. Therefore, the methods employed to determine the Norton equivalent are the
same as those used to find the Thevenin equivalent.
in ebook+.
8.9 SINUSOIDAL STEADY-STATE POWER

8.9.1 Instantaneous Power, Average Power, and Reactive Power
For an element in a circuit with sinusoidal excitation, such as that shown in Figure
8.37, the instantaneous power is p ( t ) = i ( t ) v ( t ). (The passive sign convention applies
the same way as in DC circuits.)
If v ( t ) = Vm cos (ω t + φv ) and i ( t ) = I m cos (ω t + φi ) , then
p ( t ) = Vm I m cos (ω t + φv ) cos (ω t + φi ) . (8.123)
If we shift the time reference by −φi / ω , then
p ( t ) = Vm I m cos (ω t + φv − φi ) cos (ω t ) . (8.124)
We can use the trigonometric identity for the product of two cosines:
1 1
cos α cos β = cos (α − β ) − cos (α + β ). Let α = ω t + φv − φi and β = ω t, yielding
2 2
FIGURE 8.36 A network containing impedances and sources along with its Norton
equivalent.
FIGURE 8.37 An element in a circuit with sinusoidal excitation.

Vm I m V I
p (t ) = cos (φv − φi ) + m m cos ( 2ω t + φv − φi ) . (8.125)
2 2
Next, we will use the identity cos (α + β ) = cos α cos β − sin α sin β ; let α = φv − φi
and β = 2ω t , yielding
Vm I m V I
p (t ) = cos (φv − φi ) + m m cos (φv − φi ) cos ( 2ω t )
2 2
(8.126)
V I
− m m sin (φv − φi ) sin ( 2ω t ) .
2
This may be rewritten in the simpler form
p ( t ) = P + P cos ( 2ω t ) − Q sin ( 2ω t ) , (8.127)
where
Vm I m
P= cos (φv − φi ) (8.128)
2
and
Vm I m
Q= sin (φv − φi ) . (8.129)
2
If we average the instantaneous power in (8.127) over any integral number of p eriods,
we obtain P; therefore, P represents the average power for the element under consid-
eration. Because we are using the passive sign convention, a positive value represents
power dissipated whereas a negative value shows power developed. The term involv-
ing Q averages to zero for any integral number of periods. We therefore refer to Q
as reactive power, because it is associated with reactive components of impedance
and it results from the component of current which is out of phase with the voltage.
Reactive power alters the instantaneous power and current, and these are important
effects which must be considered when rating components, interconnections, and
systems, but it represents the sloshing back and forth of power through energy stor-
age and release rather than the dissipation of power.
The cosine appearing in the average power is called the power factor, PF, and the
sine appearing in the reactive power is referred to as the reactive factor, RF:
PF = cos (φv − φi ) (8.130)

and
RF = sin (φv − φi ) . (8.131)
Because the cosine is an even function, the PF does not explicitly contain informa-
tion about the sign of (φv − φi ). However, it is customary to specify whether the PF
is leading or lagging. In the case of a lagging PF, the current lags the voltage and
(φv − φi ) > 0 . This represents a load with net inductive character. In the case of a lead-
ing PF, the current leads the voltage and (φv − φi ) < 0 . This represents the case of a
net capacitive load.
For efficient power delivery, it is desirable to maximize the PF (to unity if p ossible)
and minimize the RF (to zero if possible). In a large plant with many machines and
motors, the PF will tend to be lagging but may be corrected by banks of capacitors.
In a plant with many electronically-controlled furnaces, the PF may be leading and
could be corrected by installing an inductor bank.
8.9.2 Average Power and Root Mean Square

(rms) Values of Voltage or Current
If we apply a periodic voltage waveform v to a resistor, the average power P can be
found by integrating the instantaneous power p = v 2 / R over a period T of the voltage
waveform and dividing by the period:
1 T 2
1
T
1
T
v 2 v dt
V2 ∫
P=
T ∫ pdt = T ∫
0 0
R
dt = T 0
R
= rms ,
R
(8.132)
where Vrms is the root mean square (rms) voltage, also referred to as the effective
v oltage, and is given by
T
1 2
Vrms =
T ∫
v dt .
0
(8.133)
To find the root mean square value, we can remember “rms” and do the operations in
reverse order: we square the voltage, we take the mean, and then we take the root.
Now, consider the case of a sinusoidal waveform (which is arguably the most
important to us). Suppose the time-domain voltage is given by v ( t ) = Vm cos (ω t + φv ).
We may integrate over any time interval equal to the period:
t0 + T
1
Vrms =
T ∫V
t0
2
m cos2 (ω t + φv ) dt . (8.134)
If we choose t0 to offset the phase difference and shift the time reference,
T
1 t
T
1 1
Vrms =
T
0
∫
Vm2 cos2 (ω t ) dt = Vm  +
T  2 4ω
sin ( 2ω t )
0
. (8.135)
Because T = 2π / ω ,
1 1 T 1  4πω  1  V
Vrms = Vm = Vm  −0+ sin   − sin ( 0 ) = m . (8.136)
T T 2 4ω  ω 4ω  2
Therefore, the root mean square value of a sinusoidal voltage is equal to the
amplitude divided by the square root of two. A similar conclusion holds for a
sinusoidal current waveform.
8.9.3 Complex Power S
The average power in an element with sinusoidal excitation is
Vm I m V I
P= cos (φv − φi ) = m m cos (φv − φi )
2 2 2 (8.137)
= Vrms I rms cos (φv − φi ) ,
and the reactive power is

Vm I m V I
Q= sin (φv − φi ) = m m sin (φv − φi )
2 2 2 (8.138)
= Vrms I rms sin (φv − φi ) .
We can conveniently express both using a single complex quantity which we refer to
as the complex power S:
S = P + jQ = Vrms I rms cos (φv − φi ) + jVrms I rms sin (φv − φi )
= Vrms I rms exp (φv − φi ) = Vrms exp (φv ) I rms exp ( −φi ) (8.139)
= Vrms I rms
*
.
Therefore, the complex power for a two-terminal element may be determined by
multiplying the phasor voltage by the conjugate of the phasor current. It should
be recognized that the passive sign convention applies, so if either reference polarity
from Figure 8.37 were reversed it would be necessary to include a minus sign in the
complex power equation.
For an impedance, we can utilize Ohm’s law to develop another expression for the
complex power:
= ( ZI rms ) I rms = Z I rms = ( R + jX ) I rms .

2 2
S = Vrms I rms
* *
(8.140)
Hence,
2
P = R I rms (8.141)
and
2
Q = X I rms . (8.142)
If we display the complex power on the complex plane, the resulting right triangle
formed by dropping a vertical to the horizontal is referred to as the power triangle.
An example is shown in Figure 8.38. The length of the hypotenuse, S = P 2 + Q 2 ,
FIGURE 8.38 Complex power and power triangle for a load.
is referred to as the apparent power and is given by the product of the rms voltage
amplitude and rms current amplitude: S = Vrms I rms . The other two sides of the tri-
angle have lengths equal to P = Vrms I rms cos (φv − φi ) and Q = Vrms I rms sin (φv − φi ). In
the example shown, both P and Q are positive, representing a load with a lagging PF,
and the power triangle is in the first quadrant. For a load with a leading PF, the power
triangle would be in the fourth quadrant. The power triangle for a source developing
power would be in the third or fourth quadrant, depending on whether its load was
leading or lagging, respectively. The angle φv − φi is referred to as the power angle.
The apparent power, average power, and reactive power all have units of VA.
However, it is customary to distinguish between them by using VA for apparent
power, W for average power, and VARS (volt-amperes reactive) for the reactive
power.
It should be clear now that all complex power calculations involve rms values, and
we will not always explicitly use an “rms” subscript, although we will use the nota-
tions V ( rms ) and A ( rms ) for units. Other notations are used as well, so it is impor-
tant to always be aware of whether rms or amplitude values are being used.
As an example of complex power calculation, consider the circuit in Figure 8.39,
rendered in the phasor domain.
The phasor current is
V 120 ∠π / 4 V ( rms ) 120 ∠π / 4 V ( rms )
I= = = = 15∠π / 12 A ( rms ) . (8.143)
Z (
4 3 + j4 Ω ) 8∠π / 6 Ω
( )
The complex power for the 4 3 + j 4 Ω load is
S L = VI * = 120 ∠π / 4 V ( rms )  15∠ − π / 12 A ( rms ) 

(8.144)
= (1559 + j900 ) VA.
FIGURE 8.39 AC circuit for the determination of the complex power.
Therefore, for the load, the average power is 1559 W and the reactive power is
900 VARS.
The apparent power for this load is
S L = VI = (120 V ( rms ))(15 A ( rms )) = 1800 VA. (8.145)
This is also the length of the hypotenuse for the power triangle:
(1559 VA ) + (900 VA )
2 2
SL = P 2 + Q2 = = 1800 VA. (8.146)
The PF for the load is
PF = cos (φv − φi ) = cos ( π / 4 − π / 6 ) = 0.866 (lagging); (8.147)
and the RF for the load
RF = sin (φv − φi ) = sin ( π / 4 − π / 6 ) = 0.5. (8.148)
The apparent power for the source, using the passive sign convention, is
S S = −VI * = − 120 ∠π / 4 V ( rms )  15∠ − π / 12 A ( rms ) 

(8.149)
= ( −1559 − j900 ) VA.
Figure 8.40 shows the power triangles for the load and source in this example.
8.10 MAXIMUM POWER TRANSFER IN CIRCUITS

WITH SINUSOIDAL EXCITATION
As in the DC case, an important application of Thevenin’s theorem (or Norton’s theo-
rem) is in solving maximum power transfer problems. Suppose a load impedance Z L
is connected to a two-terminal network involving sources and impedances as shown
FIGURE 8.40 Power triangles for the load and source of the example circuit
on the left-hand side of Figure 8.41. We can represent the two-terminal network by
its Thevenin equivalent as shown on the right of this figure.
We want to know the maximum average power which can be delivered to the load,
and what value of load impedance will give rise to this maximum power transfer.
This problem can be easily solved using the Thevenin representation for the original
circuit.
In order to solve this problem, we recognize that Z Th = RTh + jX Th and Z L = RL + jX L .
In the following, it is assumed that the Thevenin voltage is an rms value, which will
give rise to an rms current. The load current may be found by Ohm’s law:
VTh
IL = . (8.150)
( RTh + RL ) + j ( X Th + X L )
The magnitude of the load current is
VTh
IL = , (8.151)
( RTh + RL )2 + ( X Th + X L )2
and the average power in the load is
2
2 VTh RL
PL = I L RL = . (8.152)
( RTh + RL )2 + ( X Th + X L )2
In order to maximize the average power in the load with respect to the load reactance,
we can take the partial derivative and set it to zero:
−2 ( X Th + X L ) VTh RL
2
∂ PL / ∂ X L = 2 = 0. (8.153)
( RTh + RL )2 + ( X Th + X L )2 
 
FIGURE 8.41 A load impedance connected to a two-terminal network represented by its

Thevenin equivalent.
This is true only if
X L = − X Th . (8.154)
Next, we can maximize the average power in the load with respect to the load resis-
tance, using the same approach:
( RTh + RL )2 + ( X Th + X L )2  VTh 2 −2 ( RTh + RL ) VTh RL

2
∂ PL / ∂ RL =  
2 − 2 = 0.
( RTh + RL )2 + ( X Th + X L )2  ( RTh + RL )2 + ( X Th + X L )2 
   
(8.155)
2
Multiplying through by ( RTh + RL ) + ( X Th + X L )  / VTh , we obtain
2 2 2
( RTh + RL )2 + ( X Th + X L )2 − 2 RL ( RTh + RL ) = 0. (8.156)
Expanding,
+ 2 RTh RL + RL2 + ( X Th + X L ) − 2 RL RTh − 2 RL2 = 0.

2 2
RTh (8.157)
Simplifying,
+ ( X Th + X L )
2
RL2 = RTh
2
(8.158)
and
+ ( X Th + X L ) .
2
RL = RTh
2
(8.159)
Therefore, the average power in the load is maximized if X L = − X Th and RL = RTh , or

Z L = Z Th
*
. (8.160)
In this ideal case, the average power in the load will be

2 2
VTh RL VTh
PL = 2 = . (8.161)
( RTh + RL ) + ( X Th + X L )
2
4 RL
If there are restrictions on the load impedance, then the load reactance should be set
as close as possible to − X L , and then the load resistance should be set as close as pos-
+ ( X Th + X L ) . For example, for the case in which the load impedance
2 2
sible to RTh
is restricted to be purely resistive (real, not complex), X L = 0 and the load resistance
should be chosen to be
RL = RTh
2
+ X Th
2
. (8.162)
As an example, consider the load connected to the two-terminal network shown in

Figure 8.42. We would like to find the value of the complex load impedance, which
will maximize the average power delivered to the load, and this value of power.
Second, we would like to find the purely-resistive load impedance, which will maxi-
mize the average power delivered to the load and the corresponding power.
We start by doing the open-circuit analysis with respect to the terminals where the
load impedance is to be connected as shown in Figure 8.43.
FIGURE 8.42 A load impedance connected to a two-terminal network for the consideration
of maximum power transfer.
FIGURE 8.43 Open-circuit analysis of a two-terminal network for the consideration of

N1
(
V1 − 40 3 + j 40 )+ V1 V1 − 80
+ = 0. (8.163)
2 + j3 − j6 7 + j 4
 1 1 1  40 3 + j 40 80
N 1 V1  + +  = + . (8.164)
 2 + j3 − j6 7 + j 4  2 + j3 7 + j4
Solving,
V1 = (110.6 − j3.30 ) V ( rms ) (8.165)
and by the voltage-divider rule,
 3 + j4 
VTh = VOC = (80 + j 0 ) V ( rms ) + V1 
 4 + 3 + j 4  (8.166)
= ( 98.2 + j5.65) V ( rms ) .
Next, we will consider the short-circuit analysis as depicted in Figure 8.44.

N1
(
V1 − 40 3 + j 40 )+ 1 V
+ 1 = 0. (8.167)
2 + j3 − j6 4
 1 1 1  40 3 + j 40
N 1 V1  + + = . (8.168)
 2 + j 3 − j 6 4 2 + j3
FIGURE 8.44 Short-circuit analysis of a two-terminal network for the consideration of

Solving,
V1 = ( 51.8 − j16.13) V ( rms ) . (8.169)
The short-circuit current is
V1 80 V ( rms )
I SC = + = ( 22.6 − j16.83) A ( rms ) . (8.170)
4 Ω (3 + j4 ) Ω
The Thevenin impedance is
VOC
Z Th = = ( 2.68 + j 2.25) Ω. (8.171)
I SC
If there are no restrictions on Z L, then the average power in the load is maximized
with Z L = Z Th
*
= ( 2.68 − j 2.25) Ω, and the value of average power in this load
impedance is
2 2
VTh RL VTh
PL = 2 = = 904 W. (8.172)
( RTh + RL ) + ( X Th + X L )
2
4 RL
If on the other hand Z L is restricted to be real, so that X L = 0 , then the average power
in the load is maximized with RL = RTh 2
+ X Th
2
= 3.50 Ω, and the average power in
the load with this impedance is
2
VTh RL
PL = = 784 W. (8.173)
( RTh + RL )2 + ( X Th )2
Figure 8.45 shows both cases; we can see that in the ideal case the average load power
peaks at 904 W with RL = 2.68 Ω, and in the restricted case the average power peaks
at 784 W with RL = 3.50 Ω.
8.11 THREE-PHASE CIRCUITS AND SYSTEMS

Power transmission and distribution is usually done using three-phase circuits and
systems, and the reason for this is efficiency. To see this, first consider the delivery
of AC power to three load impedances using three parallel single-phase systems (all
at a common phase angle) as shown in Figure 8.46. Six resistive transmission lines
are used, and it is assumed that they all have the same series resistance RS . Suppose
the voltages all have the same magnitude VM , and the load impedances all are equal:
Z A = Z B = ZC = Z . Then, the load currents are all equal, I A = I B = IC = I , and the
2
total power loss in the series resistances is Ploss = 6 I R.
Now consider the delivery of AC power to the same three load impedances using
a three-phase system as shown in Figure 8.47. Only a single return line is needed, so
a total of four resistive transmission lines is used, and they are assumed to each have
the same series resistance RS . The phases of the three voltage sources are chosen
so that the three return currents will cancel, and the summed current in the single
FIGURE 8.45 Average power in the load as a function of load resistance for the example
circuit of Figure 8.42, both for the ideal case (X L = − X Th ) and for the case in which the load
impedance is restricted to be real (X L = 0 ).
FIGURE 8.46 Delivery of power to three equal load impedances using resistive lines and
three single-phase systems.
FIGURE 8.47 Delivery of power to three equal load impedances using a three-phase system.
return wire is zero: I N = I A + I B + IC ≈ 0 . The voltages all have the same magni-
tude VM , though they are at different phases, the load impedances all are equal:
Z A = Z B = ZC = Z , and the load currents are all equal in magnitude though at dif-
ferent phases: I A = I B = IC = I . In this case, because of the elimination of the
power loss in the three return lines, the total power loss in the series resistances is
2
Ploss = 3 I R. Therefore, the power loss in the series wiring is halved compared to
the single-phase case, and this is significant. Typically, the power losses in the series
resistance amount to 3%, but would be twice this or 6% if single-phase power trans-
mission were used. In the United States, a 3% savings in power is enough to supply
all of New Jersey!
In the example considered here, the system was balanced, so the loss in the return
line was ideally zero. (In a balanced system, the voltage magnitudes are equal, the
source phases are spaced by 120°, and the load impedances are equal.) Although real
systems are never exactly balanced, they tend to be approximately balanced, and the
benefit in efficiency is nearly the same as for the balanced case.
8.11.1 Three-Phase Configurations
There are several possible configurations for a three-phase system because the
sources may be connected as a wye (Y) or delta (Δ), and similarly the loads may
be connected in a wye or a delta. Figure 8.48 displays two possible ways of draw-
ing a wye-connected source. Although the form in 8.48a more strongly resembles a
“wye,” the form on the left (also referred to as a “tee”) is often used in schematics
for convenience.
FIGURE 8.48 Two equivalent representations of a wye-connected source. (a) Closely

resembles a “wye” but the representation in (b) is often used for convenience. The representa-
tion in (b) is referred to as a “tee.”
Figure 8.49 displays three possible ways of drawing a delta-connected source.

Although the form in 8.49a most strongly resembles a “delta,” the other two forms are
often used for convenience. The representation in 8.49b is sometimes called a “pi.”
Four basic configurations for a three-phase system are the Y-Y, Y-Δ, Δ-Y, and
Δ-Δ, where the first symbol refers to the source and the second refers to the load.
These four configurations are shown in Figure 8.50. It is important to note that a
ground (neutral) connection is only available in a wye, and only in the Y-Y configura-
tion is it possible to connect the neutral points of the source and load.
The positive phase sequence normally used is A-B-C; so phase A leads
phase B and phase B leads phase C. Each phase difference is 2π / 3, or 120°, and
phase A is our reference. Hence, VB lags VA by 120°, and VC lags VB by 120°.
This is shown in Figure 8.51. The phase angle for VC may be expressed equiva-
lently as −240° or 120°, but the latter is more commonly used. For the example
shown, VM = 120 V ( rms ) , and the three phase voltages are VA = 120 ∠0° V ( rms ),
VB = 120 ∠ − 120° V ( rms ), and VC = 120 ∠120° V ( rms ). VA , VB , and VC are referred
to as the “phase voltages” because they appear across one of the circuit elements
(in this case, sources). The line voltages may be determined by Kirchhoff’s
law. Thus, VAB = VA − VB = 3VM ∠30° , VBC = VB − VC = 3VM ∠ − 90°, and
VCA = VC − VA = 3VM ∠150° , as shown in Figure 8.51. These are called line volt-
ages because they exist between two lines. Hence, in a wye connection of sources,
the line voltages are larger in magnitude than the phase voltages by a factor of 3.
Figure 8.52 shows the positive phase sequence for a delta-connected source. Here,
VBC lags VAB by 120°, and VCA lags VBC by 120°. Phase angles are referenced with respect
to VAB. For the example shown, VM = 208 V ( rms ), and the three phase voltages are
VAB = 208∠0° V ( rms ), VBC = 208∠ − 120° V ( rms ), and VCA = 208∠120° V ( rms ).
FIGURE 8.49 Three equivalent representations of a delta-connected source. (a) Closely

resembles a “delta” but the other two are often used for convenience. The representation in
(b) is sometimes referred to as a “pi.” (c) is another convenient representation which avoids
angled elements.
FIGURE 8.50 Four basic configurations for a three-phase system. (a) Y-Y; (b) Y-Δ; (c) Δ-Y;
and (d) Δ-Δ.
FIGURE 8.51 The positive phase sequence in a wye-connected source.
FIGURE 8.52 The positive phase sequence in a delta-connected source.
VAB, VBC , and VCA are referred to as the “phase voltages” because they appear across
one of the sources. The line voltages are equal to the phase voltages in the case of a
delta connection, because each source is connected between two lines.
8.11.2 Balanced Wye–Wye System

Consider the balanced wye–wye system shown in Figure 8.53. It is balanced because
the three sources have the same magnitude, the source phases are spaced by 120° as
dictated by the positive phase sequence, and each phase experiences the same total
impedance. Here, (1 + j 0.75) Ω represents the Thevenin impedance for each source,
0.5 Ω represents the wiring resistance for each line, and ( 24 + j6 ) Ω represents the
impedance for each load.
FIGURE 8.53 Balanced wye–wye system.
Because the system is balanced, zero voltage will develop at the neutral point of
the load, and zero current will flow in the neutral line. We can show this by use of the
node voltage method with the nodes labeled as shown in Figure 8.54. (The mesh cur-
rent method could also be used, but this would involve three meshes and three equa-
tions instead of two essential nodes and one equation in the node voltage method.)
v n − VA v n − VB v n − VC v
N1 + + + n = 0. (8.174)
25.5 + j6.75 25.5 + j6.75 25.5 + j6.75 0.5

 3 1  VA + VB + VC
N1 vn  + = . (8.175)
 25.5 + j6.75 0.5  25.5 + j6.75
Solving,
−1
V + VB + VC  3 1 
vn = A +
25.5 + j6.75  25.5 + j6.75 0.5 

(120 )V ( rms ) + (120 cos ( −120°) + j120 sin ( −120°)) V ( rms )

+ (120 cos (120° ) + j120 sin (120° )) V ( rms )
= (8.176)
25.5 + j 6.75
−1
 3 1 
× +  = 0.
 25.5 + j 6.75 0.5 
FIGURE 8.54 Node voltage analysis of a balanced wye–wye system.
Therefore, in the balanced wye–wye system, zero voltage develops at the neutral
point because the three source voltages add to zero and their contributions are
equally weighted in the balanced circuit. Because of this, determination of the line
currents is simplified.
I A′ a =
(120 + j 0 ) V ( rms )
( 25.5 + j6.75) Ω (8.177)
= ( 4.40 − j1.164 ) A ( rms ) = 4.55∠ − 14.8° A ( rms ) ,
I B'b =
(120 cos ( −120°) + j120 sin ( −120°)) V ( rms )
( 25.5 + j6.75) Ω (8.178)
= ( −3.21 − j3.23) A ( rms ) = 4.55∠ − 134.8° A ( rms ) ,
IC'c =
(120 cos (120°) + j120 sin (120°)) V ( rms )
( 25.5 + j6.75) Ω (8.179)
= ( −1.191 + j 4.39 ) A ( rms ) = 4.55∠105.2° A ( rms ) .
The phasor voltages and currents are shown in Figure 8.55. It can be seen that the line
currents have a similar phase relationship to the phase voltages; that is, I Bb lags I Aa
by 120° and ICc lags I Bb by 120°.
8.11.3 Balanced Delta–Delta System

Consider the balanced delta–delta system shown in Figure 8.56. Here, 0.5 Ω repre-
sents the Thevenin impedance for each source, 0.25 Ω represents the wiring resis-
tance for each line, and ( 20 + j 4 ) Ω represents the impedance for each load.
FIGURE 8.55 Phasor diagrams for a balanced wye–wye system.
FIGURE 8.56 Balanced delta–delta system.
This system may be solved using the mesh current method with the meshes
labeled as shown in Figure 8.57. (The node voltage method could also be used, but
this involves six essential nodes and five equations, whereas the mesh current method
involves four meshes and four equations.)
In units of V, A, and Ω, the mesh current equations are
M 1 VCA + 0.5 I1 + 0.5 ( I1 − I 2 ) + VAB + 0.5 ( I1 − I 3 ) + VBC = 0, (8.180)
M 2 − VAB + 0.5 ( I 2 − I1 ) + 0.25 I 2 + ( 20 + j 4 ) ( I 2 − I 4 ) + 0.25 ( I 2 − I 3 ) = 0, (8.181)
M 3 − VBC + 0.5 ( I 3 − I1 ) + 0.25 ( I 3 − I 2 ) + ( 20 + j 4 ) ( I 3 − I 4 ) + 0.25 I 3 = 0, (8.182)

FIGURE 8.57 Mesh current analysis of a balanced delta–delta system.
and
M4 ( 20 + j 4 ) ( I4 − I2 ) + ( 20 + j 4 ) I4 + ( 20 + j 4 ) ( I4 − I3 ) = 0. (8.183)
M 1 I1 [1.5] + I 2 [ −0.5] + I 3 [ −0.5] = −VAB − VBC − VCA , (8.184)
M2 I1 [ −0.5] + I 2 [ 21 + j 4 ] + I 3 [ −0.25] + I 4 [ −20 − j 4 ] = VAB , (8.185)
M 3 I1 [ −0.5] + I 2 [ −0.25] + I 3 [ 21 + j 4 ] + I 4 [ −20 − j 4 ] = VBC , (8.186)

and
M4 I 2 [ −20 − j 4 ] + I3 [ −20 − j 4 ] + I 4 [ 60 + j12 ] = 0. (8.187)
In matrix form,
 −0.5 −0.5    
 1.5 0  I1 −VAB − VBC − VCA
  
 −0.5 21 + j 4 −0.25 −20 − j 4  I2   VAB 
  = 
 −0.5 −0.25 21 + j 4 −20 − j 4  I3   VBC 
 −20 − j 4    
 0 −20 − j 4 60 + j12 I4 0
    
−0.5    
0.5 0  I1 −VAB − VBC − VCA
  
+ j4 −0.25 −20 − j 4
 I2   VAB 
 = .
.25 21 + j 4 −20 − j 4  I3   VBC 
− j4    
−20 − j 4 60 + j12   I4   0 
  (8.188)
Solving,
 
 I1   (3.19 − j9.08) A ( rms ) 
   
 I2   (12.63 − j10.86) A ( rms ) 
 = . (8.189)


I3  
 
( −3.08 − j16.38) A ( rms ) 
I4 
   ( 3.19 − j9.08) A ( rms ) 
 
The line currents are
 (12.64 − j10.86) A ( rms )   16.66∠ − 40.7° A ( rms ) 

 I A'a    
   
 I B'b = ( −15.72 − j5.52) A ( rms )  =  16.66∠ − 160.7° A ( rms ) ,
  
 IC'c   ( 3.08 + j16.37) A ( rms )   16.66∠79.3° A ( rms )
     
(8.190)
and the phase currents are
 (9.45 − j1.779) A ( rms )   9.62∠ − 10.7° A ( rms ) 

 I ab    
   
 Ibc = ( −6.27 − j 7.30 ) A ( rms )  =  9.62∠ − 130.7 A ( rms ) . (8.191)
  
 I ca   ( −3.19 + j9.08) A ( rms )   9.62∠109.3° A ( rms )
     
Figure 8.58 shows the phase voltages, line currents, and phase currents on phasor
diagrams. It can be seen that the line currents all exhibit the same magnitude and the
same phase relationship as the phase voltages; that is, I B'b lags I A'a by 120° and IC'c
lags I B'b by 120°. The phase currents all have equal magnitude, but this magnitude is
1 / 3 times the magnitude of the line currents. Also, the phase currents exhibit the
same phase relationship as the phase voltages; Ibc lags I ab by 120° and I ca lags Ibc by
120°.
FIGURE 8.58 Phasor diagrams for a balanced delta–delta system.

8.11.4 Unbalanced Three-Phase System

Any unbalanced three-phase system may be analyzed using either the node voltage
method or the mesh current method. As one example consider the wye–wye system
shown in Figure 8.59. This system is unbalanced because the three load impedances
are not equal, and therefore a non-zero voltage will develop at the neutral point of
the load.
The non-zero voltage at the neutral point of the load may be found by the node
voltage method, as shown in Figure 8.60, and once this voltage is known the line cur-
rents may be readily determined.
FIGURE 8.59 Unbalanced wye–wye system.
FIGURE 8.60 Node voltage analysis of an unbalanced wye–wye system.


v n − VA v n − VB v n − VC v
N1 + + + n = 0. (8.192)
29.5 + j5.75 25.5 + j6.75 21.5 + j 7.75 0.5
 1 1 1 1  VA VB VC
N1 vn  + + +  = + +
 29.5 + j5.75 25.5 + j6.75 21.5 + j 7.75 0.5  29.5 + j5.75 25.5 + j6.75 21.5 +
1 1  VA VB VC
+ + = + + .
j 7.75 0.5  29.5 + j5.75 25.5 + j6.75 21.5 + j 7.75 (8.193)
6.75 21.5 +
Solving,
v n = ( −0.1104 + j 0.556 ) V ( rms ) . (8.194)
Notice that even though this is an unbalanced system only a small voltage develops
at the neutral point of the load because a line has been run between the two neutrals.
The line currents are
VA − v n
I A′ a = = ( 3.92 − j 0.783) A ( rms )
( 29.5 + j5.75) Ω (8.195)
= 4.00 ∠ − 11.3° A ( rms ) ,
VB − v n
I B ′b = = ( −3.21 − j3.25) A ( rms )
( 29.5 + j5.75) Ω (8.197)
= 4.56∠ − 134.6° A ( rms ) ,
and
VA − v n
IC ′c = = ( −0.932 + j5.14 ) A ( rms )
( 25.5 + j6.75) Ω (8.198)
= 5.23∠100.3° A ( rms ) .
These line currents (which are the same as the phase currents for the wye load) are
different in magnitude and do not retain the phase relationship of the source voltages
because of the imbalance in impedances. This gives rise to a current in the neutral
line:
I Nn = − I A'a − I B'b − IC'c = ( 0.221 − j1.113) A ( rms ) . (8.199)
Note, however, that this is much smaller in magnitude than the line currents.
The phase voltages at the load may be found by use of KVL:
Van = v n + I A′a ( 28 + j5) Ω
(8.200)
= (113.5 − j1.765) V ( rms ) = 113.5∠ − 0.9° V ( rms ) ,
Vbn = v n + I B ′b ( 24 + j6 ) Ω
(8.201)
= ( −57.6 − j96.6 ) V ( rms ) = 112.5∠ − 120.8° V ( rms ) ,
and
Vcn = v n + IC ′c ( 20 + j 7 ) Ω
(8.202)
= ( −54.7 + j96.9 ) V ( rms ) = 111.3∠119.5° V ( rms ) .
Similarly, the line voltages are

Vab = Van − Vbn
(8.203)
= (171.2 + j94.9 ) V ( rms ) = 195.7∠29.0° V ( rms ) ,
Vbc = Vbn − Vcn
(8.204)
= ( −2.87 − j193.6 ) V ( rms ) = 193.6∠ − 90.8° V ( rms ) ,
and
Vca = Vcn − Van
(8.205)
= ( −168.3 + j98.7 ) V ( rms ) = 195.1∠149.6° V ( rms ) .
The phasor diagrams of Figure 8.61 show the line voltages, the phase voltages, and
the line currents (same as the phase currents). The expected symmetry of a balanced
system is not preserved exactly, but holds approximately.
8.12 MUTUAL INDUCTANCE AND TRANSFORMERS

8.12.1 Fundamental Considerations
We saw in Chapter 6 that when a coil of wire produces magnetic flux which links that
same coil, there is a self-inductance, and by the Faraday law a voltage Ldi / dt is devel-
oped when the current changes with time. Here, we will examine the self-inductance
FIGURE 8.61 Phasor diagrams for an unbalanced wye–wye system.

in more detail and then extend those ideas to the situation involving two coils linked
by some common magnetic flux (a transformer with mutual inductance M ).
Consider a single coil wrapped on a core of magnetic medium as shown in
Figure 8.62.
If the magnetic medium is linear, then the magnetic flux φ (in Wb) is given by
φ = AB = Aµ H = Aµ Ni = Ni, (8.206)
where A is the cross-sectional area (m2), B is the flux density (Wb/m2), µ is the per-
meability of the medium (Wbm−2A−1), N is the number of turns in the coil, i is the
current in the coil, and  is the permeance of the core (Wb/A). By the Faraday law,
dλ d ( Nφ ) d di di
v= = = N ( Ni ) = N 2 = L , (8.207)
dt dt dt dt dt
where λ = Nφ is the flux linkage (Wb) and L is the self-inductance (H). Now c onsider
the case of two magnetically-couple coils on the same magnetic core as shown in
Figure 8.63. A voltage v1 is applied to the primary (input) coil, resulting in a current
i1. The secondary (output) coil is open-circuited, so no current flows in it, but there is
an induced voltage v2 .
The flow of current in the primary gives rise to a total magnetic flux φ1 = φ11 + φ12,
where φ12 is the portion of the flux linking both coils and φ11 is the portion of the flux
which links only the primary. The permeance 1 = 11 + 12 likewise has two compo-
nents associated with the two components of flux. By the Faraday law, the primary
voltage is
dλ1 d ( N1φ1 ) d d
v1 = = = N1 (φ11 + φ12 ) = N1 ( N111i1 + N112i1 )
dt dt dt dt
(8.208)
di di di
= N ( 11 + 12 ) 1 = N121 1 = L1 1 .
2
1
dt dt dt
FIGURE 8.62 A coil of wire wrapped on a core of magnetic medium.

FIGURE 8.63 Two magnetically-coupled coils on a single core.
Similarly, the voltage induced in the secondary is
dλ2 d ( N 2φ21 ) d di di
v2 = = = N 2 ( N 212i1 ) = N1N 212 1 = M12 1 , (8.209)
dt dt dt dt dt
where M12 is the mutual inductance (H) associated with flux created by the primary
and linking the secondary. If 21 = 12 then M 21 = M12 = M and we can use a single
value of mutual inductance without subscripts. It can be shown that the secondary
coil has its own self-inductance L2 and that
M = k L1L2 , (8.210)
where k is the coefficient of coupling, and 0 ≤ k ≤ 1. Thus, M ≤ L1L2 .
8.12.2 The Dot Convention for Polarities

When solving circuits that contain magnetically-coupled coils (transformers),
a system of dots is used so that the polarities of mutual inductance terms may be
determined unambiguously. The placement of these dots is dictated by the physical
construction of the transformer, and the process for finding the dot placements may
be understood with the aid of Figure 8.64.
The process starts by arbitrarily placing a dot on one terminal of the primary coil;
we will place this dot on the top terminal. Second, we flow current i1 into this dotted
terminal and use the right-hand rule to find the direction of the resulting flux φ1 in
the core. In this case, it is clockwise as shown in the figure. Third, we flow current
i2 into either terminal of the secondary and find the resulting flux in the core by the
right-hand rule. Here, we flow current into the top terminal of the secondary and
this results in clockwise flux φ2 . Finally, if the flux directions for φ1 and φ2 are the
same, we dot the terminal where i2 enters. In this case, we dot the top terminal of the
secondary, so both top terminals are dotted. Now we know that if di1 / dt is positive,
FIGURE 8.64 The dot convention and determination of dot placement.
inducing a positive value of v1 (positive at the dot) by way of the self-inductance,

it will also induce a positive value of v2 (positive at the dot) by way of the mutual
inductance.
To further explore the application of the dot convention in finding polarities of
voltage terms in a circuit containing a transformer, refer to Figure 8.65.
The primary voltage is given by
di1 di
v1 = L1 −M 2. (8.211)
dt dt
The sign of the mutual inductance term comes about because if di2 / dt is positive it
induces a self-inductance component of v2 which is negative at the secondary dot and
also produces a mutual inductance component of v1 which is negative at the primary
dot. This is therefore a negative contribution to v1. By similar reasoning, the second-
ary voltage is given by
di2 di
v 2 = − L2 +M 1. (8.212)
dt dt
The time-domain mesh currents are therefore
di1 di di
M 1 − vs + Rsi1 + Ls + L1 1 − M 2 = 0 (8.213)
dt dt dt
and
di2 di di
M 2 L2 − M 1 + Rsi1 + Ls 1 = 0. (8.214)
dt dt dt
Often the dots may be omitted from a transformer, and then it can be assumed that
they are both on the top terminals (or equivalently, both on the bottom terminals).
FIGURE 8.65 Use of the dot convention to determine voltage polarities.
8.12.3 The Linear Transformer in the Phasor Domain

Although the previous section used time-domain mesh equations (differential equa-
tions) to illustrate the use of the dot convention, we will normally apply impedance
and phasor concepts for the AC steady-state analysis of circuits involving transform-
ers using algebraic equations. Figure 8.66 illustrates a phasor-domain representa-
tion of a linear transformer circuit, in which the time-domain self-inductances and
mutual inductance have been replaced by jω L1, jω L2, and jω M .
For this circuit, the mesh equations are
M 1 − Vs + Z s I1 + R1 I1 + jω L1 I1 − jω MI 2 = 0 (8.215)
and
M 2 − jω MI1 + jω L1 I 2 + R2 I 2 + Z L I 2 = 0. (8.216)
 Z + R + jω L − jω M  I   V 
 s 1 1
 1  =  s . (8.217)
 − jω M jω L1 + R2 + Z L  I 
   2   0 
Solving,
Vs − jω M
0 jω L1 + R2 + Z L Vs ( jω L1 + R2 + Z L )
I1 = =
Z s + R1 + jω L1 − jω M ( Z s + R1 + jω L1 ) (ω L1 + R2 + Z L ) + ω 2 M
− jω M jω L1 + R2 + Z L
(8.218)
FIGURE 8.66 A linear transformer circuit rendered in the phasor domain.
and
Z s + R1 + jω L1 Vs
− jω M 0 jω MVs
I2 = = .
Z s + R1 + jω L1 − jω M ( Z s + R1 + jω L1 ) (ω L1 + R2 + Z L ) + ω 2 M
− jω M jω L1 + R2 + Z L
(8.219)
As a specific example, consider the linear transformer circuit of Figure 8.67.
The mesh equations, in units of A, V, and Ω, are
M 1 − 50 + ( 4 + j 2 ) I1 + 30 I1 + j900 I1 − j50 I 2 = 0 (8.220)

and
M 2 − j50 I1 + j10 I 2 + 3 I 2 + ( 20 + j3) I 2 = 0. (8.221)
 34 + j900 − j50   I1   50 
  = . (8.222)
 − j50 23 + j13   I 2   0 

Solving,
I1 = ( 7.8 + j57.5) mA ( rms ) (8.223)
and
I 2 = (102.1 − j 40.6 ) mA ( rms ) . (8.224)
FIGURE 8.67 An example linear transformer circuit.
8.12.4 The Ideal Transformer

Often an ideal transformer model may be used to analyze transformer circuits with
satisfactory accuracy. The three attributes of an ideal transformer are the following:
(i) the coupling coefficient is unity, so that M = L1L2 ; (ii) the self-inductances are
infinite; and (iii) the coil losses due to resistance are negligible. Therefore for an
ideal transformer such as the one shown in Figure 8.68, there is no need to specify
the self or mutual inductances, and instead we specify the turns ratio, which may be
expressed in the form N1 : N 2 or as a voltage ratio V1 : V2 .
Using the reference polarities and dot placement in Figure 8.68, the basic relation-
ships for the ideal transformer are
V1 N1
= (8.225)
V2 N 2
and
N1 I1 = − N 2 I 2 . (8.226)
Combining these, we see that
V1 I1
= V I . (8.227)
22
primary volt amperes secondary volt amperes
Therefore, a transformer which steps up the voltage will step down the current, and
vice versa.
Consider the general case of a source with series impedance Z S driving a load
with impedance Z L through an ideal transformer with a turns ratio N1 : N 2, as shown
in Figure 8.69.
The mesh equations are
M 1 − VS + Z S I1 + V1 = 0 (8.228)
and
M 2 − V2 + Z 2 I 2 = 0. (8.229)
But
2
N  N  N  N  N 
V1 =  1  V2 =  1  Z L I 2 =  1  Z L  1  I1 =  1  Z L I1 . (8.230)
 N2   N2   N2   N2   N2 
FIGURE 8.68 Ideal transformer.
FIGURE 8.69 Use of an ideal transformer to drive a load impedance.
Substituting this into the M1 equation,
N  N 
M 1 − VS + Z S I1 +  1  Z L  1  I1 = 0, (8.231)
 N2   N2 
and solving,
VS
I1 = 2 . (8.232)
N 
ZS +  1  ZL
 N2 
Therefore, the apparent load impedance seen looking into the primary side of the
transformer is ( N1 / N 2 ) Z L , and therefore an interesting function of the transformer
2
is that of impedance matching. An example would be a case where maximum power

transfer is desired but practical constraints make it impossible to match the load to
the Thevenin impedance of the source.
As a specific example, consider the ideal transformer circuit in Figure 8.70.
The primary current is
FIGURE 8.70 An example ideal transformer circuit.
I1 =
VS
=
( 4800 + j 0 ) V ( rms )
N 
2
( 20 + j 4 ) Ω + ( N1 / N 2 )2 (10 + j6) Ω
ZS +  1  ZL (8.233)
 N2 
= ( 0.1411 − j 0.0846 ) A ( rms ) ,
and the secondary current is

I 2 = I1 ( N1 / N 2 ) = ( 7.06 − j 4.23) A ( rms ) . (8.234)
The primary voltage is

V1 = VS − I1 Z S = ( 4797 + j 0.113) V ( rms ) , (8.235)
and the secondary voltage is

V2 = V1 ( N 2 / N1 ) = ( 95.9 + j 0.023) V ( rms ) . (8.236)
The complex power for the source is
SS = −VS I1* = ( −677.3 − j 406.2 ) VA, (8.237)
so the source develops 677.3 W average power.

The complex power for the load is
S L = V2 I 2* = ( −676.8 − j 406.0 ) VA, (8.238)
so 99.9% of the average power developed by the source is delivered to the load. This
high efficiency is possible despite the relatively large magnitude of source impedance
because of the action of the transformer.
8.13 SUMMARY
In a circuit driven by one or more sinusoidal sources with a particular frequency, we
may use AC steady-state analysis to determine the voltages and currents. The volt-
ages and currents are all sinusoidal with the same frequency as the source(s) so we
only need to find their magnitudes and phases. In order to avoid the need to solve dif-
ferential equations in the time domain, we transform to the phasor domain. Passive
components are replaced with complex impedances; the impedance of a resistor is R,
the impedance of an inductor is jω L, and the impedance of a capacitor is 1 / ( jω C ).
The real part of an impedance Z is a resistance R and the imaginary part is j times a
reactance X, so that in general Z = R + jX . Impedances combine in series and paral-
lel like resistances. Voltages and currents are treated as complex phasors. The pha-
sor has a magnitude and a phase, which corresponds to the magnitude and phase
in the time domain. A phasor may be expressed in polar or rectangular form and
may be plotted visually on the complex plane in a phasor diagram. In the phasor
domain, Ohm’s law and Kirchhoff’s laws apply. Therefore, we may use the node volt-
age method, the mesh current method, the current-divider rule, the voltage-divider
rule, and Thevenin’s and Norton’s theorems in the phasor domain for AC steady-state
analysis.
The instantaneous power for an element in a circuit with sinusoidal excitation is
sinusoidal with a frequency twice the frequency of the source(s). Of more interest
than the instantaneous power are the average power P and the reactive power Q.
The complex power S embodies both quantities: S = P + jQ . To find the complex
power for an element, we multiply the phasor voltage by the conjugate of the current:
S = VI * . For this calculation, both the current and the voltage should be in root mean
square (rms) form, and the passive sign convention should be applied to determine
whether a minus sign should be applied in the complex power equation.
For maximum power transfer from a two-terminal network to a load impedance,
the load impedance should be set to the conjugate of the Thevenin impedance for
the two-terminal network. If there are constraints on Z L = RL + jX L which make this
impossible, then the load reactance should be set as close as possible to − X Th , and
+ ( X L + X Th ) .
2 2
then the load resistance should be set as close as possible to RTh
Three-phase circuits and systems are commonly used for power transmission
and distribution. They make use of three sinusoidal sources at 120° intervals, which
decreases transmission losses significantly and improves efficiency. Sources and
loads may be connected in wye or delta configurations, leading to four basic combi-
nations. Other configurations are possible if transformers are connected to the source
or the load. Three-phase systems may be analyzed using mesh or nodal analysis.
Transformers utilize two or more coils which are magnetically coupled to step
up or step down a voltage using the mutual inductance between the coils. In a linear
transformer, the mutual inductance is used in the time or phasor domain to write
mesh equations. For an ideal transformer, only the turns ratio of the transformer is
used to find approximate currents and voltages. In either case, mesh analysis is pre-
ferred and nodal analysis may be cumbersome.
To evaluate your mastery of chapter eight, solve Example Exam 8.1 in ebook+ or
Example Exam 8.2 in ebook+.
PROBLEMS
Problem 8.1. Find the time-domain currents iL ( t ), iR ( t ), and iC ( t ) of the cir-
cuit in Figure P8.1, and plot them together as functions of time with the time
interval from zero to 50 ms. Assume the circuit operates under sinusoidal
steady-state conditions.
FIGURE P8.1 Parallel circuit with sinusoidal excitation
Problem 8.2. Find the time-domain voltages v A ( t ), v B ( t ), and vC ( t ) in the

diagram of Figure P8.2. Determine the associated phasor-domain voltages
VA, VB , and VC and plot these on a phasor diagram. Assume the circuit oper-
ates under sinusoidal steady-state conditions.
FIGURE P8.2 Circuit with sinusoidal excitation and two meshes.

Problem 8.3. Find the time-domain currents iX ( t ), iY ( t ), and iZ ( t ) in the dia-

gram of Figure P8.3. Determine the associated phasor-domain voltages I X ,
IY , and I Z and plot these on a phasor diagram. Assume the circuit operates
under sinusoidal steady-state conditions.
FIGURE P8.3 Circuit with sinusoidal excitation and four meshes.
Problem 8.4. For the network in Figure P8.4, calculate the complex imped-
ance Z ab with respect to the terminals a and b at a radial frequency of
10, 000 rad/s. Also find the complex admittance Yab at this same frequency.
FIGURE P8.4 Two-terminal network involving three reactive elements and three
resistances.
Problem 8.5. For the network in Figure P8.5, find the complex impedance
Z ab as a function of radial frequency. Plot the real and imaginary parts of
this impedance, both as functions of the radial frequency, for the frequency
range from 10 2 rad/s to 10 5 rad/s .
FIGURE P8.5 Two-terminal network involving two reactive elements and two resistances.
Problem 8.6. For the network in Figure P8.6, find the complex impedance
Z ab as a function of the capacitance C, assuming ω = 5000 rad/s. Plot the
real and imaginary parts of this impedance, both as a function of the capaci-
tance C, choosing an appropriate range of this capacitance. Is there a value
of the capacitance C which makes the impedance real? If so, what is the
value of capacitance and the resulting impedance?
FIGURE P8.6 Two-terminal network involving reactive elements and resistances in two
meshes.
Problem 8.7. For the circuit in Figure P8.7, determine the phasor voltages
V1, V2 , and V3 with respect to ground. Assume the circuit operates under
sinusoidal steady-state conditions.
FIGURE P8.7 Phasor-domain AC circuit with single source, three reactive elements, and
four resistors.
Problem 8.8. For the circuit in Figure P8.8, find the phasor voltages VA,
VB , and VC . Assume the circuit operates under sinusoidal steady-state
conditions.
FIGURE P8.8 Phasor-domain AC circuit with two sources, three reactive elements, and
four resistors.
Problem 8.9. Find the phasor currents I A, I B, and IC of the circuit shown
in Figure P8.9. Assume the circuit operates under sinusoidal steady-state
conditions.
FIGURE P8.9 Phasor-domain AC circuit with two sources, two reactive elements, and three
resistors.
Problem 8.10. For the circuit shown in Figure P8.10, determine the pha-
sor voltages VA, VB , and VC . Assume the circuit operates under sinusoidal
steady-state conditions.
FIGURE P8.10 Phasor-domain AC circuit with five essential nodes and two special cases
for the node voltage method.
Problem 8.11. Find the phasor currents I A and I B of the circuit shown in
Figure P8.11. Assume the circuit operates under sinusoidal steady-state
conditions.
FIGURE P8.11 Phasor-domain AC circuit with three meshes and two special cases for the
mesh current method.
Problem 8.12. For the circuit shown in Figure P8.12, determine the phasor
voltages V1, V2 , and V3. Assume the circuit operates under sinusoidal steady-
state conditions.
FIGURE P8.12 Phasor-domain AC circuit with four meshes and two special cases for the
mesh current method.
Problem 8.13. Find the phasor currents I X , IY , and I Z of the circuit shown
in Figure P8.13. Assume the circuit operates under sinusoidal steady-state
conditions.
FIGURE P8.13 P
hasor-domain AC circuit with a supermesh containing a known mesh current.
Problem 8.14. Determine the phasor currents I A, I B, and IC of the circuit

shown in Figure P8.14. Assume the circuit operates under sinusoidal steady-
state conditions.
FIGURE P8.14 Phasor-domain AC circuit with four meshes, including a supermesh and a
known mesh current.
Problem 8.15. Use superposition to find the time-domain currents i1 ( t ) and

i2 ( t ) of the circuit in Figure P8.15. Assume the circuit operates under sinu-
soidal steady-state conditions.
FIGURE P8.15 Time-domain AC circuit operating with two different frequencies.
Problem 8.16. Calculate the rms value of the periodic voltage waveform
shown in Figure P8.16. The period is 10 ms.
FIGURE P8.16 Periodic voltage waveform with triangular sections.

Problem 8.17. Find the rms value of the periodic voltage waveform of Figure
P8.17. The period is 2 ms.
FIGURE P8.17 Periodic voltage waveform having triangular and rectangular sections.
Problem 8.18. Determine the complex power for each of the sources of the
circuit in Figure P8.18. Assume the circuit operates under sinusoidal steady-
state conditions.
FIGURE P8.18 Phasor-domain AC circuit.

Problem 8.19. For the circuit in Figure P8.19, determine the complex power
for each of the sources. Construct the power triangle for each source, label-
ing all important features.
FIGURE P8.19 Phasor-domain AC circuit.
Problem 8.20. In the configuration of Figure P8.20, impedance Z1 consumes

15 kW at a lagging power factor of 0.94 while impedance Z 2 has an apparent
power of 10 kVA at a leading power factor of 0.90. Find the impedances Z1
and Z 2, the phasor currents I1 and I 2, and the complex power for the source.
FIGURE P8.20 Parallel impedances connected to a voltage source.

Problem 8.21. For the circuit in Figure P8.21, impedance Z1 has an appar-
ent power of 40 kVA at a lagging power factor of 0.85 while impedance Z 2
has an apparent power of 30 kVA at a leading power factor of 0.92. Find the
impedances Z1 and Z 2, the phasor currents I1 and I 2. Determine the value
of the impedance Z corr which will correct the source power factor to unity.
(If there is more than one possible value of Z corr, it is desirable to minimize
power loss.)
FIGURE P8.21 Three parallel impedances connected to a voltage source.
Problem 8.22. For the circuit in Figure P8.22, impedance Z1 has an apparent
power of 200 kVA at a leading power factor of 0.93 while impedance Z 2 has
an apparent power of 300 kVA at a lagging power factor of 0.96. Find the
impedances Z1 and Z 2, the phasor current I S , the phasor voltages and V2 , and
the complex power for the source.
FIGURE P8.22 Series impedances connected to a voltage source.

FIGURE P8.23 A two-terminal network containing only independent sources and impedances.
Problem 8.24. For the network in Figure P8.24, find the Norton equivalent
FIGURE P8.24 A two-terminal network containing mixed sources and impedances.

Problem 8.25. For the circuit in Figure P8.25, determine the load impedance
Z L which will dissipate maximum power. Assuming the load impedance is
set to this value, find the phasor load voltage VL, the phasor load current I L,
and the complex power S L for the load.
FIGURE P8.25 Two-terminal network with an unspecified load impedance connected.
Problem 8.26. For the circuit in Figure P8.26, plot the average power in the
load resistor as a function of the load resistance RL . Use a logarithmic scale
for resistance with a range of resistance values 0.1 Ω ≤ RL ≤ 1000 Ω. Find
the value of load resistance which will dissipate maximum average power,
and for this value of resistance, find the phasor load voltage VL, the phasor
load current I L, and the load power PL .
FIGURE P8.26 Two-terminal network with an unspecified load resistance connected.

Problem 8.27. For the circuit in Figure P8.27, calculate the phasor currents
I A, I B, and IC , and determine the complex power for each of the voltage
sources.
FIGURE P8.27 Circuit involving mutual inductance.

Problem 8.28. For the circuit in Figure P8.28, determine the phasor currents
I A, I B, and IC .
FIGURE P8.28 Circuit involving a linear transformer.
Problem 8.29. Find the phasor mesh currents I1 and I 2 in the linear trans-
former circuit of Figure P8.29. Determine the average power developed by
the voltage source and the average power delivered to the 2 Ω resistor.
FIGURE P8.29 Linear transformer circuit with two meshes.

Problem 8.30. Find the phasor currents I1 , I 2, I 3, and I 4 in the linear

transformer circuit of Figure P8.30. Determine the power developed by the
voltage source and the power loss in the 4 Ω resistor.
FIGURE P8.30 Linear transformer circuit with four meshes.
Problem 8.31. Find the phasor mesh currents I1 and I 2 of the circuit in
Figure P8.31. Determine the power developed by the voltage source, the
power delivered to the (10 + j 2 ) Ω load, and the efficiency.
FIGURE P8.31 Ideal transformer circuit containing a 50:1 transformer.

Problem 8.32. Find the phasor mesh currents I1 and I 2 of the circuit in
Figure P8.32. Find the power developed by the voltage source and the power
delivered to the ( 6 + j 2 ) Ω load. Calculate the power factor of the ( 6 + j 2 ) Ω
load, and compare this to the power factor “seen” by the voltage source.
FIGURE P8.32 Ideal transformer circuit containing a 100:1 transformer.
Problem 8.33. For the balanced wye–wye system of Figure P8.33, find
the line currents I A'a, I B'b, and IC'c, and plot these on a phasor diagram.
Determine the total power developed and the power delivered to the wye-
connected load.
FIGURE P8.33 Balanced wye–wye system.

Problem 8.34. For the balanced delta–delta system of Figure P8.34, find the
line currents I A'a, I B'b, and IC'c, and the load phase currents I ab, I Bbc, and
I ca . Determine the total power developed and the power delivered to the
delta-connected load.
FIGURE P8.34 Balanced delta–delta system.
Problem 8.35. For the balanced wye–delta system of Figure P8.35, find the
line currents I A'a, I B'b, and IC'c, and the load phase currents I ab, I Bbc, and
I ca . Plot these six currents on a phasor diagram. What do you notice about
the phase relationships between these currents?
FIGURE P8.35 Balanced wye–delta system.

Problem 8.36. For the unbalanced wye–wye system of Figure P8.33, find the
line currents I A'a, I B'b, and IC'c, and the neutral current I Nn. Plot these on a
phasor diagram. By how much do the line current phase angle differences
depart from the 120° value of the balanced system?
FIGURE P8.36 Unbalanced wye–wye system.
Problem 8.37. For the unbalanced wye–delta system of Figure P8.37, find
the line currents I A'a, I B'b, and IC'c, and the load phase currents I ab, Ibc , and
I ca . Determine the complex power for each voltage source, and the complex
power for each of the complex loads.
FIGURE P8.37 Unbalanced wye–delta system.
Problem 8.38. The wye–wye system shown in Figure P8.38 was balanced
until the c phase burned out on the load side. Find the line currents I A'a and
I B'b, and the neutral current I Nn. How does the magnitude of the neutral
current compare to the magnitude of the other two currents?
FIGURE P8.38 Unbalanced wye–wye system with one phase of the load burned out.
NOTES
1 Although mathematicians use i to denote the imaginary unit, we as electrical engineers
will use j to avoid confusion with our notation for an electrical current.
2 Euler’s relationship states that e jθ = cosθ + jsinθ .
3 When converting from a rectangular to a polar form, we must realize that
tan−1 ( − B / − A ) is not the same as tan−1 ( B / A ), because whereas the latter is in the
first quadrant the former is in the third quadrant. For example, tan−1 ( −1/ −1) = 3π / 2
whereas tan−1 ( 1/ 1) = π / 2. Many calculators do not recognize this difference. Hence,
we should always verify that the result we find is in the correct quadrant. If it isn’t, we
should add π to the result.
4 The complex plane is a Cartesian coordinate system for the representation of complex
quantities. The real part is measured along the horizontal axis while the imaginary part
is measured along the vertical axis. The complex quantity A + jB would be plotted with
the Cartesian coordinates (A,B), where j is the unit imaginary number, j = −1.
9 Frequency Response
9.1 INTRODUCTION
In the previous chapter, we considered the ac steady-state analysis of circuits oper-
ating with sinusoidal excitation at a single frequency. When there were multiple
sources, they were all considered to operate at the same frequency so we could treat
the impedances of capacitors and inductors as constants. If we had multiple sinu-
soidal sources operating at different frequencies, we could apply the same concepts
with each source and use superposition to find the overall time-domain voltages and
currents in the circuit. Often, however, we have signals that are non-sinusoidal or
non-periodic. Such signals can be considered to be built from sinusoidal components,
so the response of a circuit to such general signals can be understood by finding its
response to sinusoids as a function of frequency. In this chapter, we will therefore
explore the frequency response of circuits containing reactive components such as
capacitors and inductors.
To determine the frequency response of a two-port network with an input and an
output, we first find the transfer function H, which is the ratio of the phasor output
voltage to the phasor input voltage: H = Vout / Vin . In general, this will be a complex
quantity that varies with frequency. The amplitude response, or gain, of the circuit is
the magnitude of the transfer function as a function of frequency:
gain = H = Vout / Vin . (9.1)
Sometimes, the amplitude response is plotted in decibel units:
gain in dB = 20 log10 H = 20 log10 Vout / Vin . (9.2)
The phase response is the phase of the transfer function as a function of frequency:
phase = ∠H = ∠ (Vout / Vin ) = ∠Vout − ∠Vin . (9.3)
Taken together, the amplitude response and phase response specify the frequency
response of a circuit.
Generally, circuits will exhibit frequency-dependent behavior whether or not
it is desirable, because of the presence of reactive components. However, we may
design circuits to achieve specific frequency-dependent behavior, and such circuits
are called filters.
Broadly, filters may be designed to achieve four types of behavior. A low-pass
filter allows low-frequency components to pass through while blocking high-
frequency components of the signal. There is a transition from the low-frequency
DOI: 10.1201/9781003408529-9 391

range (the passband) to the high-frequency range (the stopband) at the cutoff fre-
quency. A high-pass filter allows high frequencies to pass while blocking low fre-
quencies, again with a transition at the cutoff frequency. The bandpass filter passes
a band of frequencies while blocking both higher and lower frequencies. It therefore
has two cutoff frequencies. A bandstop (or notch) filter blocks only a band of fre-
quencies but passes lower and higher frequencies. Like the bandpass filter, it has two
cutoff frequencies.
The cutoff frequency for a filter is defined to be the half-power frequency; in
other words, the cutoff frequency is the frequency at which the power delivered to a
resistive load has dropped to half its value in the passband. (If there are two or more
cutoff frequencies, the half-power criterion applies to each.) The power delivered to
a resistive load is proportional to the square of the magnitude of the output voltage.
Hence,
2 2
1 P Vout cutoff H cutoff
= cutoff = 2 = 2
(9.4)
2 Ppassband Vout passband H passband
and
H cutoff 1
= , (9.5)
H passband 2
so the cutoff frequency is the frequency at which the gain has dropped to 1 / 2 times
the passband gain (~70% of the passband gain). Moreover,
 H   1 
 = 20 log10   = −3 dB,
cutoff
20 log10  (9.6)
H
 passband  2
so
(
20 log10 ( H cutoff ) − 20 log10 H passband )
 1 
= 20 log10  = −3 dB, (9.7)
 2 
and the cutoff frequency is the frequency at which the gain in dB has dropped by 3 dB
relative to the passband. (It is the −3 dB frequency.)
Filters may be realized in passive circuitry (using only passive components such
as resistors, inductors, and capacitors) or in active circuitry (using active devices such
as operational amplifiers and transistors as well as passive devices). In the following
sections, we will investigate a few example filter circuits, both passive and active
types, to illustrate the general principles of frequency response analysis. However,
the same general approach may be applied to other filters as well, even if they involve
higher order and much greater complexity.
Frequency Response 393
9.2 PASSIVE FILTERS

A passive filter is constructed using only passive components (resistors, inductors,
and capacitors). An example is the first-order resistor-capacitor (RC) low-pass filter
The transfer function for this filter may be found by application of the voltage-
divider rule. If we use the compact notation s = jω , the impedance of the capacitor
is 1 / ( sC ), and the transfer function is
Vout 1 / ( sC ) 1
H= = = . (9.8)
Vin R + 1 / ( sC ) 1 + sRC
The amplitude response is given by

1 1 1 1
H = = = = . (9.9)
1 + sRC 1 + jω RC 1 + j 2πfRC 1 + ( 2πfRC )
2
The passband gain is unity, so at the cutoff frequency

1 1
H = = . (9.10)
1 + ( 2πfc RC ) 2
2
Solving for the cutoff frequency,

1
fc = . (9.11)
2πRC
The phase response is given by
 1 
∠H = ∠  = −∠ (1 + sRC ) = −∠ (1 + jω RC )
 1 + sRC 
(9.12)
= −∠ (1 + j 2πfRC ) = − tan −1
( 2πfRC ) .
Figure 9.2 shows the amplitude and phase response for an RC first-order low-pass fil-
ter with R = 1000 Ω and C = 100 nF. For this combination fc = 1.59 kHz, and we can
FIGURE 9.1 First-order RC low-pass filter.

FIGURE 9.2 Amplitude and phase response for an RC first-order low-pass filter.
see that this is the −3 dB frequency. The passband gain is unity (0 dB) and the stop-
band slope is −6 dB/octave or −20 dB/decade. (An octave is a factor of two change in
frequency while a decade is a factor of ten change in frequency.)
We can also construct a first-order RC high-pass filter, by swapping the positions
of the capacitor and resistor from the previous example. This is shown in Figure 9.3.
The transfer function is
Vout R 1
H= = = . (9.13)
Vin R + 1 / ( sC ) 1 + 1 / ( sRC )
The amplitude response is given by
1 1 1 1
H = = = = .
1 + 1 / ( sRC ) 1 + 1 / ( jω RC ) 1 − j (1 / ( 2πfRC ) ) 1 + 1 / ( 2πfRC )
2
(9.14)
The passband gain is unity, so at the cutoff frequency
1 1
H = = . (9.15)
1 + 1 / ( 2πfRC ) 2
2
Solving for the cutoff frequency,

1
fc = . (9.16)
2πRC
This is the same as the cutoff frequency for the low-pass filter, but in this case the
passband is in the range above fc. The phase response is given by
 1 
∠H = ∠  = −∠ (1 + 1 / ( sRC )) = −∠ (1 − j / (ω RC ))
 1 + 1 / ( sRC )  (9.17)
= −∠ (1 − j / ( 2πfRC ) ) = − tan −1
( −1 / (2πfRC ) .
FIGURE 9.3 First-order RC high-pass filter.
Figure 9.4 shows the amplitude and phase response for an RC first-order high-pass
filter with R = 1000 Ω and C = 100 nF, with fc = 1.59 kHz. As for the low-pass filter,
the passband gain is unity (0 dB) but the stopband slope is positive (6 dB/octave or
20 dB/decade).
Passive filters of higher order may be constructed as well. For example, the circuit
of Figure 9.5 is a second-order low-pass filter.
The transfer function for this filter may be found by use of the node voltage
method, with the essential nodes labeled in Figure 9.6.
The node voltage equation is
V1 − Vin V1 V1
+ + = 0. (9.18)
R 1 / ( sC ) R + 1 / ( sC )
1 1 1  Vin
V1  + + = . (9.19)
 R 1 / ( sC ) R + 1 / ( sC )  R
Multiplying through by R,
 R R 
V1 1 + +  = Vin , (9.20)
 1 / ( sC ) R + 1 / ( sC ) 
Simplifying,
sRC 
V1 1 + sRC + = Vin , (9.21)
 1 + sRC 
 (1 + sRC )2 + sRC 
V1   = Vin , (9.22)
 1 + sRC 
and
 1 + sRC 
V1 = Vin  . (9.23)
 (1 + sRC ) + sRC 
2
FIGURE 9.4 Amplitude and phase response for an RC first-order high-pass filter.
FIGURE 9.5 Second-order low-pass filter.
FIGURE 9.6 Second-order low-pass filter labeled for nodal analysis.
By the voltage-divider rule,
 1 
   1   1 + sRC  1 
Vout = V1  sC  = V1  1 + sRC  = Vin  1 + sRC 2 + sRC   1 + sRC  ,
( )
1  
R+   
 sC 
(9.24)
 1   1 .
= Vin   = Vin  2 2 2
( ) 
2
 1 + sRC + sRC   s R C + 3sRC + 1
The transfer function is therefore

Vout  1 = 1
H= = 2 2 2  . (9.25)
Vin  s R C + 3sRC + 1  1 − ( 2πfRC )2  + j6πfRC
 
Figure 9.7 shows the amplitude and phase response for the second-order filter circuit
with R = 1000 Ω and C = 100 nF. Although the corner frequency (the frequency where
the two straight-line pieces of the amplitude response appear to meet) is 1.59 kHz, this
corner frequency is not the same as the cutoff frequency. This is because the response
at the corner frequency is −6 dB, and the actual cutoff frequency is approximately
600 Hz and we can see that this is the −3 dB frequency. The passband gain is unity
(0 dB) and the stopband slope is twice that for the first-order filter (−12 dB/octave
or −40 dB/decade).
To review, see Presentation 9.2 in ebook+
To test your knowledge, try Quiz 9.2 in ebook+. To put your knowledge to p ractice,
try Laboratory Exercise 9.1 in ebook+.
9.3 ACTIVE FILTERS

Active filters are commonly built using operational amplifiers, although they may
also be designed with discrete transistors. In either case, these filter circuits are most
easily analyzed using the node voltage method.
9.3.1 Sallen and Key Low-Pass Filter

As an example of an active filter, consider the Sallen and Key low-pass filter shown
in Figure 9.8.
When writing the node voltage equations, we note that the voltage at the
non-inverting input of the op amp is equal to Vout because of the virtual short. Thus,
for node one,
V1 − Vin V1 − Vout V1 − Vout
N1 + + = 0. (9.26)
R R 1 / ( sC )
FIGURE 9.7 Amplitude and phase response for a second-order low-pass filter.
FIGURE 9.8 Sallen and Key low-pass filter.
For the non-inverting input node,

Vout − V1 V
N2 + out = 0. (9.27)
R 1 / ( sC )

1 1 1   1 1  Vin
N 1 V1  + +  + Vout  − − = (9.28)
 R R 1 / ( sC )   R 1 / ( sC )  R
and
1 1 1 
N 2 V1  −  + Vout  +  = 0. (9.29)
 R  R 1 / ( sC ) 
Simplifying,
N 1 V1 [ 2 + sRC ] + Vout [ −1 − sRC ] = Vin (9.30)
and
N 2 V1 [ −1] + Vout [1 + sRC ] = 0. (9.31)
In matrix form,
 2 + sRC −1 − sRC   V1   Vin 

  = . (9.32)
 −1 1 + sRC   Vout   0 
Solving,
2 + sRC Vin
−1 0 Vin
Vout = =
2 + sRC −1 − sRC ( 2 + sRC )(1 + sRC ) − (1 + sRC )
−1 1 + sRC
Vin
= . (9.33)
s R C + 2sRC + 1
2 2 2

1
H= . (9.34)
s 2 R 2C 2 + 2sRC + 1
Figure 9.9 shows the amplitude and phase response for this filter, with R = 10 kΩ,
C = 2.2 nF, and a corner frequency of 1 / ( 2πRC ) = 7.23 kHz.
9.3.2 Sallen and Key High-Pass Filter

As a second example, the Sallen and Key high-pass filter is shown in Figure 9.10.
For node one,
V1 − Vin V1 − Vout V1 − Vout
N1 + + = 0. (9.35)
1 / ( sC ) 1 / ( sC ) R
For the non-inverting input node,
Vout − V1 Vout
N2 + = 0. (9.36)
1 / ( sC ) R
FIGURE 9.9 Amplitude and phase response for a Sallen and Key LPF with R = 10 kΩ ,
C = 2.2 nF , and a corner frequency of 1 / ( 2πRC ) = 7.23 kHz .
FIGURE 9.10 Sallen and Key high-pass filter.

 1 1 1  1 1 Vin
N 1 V1  + +  + Vout  − − = (9.37)
 1 / ( sC ) 1 / ( sC ) R   1 / ( sC ) R  1 / ( sC )
and
 1   1 1
V1  −  + Vout  +  = 0. (9.38)
 1 / ( sC )   1 / ( sC ) R 
Simplifying,
N 1 V1 [ 2sRC + 1] + Vout [ − sRC − 1] = sRCVin (9.39)
and
N 2 V1 [ − sRC ] + Vout [ sRC + 1] = 0. (9.40)
In matrix form,
 2sRC + 1 − sRC − 1   V1   sRCVin 

 − sRC  = . (9.41)
 sRC + 1   Vout   0 
Solving,
2sRC + 1 sRCVin
− sRC 0 − s 2 R 2C 2Vin
Vout = =
2sRC + 1 − sRC − 1 ( 2sRC + 1)( sRC + 1) − ( − sRC )( − sRC − 1)
− sRC sRC + 1
− s 2 R 2C 2Vin
= 2 2 2
(9.42) .
s R C + 2sRC + 1
− s 2 R 2C 2
H= . (9.43)
s R C 2 + 2sRC + 1
2 2
Figure 9.11 shows the amplitude and phase response for this filter, with R = 10 kΩ,
C = 2.2 nF, and a corner frequency of 1 / ( 2πRC ) = 7.23 kHz.
9.3.3 Multiple Feedback Bandpass Filter

As a third example, the multiple feedback bandpass filter is shown in Figure 9.12.
For node one,
V1 − Vin V1 V − Vout
N1 + + 1 = 0. (9.44)
R1 1 / ( sC ) 1 / ( sC )
FIGURE 9.11 Amplitude and phase response for a Sallen and Key high-pass filter (HPF)
with R = 10 kΩ , C = 2.2 nF , and a corner frequency of 1 / ( 2πRC ) = 7.23 kHz .
FIGURE 9.12 Multiple feedback bandpass filter.
For the inverting input node,

−V1 −V
N2 + out = 0. (9.45)
1 / ( sC ) R2
1 1 1   1  Vin
N 1 V1  + +  + Vout  − = (9.46)
 R1 1 / ( sC ) 1 / ( sC )   1 / ( sC )  R1
and
 1   1 
N 2 V1  −  + Vout  −  = 0. (9.47)
 1 / ( sC )   R2 
Simplifying,
N 1 V1 [1 + 2sR1C ] + Vout [ − sR1C ] = Vin (9.48)
and
V1 [ − sR2C ] + Vout [ −1] = 0. (9.49)
In matrix form,
 1 + 2sR1C − sR1C   V1   Vin 

  = . (9.50)
 − sR2C −1   Vout   0 
Solving,
1 + 2sR1C Vin
− sR2C 0
Vout =
1 + 2sR1C − sR1C
(9.51)
− sR2C −1
− sR2CVin − sR2CVin
= = .
−1 − 2sR1C − ( − sR2C )( − sR1C ) s 2 R1R2C 2 + 2sR1C + 1
− sR2C
H= . (9.52)
s 2 R1R2C 2 + 2sR1C + 1
The general form of the transfer function for a second-order bandpass filter is

H = Ar 
( j / Q )( f / f0 ) 
, (9.53)
 1 − ( f / f0 ) + ( j / Q )( f / f0 ) 
2
where f0 is the center frequency for the passband, Ar is the resonant gain at the center
frequency, and Q is the quality factor. One interpretation of the quality factor is the
ratio of the center frequency to the bandwidth, where the bandwidth is the difference
between the two cutoff frequencies. By comparing these two equations for the trans-
fer function, we find that for the multiple feedback bandpass filter,
1
f0 = , (9.54)
2πC R1R2
R2
Ar = − , (9.55)
2 R1
and
1 R2
Q= . (9.56)
2 R1
Figure 9.13 shows the amplitude and phase response for two designs of this filter.
For the first design, C = 10 nF, R1 = 1kΩ, and R2 = 4 kΩ, giving a center frequency of
7.96 kHz, a quality factor of 1.0, and a bandwidth of 7.96 kHz. For the second design,
FIGURE 9.13 Amplitude and phase response for multiple feedback bandpass filters with
two designs. For the first design, C = 10 nF , R1 = 1kΩ, and R2 = 4 kΩ , giving a center fre-
quency of 7.96 kHz , a quality factor of 1.0 , and a bandwidth of 7.96 kHz . For the second
design, C = 10 nF , R1 = 2 kΩ , and R2 = 2 kΩ , giving a center frequency of 7.96 kHz , a
quality factor of 0.50 , and a bandwidth of 15.92 kHz .
C = 10 nF, R1 = 2 kΩ , and R2 = 2 kΩ , giving a center frequency of 7.96 kHz, a quality

factor of 0.50, and a bandwidth of 15.92 kHz.
To test your knowledge, try Quiz 9.3. To put your knowledge to practice, try
Laboratory Exercises 9.2 and 9.3 in ebook+.
9.4 SUMMARY
In circuits with reactive components (capacitors and inductors), the phasor voltages
and currents vary with frequency. Filters are circuits designed to be frequency
selective in a desired fashion. Broadly speaking, there are four basic types of filters:
low pass, high pass, bandpass, and bandstop. Filters may be further character-
ized as passive or active; a passive filter uses only passive components (resistors,
capacitors, inductors) whereas an active filter also contains active components such
as transistors or operational amplifiers. The transfer function H for a filter is the
phasor ratio of the output and input voltages: H = Vout / Vin . Generally, the transfer
function for a circuit may be found by the use of the node voltage method. The
amplitude response is the magnitude of H as a function of frequency. The phase
response is the phase angle of H as a function of frequency. Together, the ampli-
tude response and phase response make up the frequency response of the filter.
Often, the amplitude response is plotted in decibel (dB) units, where the amplitude
response in dB is 20 log10 H . The cutoff frequency for a filter is the half-power
or −3dB frequency. If a filter has more than one cutoff frequency, this criterion
applies to each.
To evaluate your comprehensive knowledge of Chapters 1–9, solve Example Exam
9.1 in ebook+ or Example Exam 9.2 in ebook+.
PROBLEMS
Problem 9.1. Find the transfer function for the filter circuit shown in
Figure P9.1. Plot the amplitude response using a decibel scale for the response
and a logarithmic scale for the frequency. Plot the phase response using a
logarithmic scale for frequency. Use an appropriate range of frequency span-
ning four decades. Determine the nature of the filter response (i.e., low pass,
high pass, bandpass, or band reject) and determine the cutoff frequency(ies).
FIGURE P9.1 First-order RC low-pass filter with R = 2kΩ and C = 22 nF.
Problem 9.2. Find the transfer function for the filter circuit shown in Figure
P9.2. Plot the amplitude response using a decibel scale for the response and
a logarithmic scale for the frequency. Plot the phase response using a loga-
rithmic scale for frequency. Use an appropriate range of frequency spanning
four decades. Determine the nature of the filter response (i.e., low pass, high
pass, bandpass, or band reject) and determine the cutoff frequency(ies).
FIGURE P9.2 First-order RC high-pass filter with R = 2kΩ and C = 0.1 μF.
P9.3. Plot the amplitude response using a decibel scale for the response
and a logarithmic scale for the frequency. Plot the phase response using
a logarithmic scale for frequency. Use an appropriate range of frequency
spanning four decades. Determine the nature of the filter response (i.e.,
low pass, high pass, bandpass, or band reject) and determine the cutoff
frequency(ies).
FIGURE P9.3 First-order resistor-inductor (RL) low-pass filter with R = 3.3 kΩ and
L = 20 mH.
Figure P9.4. Plot the amplitude response using a decibel scale for the
response and a logarithmic scale for the frequency. Plot the phase response
using a logarithmic scale for frequency. Use an appropriate range of fre-
quency spanning four decades. Determine the nature of the filter response
(i.e., low pass, high pass, bandpass, or band reject) and determine the cutoff
frequency(ies).
FIGURE P9.4 First-order RC high-pass filter including two resistors.

frequency(ies).
FIGURE P9.5 First-order RL high-pass filter including two resistors.

frequency(ies).
FIGURE P9.6 Second-order resistor-inductor-capacitor (RLC) low-pass filter with R = 1

kΩ, L = 0.1 mH, and C = 20 nF.
FIGURE P9.7 Second-order RLC filter with R = 100 Ω, L = 2 mH, and C = 2 μF.
FIGURE P9.8 Second-order RLC filter with R = 10 kΩ, L = 10 mH, and C = 10 μF.
frequency(ies).
FIGURE P9.9 Second-order low-pass filter with two identical RC sections.
frequency(ies).
FIGURE P9.10 Second-order low-pass filter with two RC sections.

frequency(ies).
FIGURE P9.11 Third-order low-pass filter with three identical RC sections.
Figure P9.12. Plot the amplitude response using a decibel scale for the
response and a logarithmic scale for the frequency. Plot the phase response
using a logarithmic scale for frequency. Use an appropriate range of fre-
quency spanning four decades. Determine the nature of the filter response
(i.e., low pass, high pass, bandpass, or band reject) and determine the cutoff
frequency(ies).
FIGURE P9.12 Third-order filter with three RL sections.

FIGURE P9.13 Second-order active filter involving an op amp, two resistors, and two
capacitors.
FIGURE P9.14 Second-order active filter involving an op amp, four resistors, and two
capacitors.
frequency(ies).
FIGURE P9.15 Second-order active filter involving an op amp, two resistors, and two
inductors.
frequency(ies).
FIGURE P9.16 Second-order active filter involving an op amp, four resistors, and two
capacitors.
FIGURE P9.17 Second-order active filter involving an op amp, two identical capacitors, and
two distinct resistors.
Problem 9.18. Design the filter circuit using the topology shown in Figure
P9.18 to achieve a nominal cutoff frequency of 15 kHz ±10%. (The nominal
cutoff frequency is the value calculated without taking component toler-
ances into account. Note that because this is a second-order filter the cor-
ner frequency will differ slightly from the cutoff frequency.) Use standard
5% tolerance resistor values and standard 20% tolerance capacitor values.
Verify the amplitude response and cutoff frequency.
FIGURE P9.18 Second-order low-pass active filter involving an op amp and unspecified
values of resistances and capacitances.
P9.19 to achieve a nominal quality factor of 2.0 and a nominal center fre-
quency of 5 kHz ± 10%. (The nominal values are those calculated without
taking component tolerances into account.) Use standard 5% tolerance
resistor values and standard 10% tolerance capacitor values. Plot the ampli-
tude response, verify the center frequency, and determine the bandwidth for
the filter.
FIGURE P9.19 Second-order bandpass active filter involving an op amp and unspecified
values of resistances and capacitances.
P9.20 to achieve a nominal quality factor of 5.0 and a nominal center fre-
quency of 10 kHz ± 10%. (The nominal values are those calculated with-
out taking component tolerances into account.) Use standard 5% tolerance
resistor values and standard 20% tolerance capacitor values. Plot the ampli-
tude response, verify the center frequency, and determine the bandwidth for
the filter.
FIGURE P9.20 Second-order bandpass active filter involving two capacitors and two dis-
tinct resistors, all of which have unspecified values.
APPENDIX A
Resistor Color Code
The values of resistors are indicated using colored bands and the code explained in
Table App A.1 and Figure App A.1.
TABLE APP A.1

The Resistor Color Code
Color Digit Multiplier Tolerance
Black 0 100
Brown 1 101 1%
Red 2 102 2%
Orange 3 103
Yellow 4 104
Green 5 105 0.5%
Blue 6 106 0.25%
Violet 7 107 0.1%
Grey 8 108
White 9 109
Gold 5%
Silver 10%
None 20%
FIGURE APP A.1 Explanation of the bands used for the resistor color code.
416
APPENDIX B
Standard Values of 5% Resistors
The commercial values of resistors with 5% tolerance have been standardized to

those given in Table App B.1. These values repeat every decade. Therefore, 15 Ω,
150 Ω, and 1.5 kΩ are all standard values. The adjacent values differ by approxi-
mately 10% so the ranges will meet or overlap slightly.
TABLE APP B.1

Standard Values of Resistors with 5% Tolerance
1.0 1.1 1.2 1.3 1.5 1.6
1.8 2.0 2.2 2.4 2.7 3.0
3.3 3.6 3.9 4.3 4.7 5.1
5.6 6.2 6.8 7.5 8.2 9.1
The values given repeat every decade.
417
APPENDIX C
Standard Values of 10% Capacitors
The commercial values of capacitors with 10% tolerance have been standardized
to those given in Table App C.1. The values repeat every decade. Therefore, 22 pF,
220 nF, and 2.2 μF are all standard values. The adjacent values differ by approxi-
mately 20% so the ranges will meet or overlap slightly.
TABLE APP C.1

Standard Values for Capacitors with 10% Tolerance
1.0 1.2 1.5 1.8 2.2 2.7
3.3 3.9 4.7 5.6 6.8 8.2
The values repeat every decade.
418
APPENDIX D
Ceramic Capacitors
Capacitor values are generally given in pF (1 pF = 10 −12 F). A ceramic capacitor will
typically give its value using three numbers; the first two represent digits and the
third is a multiplier. For example, “223” designates 22,000 pF or 22 nF as shown in
Figure App D.1.
FIGURE APP D.1 A ceramic capacitor with an explanation of the capacitance code.
419
APPENDIX E
Electrolytic Capacitors
Electrolytic capacitors generally give their capacitance in μF as in the example

shown in Figure App E.1. Also given on the case is the voltage rating and the polar-
ity (for polarized capacitors). It is important to not reverse the polarity across an
electrolytic capacitor; it may evolve hydrogen gas, explode, and cause personal
injury.
FIGURE APP E.1 Electrolytic capacitor.
420
APPENDIX F
Complex Numbers
In order to solve AC circuits algebraically, without the need for differential equa-
tions, we will make extensive use of complex numbers and complex mathematics.
It should be understood that this represents a system of shortcuts and that we are
using complex quantities to represent real circuit elements, real currents, and real
voltages. Nonetheless, working with complex quantities is a critical part of sinusoidal
steady-state analysis so we will review their mathematics.
A complex number A + jB involves a real component A and an imaginary com-
ponent, jB, where j is the imaginary unit,1 j = −1. This complex number may be
shown on the complex plane using Cartesian (rectangular) coordinates or polar coor-
dinates of the form R∠θ , as shown in Figure App F.1.
Using Euler’s relationship,2 we can convert from rectangular coordinates to polar
coordinates3:
FIGURE APP F.1 A complex quantity A + jB shown in the complex plane.
( )
1/2 −1
A + jB → A2 + B 2 e j tan ( B / A) = Re jθ . (F.1)

rectangular coordinates polar coordinates
421
422 APPENDIX F
We can also convert from polar coordinates to rectangular coordinates:
Re jθ
→ R cos θ + jR sin θ = A + jB . (F.2)
polar coordinates

rectangular coordinates
Often, we will express complex numbers in polar form using the shorthand notation
R∠θ ; it should be recognized that this means the same thing as Re jθ .
When adding complex quantities,
( A + jB ) + (C + jD ) = ( A + C ) + j ( B + D ) (F.3)
and
A∠α + B∠β = ( A cos α + B cos β ) + j ( A sin α + B sin β ) . (F.4)
When multiplying complex quantities,
( A + jB )(C + jD ) = ( AC − BD ) + j ( BC + AD ) (F.5)
and
( A∠α )( B∠β ) = AB∠ (α + β ) . (F.6)
When dividing complex quantities,
A + jB ( A + jB ) (C − jD ) ( AC + BD ) + j ( BC − AD )
= = (F.7)
C + jD (C + jD ) (C − jD ) C 2 + D2
and
A∠α
= ( A / B ) ∠ (α − β ) . (F.8)
B∠β
Finally, we note that 1 / j = − j , because
1  1  j  j
= = = − j. (F.9)
j  j   j  −1
NOTES
1 Although mathematicians use i to denote the imaginary unit, we as electrical engineers
will use j to avoid confusion with our notation for an electrical current.
2 Euler’s relationship states that e jθ = cosθ + jsinθ .
3 When converting from a rectangular to a polar form, we must realize that
tan−1 ( − B / − A ) is not the same as tan−1 ( B / A ), because whereas the latter is in the
first quadrant the former is in the third quadrant. For example, tan−1 ( −1/ −1) = 3π / 2
whereas tan−1 ( 1/ 1) = π / 2. Many calculators do not recognize this difference. Hence,
we should always verify that the result we find is in the correct quadrant. If it isn’t, we
should add π to the result.
APPENDIX G
Cramer’s Method
When using the node-voltage method or the mesh-current method, we need to solve
systems of simultaneous equations. One way to do this is by Cramer’s method.
Cramer’s method is a matrix approach which is convenient when solving either sym-
bolically, as when finding a transfer function, or numerically, as when finding spe-
cific voltages. Other matrix approaches may be used as well, and in general, these
are more convenient than substitution or subtraction when solving three or more
equations. These other approaches are discussed in detail in books on linear algebra.
Here though, we focus on Cramer’s method, which is used throughout this book for
solving node and mesh equations.
Suppose we need to solve a system of two equations involving two unknowns x1
and x 2:
A11x1 + A12 x 2 = B1 (G.1)
and
A21x1 + A22 x 2 = B2 . (G.2)
These two equations may be written in matrix form as
 A11 A12   x1  B1
  = . (G.3)
 A21 A22 x B2
  2 
To solve for each of the unknowns, we calculate a ratio of determinants. When find-
ing the first unknown x1, the numerator is the determinant of a modified matrix
involving the replacement of the first column by the matrix B, and the denominator
is the determinant of the original matrix:
B1 A12
B2 A22 B1 A22 − B2 A12
x1 = = . (G.4)
A11 A12 A11 A22 − A21 A12
A21 A22
When finding the second unknown x 2, the numerator is the determinant of a modi-
fied matrix involving the replacement of the second column by the matrix B, and the
denominator is the determinant of the original matrix:
423
424 APPENDIX G
A11 B1
A21 B2 B1 A22 − B2 A12
x2 = = . (G.5)
A11 A12 A11 A22 − A21 A12
A21 A22
We can extend this to a system of three or more equations as well. For example, in
the case of three equations in three unknowns x1, x 2, and x3, the system of equations
could be written as
A11x1 + A12 x 2 + A13 x3 = B1 , (G.6)
A21x1 + A22 x 2 + A23 x3 = B2 , (G.7)
and
A31x1 + A32 x 2 + A33 x3 = B3 . (G.8)
In matrix form,
 A11 A12 A13   x1  B1

  
 A21 A22 A23   x2 = B2 . (G.9)
 A31 A32 A33   x3  B3
  
To solve for the nth unknown, we take the ratio of two determinants; the numerator is
the determinant of a modified matrix in which the nth column has been replaced by
matrix B and the denominator is the determinant of the original matrix. For example,
to find x1,
B1 A12 A13
B2 A22 A23 B1 A22 A33 + A12 A23 B3 + A13 B2 A32
B3 A32 A33 − A13 A22 B3 − A12 B2 A33 − B1 A23 A32
x1 = = . (G.10)
A11 A12 A13 A11 A22 A33 + A12 A23 A31 + A13 A21 A32
A21 A22 A23 − A13 A22 A31 − A12 A21 A33 − A11 A23 A32
A31 A32 A33
The method of finding a determinant is explained in Figures App G.1 and App G.2.
For a 2 × 2 matrix as shown in Figure App G.2, we simply subtract the NE-SW
diagonal product from the NW-SE diagonal product, and a numerical example is
given on the right. For a matrix of dimension 3 × 3 or greater, we first concatenate the
matrix with itself before finding the diagonal products, as shown in Figure App G.2.
Although a 3 × 3 example is shown, this same general procedure applies to matrices
of higher dimension.
APPENDIX G 425
FIGURE APP G.1 Finding the determinant of a 2 × 2 matrix.
FIGURE APP G.2 Finding the determinant of a 3 × 3 matrix.

Index
active filters 397–403 parallel RLC circuit 281, 287
admittance 319–320 series RLC circuit 262
alternating current 306 decade 394
Ampere 3 decibel 391
apparent power 341 delta 18–19, 349–352
assumptions of circuit theory 1 dependent sources 5–6
current‑controlled current source (CCCS)
bandpass filters 392, 400–403 5–6, 182–188, 216–221
bandstop filters 392 current‑controlled voltage source (CCVS)
branch 7, 40 5–6, 53–55
node voltage method 49–51
capacitor voltage‑controlled current source (VCCS)
ceramic 419 5–6
circuit symbol 201 voltage‑controlled voltage source (VCVS)
displacement current 202 5–6, 49–51, 334–336
electrolytic 420 determinants 44, 423–425
energy 203 difference amplifier 82–83
parallel 203–204 displacement current 202
physical structure 201 dot convention 362–363
polarized 420 double supermesh 128–129
series 204–205
standard values 418 electric fields 2
voltage 202 electrical charge 2
Cartesian coordinates 307 electrical current 2
center frequency 402 electrolytic capacitor 420
ceramic capacitor 419 equivalent resistance
characteristic equation parallel resistors 15–16
general RLC circuit 290 series and parallel combinations 16–18
parallel RLC circuit 279 series resistors 12–14
series RLC circuit 261 essential node 6
coefficient of coupling 362
color code 416 Farad 202
complex numbers 307–308, 421–422 feedback resistor 73
complex plane 307–308 filters
complex power 340–341 active 397–403
conductance 320 bandpass 392, 400–403
Coulomb 2 bandstop 392
Cramer’s method 43, 423–425 center frequency 402
Cramer’s rule see Cramer’s method cutoff frequency 392
critically‑damped half‑power frequency 392
parallel RLC circuit 279–280, 284–286 high‑pass 392, 394–396, 399–400
series RLC circuit 261, 268–271 low‑pass 391, 393–394, 395–396, 397–399
current‑controlled current source (CCCS) 5–6, multiple feedback bandpass filter 400–403
182–188, 216–221 passband 392
current‑controlled voltage source (CCVS) 5–6, passive 393–397
53–55, 131–133 quality factor 402
current‑divider rule 15–16 resonant gain 402
AC circuits 318 Sallen and Key high‑pass filter 399–400
cutoff frequency 392 Sallen and Key low‑pass filter 397–399
stopband 392
damped radian frequency transfer function 391
427
428 Index
first‑order circuits 201 make‑before‑break switch 226

flux density 222 matrix 43
frequency response 391–403 maximum power transfer theorem 180–182
amplitude response 391 AC circuits 342–345
cutoff frequency 392 mesh 114
phase response 391 mesh analysis see mesh current method
transfer function 391 mesh current method 114–142
AC circuits 326–328
gain‑bandwidth product 90 compared to node voltage method 136–139
Gauss’ law 201 dependent source 131–135
double supermesh 128–129
half‑power frequency 392 known mesh current 122–125
Henry 222 supermesh 125–128
high‑pass filter 392, 394–396, 399–400 multiple feedback bandpass filter 400–403
mutual inductance 360–369
ideal transformer 366–367
imaginary unit 307 natural and step response
impedance 309–320 parallel RLC circuit 280–281
capacitor 313–315, 320 RC circuit 214–216
inductor 311–313, 320 RL circuit 229–232
parallel 317–318 series RLC circuit 273–278
resistor 310–311, 320 natural response
series 315–317 parallel RLC circuit 278–280
series and parallel combinations 318–319 RC circuit 205–207
impedance shortcut analysis 333 RL circuit 225–227
inductor series RLC circuit 260–262
circuit symbol 221 neper frequency
current 222 general RLC circuit 290
inductance 222 parallel RLC circuit 279
parallel 224–225 series RLC circuit 261
physical structure 221 nodal analysis see node voltage method
series 223–224 node 6, 40
voltage 222 essential 6, 40
infinite input impedance 71 reference 41
input bias current 90 voltages 41
input offset current 90 node voltage method 40–59
input offset voltage 91 AC circuits 322–326
input resistance 91 alternate node numbering 44–46
inverting amplifier 79–80 compared to mesh current method 136–139
variable gain 84–86 dependent source 49–51
known node voltage 51–55
Kirchhoff’s current law 6–8 supernode 56–59
Kirchhoff’s voltage law 8–9 non‑inverting amplifier 80–81
known mesh current 122–125 variable gain 85–86
known node voltage 51–55 non‑planar circuit 115
Norton’s theorem 180
lagging power factor 338 AC circuits 328–330
leading power factor 338 Norton current 337
line currents 354 Norton impedance 337
line voltages 350, 352 Norton resistance 180
linear transformer 364–366
loop 114 octave 394
low‑pass filter 391, 393–394, 395–396, 397–399 Ohm’s law 6
lumped parameter system 1 open‑circuit analysis 156
AC circuits 328–330
magnetic field intensity 222 open‑circuit voltage 156
magnetic flux 221, 361 AC circuits 328–330
Index 429
open‑loop gain 70–71, 91 potential difference 2

operational amplifier 70–95 potentiometer 84
design 84–89 power 4
difference amplifier 82–83 power factor 338
gain‑bandwidth product 90 power triangle 340–341
infinite input impedance 71 primary 361
input bias current 90
input offset current 90 quality factor 402
input offset voltage 91
input resistance 91 RC circuit
inverting amplifier 79–80 natural response 205–207
linear operation 70 natural and step response 214–216
non‑ideal characteristics 89–94 sequential switching 238–247
non‑inverting amplifier 80–81 step response 210–212
open‑loop gain 70–71, 91 time constant 212
output resistance 91 reactance 319–320
saturation 71 capacitor 313–315, 320
slew rate 90 inductor 311–313, 320
summing amplifier 81–82 resistor 310–311, 320
symbol 70 reactive factor 338
virtual short 71–72 reactive power 337
output resistance 91 reference node 41
overdamped resistance 6–7
parallel RLC circuit 279–280, 282–284 color code 416
series RLC circuit 261, 263–268 feedback 73
parallel 14–16
parallel series 12–14
capacitors 203–204 shortcut 160
impedances 317–318 standard values 417
inductors 224–225 Thevenin 156
resistors 14–16 resonant frequency
parallel RLC circuit general RLC circuit 290
characteristic equation 281 parallel RLC circuit 279
critically damped 279–280, 284–286 series RLC circuit 261
damped radian frequency 281, 287 resonant gain 402
natural response 278–280 right‑hand rule 221
neper frequency 279 RL circuit
overdamped 279–280, 282–284 natural response 225–227
resonant frequency 279 natural and step response 229–232
step and natural response 280–281 time constant 227
underdamped 279–280, 285–288 step response 228–229
passband 392 RLC circuit
passive filters 393–397 general 288–291
passive sign convention 4–5 parallel 278–288
path 6, 40, 114 series 260–278
permeability 222, 361 rms see root mean square
permeance 361 root mean square (rms) value 339–340
permittivity 202
phase currents 357 Sallen and Key
phase voltages 350, 352 high‑pass filter 399–400
phasor 308–309 low‑pass filter 397–399
phasor diagram 324 saturation 71
pi see delta second‑order circuit 260
planar circuit 115 secondary 361
polar coordinates 307 sequential switching 238–247
positive phase sequence 350 series resistors 12–14
430 Index
series RLC circuit configurations 349–352

characteristic equation 261 delta 349–350
critically damped 261, 268–271 line currents 354
damped radian frequency 262 line voltages 350, 352
natural response 260–262 phase currents 357
neper frequency 261 phase voltages 350, 352
overdamped 261, 263–268 positive phase sequence 350
step and natural response 273–278 unbalanced 358–360
underdamped 262, 271–273 wye 349–350
short‑circuit analysis 155–156 Thevenin voltage 155
AC circuit 328–330 AC circuits 328–330
short‑circuit current 155–156 three‑phase circuits 347–360
AC circuit 328–330 time constant
single‑pole, double‑throw switch 205 RC circuit 212
single‑pole, single‑throw switch 208 RL circuit 227
sinusoid 308–309 tolerance 416, 419
sinusoidal steady‑state analysis 306 transfer function 391
sinusoidal stead‑state power 337–339 transformation
slew rate 90 delta‑to‑wye 18–20
source transformation 177–179 source 177–179
AC circuits 336 source transformations in AC circuits 336
sources 5–6 wye‑to‑delta 18–20
step and natural response see natural and step transformer
response coefficient of coupling 362
step response dot convention 362–363
parallel RLC circuit 280–281 ideal 366–367
RC circuit 210–212 impedance matching 367
RL circuit 228–229 linear 364–366
series RLC circuit 273–278 mutual inductance 360–362
stopband 392 primary 362
summing amplifier 81–82 secondary 362
variable gain 87 transient response
supermesh 125–128 parallel RLC circuit 280–281
supernode 56–59 RC circuit 214–216
superposition 22–24 RL circuit 229–232, 306–307
susceptance 320 series RLC circuit 273–278
switch
make‑before‑break 226 underdamped
single‑pole, double‑throw 205 parallel RLC circuit 279–280, 285–288
single‑pole, single‑throw 208 series RLC circuit 262, 271–273
tee see wye validity 9–11

test‑source analysis 167–172, 173–177 virtual ground 72
AC circuits 328–330 virtual short 71–72
Thevenin’s theorem 155 Volt 2
AC circuits 328–330 voltage 2
dependent sources 173–177 voltage‑controlled current source (VCCS) 5–6,
independent sources 157–161 133–135
mixed sources 161–173 voltage‑controlled voltage source (VCVS) 5–6,
resistance shortcut analysis 160 49–51, 334–336
short‑circuit analysis 155–156 voltage divider rule 12–14
test‑source analysis 167–172, 173–177 AC circuits 316
Thevenin impedance 328–330
Thevenin resistance 155 Watt 4
balanced delta‑delta 354–357 Wheatstone bridge 18–22
balanced wye‑wye 352–354 wye 18–20, 349–352

A Practical Introduction To Electrical Circuits

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A Practical Introduction

First edition published 2024

and by CRC Press

CRC Press is an imprint of Taylor & Francis Group, LLC

© 2024 John E. Ayers

ISBN: 9781032528151 (hbk)

Access the support material www.routledge.com/9781032528168

Chapter 1 Beginning Concepts and Resistive Circuits..........................................1

Chapter 2 Nodal Analysis....................................................................................40

Chapter 3 Operational Amplifier Circuits........................................................... 70

3.8 Difference Amplifier................................................................ 82

Chapter 4 Mesh Analysis................................................................................... 114

Chapter 5 Thevenin’s and Norton’s Theorems................................................... 155

Chapter 6 First-Order Circuits........................................................................... 201

6.13 General Case of the Natural and Step Response

Chapter 7 Second-Order Circuits.......................................................................260

Chapter 8 Sinusoidal Steady-State Analysis......................................................306

8.10 Maximum Power Transfer in Circuits

Chapter 9 Frequency Response.......................................................................... 391

APPENDIX A: Resistor Color Code..................................................................... 416

1.1 WHY CIRCUIT THEORY IS IMPORTANT

1.2 ASSUMPTIONS OF CIRCUIT THEORY

1.3 CHARGES, VOLTAGES, AND CURRENTS

1.4 POWER, ENERGY, AND THE PASSIVE SIGN CONVENTION

FIGURE 1.4 (a and b) Examples of application of the passive sign convention.

1.5 INDEPENDENT AND DEPENDENT SOURCES

1.6 THE RESISTOR AND OHM’S LAW

1.7 KIRCHHOFF’S CURRENT LAW

FIGURE 1.6 The resistor.

and for node C,

1.8 KIRCHHOFF’S VOLTAGE LAW

Application of KVL to the loop on the lower left yields

and for the loop on the lower right, we obtain

1.9 KIRCHHOFF’S LAWS AND THE VALIDITY

−Vw + Vx − 18 V + 12 V −Vy = 0, (1.20)

FIGURE 1.9 An example circuit for the determination of its validity.

1.5 A − 1A + 0.5 A = 0, (1.23)

FIGURE 1.10 A second circuit for the determination of its validity.

FIGURE 1.11 Two series resistors.

1.10 SERIES RESISTORS AND THE VOLTAGE-DIVIDER RULE

Solving for the current,

FIGURE 1.12 Three series resistors.

The use of Ohm’s law then yields the VDR equations:

1.11 PARALLEL RESISTORS AND THE CURRENT-DIVIDER RULE

By Ohm’s law, we find that

FIGURE 1.13 Two parallel resistors.

We can determine the other currents in a similar fashion:

1.12 SERIES–PARALLEL COMBINATIONS OF RESISTORS

The source current can be found by Ohm’s law:

The voltage VA may be found by using Ohm’s law:

VA = I1 ( 3 Ω ) = ( 0.667 A )( 3 Ω ) = 2.00 V. (1.53)

We can find I 3 and I 4 by two more applications of the CDR:

The voltages VB and VC may be found using Ohm’s law:

VB = I 3 ( 2.5 Ω ) = ( 0.800 A )( 2.5 Ω ) = 2.00 V (1.56)

VC = − I S (1Ω ) = − (1.000 A )(1Ω ) = −1.00 V. (1.57)

FIGURE 1.16 Wheatstone bridge circuit.

1.13 OTHER CONFIGURATIONS AND DELTA–WYE AND

FIGURE 1.17 Delta-to-wye and wye-to-delta transformations.

RCA = R3 + R1. (1.66)

1.9 KIRCHHOFF’S LAWS AND THE VALIDITY

1.13 OTHER CONFIGURATIONS AND DELTA–WYE AND

2.3 THE NODE VOLTAGE METHOD AND

2.4 THE NODE VOLTAGE METHOD WITH