Memory Systems

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NMAM

Institute of Technology

Computer Organization and Architecture


22CS302

Dr. Raghunandan K. R.𝑩.𝑬.,𝑴.𝑻𝒆𝒄𝒉,𝑷𝒉.𝑫


Associate Professor
Department of Computer Science and Engg.
Computer Organization and Architecture 19CS304
Fundamental Concepts
The Memory System
Some basic concepts

• Maximum size of the Main Memory


• byte-addressable
• CPU-Main Memory Connection
Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2 k addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)
Some basic concepts(Contd.,)

 Measures for the speed of a memory:


▪ Memory access time.
▪ Memory cycle time.

 Several techniques to increase the effective


size and speed of the memory:
▪ Cache memory (to increase the effective speed).- Used to reduce MAT
▪ Virtual memory (to increase the effective size).-Used to reduce MCT
Semiconductor RAM memories
The Memory System
Semiconductor RAM memories

• Introduced in the year 1960’s- They were more expensive

• Later it replaced by Magnetic Core memories.

• Mid of 1980’s rapid advance in VLSI technology, the cost of semi-

conductor dropped drastically.

• Available in a wide range of speed.

• Cycle time ranges from 100ns to 10ns


Internal organization of memory chips (Contd.,)

7 7 1 1 0 0
W0




FF FF
A0 W1




A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2
• • • • • •
A3

W15


Sense / Write Sense / Write Sense / Write R /W


circuit circuit circuit
CS

Data input /output lines: b 7 b1 b0


Internal organization of memory chips (Contd.,)
• Each memory cell can hold one bit of information.
• Memory cells are organized in the form of an array. In which each cell
capable of storing one bit of information.
• Each row of cell constitutes a memory word and all cells of a row are
connected to a common line, known as the “word line”. Which is driven
by address decoder.
• Cells in each column are connected to a Sense/Write circuit by 2 bit lines.
• These sense/write circuits are connected to the data input/output lines
of the memory chip.
• READ: Circuit sense/read the information stored in the cells, which is
selected by a word line and transmit the information to the output data
lines.
• WRITE: The sense/Write circuit receives input information from the data
lines and store the information in the selected cells by a word line.
Internal organization of memory chips (Contd.,)
Arrangements:

• Small chip consisting of 16 words of 8 bits data. Which is referred as 16*8

organization(stores 16*8=128 bits)

• External connection= 14

• Address lines=4

• Data lines =8

• Control lines=2

• By default Power supply and Ground connection.


Internal organization of memory chips (Contd.,)

7 7 1 1 0 0
W0




FF FF
A0 W1




A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2
• • • • • •
A3

W15


Sense / Write Sense / Write Sense / Write R /W


circuit circuit circuit
CS

Data input /output lines: b 7 b1 b0


Internal organization of memory chips (Contd.,)
Arrangements:

• Suppose memory circuit stores 1K(1024) bits

• This can be arranged as (128*8=1024)

• External connection= 19

• Address lines=7

• Data lines =8

• Control lines=2

• By default Power supply and Ground connection.


1K*1 MEMORY FORMAT
Internal organization of memory chips (Contd.,)
Arrangements:

• In this 10 bit address is divided into 2 groups of 5 bits each to form the

row and column address

• A row address selects a row of 32 cells ; all of which is accessed in

parallel.

• A column address, only one of these cells are connected to the external

data lines by the output of Multiplexer and input of Demultiplexer.


CMOS(Complementary Metal-Oxide-Semiconductor)

• It is a fundamental building block used in modern digital integrated circuits, particularly in memory

storage devices like SRAM and DRAM.

• CMOS memory cells are designed to store binary data, typically a 0 or 1, in a stable and reliable manner.

Advantages :

• Low power consumption,

• High-speed operation,

• Scalability, making them suitable for a wide range of applications.


CMOS MEMORY CELL
CMOS-How it Works?

CMOS technology relies on two types of complementary transistors:

• NMOS (N-channel Metal-Oxide-Semiconductor) and PMOS (P-channel Metal-Oxide-Semiconductor).

• These transistors are used to control the flow of electrical current in a circuit.

Complementary pairs:

• NMOS and PMOS transistors are used in pairs, with one being the complement of the other.

• When one is on (conducting), the other is off (non-conducting), and vice versa.

• This property is crucial for low power consumption and minimal power leakage in CMOS circuits.
CMOS-How it Works?
Basic operation:

• NMOS transistor: When a voltage is applied to the gate of an NMOS transistor, and it exceeds a certain threshold

voltage, the transistor turns on, allowing current to flow between the source and the drain.

• PMOS transistor: Conversely, a voltage applied to the gate of a PMOS transistor below its threshold voltage turns it on,

allowing current to flow from the source to the drain.

Logic gates:

• CMOS logic gates, such as AND, OR, and NOT gates, are constructed using combinations of NMOS and PMOS transistors.

• For example, an NMOS transistor can be used for the pull-down network of an AND gate, while a PMOS transistor is

used for the pull-up network. This configuration results in the gate being off when the input conditions are not met and

on when they are.

Low power consumption:

• One of the primary advantages of CMOS technology is its low static power consumption.

• When an input is not changing, CMOS gates consume very little power because the complementary transistors ensure

that one of them is off at all times.


SRAM Cell
SRAM Cell
• Two transistor inverters are cross connected to implement a basic flip-flop.
• The cell is connected to one word line and two bits lines by transistors T1 and T2
• When word line is at ground level, the transistors are turned off and the latch
retains its state
• Read operation: In order to read state of SRAM cell, the word line is activated to
close switches T1 and T2. Sense/Write circuits at the bottom monitor the state of b
and b’
b b

T1 T 2
X Y

Word line
Bit lines
DRAM CELL
DRAM-How it Works?
Data Transfer:

Once data is read from a DRAM cell, it can be transferred to the CPU or other parts of the computer for processing. Similarly, data can be written

back to a specific DRAM cell when the CPU wants to store information.

Write operation:

• Transistor T is Turned On and an appropriate voltage is applied at the bit line. This causes the known amount of charge to be stored in the

capacitor.

• When Transistor T is off, the capacitors begin to discharge. This is caused by the capacitors own leakage resistance and by the fact that the

transistors continues to conduct a tiny amount of current ( measured in Picometers) Hence the information stored in the cell can be

retrieved correctly only if it is read before the change on the capacitors drop bellow threshold value.

Read Operation :

• The transistor in a selected cell is turned on.

• The sense amplifier connected to the bit line detects whether the charge stored on the capacitor is above the threshold value. If so it drives

the bit line to full voltage(logic 1).

• If the charge bellow threshold value , it pulls the bit line to ground level with logic 0.
DRAM-How it Works?
Capacitor-Based Storage:

• The fundamental storage element in DRAM is a tiny capacitor paired with a transistor.

• Each cell in a DRAM chip consists of a single capacitor and a single access transistor. The capacitor can be either charged (representing a

binary 1) or uncharged (representing a binary 0).

Refreshing:

• Unlike static memory (SRAM), which retains data as long as power is supplied, DRAM cells store data as electrical charges in the capacitors.

• These charges tend to leak over time due to the electrical properties of the storage capacitors and the transistors.

• To counteract this leakage, DRAM must be constantly refreshed. This means that the data in each DRAM cell needs to be read and then

immediately written back into the cell, effectively restoring the charge, typically several thousand times per second.

Row and Column Access:

• When the CPU needs to read or write data from or to DRAM, it first provides the address of the memory location it needs to access.

Sense Amplifiers:

• After the row and column are selected, a sense amplifier is used to read the charge on the capacitor. A charge in the capacitor is interpreted

as a binary 1, and a lack of charge is interpreted as a binary 0.


Difference Between SRAM and DRAM

SRAM DRAM
◆ Very fast ◆ Slower than SRAM
◆ Very Expensive ◆ Cheaper than SRAM
◆ Used in Cache memory and CPU register ◆ Used in most computer as main
◆ Consist of circuits that are capable of memory
retaining their state as long as the power is ◆ Need to be refreshed periodically
applied.
◆ Do not retain their state
◆ Volatile memories, because their contents indefinitely.
are lost when power is interrupted.
◆ Contents must be periodically
◆ Access times of static RAMs are in the refreshed.
range of few nanoseconds.
◆ Contents may be refreshed while
◆ However, the cost is usually high accessing them for reading.
Dynamic RAMs (DRAMs):

• Asynchronous Dynamic RAMs (DRAMs)


• Synchronous Dynamic RAMs (SDRAMs)
Synchronous DRAM V/S Asynchronous DRAM

Synchronous DRAM Asynchronous DRAM


◆ Synchronous DRAM uses the system ◆ Asynchronous DRAM does not use the
clock to coordinate the memory system clock to coordinate the memory
access while access.
◆ System clock is needed to coordinate ◆ Does not use System clock to coordinate
the memory access the memory access
◆ Provide High performance and better ◆ Provide low performance
control
◆ Modern PC with high speed memory ◆ Traditional PC with low speed memory
uses Synchronous DRAM uses Asynchronous DRAM
◆ Faster and Efficient ◆ Slower
Asynchronous DRAMs
• Internal Organization of 2M*8(16 megabit memory chip)

• Memory is organized as 4K*4K array


• { 4096 rows* 512 columns}➔ 12 bit+9 bits➔21 bits
Asynchronous DRAMs

RAS • Each row can store 512 bytes.


12 bits to select a row, and 9
Row Row 4096 (512  8) bits to select a group in a row.
address
latch decoder cell array Total of 21 bits.
• First apply the row address,
RAS signal latches the row
address. Then apply the
A 20 - 9  A 8 - 0 Sense / Write CS
circuits column address, CAS signal
R /W
latches the address.
• Timing of the memory unit is
Column
address Column controlled by a specialized unit
decoder
latch which generates RAS and CAS.
• This is asynchronous DRAM
CAS D7 D0
Fast page mode feature
 Suppose if we want to access the consecutive bytes in the selected row.

 Then following actions can be done without having to reselect the row.

▪ Add a latch at the output of the sense circuits in each row.

▪ All the latches are loaded when the row is selected.

▪ Different column addresses can be applied to select and place different bytes on the
data lines.

 Consecutive sequence of column addresses can be applied under the control signal CAS,
without reselecting the row.

▪ Allows a block of data to be transferred at a much faster rate than random accesses.

▪ A small collection/group of bytes is usually referred to as a block.

 This transfer capability is referred to as the fast page mode feature.


Synchronous DRAMs

Refresh
counter

Row
address Ro w
decoder Cell array
latch
Row/Column
address ◆ Synchronous DRAM
Column Co lumn ◆ Need clock signal for
address Read/Write
decoder circuits & latches synchronize operation
counter
◆ Can be used with clock speed
100 and 133 MHz
◆ Built in refresh circuitry
Clock
RAS Mode register
CA S and Data input Data output
register register
R /W timing control

CS

Data
Synchronous DRAMs
•Operation is directly synchronized
with processor clock signal.
Refresh •The outputs of the sense circuits are
counter
connected to a latch.
•During a Read operation, the
contents of the cells in a row are
Row
address Ro w
Cell array
loaded onto the latches.
decoder
latch •During a refresh operation, the
Row/Column
contents of the cells are refreshed
address
Column
without changing the contents of
Co lumn Read/Write
address
decoder circuits & latches the latches.
counter
•Data held in the latches correspond
to the selected columns are transferred
to the output.
Clock
•For a burst mode of operation,
RAS Mode register
Data input Data output successive columns are selected using
CA S and
R /W timing control
register register column address counter and clock.
CS
CAS signal need not be generated
externally. A new data is placed during
raising edge of the clock
Data
Synchronous DRAM V/S Asynchronous DRAM

Synchronous DRAM Asynchronous DRAM


◆ Synchronous DRAM uses the system ◆ Asynchronous DRAM does not use the
clock to coordinate the memory system clock to coordinate the memory
access while access.
◆ System clock is needed to coordinate ◆ Does not use System clock to coordinate
the memory access the memory access
◆ Provide High performance and better ◆ Provide low performance
control
◆ Modern PC with high speed memory ◆ Traditional PC with low speed memory
uses Synchronous DRAM uses Asynchronous DRAM
◆ Faster and Efficient ◆ Slower
Read-Only Memories (ROMs)
The Memory System
Read-Only Memories (ROMs) Comparisons

PROM EPROM EEPROM FLASH DRIVES

Programming Can be programmed only Can be programmed, Can be electrically Electrically


: once, typically during erased, and reprogrammed programmed and erased programmable and
manufacturing using UV light exposure without UV light. erasable in blocks

Erasability: Not erasable or Requires UV light exposure Can be electrically erased Erased and
reprogrammable for erasure. and reprogrammed reprogrammed in
multiple times. blocks

Data Data is permanent and Can be reprogrammed Retains data without Retains data
Persistence: can't be changed multiple times until the power and can be without power,
end of its life cycle. updated as needed. used for large-scale
data storage.

Use Cases Typically used for fixed Used in early computers Commonly used for USB flash drives,
firmware or software that and embedded systems storing configuration solid-state drives
doesn't need to be where infrequent updates settings, BIOS data, and (SSDs), memory
updated. are required. small firmware updates. cards, and other
mass storage
applications.
Read-Only Memories (ROMs) Comparisons

• Programming Method: PROM, EPROM, and EEPROM use electrical programming,


while Flash drives use NAND flash memory, which is also electrically
programmable.

• Erasability: PROM is not erasable, EPROM requires UV light for erasure, EEPROM is
electrically erasable, and Flash drives are electrically erasable in blocks.

• Data Persistence: PROM and EPROM are non-volatile but non-reprogrammable.


EEPROM and Flash drives are non-volatile and reprogrammable.

• Use Cases: PROM is used for one-time programming, EPROM for applications with
occasional updates, EEPROM for data that may change over time (like BIOS
settings), and Flash drives for mass storage.
Memory Hierarchy
Pr ocessor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing Increasing Increasing •Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk that will be used in the near future as
secondary close to the processor as possible.
memory
Cache Memories
The Memory System
Cache Memories
 Processor is much faster than the main memory.

▪ As a result, the processor has to spend much of its time waiting while
instructions and data are being fetched from the main memory.

▪ Major obstacle towards achieving good performance.


 Speed of the main memory cannot be increased beyond a certain point.

 Cache memory is an architectural arrangement which makes the main memory


appear faster to the processor than it really is.
 Cache memory is based on the property of computer programs known as
“locality of reference”.
Locality of Reference
 Analysis of programs indicates that many instructions in localized areas of a
program are executed repeatedly during some period of time, while the others
are accessed relatively less frequently.
▪ These instructions may be the ones in a loop, nested loop or few procedures
calling each other repeatedly.
▪ This is called “locality of reference”.
 Temporal locality of reference:
▪ Recently executed instruction is likely to be executed again very soon.
 Spatial locality of reference:
▪ Instructions with addresses close to a recently instruction are likely
to be executed soon.
Cache memories

Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred from the main memory to
the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the cache.
• At any given time, only some blocks in the main memory are held in the cache. Which
blocks in the main memory are in the cache is determined by a “mapping function”.
• When the cache is full, and a block of words needs to be transferred from the main
memory, some block of words in the cache must be replaced. This is determined by a
“replacement algorithm”.
Cache hit
• Existence of a cache is transparent to the processor. The processor issues Read and
Write requests in the same manner.
• If the data is in the cache it is called a Read or Write hit.
• Read hit:

▪ The data is obtained from the cache.


• Write hit:

▪ Cache has a replica of the contents of the main memory.

▪ Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.

▪ Update the contents of the cache, and mark it as updated by setting a bit known
as the dirty bit or modified bit. The contents of the main memory are updated
when this block is replaced. This is write-back or copy-back protocol.
Hit Rate and Miss Penalty
• Hit rate :The cache hit rate is the percentage of requests for data that can be
served by the cache, rather than having to be retrieved from the Backing store.

• A hit ratio is a calculation of cache hits, and comparing them with how many total
content requests were received.

• A miss ratio is the flip side of this where the cache misses are calculated and
compared with the total number of content requests that were received

• Miss penalty: Miss Penalty refers to the extra time required to bring the data into
cache from the Main memory whenever there is a “miss” in the cache

• Hit rate can be improved by increasing block size, while keeping cache size
constant

• Miss penalty can be reduced if load-through approach is used when loading new
blocks into cache.
Cache miss
• If the data is not present in the cache, then a Read miss or Write miss occurs.
• Read miss:

▪ Block of words containing this requested word is transferred from the memory.

▪ After the block is transferred, the desired word is forwarded to the processor.

▪ The desired word may also be forwarded to the processor as soon as it is


transferred without waiting for the entire block to be transferred. This is called
load-through or early-restart.
• Write-miss:

▪ Write-through protocol is used, then the contents of the main memory are
updated directly.

▪ If write-back protocol is used, the block containing the addressed word is first
brought into the cache. The desired word is overwritten with new information.
Cache Coherence Problem
• A bit called as “valid bit/Dirty bit” is provided for each block.

• If the block contains valid data, then the bit is set to 1, else it is 0.

• Valid bits are set to 0, when the power is just turned on.

• When a block is loaded into the cache for the first time, the valid bit is set to 1.

• Data transfers between main memory and disk occur directly bypassing the cache.

• When the data on a disk changes, the main memory block is also updated.

• However, if the data is also resident in the cache, then the valid bit is set to 0.

• What happens if the data in the disk and main memory changes and the write-back

protocol is being used?

• In this case, the data in the cache may also have changed and is indicated by the

dirty bit.

• The copies of the data in the cache, and the main memory are different. This is
EAT(effective access time)=
• A single-level cache is pretty easy to model mathematically.
• Each access is either a hit or a miss, so Average memory access time (AMAT) is:
EAT(effective access time)= Emat = hit time + miss rate * miss penalty

=Hc+(1-h)M

=p*m +(1-p)*S

=P x hit memory time + (1-P) x miss memory time.

Where: P is Hit ratio.

A computer has single cache with 2ns hit time and 98%hit rate. Main memory has 40ns
access time what is Effective Access Time?
A computer has single cache with 2ns hit time and 98%hit rate.
Main memory has 40ns access time what is Effective Access Time?
????
2 ns + .02 * 40 ns = 2.8 ns

If we add an on-chip cache with a .5 ns hit time and a 94% hit rate,
what is the computer’s effective access time? How much of a
speedup does the on-chip cache give the computer?

➔ With the on-chip cache, we have .5 ns + .06 * (2 ns + .02 * 40 ns) = .668 ns. The
speedup is 2.8 / .668 = 4.2.
Caches on the processor chip

• In high performance processors 2 levels of


caches are normally used.
• Avg access time in a system with 2 levels of
caches is
T ave = h1c1+(1-h1)h2c2+(1-h1)(1-h2)M
The Memory System
PAGE REPLACEMNET ALGORITHMS
Page Fault:

• A page fault happens when a running program accesses a memory page that
is mapped into the virtual address space but not loaded in physical
memory. Since actual physical memory is much smaller than virtual memory,
page faults happen.

• In case of a page fault, Operating System might have to replace one of the
existing pages with the newly needed page.

• Different page replacement algorithms suggest different ways to decide


which page to replace.

• The target for all algorithms is to reduce the number of page faults.
Page Replacement Algorithms:

• First In First Out (FIFO): This is the simplest page replacement algorithm. In this
algorithm, the operating system keeps track of all pages in the memory in a queue, the
oldest page is in the front of the queue. When a page needs to be replaced page in the
front of the queue is selected for removal.

Example 1: Consider page reference string 1, 3, 0, 3, 5, 6, 3 with 3 page frames. Find the
number of page faults.
Page Replacement Algorithms:

• Least Recently Used: In this algorithm, page will be replaced which is least
recently used.

• Example-: Consider the page reference string 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2,


3 with 4 page frames. Find number of page faults.
Page Replacement Algorithms:

• Optimal Page replacement: In this algorithm, pages are replaced which


would not be used for the longest duration of time in the future.

• Example-2: Consider the page references 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 3


with 4 page frame. Find number of page fault.
PROBLEMs on Page Replacement Algorithms:

Given page reference string: 1,2,3,4,2,1,5,6,2,1,2,3,7,6,3,2,1,2,3,6.


Compare the number of page faults for LRU, FIFO and Optimal page
replacement algorithm
Mapping functions

 Mapping functions determine how memory


blocks are placed in the cache.
 A simple processor example:
▪ Cache consisting of 128 blocks of 16 words each.
▪ Total size of cache is 2048 (2K) words.
▪ Main memory is addressable by a 16-bit address.
▪ Main memory has 64K words.
▪ Main memory has 4K blocks of 16 words each.
 Three mapping functions:
▪ Direct mapping
▪ Associative mapping
▪ Set-associative mapping.
Direct mapping
Main
memory Block 0 •Block j of the main memory maps to j modulo 128 of
the cache. 0 maps to 0, 129 maps to 1.
Cache Block 1
•More than one memory block is mapped onto the same
tag
Block 0 position in the cache.
tag
Block 1 •May lead to contention for cache blocks even if the
cache is not full.
Block 127 •Resolve the contention by allowing new block to
Block 128 replace the old block, leading to a trivial replacement
tag algorithm.
Block 127 Block 129
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Tag Block Word
Block 255 the the next 7 bits determine which cache
5 7 4 Block 256 block this new block is placed in.
- High order 5 bits determine which of the possible
Main memory address Block 257
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.

Block 4095
Associative mapping
Main Block 0
memory

Cache Block 1
tag
Block 0 •Main memory block can be placed into any cache
tag
Block 1
position.
•Memory address is divided into two fields:
Block 127 - Low order 4 bits identify the word within a block.
Block 128 - High order 12 bits or tag bits identify a memory
tag block when it is resident in the cache.
Block 127 Block 129
•Flexible, and uses cache space efficiently.
•Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
Word
Block 255 the need to search all 128 patterns to determine
Tag
12 4 Block 256 whether a given block is in the cache.

Main memory address Block 257

Block 4095
Set-Associative mapping

Cache
Main
memory Block 0 Blocks of cache are grouped into sets.
tag Block 0 Mapping function allows a block of the main
Block 1
tag Block 1
memory to reside in any block of a specific set.
Divide the cache into 64 sets, with two blocks per set.
tag Block 2
Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63
Memory address is divided into three fields:
Block 64 - 6 bit field determines the set number.
tag
Block 126 Block 65 - High order 6 bit fields are compared to the tag
fields of the two blocks in a set.
tag Set-associative mapping combination of direct and
Block 127
associative mapping.
Number of blocks per set is a design parameter.
Block 127
Tag Block Word - One extreme is to have all the blocks in one set,
6 6 4 Block 128 requiring no set bits (fully associative mapping).
Main memory address Block 129 - Other extreme is to have one block per set, is
the same as direct mapping.

Block 4095
Performance considerations
The Memory System
Performance considerations

• A key design objective of a computer system is to achieve the


best possible performance at the lowest possible cost.
– Price/performance ratio is a common measure of success.
• Performance of a processor depends on:
– How fast machine instructions can be brought into the processor for
execution.
– How fast the instructions can be executed.
Interleaving

 Divides the memory system into a number of memory


modules. Each module has its own address buffer register
(ABR) and data buffer register (DBR).
 Arranges addressing so that successive words in the
address space are placed in different modules.
 When requests for memory access involve consecutive
addresses, the access will be to different modules.
 Since parallel access to these modules is possible, the
average rate of fetching words from the Main Memory can
be increased.
Consecutive words in a module
k bits m bits

Module Address in module MM address

ABR DBR ABR DBR ABR DBR

Module Module Module

0 i n- 1
Consecutive words in consecutive module

m bits k bits

Address in module Module MM address

ABR DBR ABR DBR ABR DBR

Module Module Module


k
0 i 2 - 1
Methods of address layouts

k bits mbits
mbits k bits
Module Address in module MM address
Address in module Module MM address

ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR

Module Module Module Module Module Module


k
0 i n- 1 0 i 2 - 1

 Consecutive words are placed in a •Consecutive words are located in


module. consecutive modules.
 High-order k bits of a memory address
determine the module. •Consecutive addresses can be located in
 Low-order m bits of a memory address consecutive modules.
determine the word within a module. •While transferring a block of data, several
 When a block of words is transferred memory modules can be kept busy at the
from main memory to cache, only one
module is busy at a time. same time.
Other Performance Enhancements
Write buffer
 Write-through:
• Each write operation involves writing to the main memory.
• If the processor has to wait for the write operation to be complete, it slows
down the processor.
• Processor does not depend on the results of the write operation.
• Write buffer can be included for temporary storage of write requests.
• Processor places each write request into the buffer and continues execution.
• If a subsequent Read request references data which is still in the write buffer,
then this data is referenced in the write buffer.
 Write-back:
• Block is written back to the main memory when it is replaced.
• If the processor waits for this write to complete, before reading the new block,
it is slowed down.
• Fast write buffer can hold the block to be written, and the new
block can be read first.
Virtual Memory
The Memory System
Address translation (contd..)

• Concepts of virtual memory are similar to the


concepts of cache memory.
• Cache memory:
– Introduced to bridge the speed gap between the processor and the main
memory.
– Implemented in hardware.

• Virtual memory:
– Introduced to bridge the speed gap between the main memory and secondary
storage.
– Implemented in part by software.

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Virtual memories

 Recall that an important challenge in the design


of a computer system is to provide a large, fast
memory system at an affordable cost.
 Architectural solutions to increase the effective
speed and size of the memory system.
 Cache memories were developed to increase the
effective speed of the memory system.
 Virtual memory is an architectural solution to
increase the effective size of the memory system.

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Virtual memory organization
Processor

Virtual address

Data MMU

Physical address

Cache

Data Physical address

Main memory

DMA transfer

Disk storage

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Address translation (contd..)
PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as page
+ number and offset.
PAGE TABLE
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.

Page table holds information


about each page. This includes
the starting address of the page
in the main memory. Control Page frame
bits in memory Page frame Offset

Physical address in main memory

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Address translation Using TLB
Address translation (contd..)
Virtual address from processor

Virtual page number Offset TLB


High-order bits of the virtual address
generated by the processor select the
TLB
virtual page.
Virtual page Control Page frame
number bits in memory These bits are compared to the virtual
page numbers in the TLB.
If there is a match, a hit occurs and
the corresponding address of the page
No frame is read.
=?
If there is no match, a miss occurs
Yes
and the page table within the main
Miss
memory must be consulted.
Hit

Page frame Offset

Physical address in main memory

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Address translation (contd..)

 What happens if a program generates an


access to a page that is not in the main
memory?
 In this case, a page fault is said to occur.
▪ Whole page must be brought into the main memory from the disk, before
the execution can proceed.

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 Upon detecting a page fault by the MMU, following actions occur:
▪ MMU asks the operating system to intervene by raising an exception.
▪ Processing of the active task which caused the page fault is interrupted.
▪ Control is transferred to the operating system.
▪ Operating system copies the requested page from secondary storage to the main
memory.
▪ Once the page is copied, control is returned to the task which was interrupted.
Address translation (contd..)

 When a new page is to be brought into the main


memory from secondary storage, the main memory
may be full.
▪ Some page from the main memory must be replaced with this new page.
 How to choose which page to replace?
▪ This is similar to the replacement that occurs when the cache is full.
▪ The principle of locality of reference (?) can also be applied here.
▪ A replacement strategy similar to LRU can be applied.
 Since the size of the main memory is relatively larger
compared to cache, a relatively large amount of
programs and data can be held in the main memory.
▪ Minimizes the frequency of transfers between secondary storage and main memory.

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Address translation (contd..)

 A page may be modified during its residency in


the main memory.
 When should the page be written back to the
secondary storage?
 Recall that we encountered a similar problem in
the context of cache and main memory:
▪ Write-through protocol(?)
▪ Write-back protocol(?)
 Write-through protocol cannot be used, since it
will incur a long delay each time a small amount
of data is written to the disk.

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END

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