Memory Systems
Memory Systems
Memory Systems
Institute of Technology
Control lines
( R / W, MFC, etc.)
Some basic concepts(Contd.,)
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Address Memory
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decoder • • • • • •
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• External connection= 14
• Address lines=4
• Data lines =8
• Control lines=2
7 7 1 1 0 0
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Address Memory
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decoder • • • • • •
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• External connection= 19
• Address lines=7
• Data lines =8
• Control lines=2
• In this 10 bit address is divided into 2 groups of 5 bits each to form the
parallel.
• A column address, only one of these cells are connected to the external
• It is a fundamental building block used in modern digital integrated circuits, particularly in memory
• CMOS memory cells are designed to store binary data, typically a 0 or 1, in a stable and reliable manner.
Advantages :
• High-speed operation,
• These transistors are used to control the flow of electrical current in a circuit.
Complementary pairs:
• NMOS and PMOS transistors are used in pairs, with one being the complement of the other.
• When one is on (conducting), the other is off (non-conducting), and vice versa.
• This property is crucial for low power consumption and minimal power leakage in CMOS circuits.
CMOS-How it Works?
Basic operation:
• NMOS transistor: When a voltage is applied to the gate of an NMOS transistor, and it exceeds a certain threshold
voltage, the transistor turns on, allowing current to flow between the source and the drain.
• PMOS transistor: Conversely, a voltage applied to the gate of a PMOS transistor below its threshold voltage turns it on,
Logic gates:
• CMOS logic gates, such as AND, OR, and NOT gates, are constructed using combinations of NMOS and PMOS transistors.
• For example, an NMOS transistor can be used for the pull-down network of an AND gate, while a PMOS transistor is
used for the pull-up network. This configuration results in the gate being off when the input conditions are not met and
• One of the primary advantages of CMOS technology is its low static power consumption.
• When an input is not changing, CMOS gates consume very little power because the complementary transistors ensure
T1 T 2
X Y
Word line
Bit lines
DRAM CELL
DRAM-How it Works?
Data Transfer:
Once data is read from a DRAM cell, it can be transferred to the CPU or other parts of the computer for processing. Similarly, data can be written
back to a specific DRAM cell when the CPU wants to store information.
Write operation:
• Transistor T is Turned On and an appropriate voltage is applied at the bit line. This causes the known amount of charge to be stored in the
capacitor.
• When Transistor T is off, the capacitors begin to discharge. This is caused by the capacitors own leakage resistance and by the fact that the
transistors continues to conduct a tiny amount of current ( measured in Picometers) Hence the information stored in the cell can be
retrieved correctly only if it is read before the change on the capacitors drop bellow threshold value.
Read Operation :
• The sense amplifier connected to the bit line detects whether the charge stored on the capacitor is above the threshold value. If so it drives
• If the charge bellow threshold value , it pulls the bit line to ground level with logic 0.
DRAM-How it Works?
Capacitor-Based Storage:
• The fundamental storage element in DRAM is a tiny capacitor paired with a transistor.
• Each cell in a DRAM chip consists of a single capacitor and a single access transistor. The capacitor can be either charged (representing a
Refreshing:
• Unlike static memory (SRAM), which retains data as long as power is supplied, DRAM cells store data as electrical charges in the capacitors.
• These charges tend to leak over time due to the electrical properties of the storage capacitors and the transistors.
• To counteract this leakage, DRAM must be constantly refreshed. This means that the data in each DRAM cell needs to be read and then
immediately written back into the cell, effectively restoring the charge, typically several thousand times per second.
• When the CPU needs to read or write data from or to DRAM, it first provides the address of the memory location it needs to access.
Sense Amplifiers:
• After the row and column are selected, a sense amplifier is used to read the charge on the capacitor. A charge in the capacitor is interpreted
SRAM DRAM
◆ Very fast ◆ Slower than SRAM
◆ Very Expensive ◆ Cheaper than SRAM
◆ Used in Cache memory and CPU register ◆ Used in most computer as main
◆ Consist of circuits that are capable of memory
retaining their state as long as the power is ◆ Need to be refreshed periodically
applied.
◆ Do not retain their state
◆ Volatile memories, because their contents indefinitely.
are lost when power is interrupted.
◆ Contents must be periodically
◆ Access times of static RAMs are in the refreshed.
range of few nanoseconds.
◆ Contents may be refreshed while
◆ However, the cost is usually high accessing them for reading.
Dynamic RAMs (DRAMs):
Then following actions can be done without having to reselect the row.
▪ Different column addresses can be applied to select and place different bytes on the
data lines.
Consecutive sequence of column addresses can be applied under the control signal CAS,
without reselecting the row.
▪ Allows a block of data to be transferred at a much faster rate than random accesses.
Refresh
counter
Row
address Ro w
decoder Cell array
latch
Row/Column
address ◆ Synchronous DRAM
Column Co lumn ◆ Need clock signal for
address Read/Write
decoder circuits & latches synchronize operation
counter
◆ Can be used with clock speed
100 and 133 MHz
◆ Built in refresh circuitry
Clock
RAS Mode register
CA S and Data input Data output
register register
R /W timing control
CS
Data
Synchronous DRAMs
•Operation is directly synchronized
with processor clock signal.
Refresh •The outputs of the sense circuits are
counter
connected to a latch.
•During a Read operation, the
contents of the cells in a row are
Row
address Ro w
Cell array
loaded onto the latches.
decoder
latch •During a refresh operation, the
Row/Column
contents of the cells are refreshed
address
Column
without changing the contents of
Co lumn Read/Write
address
decoder circuits & latches the latches.
counter
•Data held in the latches correspond
to the selected columns are transferred
to the output.
Clock
•For a burst mode of operation,
RAS Mode register
Data input Data output successive columns are selected using
CA S and
R /W timing control
register register column address counter and clock.
CS
CAS signal need not be generated
externally. A new data is placed during
raising edge of the clock
Data
Synchronous DRAM V/S Asynchronous DRAM
Erasability: Not erasable or Requires UV light exposure Can be electrically erased Erased and
reprogrammable for erasure. and reprogrammed reprogrammed in
multiple times. blocks
Data Data is permanent and Can be reprogrammed Retains data without Retains data
Persistence: can't be changed multiple times until the power and can be without power,
end of its life cycle. updated as needed. used for large-scale
data storage.
Use Cases Typically used for fixed Used in early computers Commonly used for USB flash drives,
firmware or software that and embedded systems storing configuration solid-state drives
doesn't need to be where infrequent updates settings, BIOS data, and (SSDs), memory
updated. are required. small firmware updates. cards, and other
mass storage
applications.
Read-Only Memories (ROMs) Comparisons
• Erasability: PROM is not erasable, EPROM requires UV light for erasure, EEPROM is
electrically erasable, and Flash drives are electrically erasable in blocks.
• Use Cases: PROM is used for one-time programming, EPROM for applications with
occasional updates, EEPROM for data that may change over time (like BIOS
settings), and Flash drives for mass storage.
Memory Hierarchy
Pr ocessor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing Increasing Increasing •Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk that will be used in the near future as
secondary close to the processor as possible.
memory
Cache Memories
The Memory System
Cache Memories
Processor is much faster than the main memory.
▪ As a result, the processor has to spend much of its time waiting while
instructions and data are being fetched from the main memory.
Main
Processor Cache memory
• Processor issues a Read request, a block of words is transferred from the main memory to
the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the cache.
• At any given time, only some blocks in the main memory are held in the cache. Which
blocks in the main memory are in the cache is determined by a “mapping function”.
• When the cache is full, and a block of words needs to be transferred from the main
memory, some block of words in the cache must be replaced. This is determined by a
“replacement algorithm”.
Cache hit
• Existence of a cache is transparent to the processor. The processor issues Read and
Write requests in the same manner.
• If the data is in the cache it is called a Read or Write hit.
• Read hit:
▪ Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
▪ Update the contents of the cache, and mark it as updated by setting a bit known
as the dirty bit or modified bit. The contents of the main memory are updated
when this block is replaced. This is write-back or copy-back protocol.
Hit Rate and Miss Penalty
• Hit rate :The cache hit rate is the percentage of requests for data that can be
served by the cache, rather than having to be retrieved from the Backing store.
• A hit ratio is a calculation of cache hits, and comparing them with how many total
content requests were received.
• A miss ratio is the flip side of this where the cache misses are calculated and
compared with the total number of content requests that were received
• Miss penalty: Miss Penalty refers to the extra time required to bring the data into
cache from the Main memory whenever there is a “miss” in the cache
• Hit rate can be improved by increasing block size, while keeping cache size
constant
• Miss penalty can be reduced if load-through approach is used when loading new
blocks into cache.
Cache miss
• If the data is not present in the cache, then a Read miss or Write miss occurs.
• Read miss:
▪ Block of words containing this requested word is transferred from the memory.
▪ After the block is transferred, the desired word is forwarded to the processor.
▪ Write-through protocol is used, then the contents of the main memory are
updated directly.
▪ If write-back protocol is used, the block containing the addressed word is first
brought into the cache. The desired word is overwritten with new information.
Cache Coherence Problem
• A bit called as “valid bit/Dirty bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to 1.
• Data transfers between main memory and disk occur directly bypassing the cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.
• What happens if the data in the disk and main memory changes and the write-back
• In this case, the data in the cache may also have changed and is indicated by the
dirty bit.
• The copies of the data in the cache, and the main memory are different. This is
EAT(effective access time)=
• A single-level cache is pretty easy to model mathematically.
• Each access is either a hit or a miss, so Average memory access time (AMAT) is:
EAT(effective access time)= Emat = hit time + miss rate * miss penalty
=Hc+(1-h)M
=p*m +(1-p)*S
A computer has single cache with 2ns hit time and 98%hit rate. Main memory has 40ns
access time what is Effective Access Time?
A computer has single cache with 2ns hit time and 98%hit rate.
Main memory has 40ns access time what is Effective Access Time?
????
2 ns + .02 * 40 ns = 2.8 ns
If we add an on-chip cache with a .5 ns hit time and a 94% hit rate,
what is the computer’s effective access time? How much of a
speedup does the on-chip cache give the computer?
➔ With the on-chip cache, we have .5 ns + .06 * (2 ns + .02 * 40 ns) = .668 ns. The
speedup is 2.8 / .668 = 4.2.
Caches on the processor chip
• A page fault happens when a running program accesses a memory page that
is mapped into the virtual address space but not loaded in physical
memory. Since actual physical memory is much smaller than virtual memory,
page faults happen.
• In case of a page fault, Operating System might have to replace one of the
existing pages with the newly needed page.
• The target for all algorithms is to reduce the number of page faults.
Page Replacement Algorithms:
• First In First Out (FIFO): This is the simplest page replacement algorithm. In this
algorithm, the operating system keeps track of all pages in the memory in a queue, the
oldest page is in the front of the queue. When a page needs to be replaced page in the
front of the queue is selected for removal.
Example 1: Consider page reference string 1, 3, 0, 3, 5, 6, 3 with 3 page frames. Find the
number of page faults.
Page Replacement Algorithms:
• Least Recently Used: In this algorithm, page will be replaced which is least
recently used.
Block 4095
Associative mapping
Main Block 0
memory
Cache Block 1
tag
Block 0 •Main memory block can be placed into any cache
tag
Block 1
position.
•Memory address is divided into two fields:
Block 127 - Low order 4 bits identify the word within a block.
Block 128 - High order 12 bits or tag bits identify a memory
tag block when it is resident in the cache.
Block 127 Block 129
•Flexible, and uses cache space efficiently.
•Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
Word
Block 255 the need to search all 128 patterns to determine
Tag
12 4 Block 256 whether a given block is in the cache.
Block 4095
Set-Associative mapping
Cache
Main
memory Block 0 Blocks of cache are grouped into sets.
tag Block 0 Mapping function allows a block of the main
Block 1
tag Block 1
memory to reside in any block of a specific set.
Divide the cache into 64 sets, with two blocks per set.
tag Block 2
Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63
Memory address is divided into three fields:
Block 64 - 6 bit field determines the set number.
tag
Block 126 Block 65 - High order 6 bit fields are compared to the tag
fields of the two blocks in a set.
tag Set-associative mapping combination of direct and
Block 127
associative mapping.
Number of blocks per set is a design parameter.
Block 127
Tag Block Word - One extreme is to have all the blocks in one set,
6 6 4 Block 128 requiring no set bits (fully associative mapping).
Main memory address Block 129 - Other extreme is to have one block per set, is
the same as direct mapping.
Block 4095
Performance considerations
The Memory System
Performance considerations
0 i n- 1
Consecutive words in consecutive module
m bits k bits
k bits mbits
mbits k bits
Module Address in module MM address
Address in module Module MM address
ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR
• Virtual memory:
– Introduced to bridge the speed gap between the main memory and secondary
storage.
– Implemented in part by software.
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Virtual memories
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Virtual memory organization
Processor
Virtual address
Data MMU
Physical address
Cache
Main memory
DMA transfer
Disk storage
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Address translation (contd..)
PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as page
+ number and offset.
PAGE TABLE
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.
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Address translation Using TLB
Address translation (contd..)
Virtual address from processor
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Address translation (contd..)
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Upon detecting a page fault by the MMU, following actions occur:
▪ MMU asks the operating system to intervene by raising an exception.
▪ Processing of the active task which caused the page fault is interrupted.
▪ Control is transferred to the operating system.
▪ Operating system copies the requested page from secondary storage to the main
memory.
▪ Once the page is copied, control is returned to the task which was interrupted.
Address translation (contd..)
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Address translation (contd..)
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END
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