Fundamental Concepts
Fundamental Concepts
Fundamental Concepts
Control lines
( R / W, MFC, etc.)
Measures for the speed of a memory:
memory access time.
memory cycle time.
An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost
target.
Several techniques to increase the
effective size and speed of the memory:
Cache memory (to increase the effective speed).
Virtual memory (to increase the effective size).
Semiconductor RAM memories
Each memory cell can hold one bit of information.
Memory cells are organized in the form of an array.
One row is one memory word.
All cells of a row are connected to a common line, known as
the “word line”.
Word line is connected to the address decoder.
Sense/write circuits are connected to the data input/output
lines of the memory chip.
7 7 1 1 0 0
W0
•
•
•
FF FF
A0 W1
•
•
•
A1
Address Memory
• • • • • •
decoder • • • • • • cells
A2 • • • • • •
A3
W15
•
•
•
T1 T2
Word line
Bit lines
Static RAMs (SRAMs):
Consist of circuits that are capable of retaining their state as long as the
power is applied.
Volatile memories, because their contents are lost when power is
interrupted.
Access times of static RAMs are in the range of few nanoseconds.
However, the cost is usually high.
Dynamic RAMs (DRAMs):
Do not retain their state indefinitely.
Contents must be periodically refreshed.
Contents may be refreshed while accessing them for reading.
Each row can store 512
RAS bytes. 12 bits to select a
row, and 9 bits to select a
Row group in a row. Total of 21
address Row 4096 512 8
latch decoder cell array bits.
• First apply the row
address, RAS signal
latches the row address.
A20 - 9 A8 - 0 Sense / Write CS Then apply the column
circuits
R/ W address, CAS signal
latches the address.
• Timing of the memory unit
Column
address Column is controlled by a
decoder
latch specialized unit which
generates RAS and CAS.
CAS D7 D0 • This is asynchronous
DRAM
Suppose if we want to access the consecutive bytes
in the selected row.
This can be done without having to reselect the row.
Add a latch at the output of the sense circuits in each row.
All the latches are loaded when the row is selected.
Different column addresses can be applied to select and place different
bytes on the data lines.
Consecutive sequence of column addresses can be
applied under the control signal CAS, without
reselecting the row.
Allows a block of data to be transferred at a much faster rate than random
accesses.
A small collection/group of bytes is usually referred to as a block.
This transfer capability is referred to as the
fast page mode feature.
•Operation is directly synchronized
Refresh
counter with processor clock signal.
•The outputs of the sense circuits are
connected to a latch.
Row
•During a Read operation, the
Row
address decoder Cell array contents of the cells in a row are
latch
Row/Column loaded onto the latches.
address •During a refresh operation, the
Column Column Read/Write contents of the cells are refreshed
address
counter decoder circuits & latches without changing the contents of
the latches.
•Data held in the latches correspond
Clock
to the selected columns are transferred
R AS to the output.
Mode register
CAS and Data input Data output •For a burst mode of operation,
register register
R/ W timing control successive columns are selected using
CS column address counter and clock.
CAS signal need not be generated
externally. A new data is placed during
Data
raising edge of the clock
Memory latency is the time it takes to
transfer a word of data to or from memory
Memory bandwidth is the number of bits
or bytes that can be transferred in one
second.
DDRSDRAMs
Cell array is organized in two banks
21-bit
A0
addresses 19-bit internal chip address Implement a memory unit of 2M
A1 words of 32 bits each.
Use 512x8 static memory chips.
A19
A20
Each column consists of 4 chips.
Each chip implements one byte
position.
A chip is selected by setting its
chip select control line to 1.
Selected chip places its data on the
2-bit
decoder data output line, outputs of other
chips are in high impedance state.
21 bits to address a 32-bit word.
High order 2 bits are needed to
512K 8
memory chip
D31-24 D23-16 D 15-8 D7-0
select the row, by activating the
four Chip Select signals.
512K 8 memory chip
19 bits are used to access specific
byte locations inside the selected
19-bit 8-bit data
address input/output chip.
Chip select
Large dynamic memory systems can be
implemented using DRAM chips in a similar way
to static memory systems.
Placing large memory systems directly on the
motherboard will occupy a large amount of space.
Also, this arrangement is inflexible since the memory system cannot be expanded
easily.
Packaging considerations have led to the
development of larger memory units known as
SIMMs (Single In-line Memory Modules) and
DIMMs (Dual In-line Memory Modules).
Memory modules are an assembly of memory
chips on a small board that plugs vertically onto a
single socket on the motherboard.
Occupy less space on the motherboard.
Allows for easy expansion by replacement .
Recall that in a dynamic memory chip, to reduce the
number of pins, multiplexed addresses are used.
Address is divided into two parts:
High-order address bits select a row in the array.
They are provided first, and latched using RAS signal.
Low-order address bits select a column in the row.
They are provided later, and latched using CAS signal.
However, a processor issues all address bits at the
same time.
In order to achieve the multiplexing, memory
controller circuit is inserted between the processor
and memory.
Row/Column
Address address
RAS
R/ W
CAS
Memory
Request controller R/ W
Processor Memory
CS
Clock
Clock
Data
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Read-Only Memories (ROMs)
SRAM and SDRAM chips are volatile:
Lose the contents when the power is turned off.
Many applications need memory devices to retain contents
after the power is turned off.
For example, computer is turned on, the operating system must
be loaded from the disk into the memory.
Store instructions which would load the OS from the disk.
Need to store these instructions so that they will not be lost after
the power is turned off.
We need to store the instructions into a non-volatile memory.
Non-volatile memory is read in the same manner as volatile
memory.
Separate writing process is needed to place information in this
memory.
Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
Read-Only Memory:
Data are written into a ROM when it is manufactured.
Programmable Read-Only Memory (PROM):
Allow the data to be loaded by a user.
Process of inserting the data is irreversible.
Storing information specific to a user in a ROM is expensive.
Providing programming capability to a user may be better.
Cache Block 1
the cache. 0 maps to 0, 129 maps to 1.
tag
•More than one memory block is mapped onto the sam
Block 0 position in the cache.
tag
Block 1 •May lead to contention for cache blocks even if the
cache is not full.
Block 127
•Resolve the contention by allowing new block to
Block 128 replace the old block, leading to a trivial replacement
tag
Block 127 Block 129
algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Block 255 the the next 7 bits determine which cache
Tag Block Word
5 7 4 Block 256 block this new block is placed in.
- High order 5 bits determine which of the possible
Main memory address Block 257
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.
Block 4095
Main Block 0
memory
Block 1
•Main memory block can be placed into any cache
Cache
tag
position.
Block 0 •Memory address is divided into two fields:
tag
Block 1 - Low order 4 bits identify the word within a block.
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128 •Flexible, and uses cache space efficiently.
tag •Replacement algorithms can be used to replace an
Block 127 Block 129
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256
Block 4095
Cache
Main
memory Block 0 Blocks of cache are grouped into sets.
tag Block 0 Mapping function allows a block of the main
Block 1
tag
memory to reside in any block of a specific set.
Block 1
Divide the cache into 64 sets, with two blocks per set.
tag Block 2 Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63 Memory address is divided into three fields:
Block 64 - 6 bit field determines the set number.
tag - High order 6 bit fields are compared to the tag
Block 126 Block 65
fields of the two blocks in a set.
tag
Block 127 Set-associative mapping combination of direct and
associative mapping.
Number of blocks per set is a design parameter.
Tag Block Word
Block 127 - One extreme is to have all the blocks in one set,
Block 128 requiring no set bits (fully associative mapping).
5 7 4
- Other extreme is to have one block per set, is
Block 129
Main memory address the same as direct mapping.
Block 4095
Performance considerations
A key design objective of a computer system is to
achieve the best possible performance at the lowest
possible cost.
Price/performance ratio is a common measure of success.
Performance of a processor depends on:
How fast machine instructions can be brought into the processor
for execution.
How fast the instructions can be executed.
Divides the memory system into a number of
memory modules. Each module has its own address buffer
register (ABR) and data buffer register (DBR).
Arranges addressing so that successive
words in the address space are placed in
different modules.
When requests for memory access involve
consecutive addresses, the access will be to
different modules.
Since parallel access to these modules is
possible, the average rate of fetching words
from the Main Memory can be increased.
k bits bits
bits k bits
Module Address in module MM address
Address in module Module MM address
ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR
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Processor
•Memory management unit (MMU) translates
virtual addresses into physical addresses.
Virtual address
•If the desired data or instructions are in the
main memory they are fetched as described
Data MMU
previously.
•If the desired data or instructions are not in
Physical address
the main memory, they must be transferred
from secondary storage to the main memory.
Cache •MMU causes the operating system to bring
the data from the secondary storage into the
Data Physical address main memory.
Main memory
DMA transfer
Disk storage
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Assume that program and data are
composed of fixed-length units called pages.
A page consists of a block of words that
occupy contiguous locations in the main
memory.
Page is a basic unit of information that is
transferred between secondary storage and
main memory.
Size of a page commonly ranges from 2K to
16K bytes.
Pages should not be too small, because the access time of a secondary
storage device is much larger than the main memory.
Pages should not be too large, else a large portion of the page may not be
used, and it will occupy valuable space in the main memory.
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Concepts of virtual memory are similar to
the concepts of cache memory.
Cache memory:
Introduced to bridge the speed gap between the processor and the main
memory.
Implemented in hardware.
Virtual memory:
Introduced to bridge the speed gap between the main memory and
secondary storage.
Implemented in part by software.
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Each virtual or logical address generated by a
processor is interpreted as a virtual page number
(high-order bits) plus an offset (low-order bits) that
specifies the location of a particular byte within
that page.
Information about the main memory location of
each page is kept in the page table.
Main memory address where the page is stored.
Current status of the page.
Area of the main memory that can hold a page is
called as page frame.
Starting address of the page table is kept in a
page table base register.
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Virtual page number generated by the
processor is added to the contents of the
page table base register.
This provides the address of the corresponding entry in the page table.
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PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as page
+ number and offset.
PAGE TABLE
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.
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Page table entry for a page also includes
some control bits which describe the status
of the page while it is in the main memory.
One bit indicates the validity of the page.
Indicates whether the page is actually loaded into the main memory.
Allows the operating system to invalidate the page without actually removing
it.
One bit indicates whether the page has been
modified during its residency in the main
memory.
This bit determines whether the page should be written back to the disk
when it is removed from the main memory.
Similar to the dirty or modified bit in case of cache memory.
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Other control bits for various other types
of restrictions that may be imposed.
For example, a program may only have read permission for a page, but
not write or modify permissions.
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Where should the page table be located?
Recall that the page table is used by the MMU for
every read and write access to the memory.
Ideal location for the page table is within the MMU.
Page table is quite large.
MMU is implemented as part of the processor
chip.
Impossible to include a complete page table on
the chip.
Page table is kept in the main memory.
A copy of a small portion of the page table can be
accommodated within the MMU.
Portion consists of page table entries that correspond to the most recently accessed
pages.
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A small cache called as Translation
Lookaside Buffer (TLB) is included in the
MMU.
TLB holds page table entries of the most recently accessed pages.
Recall that cache memory holds most
recently accessed blocks from the main
memory.
Operation of the TLB and page table in the main memory is similar to the
operation of the cache and main memory.
Page table entry for a page includes:
Address of the page frame where the page resides in the main memory.
Some control bits.
In addition to the above for each page, TLB
must hold the virtual page number for each
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Virtual address from processor
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How to keep the entries of the TLB coherent
with the contents of the page table in the
main memory?
Operating system may change the contents
of the page table in the main memory.
Simultaneously it must also invalidate the corresponding entries in the TLB.
A control bit is provided in the TLB to
invalidate an entry.
If an entry is invalidated, then the TLB gets
the information for that entry from the page
table.
Follows the same process that it would follow if the entry is not found in the
TLB or if a “miss” occurs.
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What happens if a program generates
an access to a page that is not in the
main memory?
In this case, a page fault is said to
occur.
Whole page must be brought into the main memory from the disk,
before the execution can proceed.
Upon detecting a page fault by the
MMU, following actions occur:
MMU asks the operating system to intervene by raising an
exception.
Processing of the active task which caused the page fault is
interrupted.
Control is transferred to the operating system.
Operating system copies the requested page from secondary
storage to the main memory.
Once the page is copied, control is returned to the task which was
interrupted. 60
Servicing of a page fault requires
transferring the requested page from
secondary storage to the main memory.
This transfer may incur a long delay.
While the page is being transferred the
operating system may:
Suspend the execution of the task that caused the page fault.
Begin execution of another task whose pages are in the main memory.
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How to ensure that the interrupted task
can continue correctly when it resumes
execution?
There are two possibilities:
Execution of the interrupted task must continue from the point where it
was interrupted.
The instruction must be restarted.
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When a new page is to be brought into the main
memory from secondary storage, the main
memory may be full.
Some page from the main memory must be replaced with this new page.
How to choose which page to replace?
This is similar to the replacement that occurs when the cache is full.
The principle of locality of reference (?) can also be applied here.
A replacement strategy similar to LRU can be applied.
Since the size of the main memory is relatively
larger compared to cache, a relatively large
amount of programs and data can be held in the
main memory.
Minimizes the frequency of transfers between secondary storage and main memory.
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A page may be modified during its residency
in the main memory.
When should the page be written back to the
secondary storage?
Recall that we encountered a similar problem
in the context of cache and main memory:
Write-through protocol(?)
Write-back protocol(?)
Write-through protocol cannot be used, since
it will incur a long delay each time a small
amount of data is written to the disk.
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