MODULE 4

 Maximum size of the Main Memory

 byte-addressable
 CPU-Main Memory Connection

Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2 k addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)
 Measures for the speed of a memory:

Memory Access Time: It is the time that elapses between
Initiation of an operation & Completion of that operation.
 Memory Cycle Time: It is the minimum time delay
that required between the initiation of the two
successive memory-operations.
 An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost
target.
 Several techniques to increase the
effective size and speed of the memory:
 Cache memory (to increase the effective speed).
 Virtual memory (to increase the effective size).
 Each memory cell can hold one bit of information.
 Memory cells are organized in the form of an array.
 One row is one memory word.
 All cells of a row are connected to a common line,
known as the “word line”.
 Word line is connected to the address decoder.
 Sense/write circuits are connected to the data
input/output lines of the memory chip.
 7 7 1 1 0 0
W0

•
•
•
FF FF
A0 W1

•
•
•
A1
Address Memory
decoder • • • • • • cells
A2 • • • • • •
• • • • • •
A3

W15
•
•
•

Sense / Write Sense / Write Sense / Write R /W

circuit circuit circuit
CS

Data input /output lines: b7 b1 b0

 For 128 bit cells organized as 16*8 memory circuit; 4 lines for address, 8
lines for data, and 2 lines for control signals and 2 lines for power signals, total
16lines are required

For 1024 bit cells organized as (128*8) memory circuit; 7 lines for address, 8
lines for data, 2 lines for control signals and 2 lines for power signals, total 19
lines are required.
For 1024 bit cells organized as (1024*1) memory circuit; 10 lines for address, 1
line for data, 2 lines for control signals and 2 lines for power signals, total 15
lines are required
 Two inverters are cross connected to form a latch (Figure 8.4).
 The latch is connected to 2-bit-lines by transistors T1 and T2.
 The transistors act as switches that can be opened/closed under
the control of the word-line.
 When the word-line is at ground level, the transistors are turned
off and the latch retain its state.

b b

T1 T2
X Y

Word line
Bit lines
Read Operation
 To read the state of the cell, the word-line is activated to close
switches T1 and T2.
 If the cell is in state 1, the signal on bit-line b is high and the signal
on the bit-line b’ is low.
 Thus, b and b‟ are complement of each other.
Sense/Write circuit
 → monitors the state of b & b’ and
 → sets the output accordingly.
Write Operation
 The state of the cell is set by
→ placing the appropriate value on bit-line b and its complement on b’
and
→ then activating the word-line. This forces the cell into the
corresponding state.
 The required signal on the bit-lines is generated by Sense/Write
circuit.
Advantages:
 It has low power consumption . the
current flows in the cell only when the
cell is active.
 Static RAM‟s can be accessed quickly. It
access time is few nanoseconds.
Disadvantage: SRAMs are said to be
volatile memories. Because their
contents are lost when power is
interrupted.
 Static RAMs (SRAMs):
 Consist of circuits that are capable of retaining their state as
long as the power is applied.
 Volatile memories, because their contents are lost when power
is interrupted.
 Access times of static RAMs are in the range of few
nanoseconds.
 However, the cost is usually high.

Dynamic RAMs (DRAMs):
 Do not retain their state indefinitely.
 Contents must be periodically refreshed.
 Contents may be refreshed while accessing them for reading.
•Less expensive RAMs can be implemented if simple cells are used.
•Such cells cannot retain their state indefinitely. Hence they are called Dynamic
RAM (DRAM).
•The information stored in a dynamic memory-cell in the form of a charge on a
capacitor.
•This charge can be maintained only for tens of milliseconds.
•The contents must be periodically refreshed by restoring this capacitor charge to its
full value
 In order to store information in the cell, the transistor T is turned
 The appropriate voltage is applied to the bit-line which charges
the capacitor.
 After the transistor is turned off, the capacitor begins to
discharge.
 Hence, information stored in cell can be retrieved correctly
before threshold value of capacitor drops down.
 During a read-operation,
 → transistor is turned ON
 → a sense amplifier detects whether the charge on the capacitor
is above the threshold value.
 If (charge on capacitor) > (threshold value) à Bit-line will have
logic value 1.
 If (charge on capacitor) < (threshold value) à Bit-line will set to
logic value 0.
  Each row can store 512
RAS bytes. 12 bits to select
a row, and 9 bits to
select a group in a row.
Row Row 4096  512 8
address
decoder cell array
Total of 21 bits.
latch • First apply the row
address, RAS signal
latches the row
address. Then apply the
A20- 9  A8 - 0 Sense / Write CS
circuits column address, CAS
R /W
signal latches the
address.
• Timing of the memory
Column
Column
address decoder unit is controlled by a
latch specialized unit which
generates RAS and CAS.
CAS D7 D0 • This is asynchronous
DRAM
 Suppose if we want to access the consecutive
bytes in the selected row.
 This can be done without having to reselect
the row.
 Add a latch at the output of the sense circuits in each row.
 All the latches are loaded when the row is selected.
 Different column addresses can be applied to select and place
different bytes on the data lines.
 Consecutive sequence of column addresses
can be applied under the control signal CAS,
without reselecting the row.
 Allows a block of data to be transferred at a much faster rate than
random accesses.
 A small collection/group of bytes is usually referred to as a block.
 This transfer capability is referred to as the
fast page mode feature.
Read-Only Memories (ROMs)
 SRAM and SDRAM chips are volatile:
 Lose the contents when the power is turned off.
 Many applications need memory devices to retain
contents after the power is turned off.
 For example, computer is turned on, the operating
system must be loaded from the disk into the memory.
 Store instructions which would load the OS from the disk.
 Need to store these instructions so that they will not be
lost after the power is turned off.
 We need to store the instructions into a non-volatile
memory.
 Non-volatile memory is read in the same manner as
volatile memory.
 Separate writing process is needed to place information
in this memory.
 Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
 Read-Only Memory:
 Data are written into a ROM when it is manufactured.
 Programmable Read-Only Memory
(PROM):
 Allow the data to be loaded by a user.
 Process of inserting the data is irreversible.
 Storing information specific to a user in a ROM is expensive.
 Providing programming capability to a user may be better.

 Erasable
Programmable Read-Only
Memory (EPROM):
 Stored data to be erased and new data to be loaded.
 Flexibility, useful during the development phase of digital systems.
 Erasable, reprogrammable ROM.
 Erasure requires exposing the ROM to UV light.
 Electrically Erasable Programmable Read-Only
Memory (EEPROM):
 To erase the contents of EPROMs, they have to be exposed to ultraviolet light.
 Physically removed from the circuit.
 EEPROMs the contents can be stored and erased electrically.
 Flash memory:
 Has similar approach to EEPROM.
 Read the contents of a single cell, but write the
contents of an entire block of cells.
 Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.
 Power consumption of flash memory is very low,
making it attractive for use in equipment that is
battery-driven.
 Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
A big challenge in the design of a
computer system is to provide a
sufficiently large memory, with a
reasonable speed at an affordable cost.
 Static RAM:
 Very fast, but expensive, because a basic SRAM cell has a complex
circuit making it impossible to pack a large number of cells onto a
single chip.
 Dynamic RAM:
 Simpler basic cell circuit, hence are much less expensive, but
significantly slower than SRAMs.
 Magnetic disks:
 Storage provided by DRAMs is higher than SRAMs, but is still less than
what is necessary.
 Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
 Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing •Relatively small amount of memory that
Increasing Increasing
size speed cost percanbit be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk
that will be used in the near future as
secondary close to the processor as possible.
memory
Cache Memories
 Processor is much faster than the main
memory.
 As a result, the processor has to spend much of its time waiting while
instructions and data are being fetched from the main memory.
 Major obstacle towards achieving good performance.
 Speed of the main memory cannot be
increased beyond a certain point.
 Cache memory is an architectural
arrangement which makes the main
memory appear faster to the processor
than it really is.
 Cache memory is based on the property
of computer programs known as “locality
of reference”.
 Analysisof programs indicates that
many instructions in localized areas of
a program are executed repeatedly
during some period of time, while the
others are accessed relatively less
frequently.
 These instructions may be the ones in a loop, nested loop or few
procedures calling each other repeatedly.
 This is called “locality of reference”.
 Temporal locality of reference:
 Recently executed instruction is likely to be executed again very
soon.
 Spatial locality of reference:
 Instructions with addresses close to a recently instruction are likely
to be executed soon.
 Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred

from the main memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found
in the cache.
• At any given time, only some blocks in the main memory are held in
the cache. Which blocks in the main memory are in the cache is
determined by a “mapping function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
• Existence of a cache is transparent to the processor. The
processor issues Read and
Write requests in the same manner.
• If the data is in the cache it is called a Read or Write hit.
• Read hit:
 The data is obtained from the cache.
• Write hit:
 Cache has a replica of the contents of the main memory.
 Contents of the cache and the main memory may be updated
simultaneously. This is the write-through protocol.
 Update the contents of the cache, and mark it as updated by
setting a bit known as the dirty bit or modified bit. The
contents of the main memory are updated when this block
is replaced. This is write-back or copy-back protocol.
• If the data is not present in the cache, then a Read miss or Write
miss occurs.
• Read miss:when addressed word not in cache , read miss occurs
 Block of words containing this requested word is transferred from the
memory.
 After the block is transferred, the desired word is forwarded to the
processor.
 The desired word may also be forwarded to the processor as soon as it
is transferred without waiting for the entire block to be transferred.
This is called load-through or early-restart.
• Write-miss:
• During write operation if addressed word is not in cache, a write
miss occurs
 Write-through protocol is used, then the contents of the main memory
are updated directly.
 If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
 Mapping functions determine how
memory blocks are placed in the
cache.
 A simple processor example:
 Cache consisting of 128 blocks of 16 words each.
 Total size of cache is 2048 (2K) words.
 Main memory is addressable by a 16-bit address.
 Main memory has 64K words.
 Main memory has 4K blocks of 16 words each.
 Three mapping functions:
 Direct mapping
 Associative mapping
 Set-associative mapping.
 Main Block 0•Block
memory j of the main memory maps to j modulo 128 of
Cache
the cache. 0 maps to 0, 129 maps to 1.
Block 1
tag
•More than one memory block is mapped onto the sam
Block 0 position in the cache.
tag
Block 1 •May lead to contention for cache blocks even if the
cache is not full.
Block 127
•Resolve the contention by allowing new block to
replace the old block, leading to a trivial replacement
Block 128
tag
Block 127
algorithm.
Block 129
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Block 255 the the next 7 bits determine which cache
Tag Block Word
5 7 4 Block 256 block this new block is placed in.
- High order 5 bits determine which of the possible
Main memory address Block 257
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.
Block 4095
 Main Block 0
memory
•Main memory block can be placed into any cache
Cache Block 1
tag
position.
Block 0 •Memory address is divided into two fields:
tag
Block 1 - Low order 4 bits identify the word within a block.
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128•Flexible, and uses cache space efficiently.
tag •Replacement algorithms can be used to replace an
Block 127 Block 129
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256

Main memory address Block 257

Block 4095
• Blocks of cache are grouped into sets.
• Mapping function allows a block of the
main
memory to reside in any block of a
specific set.
• Divide the cache into 64 sets, with two
blocks per set. Memory block 0, 64,
128 etc. map to block 0, and they can
occupy either of the two positions.
• Memory address is divided into three
fields:
- 6 bit field determines the set
number.
- High order 6 bit fields are compared
to the tag
fields of the two blocks in a set.
• Set-associative mapping combination
of direct and associative mapping.
• Number of blocks per set is a design
parameter.
Virtual Memory
 Recall that an important challenge in the
design of a computer system is to provide a
large, fast memory system at an affordable
cost.
 Architectural solutions to increase the
effective speed and size of the memory
system.
 Cache memories were developed to increase
the effective speed of the memory system.
 Virtual memory is an architectural solution
to increase the effective size of the memory
system.
40
 Recall that the addressable memory space
depends on the number of address bits in a
computer.
 For example, if a computer issues 32-bit addresses, the addressable memory
space is 4G bytes.
 Physical main memory in a computer is
generally not as large as the entire possible
addressable space.
 Physical memory typically ranges from a few hundred megabytes to 1G bytes.
 Large programs that cannot fit completely into
the main memory have their parts stored on
secondary storage devices such as magnetic
disks.
 Pieces of programs must be transferred to the main memory from secondary
storage before they can be executed.
41
 When a new piece of a program is to be
transferred to the main memory, and
the main memory is full, then some
other piece in the main memory must
be replaced.
 Recall this is very similar to what we studied in case of cache
memories.
 Operating system automatically
transfers data between the main
memory and secondary storage.
 Application programmer need not be concerned with this transfer.
 Also, application programmer does not need to be aware of the
limitations imposed by the available physical memory.
42
 Techniques that automatically move program
and data between main memory and secondary
storage when they are required for execution are
called virtual-memory techniques.
 Programs and processors reference an
instruction or data independent of the size of the
main memory.
 Processor issues binary addresses for
instructions and data.
 These binary addresses are called logical or virtual addresses.
 Virtual addresses are translated into physical
addresses by a combination of hardware and
software subsystems.
 If virtual address refers to a part of the program that is currently in the main
memory, it is accessed immediately.
 If the address refers to a part of the program that is not currently in the main
memory, it is first transferred to the main memory before it can be used.
43
 Processor

•Memory management unit

Virtual address
(MMU) translates virtual
addresses into physical
Data MMU addresses.
•If the desired data or
Physical address instructions are in the main
memory they are fetched as
Cache described previously.
•If the desired data or
Data Physical address instructions are not in the main
memory, they must be
Main memory transferred from secondary
storage to the main memory.
DMA transfer •MMU causes the operating
system to bring the data from
Disk storage the secondary storage into the
main memory.
44
Secondary Storage
Disk

Disk drive

Disk controller
 Magnetic Disk system consists of one or more disk mounted on a
common spindle.
 A thin magnetic film is deposited on each disk (Figure 8.27).
 Disk is placed in a rotary-drive so that magnetized surfaces move
in close proximity to R/W heads.
 Each R/W head consists of 1) Magnetic Yoke & 2) Magnetizing-Coil.
 Digital information is stored on magnetic film by applying current
pulse to the magnetizing-coil.
 Only changes in the magnetic field under the head can be sensed
during the Read-operation.
 Therefore, if the binary states 0 & 1 are represented by two
opposite states, then a voltage is induced in the head only at 0-1
and at 1-0 transition in the bit stream.
 A consecutive of 0‟s & 1‟s are determined by using the clock.
 Manchester Encoding technique is used to combine the clocking
information with data.
Advantages
Ithas a larger capacity for a given physical size.
The data integrity is high because the storage
medium is not exposed to contaminating elements.
The read/write heads of a disk system are movable.
The disk system has 3 parts:
1) Disk Platter (Usually called Disk)
2) Disk-drive (spins the disk & moves Read/write
heads)
3) Disk Controller (controls the operation of the
system.)
 Sector 0, track 1
Sector 3, track n
Sector 0, track 0

Figure 5.30. Organization of one surface of a disk.

 Each surface is divided into concentric Tracks
(Figure 8.28).
 Each track is divided into Sectors.
 The set of corresponding tracks on all surfaces of
a stack of disk form a Logical Cylinder.
 The data are accessed by specifying the surface
number, track number and the sector number.
 The Read/Write-operation start at sector
boundaries.
 Data bits are stored serially on each track.
 Sector header
 Following the data,there is an error-
correction code (ECC).
 Formatting process
 Difference between inner tracks and
outer tracks
 Access time – seek time / rotational
delay (latency time)
 Data buffer/cache
 There are 2 components involved in the
time-delay:
 1) Seek time: Time required to move
the read/write head to the proper track.
 2) Latency/Rotational Delay: The
amount of time that elapses after head is
positioned over the correct track until the
starting position of the addressed sector
passes under the R/W head.
 Seek time + Latency = Disk access time
Processor Main memory

System bus

Disk controller

Disk drive Disk drive

Figure 5.31. Disks connected to the system bus.

 Seek
 Read
 Write
 Error checking
 Redundant Array of Inexpensive Disks
 Using multiple disks makes it cheaper
for huge storage, and also possible to
improve the reliability of the overall
system.
 RAID0 – data striping
 RAID1 – identical copies of data on two
disks
 RAID2, 3, 4 – increased reliability
 RAID5 – parity-based error-recovery