Ee 501 Project2 Report

Design of a Rail to Rail Input and
Output Fully-Differential
Two-Stage Op Amp Design:
EE 501: Project 2
By Oko-Odion Ekaniyere & Alain Njipwo

Introduction:
In this project, we are tasked with designing a rail-to-rail input, rail to rail output, two stage, fully
differential amplifier. We are given as a set of specifications to achieve as design targets. This project was
implement in the TSMC 0.18µ process.
Op Amp Basic Specification Targets:

1. Power supply nominal voltage: VDD = 1.8V +- 10%.
2. Total current consumption of chip: <= 1 mA at quiescent, targeting <= 0.5mA.
3. Output driving capability: a capacitive load of 5 pF at each output node.
4. Open-loop gain bandwidth (A(s) only) product: >= 50 MHz ~=UGF, with PM>=55 deg
5. At Q-point with Vicm = 0.5 VDD, DC gain: >= 90dB
6. Slew rate: >= 100 V/μS for both Vo+ and Vo-, >= 200 V/μS for differential output.
7. Differential Vout swing range: VSS to VDD.
8. Input common mode range: VSS to VDD.
9. In gain of -1 configuration, 0.1 V step response has overshoot <= 15% over full PVT and
Vicm = 10%, 50% and 90% VDD.
10. Settling time in 0.1 V step response in gain of -1 and Vicm=50%VDD: <= 50 ns for +–
0.01% settling.
Given these specifications, we decided to use a 10µA quiescent for the cascode stack. The input
stage will draw ~20µA
Temperature Independent Current reference:

The specifications of the amplifier were achieved through carefully biasing each stage of the process. To
maintain these specifications over a wide range of operations conditions and applications, the current
used to bias the circuit should be fairly constant relative to conditions(temperature) external to the
circuit. This is the motivation for a temperature-independent current source
Biasing circuit
We chose the Widlar design for our current source design. One advantage of the Widlar current source is
it generates a PTAT current, which offers us a high gm range.
Figure 1 shows our schematic for our Widlar design. To fit the specifications for our amplifier, we ensured
that the reference operates in full saturation for 𝑉𝐷𝐷 = 1. 62 𝑡𝑜 1. 98, which represented a power
supply range of 1.8V (+-10%) and a temperature range of 𝑇𝑒𝑚𝑝 =− 40𝐶 𝑡𝑜 100𝐶 .
Fig.1: The Widlar Circuit in full saturation
This current source is designed to provide a reference current of 20uA reference current. The following
design procedure is used to determine the the transistor sizes for the current mirror:
1. We first begin by choosing a value for the channel length for the Widlar design, we chose a
length (L) of 1um for the Widlar current reference design because a long channel length helps to
improve matching.
2. Next we chose a Vov of 0.1V for all transistors, a Vov of 0.1V will prevent the transistors from
getting into subthreshold when the threshold voltage changes with temperature or other
conditions.
3. We then assign Vds to the various elements in the Widlar including the resistor. A Vds large
enough to keep each transistor in saturation is assigned to the transistors while also considering
the amount of head room available.
4. Given the Vds and the value of current flowing through the mirror we compute the initial value
of the resistor using Ohm’s law.
Finally we compute the width of all the transistors by using a MATLAB script to map the chosen Vov
to a gm/id value, and then getting a width that will give us the various specifications above for the
transistor which include a Vov and Vds.
Figure: Bandgap current output over temperature range
The stability of the current over the 0-70◦temperature range, we can see that the output varies very
slightly from the desired 20µA. Between 20µA and 18.5µA and 22µA
Rail to rail input stage

The rail to rail input is achieved using the circuit above, it consists of a complementary pmos and nmos
input pair and a non-complementary nmos and pmos input pair. When the input voltage is within the
input common mode range of the nmos and pmos complementary input pair ,Both of the
complementary input pairs will be turned on and will source current to the subsequent stage, but when
the input common mode voltage is too low or too high, only the pmos or nmos input pair will be turned
on. The amount of current it is able to source to the second stage is determined by the gm of both input
pairs. This is expressed by the equation below.
𝑖 = 𝑔𝑚𝑛𝑣𝑖𝑛 + 𝑔𝑚𝑝𝑣𝑖𝑛 = 𝑣𝑖𝑛(𝑔𝑚𝑛 + 𝑔𝑚𝑝)

Also the amount of gm each of these input pairs is able to generate is dependent on the current in these
input pairs as shown by the equation below.
𝑔𝑚,𝑡𝑜𝑡𝑎𝑙 = 𝑔𝑚𝑛 + 𝑔𝑚𝑝 = 2β𝑛𝐼𝑛 + 2β𝑝𝐼𝑝.

Rail to rail input is achieved by ensuring that each of these input stages are able to generate the same
gm when operating alone that is equivalent to the gm generated when both input pairs are operating
simultaneously. This is achieved by delivering a large current to the nmos input pair that is about four
times its original current so that it is able to deliver the same transconductance when both input pairs
are in operation. The non-complementary input pair is used to sense when one input pair is turned off
and delivers an extra three times the original current flowing through each input pair. The figure below
shows the circuit for achieving this.
Fig: complementary pmos and nmos input pair for RRI.

Rail to rail Output stage:
The rail to rail output stage was achieved by using the Monticelli circuit.
Fig. The output stage: Monticelli circuit for achieving rail to rail output.
Fig: Biasing circuit for the Monticelli RRO.
Fig: Common mode feedback circuit. CMMFB
The common mode feedback circuit is used to bias the bottom nmos of the cascode stage in order to
achieve a constant output quiescent voltage. It consists of an averaging circuit and an amplifier.
Result:
To characterize the Op-amp, we performed a series of tests to explore the performance of the amplifier.
DIFFERENTIAL MODE GAIN AND STABILITY:
Fig: Closed loop test bench for measuring the differential mode AC response
Fig: AC response for the differential amplifier.

The DC gain is 90dB, the unity gain frequency is 50.6MHz and the phase margin is 56 degree.
SLEW RATE, OVERSHOOT, AND SETTLING TIME:

The figure below shows the test bench used to measure the slew rate, overshoot and settling time of the
amplifier.
Fig: Slew rate test bench setup.

Fig: slew rate outpout
From the figure above, we see that the rising slew rate is 4.35MV/s and the falling slew rate is 3.47MV/s,
the positive overshoot is 873uV
The overshoot voltage is 37.59uV

Fig: output voltage swing range.
INPUT COMMON MODE RANGE:
Fig: test bench for input common mode range.

Fig.: input common mode range.
Fig: common mode rejection ratio.
Fig: test bench schematic for AC characteristics
CONCLUSION:
In this project, we built a rail-to-rail input and output amplifier with two stages and fully differential
output. We simulated the results and we were able to obtain 9 of the 11 specifications targeted. We
divided the work and developed components individually. The biggest challenge was integrating the
components to get them to work together. Since we do not have the PDK for th tsmc18rf process, we
were not able able to perform post layout simulation to further characterize the amplifier.

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Design of a Rail to Rail Input and

By Oko-Odion Ekaniyere & Alain Njipwo

Op Amp Basic Specification Targets:

Temperature Independent Current reference:

Fig.1: The Widlar Circuit in full saturation

Figure: Bandgap current output over temperature range

Rail to rail input stage

𝑖 = 𝑔𝑚𝑛𝑣𝑖𝑛 + 𝑔𝑚𝑝𝑣𝑖𝑛 = 𝑣𝑖𝑛(𝑔𝑚𝑛 + 𝑔𝑚𝑝)

𝑔𝑚,𝑡𝑜𝑡𝑎𝑙 = 𝑔𝑚𝑛 + 𝑔𝑚𝑝 = 2β𝑛𝐼𝑛 + 2β𝑝𝐼𝑝.

Fig: complementary pmos and nmos input pair for RRI.

DIFFERENTIAL MODE GAIN AND STABILITY:

Fig: AC response for the differential amplifier.

SLEW RATE, OVERSHOOT, AND SETTLING TIME:

Fig: Slew rate test bench setup.

The overshoot voltage is 37.59uV

INPUT COMMON MODE RANGE:

Fig: test bench for input common mode range.

Fig: test bench schematic for AC characteristics

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