UNIVERSITY OF TEXAS ARLINGTON

CMOS Comparator
Design
TSMC 0.25 um Technology
Sharath Patil, 1000673216
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CMOS COMPARATOR DESIGN IN

TSMC 0.25 um TECHNOLOGY
1. Introduction
A Comparator is used to detect whether a signal is greater or smaller than zero, or to
compare the size of one signal to another. Comparators are used in large abundance in A/D
converters [1]. In this design, simple open-loop architecture has been used to design the
comparator.

2. Design Specifications
Table 1. Design Specifications

Input Propagation Input O/p Volt Power Current Minimum Minimum

resolution time delay CMR swing Density L W
0.1 mV Less than Greater Greater 100 mW Less than 0.3 um 0.3 um
1 ns than than 600uA/1um2
1.5V 1.5V

3. Design
a) Gain
The gain required to achieve an input resolution of 0.1 mV is

VOH −VOL 1.5

A= = =15000
VIH−VIL 0.1e-3

The high gain suggests that a multistage design is required. But care should be taken to
optimize the propagation delay to meet the requirement of 1ns.

b) Propagation Delay
The overall time constant of an n stage comparator is given by [1]

(1)

Where A0 is the gain of each stage, L is the channel length of input transistors, Veff is the
overdrive voltage of the input transistors.

If a latched comparator is used, the delay is given by

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(2)

Where τ is given by

(3)

The circuit should also be capable of handling the entire input common mode range. Hence,
techniques such as Common Mode Feedback (CMFB) can be used.

4. Architecture
The architecture explained in [2] was used for the design. The block diagram is shown in
Fig. 1. The fully-differential input stage enables high input CMR and common mode noise
rejection. The latch with positive feedback is used to amplify the signals to required levels. The
post amplifier is used to amplify the signals further and convert them to single ended output.
The buffer is used to drive the required loading conditions.

Fig. 1. Architecture used for the comparator design

a) Preamplifier
The circuit of preamplifier is shown in Fig. 2. It is a simple differential amplifier with current
source loads. The gain and the delay of the amplifier has been optimized as per the
requirement.

The design was started with the required delay. Equation (1) was used for estimating the
delay. The propagation delay was desired not to be more than 0.3ns. Also a gain of 50 (34 dB)
was desired for the first stage. These specifications give us a value of nearly 500 uA for the tail
current source and gm of 1.4 mS for the input transistors.

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CMFB circuit [3] was used to define the output common mode voltage and also to improve
the input common mode range.

Fig. 2. Preamplifier Circuit

b) Differential Latch
The differential latch circuit [2] is shown in Fig. 3. It was designed to have a propagation
delay of 0.3 ns. Equations (2) and (3) were used to get a optimized design for delay and output
to input ratio. The ratio of input swing to output swing was designed to be 100.

Fig. 3. Differential Latch circuit

c) Post Amplifier
The post amplifier circuit [2] is shown in Fig. 4. It was designed to have a maximum delay of
0.3ns. But because of the high output swing and loading conditions, it is difficult to get the
desired delay of 0.3 ns. The post amplifier gain was designed to have a gain of 30 (32 dB).

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Current Mirror load was used for the differential amplifier. The output is single ended. The input
common mode is almost constant because of high CMRR of the first stage (i.e. pre amplifier).

Fig. 4. Post Amplifier Circuit

5 Layout
Layout was done using Virtuoso layout editor in Cadence. The layouts of various blocks are
as shown.

Fig. 5. Layout of Pre-amplifier

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Fig. 6. Layout of Differential Latch

Fig. 7. Layout of Post amplifier

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6 Simulation results
The testbench used for simulations is shown in Fig. 8. HSPICE was used for simulations
from cadence environment. VDD=2.5 V for all the simulations.

Fig. 8. Testbench for simulations

a) Gain of amplifiers
AC analysis was run to find the gain of preamplifier at 25C and Vcm = 1.25 V. The
frequency response plot of preamplifier is shown in Fig. 9. The DC gain is 32 dB. The dominant
pole is at 26 MHz.

Fig. 9. Frequency response of preamplifier

The frequency response plot of post amplifier is shown in Fig. 10. The DC gain is 30 dB. The
dominant pole is at 60 MHz.

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Fig. 10. Frequency response of post amplifier

b) Resolution
The negative input signal was 1.25 V+0.1mV and the positive input signal was 1.25 V.
The simulation was done at T=25 C and input common mode = 1.25 V. The simulation was run
at -40 C, 25 C and 100 C.

Fig. 11. Waveform for minimum input resolution (T=-40 C)

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Fig. 12. Waveform for minimum input resolution (T=25 C)

Fig. 13. Waveform for minimum input resolution (T=100 C)

c) Input common mode range, delay and output swing

Transient analysis was done on the circuit at various temperatures. The input signal frequency
is 10 MHz. The differential input is 0.1mV and the Common mode is varied from 800 mV to 2.2
V as shown in Fig. 14, 15 & 16 for various temperatures.

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Fig. 14. Waveform for Different Common mode inputs (T=-40 C)

Fig. 14. Waveform for Different Common mode inputs (T=25 C)

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Fig. 14. Waveform for Different Common mode inputs (T=100 C)

d) Simulation on Extracted netlist

Simulations were also done on extracted netlist. The input common mode range test done
in the previous section was done on the extracted netlist. The input signal frequency is 10 MHz.
The differential input is 0.1mV and the Common mode is varied from 800 mV to 2.2 V as shown
in Fig. 15, 16 & 17 for various temperatures.

Fig. 15. Waveform for Different Common mode inputs (T=-40 C)

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Fig. 16. Waveform for Different Common mode inputs (T=25 C)

Fig. 17. Waveform for Different Common mode inputs (T=100 C)

Simulation was also done with a 10 mV differential input and the result is shown in Fig.
18. The waveforms at the output of various blocks are shown in Figs. 19, 20 & 21.

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Fig. 18 Output for Vdiff = 10 mV

Fig. 19. Preamplifier output (Vdiff=10 mV, Vcm = 1.25V)

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Fig. 20. Differential latch output (Vdiff=10 mV, Vcm = 1.25V)

Fig. 21. Post amplifier output (Vdiff=10 mV, Vcm = 1.25V)

e) Power dissipated
The average current was measured at T=-40 C and T = 100 C and the power is tabulated in
Table 2. The current was measured with Vcm = 1.25 V and Vdiff=10 mV.

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Table 2. Power measurement

Temp Current (mA) Power (mW)

-40 C 19.3 48.25
100 14.5 36.25

7 Conclusion
The results are tabulated in Table 3. The circuit could not meet the specifications of input
common mode range, output voltage swing and current density.

Input Time Input O/p Power Current Minim Minimu

resolutio delay CMR Volt Density um L mW
n swing
Spec 0.1 mV <1 ns >1.5V > 1.5V 100 mW < 600uA/1um2 0.3 um 0.3 um
Obtained 0.1 mV 20 ns 1.2 V 1.4 V 48.25 mW 2mA/1um2 0.3 um 0.3 um

The propagation delay can be improved by optimizing the gain of the amplifier stages
and the latch. The current density problem can be easily solved by improving the buffer design.
So, future work involves improving the delay and input common mode range of the comparator
circuit.

8 References
[1] D. A. Johns, K. Martin, “Analog Integrated Circuit Design”, Wiley, New Delhi, 2008.

[2] R. J. Baker, “CMOS Circuit Design, Layout and Simulation”, Wiley, New Delhi, 2008.

[3] W. T. Ng, C. A. T. Salam, “High Speed High Resolution CMOS Voltage Comparator”,
Electronic Letters, Vol. 2, No. 6, March 1986.

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