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    SUPRIYA

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    Rebba Akhil
    The document describes a project to design a low-cost VLSI architecture for a bilateral filter to reduce noise in images. It was done under the guidance of a professor with a team of 4 students. They used Verilog HDL, Vivado, and EDA Playground tools. Different modeling approaches - gate level, behavioral, structural, data flow and switch level - were demonstrated with code examples. The goal was to reduce hardware usage by 48% compared to previous work through techniques like distance-oriented grouping and resource sharing.

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    SUPRIYA

    Uploaded by

    Rebba Akhil
    8 views19 pages
    The document describes a project to design a low-cost VLSI architecture for a bilateral filter to reduce noise in images. It was done under the guidance of a professor with a team of 4 students. They used Verilog HDL, Vivado, and EDA Playground tools. Different modeling approaches - gate level, behavioral, structural, data flow and switch level - were demonstrated with code examples. The goal was to reduce hardware usage by 48% compared to previous work through techniques like distance-oriented grouping and resource sharing.

    Original Description:

    Bilateral filter image denoising

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    The document describes a project to design a low-cost VLSI architecture for a bilateral filter to reduce noise in images. It was done under the guidance of a professor with a team of 4 students. They used Verilog HDL, Vivado, and EDA Playground tools. Different modeling approaches - gate level, behavioral, structural, data flow and switch level - were demonstrated with code examples. The goal was to reduce hardware usage by 48% compared to previous work through techniques like distance-oriented grouping and resource sharing.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    8 views19 pages

    SUPRIYA

    Uploaded by

    Rebba Akhil
    The document describes a project to design a low-cost VLSI architecture for a bilateral filter to reduce noise in images. It was done under the guidance of a professor with a team of 4 students. They used Verilog HDL, Vivado, and EDA Playground tools. Different modeling approaches - gate level, behavioral, structural, data flow and switch level - were demonstrated with code examples. The goal was to reduce hardware usage by 48% compared to previous work through techniques like distance-oriented grouping and resource sharing.

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    KRISHNA UNIVERSITY

    COLLEGE OF ENGINEERING AND TECHNOLOGY

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


    VLSI ARCHITECTURE OF
    THE BILATERAL-FILTER
    FOR IMAGE DE-NOISING

    Under the Guidance of Team Members

    Mr. K. G. VENKATA KRISHNA A. SUPRIYA (Y20ECE279002)


    Asst. Prof. (Cont.) CH.PAVAN KUMAR (Y20ECE279016)
    Dept. of E.C.E. D.KARIMULLA (Y20ECE279018)
    KRUCET R.AKHIL (L21ECE279017)
    A B STRACT

    A low-cost VLSI architecture of the bilateral filter for


    real-time image processing is proposed. Based on the
    techniques of distance-oriented grouping and hardware
    resource sharing, the usage of multipliers can decrease 4 8 %
    as compared to the previous approach.Besides, an efficient
    quantization method is applied to reduce the size of required
    look up tables.
    CONTENTS
    ● Introduction

    ● Bi-lateral filter

    ● Softwares used

    ● Verilog HDL & Modellings

    ● 8x3 Binary Encoder


    Programming code & O/P Waveforms
    INTRODUCTION
    ● Image denoising in image processing refers to
    the process of reducing or eliminating unwanted
    noise from an image.

    ● This noise can be caused by various factors


    during image acquisition or transmission.
    BI-LATERAL FILTER
    ● The bilateral filter is a technique in image processing
    used for denoising.

    ● This dual filtering process helps preserve edges while


    reducing noise, making it effective for enhancing
    image quality.

    ● The bilateral filter is a weighted average of nearby pixels,


    in a manner very similar to Gaussian convolution.
    SOFTWARES USED

    VIVADO TOOL
    EDA PLAYGROUND:

    ● ‘EDA’ means Exploratory data analysis, it is a free IDE tool


    for system verilog and VHDL.

    ● This “EDA Playground” allows users to edit,simulate &


    Synthesize and share their HDL.

    ● In this tool we can get the O/P waveforms without any


    software.
    Verilog HDL
    ● Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL).

    ● Verilog's syntax is similar to C, making it easier for those with a background in C or C-like
    languages.

    ● VHDL, on the other hand, has a more verbose syntax and strong typing, which some
    designers may find more structured and easier to understand.

    ● For our project we used Verilog HDL due to its easy syntax.
    Verilog HDL supports 5 Modellings:-
     Switch Level Modelling
     Gate Level Modelling
     Data-Flow Modelling
     Behavioural Modelling
     Structural Modelling
    VHDL Modellings
    Switch Level Modelling:
    * This model is degined by using PMOS & NMOS Switches, this model is very difficult
    compared to other models.
    Gate Level Modelling:
    * Gate level modeling is used to implement the lowest-level modules in a design, such as
    multiplexers, full-adder, etc.
    Data-Flow Modelling:
    * The data flow modeling provides a way to design circuits depending on how data flow
    between the registers and how data is processed.

    Behavioural Modelling:
    * The Verilog provides the facility to represent the behavior of design at a high-level
    abstraction similar to C language programming.

    Structural Modelling:
    * Structural Modelling is used to build top module by using sub module.
    8x3 Binary Encoder
    Gate Level Modelling
    Gate level modeling is used to implement the lowest-level modules in a
    design, such as multiplexers, full-adder, etc.

    Programming code:

    module binary_encoder 8x3 (d0,d1,d2,d3,d4,d5,d6,d7,x,y,z);


    input d0,d1,d2,d3,d4,d5,d6,d7;
    output x,y,z;
    or gate1(x,d4,d5,d6,d7);
    or gate2(y,d2,d3,d6,d7);
    or gate3(z,d1,d3,d5,d7);
    endmodule
    Behavioural Modelling
    Programming code:
    module encoder (din, dout);
    input [7:0] din;
    output [2:0] dout;
    reg [2:0] dout;
    always @(din)
    begin
    if (din ==8'b00000001) dout=3'b000;
    else if (din==8'b00000010) dout=3'b001;
    else if (din==8'b00000100) dout=3'b010;
    else if (din==8'b00001000) dout=3'b011;
    else if (din==8'b00010000) dout=3'b100;
    else if (din ==8'b00100000) dout=3'b101;
    else if (din==8'b01000000) dout=3'b110;
    else if (din==8'b10000000) dout=3'b111;
    else dout=3'bX;
    end
    endmodule
    Structural Modelling
    Programming code:

    g5 (wa0, din6_not, din4_not, din[3]),


    module enco 8x3(DOUT, D);
    g6 (wa1, din5_not, din4_not, din[3]),
    output [2:0] DOUT;
    g7 (wa2, din5_not, din4_not, din[2]),
    input [7:0] din;
    g8 (wa3, din6_not, din[5]),
    wire din7_not, din6_not, din5_not,
    g9 (wa4, din6_not, din4_not,
    din4_not, din2_not;
    din2_not, din[1]);
    wire wa0, wa1, wa2, wa3, wa4;;
    or g11(dout[2], din[7], din[6], din[5],
    //instanitate gates
    din[4]),
    not g0 (din7_not, din[7]),
    g12(dout[1], din[7], din[6], wa1, wa2),
    g1 (din6_not, din[6]),
    g13(dout[0], din[7], wa0, wa3, wa4),
    g2 (din5_not, din[5]),
    g14(V, din[0], din[1], din[2], din[3],
    g3 (din4_not, din[4]),
    din[4], din[5], din[6], din[7]);
    g4 (din2_not, din[2]);
    endmodule
    Switch Level Modelling
    Programming Code:
    module encoder_8x3 (reg,data);
    input [7:0] data;
    output reg [2:0] encoded_output;
    always @(data)
    begin
    case (data)
    8'b00000001: encoded_output = 3'b000; // Encode 1
    8'b00000010: encoded_output = 3'b001; // Encode 2
    8'b00000100: encoded_output = 3'b010; // Encode 4
    8'b00001000: encoded_output = 3'b011; // Encode 8
    8'b00010000: encoded_output = 3'b100; // Encode 16
    8'b00100000: encoded_output = 3'b101; // Encode 32
    8'b01000000: encoded_output = 3'b110; // Encode 64
    8'b10000000: encoded_output = 3'b111; // Encode 128
    default: encoded_output = 3'b000; // Default is zero
    endcase
    end
    endmodule
    Data Flow Modelling
    Programming code: Testbench Code:
    module binary_encoder(y,d); module tb;
    input [7:0] D; reg [7:0] D;
    output [2:0] y); wire [2:0] y;
    assign y[2] = D[4] | D[5] | D[6] | D[7]; int i;
    assign y[1] = D[2] | D[3] | D[6] | D[7]; binary_encoder bin_enc(D, y);
    assign y[0] = D[1] | D[3] | D[5] | D[7]; initial begin
    endmodule D=8'b1; #1;
    for(i=0; i<8; i++) begin
    Output: $display("D = %h(in dec:%0d) -> y = %0h", D, i, y);
    D = 01(in dec:0) -> y = 0 D=D<<1; #1;
    D = 02(in dec:1) -> y = 1 end
    D = 04(in dec:2) -> y = 2 intial begin
    D = 08(in dec:3) -> y = 3 $dumpfile(“dump.vcd”);
    D = 10(in dec:4) -> y = 4
    $dumpvars(1);
    D = 20(in dec:5) -> y = 5
    D = 40(in dec:6) -> y = 6
    end
    D = 80(in dec:7) -> y = 7 endmodule
    O/P Waveforms
    Summary
    ● A Low -cost and real-time VLSI architecture of a Bi-Lateral Filter is
    proposed.

    ● Distance - Oriented grouping , resource sharing & LUT reduction are


    applied to reduce the required multipliers & memory space.
    THANK YOU

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