PIC16F87XA

5.2 Using Timer0 with an External Timer0 module means that there is no prescaler for the
Clock Watchdog Timer and vice versa. This prescaler is not
readable or writable (see Figure 5-1).
When no prescaler is used, the external clock input is
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
the same as the prescaler output. The synchronization
determine the prescaler assignment and prescale ratio.
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and When assigned to the Timer0 module, all instructions
Q4 cycles of the internal phase clocks. Therefore, it is writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
necessary for T0CKI to be high for at least 2 TOSC (and BSF 1,x....etc.) will clear the prescaler. When assigned
a small RC delay of 20 ns) and low for at least 2 TOSC to WDT, a CLRWDT instruction will clear the prescaler
(and a small RC delay of 20 ns). Refer to the electrical along with the Watchdog Timer. The prescaler is not
specification of the desired device. readable or writable.
Note: Writing to TMR0 when the prescaler is
5.3 Prescaler assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
There is only one prescaler available which is mutually
assignment.
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the

REGISTER 5-1: OPTION_REG REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0

bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: To avoid an unintended device Reset, the instruction sequence shown in the
PICmicro® Mid-Range MCU Family Reference Manual (DS33023) must be exe-
cuted when changing the prescaler assignment from Timer0 to the WDT. This
sequence must be followed even if the WDT is disabled.

DS39582B-page 54  2003 Microchip Technology Inc.

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TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.

 2003 Microchip Technology Inc. DS39582B-page 55

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NOTES:

DS39582B-page 56  2003 Microchip Technology Inc.

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6.0 TIMER1 MODULE In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
The Timer1 module is a 16-bit timer/counter consisting edge of the external clock input.
of two 8-bit registers (TMR1H and TMR1L) which are
Timer1 can be enabled/disabled by setting/clearing
readable and writable. The TMR1 register pair
control bit, TMR1ON (T1CON<0>).
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled, Timer1 also has an internal “Reset input”. This Reset
is generated on overflow which is latched in interrupt can be generated by either of the two CCP modules
flag bit, TMR1IF (PIR1<0>). This interrupt can be (Section 8.0 “Capture/Compare/PWM Modules”).
enabled/disabled by setting/clearing TMR1 interrupt Register 6-1 shows the Timer1 Control register.
enable bit, TMR1IE (PIE1<0>). When the Timer1 oscillator is enabled (T1OSCEN is
Timer1 can operate in one of two modes: set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
• As a Timer
ignored and these pins read as ‘0’.
• As a Counter
Additional information on timer modules is available in
The operating mode is determined by the clock select the PICmicro® Mid-Range MCU Family Reference
bit, TMR1CS (T1CON<1>). Manual (DS33023).

REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 prescale value
10 = 1:4 prescale value
01 = 1:2 prescale value
00 = 1:1 prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS39582B-page 57

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6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS Timer1 may operate in either a Synchronous, or an
(T1CON<1>) bit. In this mode, the input clock to the Asynchronous mode, depending on the setting of the
timer is FOSC/4. The synchronize control bit, T1SYNC TMR1CS bit.
(T1CON<2>), has no effect since the internal clock is When Timer1 is being incremented via an external
always in sync. source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.

FIGURE 6-1: TIMER1 INCREMENTING EDGE

T1CKI
(Default High)

T1CKI
(Default Low)

Note: Arrows indicate counter increments.

6.3 Timer1 Operation in Synchronized If T1SYNC is cleared, then the external clock input is
Counter Mode synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
Counter mode is selected by setting bit TMR1CS. In prescaler stage is an asynchronous ripple counter.
this mode, the timer increments on every rising edge of
In this configuration, during Sleep mode, Timer1 will not
clock input on pin RC1/T1OSI/CCP2 when bit
increment even if the external clock is present since the
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
synchronization circuit is shut-off. The prescaler,
bit T1OSCEN is cleared.
however, will continue to increment.

FIGURE 6-2: TIMER1 BLOCK DIAGRAM

Set Flag bit
TMR1IF on
Overflow Synchronized
TMR1 0
Clock Input
TMR1H TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI 1
Synchronize
Prescaler
T1OSCEN FOSC/4 1, 2, 4, 8 det
Enable Internal 0
RC1/T1OSI/CCP2(2) Oscillator(1) Clock 2 Q Clock
T1CKPS1:T1CKPS0
TMR1CS

Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.

DS39582B-page 58  2003 Microchip Technology Inc.