International Journal of Engineering Research in Electronic and Communication

Engineering (IJERECE) Vol 3, Issue 3, March 2016

Verilog Implementation of Reversible Logic Gate

[1]
P Sravani [2] V Sai Koushik [3] D Srinivas
[1]
Assistant Professor [2][3] B.E Scholor
[1][2][3]
Department of ECE, Matrusri Engineering College, Hyderabad, Telangana, India
Abstract- Technologies day-to-day are becoming smaller, faster and more complex than its previous technologies being developed.
Increase in clock frequency to achieve good speed and increase in number of transistors packed onto the chip to achieve complexity
of a conventional system results in increased power consumption. All the gates used to perform Boolean algebra based
computations by the use of silicon based semiconductor technology in a Conventional logic system are irreversible in nature.

This is due to the mismatch of inputs and outputs. Reversible Logic is gaining interest in the recent past due to its less
heat dissipating characteristics. This logic circuit maps to its unique input to the output and ensure one to one mapping and basis
for emerging applications like DNA Computing, Bioinformatics, Nanotechnologies, Quantum Computing, Quantum Dot Cellular
Data, Adiabatic CMOS, Thermodynamics, Low power Design and Optical Computing to produce zero power dissipation under
ideal conditions.

This paper presents the combinational circuit and Verilog code for the basic Reversible Logic gates which are important
(Feynman, Double Feynman, Fredkin, Toffoli and peres ). Every Logic circuit which is combinational uses all these basic
Reversible Logic Gates and can be verified through Simulation using Verilog HDL.

Keywords— Reversible Logic gates, Quantum Computing, Reversible Logic, Feynman, Fredkin, Toffoli and peres.

I. INTRODUCTION The most prominent application of reversible logic

lies in quantum computers [3]. A quantum computer will be
Energy dissipation is one of the major issues in viewed as a quantum network (or a family of quantum
present day technology. Energy dissipation due to networks) composed of quantum logic gates; It has
information loss in high technology circuits and systems applications in various research areas such as Low Power
constructed using irreversible hardware was demonstrated CMOS design, quantum computing, nanotechnology, DNA
by R. Landauer[1] in the year 1960. According to computing etc.,
Landauer’s principle, the loss of one bit of information lost, Quantum networks composed of quantum logic
will dissipate kT*ln(2) joules of energy where, k is the gates; each gate performing an elementary unitary operation
Boltzmann’s constant and k=1.38x10-23 J/K, T is the on one, two or more two–state quantum systems called
absolute temperature in Kelvin[1]. The primitive qubits. Each qubit represents an elementary unit of
combinational logic circuits dissipate heat energy for every information; corresponding to the classical bit values 0 and
bit of information that is lost during the operation. This is 1. Any unitary operation is reversible and hence quantum
because according to second law of thermodynamics, networks effecting elementary arithmetic operations such as
information once lost cannot be recovered by any methods. addition, multiplication and exponentiation cannot be
Bennett [2] showed that if a computation is carried directly deduced from their classical Boolean counterparts
out in Reversible logic zero energy dissipation is possible, (classical logic gates such as AND or OR are clearly
as the amount of energy dissipated in a system is directly irreversible).Thus, quantum arithmetic must be built from
related to the number of bits erased during computation. The reversible logical components [3]. Reversible computation
design that does not result in information loss is irreversible. in a system can be performed only when the system
A set of reversible gates are needed to design reversible comprises of reversible gates. A circuit/gate is said to be
circuit. Several such gates are proposed over the past reversible if the input vector can be uniquely recovered from
decades. the output vector and there is a one-to-one correspondence
According to Moore’s law the numbers of between its input and output assignments [4-6].
transistors will double every 18 months. Thus energy
conservative devices are the need of the day. The amount of In order to achieving an optimized reversible
energy dissipated in a system bears a direct relationship to circuit, some points should be considered:
the number of bits erased during computation. Reversible 1) Fan-out is forbidden.
circuits are those circuits that do not lose information. 2) Feedback and loop are not allowed.
3) Delay should be minimum.

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4) Optimization parameters should be minimum.

Input + constant input = output + garbage. [7]
The parameters such as number of reversible gates,
number of constant inputs, garbage outputs, and quantum As with reversible gates, a reversible circuit has the
cost (QC) can be named as optimization parameters and are same number of input and output wires; the reversible
defined as: circuit with n inputs is called an n X n circuit or a circuit on
1) The inputs, which equal to 0 or 1, are constant n wires.
inputs.
2) Garbage outputs are output vectors which do not E. Quantum cost:
generate any useful function.
3) Quantum cost refers to the cost of the circuit in Quantum cost refers to the cost of the circuit in
terms of primitive gate [7]. terms of the cost of a primitive gate. It is calculated knowing
the number of primitive reversible logic gates (1*1 or 2*2)
II. BASIC DEFINITIONS OF REVERSIBLE LOGIC required to realize the circuit.

In this section some important factors in reversible F. Flexibility:

logic are explained. The main object in reversible logic
theory is the reversible function, which is defined as Flexibility refers to the universality of a reversible
follows. logic gate in realizing more functions [14].

A. Reversible Function: G. Gate Level:

The Boolean function f(x1, x2 … xn) of n Boolean This refers to the number of levels in the circuit
variables is called reversible if: which are required to realize the given logic functions.
1. The number of outputs is equal to the number of
inputs. H. Hardware Complexity:
2. Any output pattern maps to a unique input pattern.
This refers to the total number of logic operation in
In other words, reversible functions are those that perform a circuit. Means the total number of AND, OR and EXOR
permutations of the set of input vectors [7-9]. operation in a circuit [11] and [15].
For an (n, k) function, i.e. function with n-input k-
output, it is necessary to add inputs and/or outputs to make it I. Design Constraints for Reversible Logic Circuits:
reversible. This leads to the following definition.
Reversible logic imposes many design constraints
B. Reversible logic gate: that need to be either ensured or optimized for implementing
any particular Boolean functions.
Reversible Gates are circuits in which number of outputs is 1) In reversible logic circuit the number of inputs
equal to the number of inputs and there is a one to one must be equal to the number of outputs.
correspondence between the vector of inputs and outputs 2) For each input pattern there must be a unique
[10- 12]. It not only helps us to determine the outputs from output pattern.
the inputs but also helps us to uniquely recover the inputs 3) Each output will be used only once, that is, no fan
from the outputs. out is allowed.
4) The resulting circuit must be acyclic.
C. Ancilla inputs/ constant inputs:

Anicilla inputs are used to denote the present value III. REVERSIBLE LOGIC GATES
inputs that were added to an (n, k) function to make it
reversible. The constant inputs are known as ancilla inputs. In this section, we describe all about reversible
[13]. logic and reversible logic gates. Though it is already briefly
described about garbage outputs, in this section we will
D. Garbage outputs: define these with more appropriate Reversible logic gates.

Garbage is the number of outputs added to make an (i) NOT Gate: 1*1 NOT gate is the simplest among all the
n-input k-output function ((n; k) function) reversible. The reversible gates where the gate has only one input (A) and
relation between garbage outputs and constant inputs is [7]
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Engineering (IJERECE) Vol 3, Issue 3, March 2016

one output (B) such that B = A’. The block diagram for 1*1
NOT gate is shown in Fig.3.1. (Quantum Cost = 0)

Figure 3.1: 1x1 NOT GATE

Code :

module NOTGATE( input A, output P );

assign P = ~A; Figure 3.4: combinational circuit diagram of 1x1 CNOT
endmodule GATE

(iii) Double Feynman Gate: Let Iv and Ov be the input and

output vector of a 3*3 Double Feynman Gate respectively,
where Iv = (A, B, C) and Ov = (P=A, Q=A⊕B, R=A⊕C).
Fig.3.5 shows the 3*3 Double Feynman gate. (Quantum
Cost = 2)

Figure 3.2: combinational circuit diagram of 1x1 NOT

GATE
Figure 3.5: 3x3 DOUBLE FEYNMAN GATE
(ii) Feynman Gate: Let Iv and Ov be the input and output
vector of a 2*2 Feynman gate (FG) [16,17] respectively,
Code:
where Iv= (A,B) and Ov = (P=A, Q=A⊕B). The block
diagram for 2*2 Feynman gate is shown in Fig.3.3.
Module Double_Feynman( input A, B, C, output P, Q, R
(Quantum Cost = 1)
);
assign P = A;
assign Q = A^B;
assign R = A^C;
endmodule

Figure 3.3: 2x2 FEYNMAN GATE (CNOT GATE)

Code:

module Feynman( input A, B, output P, Q );

assign P = A;
assign Q = A^B;
endmodule

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Figure 3.8: combinational circuit diagram of 3x3

TOFFOLI GATE

(v) Fredkin Gate: Let Iv and Ov be the input and output

vector of a 3*3 Fredkin Gate [18,20] respectively, where
Iv=(A,B,C) and Ov=(X=A,Y=A’B⊕AC , Z=A’C⊕AB).
Figure 3.6: combinational circuit diagram of 3x3 Fig. 3.9 shows the block diagram of 3*3 Fredkin gate.
DOUBLE FEYNMAN GATE (Quantum Cost = 5)

(iv) Toffoli Gate: Let Iv and Ov be the input and output

vector of a 3*3 Toffoli Gate (TG) [18,19] respectively,
where Iv =(A, B, C) and Ov=(P=A, Q=B, R=AB⊕ C).
Fig.3.7 shows the 3*3 Toffoli gate. (Quantum Cost = 5)

Figure 3.9: 3x3 FREDKIN GATE

Code:

Figure 3.7: 3x3 TOFFOLI GATE module Fredkin( input A, B, C, output X, Y, Z );

assign X = A;
Code: assign Y =((~A)&B) ^ (A&C);
assign Z =((~A)&C) ^( A&B);
module Toffoli( input A,B,C, output P,Q,R ); endmodule
assign P = A;
assign Q = B;
assign R = (A&B)^C;
endmodule

Figure 3.10: combinational circuit diagram of 3x3

FREDKIN GATE

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(vi) Peres Gate: Let Iv and Ov be the input and output Carry = ((A XOR B) C) XOR AB
vector of a 3*3 Peres Gate [18,20,21] respectively, where
Iv=(A,B,C) and Ov=(X=A,Y=A⊕B , Z=AB⊕C). Fig. 3.11 For this we go with peres gate as it has low
shows the block diagram of 3*3 Peres gate. (Quantum Cost quantum cost as compared with the discussed above basic
= 4) Reversible Logic gates. The Peres implemented Full Adder
with its corresponding quantum cost is shown in the figure
4.1

Figure 3.11: 3x3 PERES GATE

Code:

module Peres(input A,B,C, output X,Y,Z ); Figure 4.1:Full Adder using Peres Gates
assign X = A;
assign Y =A^B; Code:
assign Z =(A&B)^C;
endmodule module FULLADDER( input A,B,Cin, output SUM,Cout
);
Peres P1(A,B,0,G1,G2,G3);
Peres P2(G2,Cin,G3,G4,SUM,Cout);
endmodule

Figure 4.2: Full Adder using Peres Gates

This PFA (Peres Full Adder) can be taken as a

Figure 3.12: combinational circuit diagram of 3x3 PERES block as shown in figure 4.3 in order to facilitate the
GATE notation of its expansion with a Quantum Cost equal to 8.
The inputs order was also changed to better fit in an
Peres Gate [11] is an important gate which has a low expansion diagram and the logic diagram is given in figure
quantum cost as compared to other gates. A single Peres 4.4.
gate can give generate and propagate outputs when the third
input C = 0. Two Peres gates can be combined to form a full
adder.

IV. 4-BIT ADDER USING PFA (PERES FULL

ADDER) BLOCK:

Some of the most used universal quantum

gates[21] and their quantum cost are shown in figures
3.1,3.3,3.5,3.7 and 3.9. All these gates are used for Figure 4.3: PFA as a block
implementing any logical function therefore they can also
implement the full adder functions sum and carry.
Sum = A XOR b XOR C

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2. Management of digital power involves moving it to

where it is needed.
3. Digital heat refers to disordered bit patterns that are
no good to anyone.
4. Management of digital heat involves moving it to
where it can be dumped.

VII. CONCLUSION
Figure 4.4: PFA traditional logic implementation.
This paper presents Verilog CODE for all
Once we take the PFA as a block, we can derive Reversible Logic Gates, which provide us to design Verilog
the algorithm to implement an n-bits adder. This algorithm CODE of any complex combinational circuit. Here we have
was implemented in this design for a 4-bit adder and can be tried to make the Verilog code as much as possible. We can
seen in figure 4.5. simulate and synthesis it using Xilinx 15.1 software and
verified using Z series board and also calculate the power
consumption and compare it with the irreversible
Combinational Circuits.

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