Scribd
Upload
26 views

CAS 8 Code

The document describes a series of VHDL modules that implement basic logic gates and circuits. It defines a half adder (HA) module, a full adder (FA) module using two HAs, a 4-bit binary adder (BA_4) using four FAs, a 4-bit controlled adder/subtractor (CAS_4) that can add or subtract based on a control bit, and an 8-bit controlled adder/subtractor (CAS_8) that uses two CAS_4 modules. The modules are hierarchical with lower level modules instantiated as components in higher level modules to build up the logic functions.

Uploaded by

bhslegion1498
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
26 views

CAS 8 Code

The document describes a series of VHDL modules that implement basic logic gates and circuits. It defines a half adder (HA) module, a full adder (FA) module using two HAs, a 4-bit binary adder (BA_4) using four FAs, a 4-bit controlled adder/subtractor (CAS_4) that can add or subtract based on a control bit, and an 8-bit controlled adder/subtractor (CAS_8) that uses two CAS_4 modules. The modules are hierarchical with lower level modules instantiated as components in higher level modules to build up the logic functions.

Uploaded by

bhslegion1498
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 3

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HA is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
s1 : out STD_LOGIC;
cout1 : out STD_LOGIC);
end HA;

architecture behavioral of HA is

begin
s1 <= a1 xor b1;
cout1 <= a1 and b1;

end behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA is
Port ( a2 : in STD_LOGIC;
b2 : in STD_LOGIC;
cin2 : in STD_LOGIC;
s2 : out STD_LOGIC;
cout2 : out STD_LOGIC);
end FA;

architecture behavioral of FA is

signal s3, s4, s5 : STD_LOGIC;

component HA is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
s1 : out STD_LOGIC;
cout1 : out STD_LOGIC);
end component;

begin
lvl1 : HA port map (a2,b2,s3,s4);
lvl2 : HA port map (cin2,s3,s2,s5);
cout2 <= s4 or s5;

end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BA_4 is
Port ( A1 : in STD_LOGIC_VECTOR (3 downto 0);
B1 : in STD_LOGIC_VECTOR (3 downto 0);
Cin1 : in STD_LOGIC;
S1 : out STD_LOGIC_VECTOR (3 downto 0);
Cout1 : out STD_LOGIC);
end BA_4;

architecture behavioral of BA_4 is

signal s6, s7, s8 : STD_LOGIC;

component FA is
Port ( a2 : in STD_LOGIC;
b2 : in STD_LOGIC;
cin2 : in STD_LOGIC;
s2 : out STD_LOGIC;
cout2 : out STD_LOGIC);
end component;

begin
lvl1 : FA port map (A1(0),B1(0),Cin1,S1(0),s6);
lvl2 : FA port map (A1(1),B1(1),s6,S1(1),s7);
lvl3 : FA port map (A1(2),B1(2),s7,S1(2),s8);
lvl4 : FA port map (A1(3),B1(3),s8,S1(3),Cout1);

end behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CAS_4 is
Port ( A2 : in STD_LOGIC_VECTOR (3 downto 0);
B2 : in STD_LOGIC_VECTOR (3 downto 0);
ctrl2 : in STD_LOGIC;
Cin2 : in STD_LOGIC;
S2 : out STD_LOGIC_VECTOR (3 downto 0);
Cout2 : out STD_LOGIC);
end CAS_4;

architecture Behavioral of CAS_4 is

signal X : STD_LOGIC_VECTOR (3 downto 0);

component BA_4 is
Port ( A1 : in STD_LOGIC_VECTOR (3 downto 0);
B1 : in STD_LOGIC_VECTOR (3 downto 0);
Cin1 : in STD_LOGIC;
S1 : out STD_LOGIC_VECTOR (3 downto 0);
Cout1 : out STD_LOGIC);
end component;

begin
X(0) <= B2(0) xor ctrl2;
X(1) <= B2(1) xor ctrl2;
X(2) <= B2(2) xor ctrl2;
X(3) <= B2(3) xor ctrl2;

lvl1 : BA_4 port map (A2(3 downto 0),B2(3 downto 0),Cin2,S2(3 downto
0),Cout2);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CAS_8 is
Port ( A3 : in STD_LOGIC_VECTOR (7 downto 0);
B3 : in STD_LOGIC_VECTOR (7 downto 0);
ctrl3 : in STD_LOGIC;
S3 : out STD_LOGIC_VECTOR (7 downto 0);
Cout3 : out STD_LOGIC);
end CAS_8;

architecture Behavioral of CAS_8 is


signal sg : STD_LOGIC;

component CAS_4 is
Port ( A2 : in STD_LOGIC_VECTOR (3 downto 0);
B2 : in STD_LOGIC_VECTOR (3 downto 0);
ctrl2 : in STD_LOGIC;
Cin2 : in STD_LOGIC;
S2 : out STD_LOGIC_VECTOR (3 downto 0);
Cout2 : out STD_LOGIC);
end component;
begin
lvl1 : CAS_4 port map (A3(3 downto 0),B3(3 downto 0),ctrl3,ctrl3,S3(3 downto
0),sg);
lvl2 : CAS_4 port map (A3(7 downto 4),B3(7 downto 4),ctrl3,sg,S3(7 downto
4),Cout3);
end Behavioral;

You might also like