Write a VHDL test bench to verify the operation of the logic

Combinational Logic circuit. Provide a simulation waveform depicting all possible

input cases

Design using VHDL (a) Dataflow style

LIBRARY IEEE;
Sudhan Shrestha, Jebish Purbey USE IEEE.STD_LOGIC_1164.ALL;
Department of Electronics and Computer Engineering, IOE
ENTITY small_ckt IS PORT (
Central Campus, Pulchowk A, B, C, D: IN STD_LOGIC;
Lalitpur, Nepal F: OUT STD_LOGIC
);
INTRODUCTION END small_ckt;

A. Features of VHDL ARCHITECTURE dataflow OF small_ckt IS

BEGIN
B. Levels of representation and abstraction F <= (((A AND B) OR (NOT B AND C))
OR ((NOT B AND C) AND D));
C. Lexical Elements END dataflow;
1. Comments
2. Identifiers (b) Behavioral style
3. Numbers LIBRARY IEEE;
4. Characters USE IEEE.STD_LOGIC_1164.ALL;
5. Strings
6. Bit Strings ENTITY small_ckt IS PORT (
A, B, C, D: IN STD_LOGIC;
D. Expressions and Operators F: OUT STD_LOGIC
);
E. Sequential Statements END small_ckt;
.
1) Variable Assignment ARCHITECTURE behavorial OF small_ckt IS
2) If Statement SIGNAL F1, F2, F3, F4: STD_LOGIC;
3) Case Statement
BEGIN
4) Loop Statements
example: PROCESS(A,B,C,D,F1,F2,F3,F4)
5) Null Statement
BEGIN
6) Assertions
F1 <= A AND B;
F2 <= NOT B AND C;
F. VHDL Structure
F3 <= F1 OR F2;
1) Entity Declaration
F4 <= F2 AND D;
2) Architecture declaration
F <= F3 OR F4;
END PROCESS example;
I. ACTIVITY I
END behavorial;
Write VHDL code to implement the logic circuit shown in
figure, which has 4 inputs (x1, x2, x3, x4) and one output (f). (c) Structural style
Provide the following architectural styles: [and1.vhd]
Dataflow style LIBRARY IEEE;
Behavioral style USE IEEE.STD_LOGIC_1164.ALL;
Structural style
ENTITY and1 IS PORT (
i1, i2: IN STD_LOGIC;
o1: OUT STD_LOGIC
);
END and1;

ARCHITECTURE dataflow OF and1 IS

BEGIN COMPONENT or1 IS PORT (
o1 <= i1 AND i2; i1, i2: IN STD_LOGIC;
END dataflow; o1: OUT STD_LOGIC
);
[or1.vhd] END COMPONENT;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; BEGIN
C1: and1 PORT MAP (i1 => A, i2 => B,
ENTITY or1 IS PORT ( o1 => F1);
i1, i2: IN STD_LOGIC; C2: andnot PORT MAP (i1 => B, i2 =>
o1: OUT STD_LOGIC C, o1 => F2);
); C3: or1 PORT MAP (i1 => F1, i2 => F2,
END or1; o1 => F3);
C4: and1 PORT MAP (i1 => F2, i2 =>
ARCHITECTURE dataflow OF or1 IS D, o1 => F4);
BEGIN C5: or1 PORT MAP (i1 => F3, i2 => F4,
o1 <= i1 OR i2; o1 => F);
END dataflow; END structural;

[andnot.vhd] (d) Test bench

LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY andnot IS PORT (
i1, i2: IN STD_LOGIC; ENTITY small_ckt_tb IS
o1: OUT STD_LOGIC END small_ckt_tb;
);
END andnot; ARCHITECTURE behav OF small_ckt_tb IS
COMPONENT small_ckt
ARCHITECTURE dataflow OF andnot IS PORT(
BEGIN A, B, C, D: IN STD_LOGIC;
o1 <= NOT i1 AND i2; F: OUT STD_LOGIC
END dataflow; );
END COMPONENT;
[small_ckt_structural.vhd]
LIBRARY IEEE; SIGNAL input_vector:
USE IEEE.STD_LOGIC_1164.ALL; STD_LOGIC_VECTOR( 3 DOWNTO 0) := "0000";
SIGNAL output: STD_LOGIC;
ENTITY small_ckt IS PORT (
A, B, C, D: IN STD_LOGIC; BEGIN
F: OUT STD_LOGIC uut: small_ckt PORT MAP(
); A => input_vector(3),
END small_ckt; B => input_vector(2),
C => input_vector(1),
ARCHITECTURE structural OF small_ckt IS D => input_vector(0),
SIGNAL F1, F2, F3, F4: STD_LOGIC; F => output
COMPONENT and1 IS PORT ( );
i1, i2: IN STD_LOGIC;
o1: OUT STD_LOGIC stim_proc: PROCESS
); BEGIN
END COMPONENT; FOR index IN 0 TO 15 LOOP
input_vector <=
COMPONENT andnot IS PORT ( std_logic_vector(to_unsigned(index,4));
i1, i2: IN STD_LOGIC; WAIT FOR 50 ns;
o1: OUT STD_LOGIC END LOOP;
); END PROCESS;
END COMPONENT; END behavioral;
 Discussion: END dataflow;

Output: (c) Behavioral style

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY bcd_gray IS PORT (

X3, X2, X1, X0: IN STD_LOGIC;
II. ACTIVITY II Y3, Y2, Y1, Y0: OUT STD_LOGIC
Write VHDL code to design a logic circuit that implements );
the truth table of BCD-to-Gray code converter. Use Karnaugh END bcd_gray;
maps to simplify the output functions. Provide the following
architectural styles: ARCHITECTURE behavorial OF bcd_gray IS
Dataflow style
Behavioral style BEGIN
Structural style PROCESS(X3,X2,X1,X0)
TABLE – I
TRUTH TABLE OF BCD-TO-GRAY CODE CONVERTER BEGIN
BCD Numbers Gray Code Numbers Y3 <= X3;
Y2 <= X2 XOR X3;
X3 X2 X1 X0 Y3 Y2 Y1 Y0
Y1 <= X1 XOR X2;
0 0 0 0 0 0 0 0 Y0 <= X0 XOR X1;
0 0 0 1 0 0 0 1 END PROCESS
0 0 1 0 0 0 1 1
END behavorial;
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0 (d) Structural style (using only NOR gates)
0 1 0 1 0 1 1 1 [xor_nor.vhd]
0 1 1 0 0 1 0 1 LIBRARY IEEE;
0 1 1 1 0 1 0 0
USE IEEE.STD_LOGIC_1164.ALL;
: : : : : : : : ENTITY xor_nor IS PORT (
1 1 1 1 1 0 0 0 a, b: IN STD_LOGIC;
o: OUT STD_LOGIC
Write a VHDL test bench to verify the operation of the logic );
circuit. Provide a simulation waveform depicting all possible END xor_nor;
input cases.
ARCHITECTURE behavorial OF xor_nor IS
SIGNAL nota, notb, xnorab: STD_LOGIC;
(a) Karnaugh Map Simplification
BEGIN
xor_nor: PROCESS (a,b,nota,notb,xnorab)
(b) Dataflow style
LIBRARY IEEE;
BEGIN
USE IEEE.STD_LOGIC_1164.ALL;
nota <= a NOR a;
notb <= b NOR b;
ENTITY bcd_gray IS PORT (
xnorab <= (a NOR notb) NOR
X3, X2, X1, X0: IN STD_LOGIC;
(nota NOR b);
Y3, Y2, Y1, Y0: OUT STD_LOGIC
o <= xnorab NOR xnorab;
);
END bcd_gray;
END PROCESS xor_nor;
ARCHITECTURE dataflow OF bcd_gray IS
END behavorial;
BEGIN
Y3 <= X3; [bcd_gray_structural.vhd]
LIBRARY IEEE;
Y2 <= X2 XOR X3;
USE IEEE.STD_LOGIC_1164.ALL;
Y1 <= X1 XOR X2;
Y0 <= X0 XOR X1;
ENTITY bcd_gray IS PORT ( );
X3, X2, X1, X0: IN STD_LOGIC;
Y3, Y2, Y1, Y0: OUT STD_LOGIC stim_proc: PROCESS
);
END bcd_gray; BEGIN
FOR index IN 0 TO 15 LOOP
ARCHITECTURE structural OF bcd_gray IS input_vector <=
std_logic_vector(to_unsigned(index,4));
COMPONENT xor_nor IS PORT ( WAIT FOR 50 ns;
a, b: IN STD_LOGIC; END LOOP;
o: OUT STD_LOGIC END PROCESS;
); END behavioral;
END COMPONENT;
Discussion:
BEGIN
C0: xor_nor PORT MAP (a => X3, b => Output:
'0', o => Y3);
C1: xor_nor PORT MAP (a => X3, b =>
X2, o => Y2);
C2: xor_nor PORT MAP (a => X2, b =>
X1, o => Y1); III. ACTIVITY III
C3: xor_nor PORT MAP (a => X1, b => Write VHDL code to implement the logic function (f) with
X0, o => Y0); three input variables x1, x2, x3. The function (f) is equal to 1 if
and only if two variables are equal to 1; otherwise, it is equal to
END structural; zero. Draw a truth table for the function (f), and use Karnaugh
maps to simplify. Provide the following architectural styles:
(e) Test Bench Dataflow style
LIBRARY IEEE; Behavioral style
USE IEEE.STD_LOGIC_1164.ALL; Structural style (using only NAND gates)
USE IEEE.NUMERIC_STD.ALL; Write a VHDL test bench to verify the operation of the logic
circuit. Provide a simulation waveform depicting all possible
ENTITY bcd_gray_tb IS input cases.
END bcd_gray_tb;
(a) Truth Table
ARCHITECTURE behavioral OF bcd_gray_tb IS
COMPONENT bcd_gray
PORT( (b) Karnaugh Map Simplification
X3, X2, X1, X0: IN STD_LOGIC;
Y3, Y2, Y1, Y0: OUT STD_LOGIC;
);
(c) Dataflow style
END COMPONENT; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
SIGNAL input_vector:
STD_LOGIC_VECTOR( 3 DOWNTO 0) := "0000"; ENTITY func IS PORT (
SIGNAL output_vector: X1, X2, X3: IN STD_LOGIC;
STD_LOGIC_VECTOR( 3 DOWNTO 0) := "0000"; F: OUT STD_LOGIC
);
BEGIN END func;
uut: bcd_gray PORT MAP(
X3 => input_vector(3), ARCHITECTURE dataflow OF func IS
X2 => input_vector(2), BEGIN
X1 => input_vector(1), F <= (X1 AND X2 AND NOT X3) OR (X3
X0 => input_vector(0), AND (X1 XOR X2));
END dataflow;
Y3 => output_vector(3),
Y2 => output_vector(2),
(d) Behavioral style
Y1 => output_vector(1),
LIBRARY IEEE;
Y0 => output_vector(0) USE IEEE.STD_LOGIC_1164.ALL;
ENTITY func IS PORT ( ARCHITECTURE behavorial OF or1 IS
X1, X2, X3: IN STD_LOGIC; SIGNAL G1, G2, G3, G4, G5: STD_LOGIC;
F: OUT STD_LOGIC
); BEGIN
END func; PROCESS (a,b,c,G1,G2,G3,G4,G5)
BEGIN
ARCHITECTURE behavioral OF func IS G1 <= a NAND a;
SIGNAL A1, A2, A3: STD_LOGIC; G2 <= b NAND b;
G3 <= G1 NAND G2;
BEGIN G4 <= G3 NAND G3;
PROCESS (X1,X2,X3,A1,A2,A3) G5 <= c NAND c;
o <= G4 NAND G5;
BEGIN END PROCESS;
A1 <= X1 AND X2 AND NOT X3;
A2 <= X1 XOR X2; END behavorial;
A3 <= A2 AND X3;
F <= A1 OR A3; [func_structural.vhd]
END PROCESS; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
END behavioral;
ENTITY func IS PORT (
(e) Structural style X3, X2, X1: IN STD_LOGIC;
[func_and1.vhd] F: OUT STD_LOGIC
LIBRARY IEEE; );
USE IEEE.STD_LOGIC_1164.ALL; END func;

ENTITY and1 IS PORT ( ARCHITECTURE structural OF func IS

a, b, c: IN STD_LOGIC; SIGNAL A1, A2, A3: STD_LOGIC;
o: OUT STD_LOGIC
); COMPONENT and1 IS PORT (
END and1; a, b, c: IN STD_LOGIC;
o: OUT STD_LOGIC
ARCHITECTURE behavorial OF and1 IS );
SIGNAL F1, F2, F3, F4: STD_LOGIC; END COMPONENT;

BEGIN COMPONENT or1 IS PORT (

a, b, c: IN STD_LOGIC;
PROCESS (a,b,c,F1,F2,F3,F4) o: OUT STD_LOGIC
BEGIN );
F1 <= a NAND a; END COMPONENT;
F2 <= F1 NAND b;
F3 <= F2 NAND F2; BEGIN
F4 <= F3 NAND c; N1: and1 PORT MAP (a => X1, b
o <= F4 NAND F4; => X2, c => X3, o => A1);
END PROCESS; N2: and1 PORT MAP (a => X2, b
=> X3, c => X1, o => A2);
END behavorial; N3: and1 PORT MAP (a => X3, b
=> X1, c => X2, o => A3);
[func_or1.vhd] N4: or1 PORT MAP (a => A1, b
LIBRARY IEEE; => A2, c => A3, o => F);
USE IEEE.STD_LOGIC_1164.ALL;
END structural;
ENTITY or1 IS PORT (
a, b, c: IN STD_LOGIC; (f) Test Bench
o: OUT STD_LOGIC LIBRARY IEEE;
); USE IEEE.STD_LOGIC_1164.ALL;
END or1; USE IEEE.NUMERIC_STD.ALL;
 ENTITY func_tb IS
END func_tb; (a) Dataflow style (for F1)
LIBRARY IEEE;
ARCHITECTURE behavioral OF func_tb IS USE IEEE.STD_LOGIC_1164.ALL;
COMPONENT func
PORT ( ENTITY sop IS PORT (
X1, X2, X3: IN STD_LOGIC; X1, X2, X3, X4: IN STD_LOGIC;
F: OUT STD_LOGIC Y: OUT STD_LOGIC
); );
END COMPONENT; END sop;

SIGNAL input: STD_LOGIC_VECTOR(2 ARCHITECTURE dataflow OF sop IS

DOWNTO 0):= "000";
SIGNAL output: STD_LOGIC :='0'; BEGIN
Y <= (NOT X1 AND NOT X3) OR (NOT X2
BEGIN AND NOT X3) OR (X1 AND X2 AND X3);
uut: func PORT MAP ( END dataflow;
X3 => input(2),
X2 => input(1), (b) Behavioral style (for F1)
X1 => input(0), LIBRARY IEEE;
F => output USE IEEE.STD_LOGIC_1164.ALL;
);
ENTITY sop IS PORT (
stim_proc: PROCESS X1, X2, X3, X4: IN STD_LOGIC;
BEGIN Y: OUT STD_LOGIC
FOR index IN 0 TO 7 LOOP );
input <= STD_LOGIC_VECTOR END sop;
(TO_UNSIGNED(index,3));
WAIT FOR 50 ns; ARCHITECTURE behavorial OF sop IS
END LOOP;
END PROCESS; BEGIN

END behavioral; PROCESS(X1,X2,X3,X4)

Discussion: BEGIN
Y <= (NOT X1 AND NOT X3) OR (NOT X2
Output: AND NOT X3) OR (X1 AND X2 AND X3);

END PROCESS;
IV. ACTIVITY IV
Write VHDL code to implement the implicit sum of END behavorial;
products (SOP) and product of sum (POS) logic functions
F1(x1,x2,x3,x4) = ∑ (m0,m1,m4,m5,m8,m9,m14,m15) (c) Structural style (using only NAND gates) (for F1)
F2(x1,x2,x3,x4) = ∏ (M0,M1,M5,M8,M9,M13,M15) [sop_and.vhd]
Draw the truth tables for the functions, and use Karnaugh LIBRARY IEEE;
maps to simplify. Provide the following architectural styles: USE IEEE.STD_LOGIC_1164.ALL;
Dataflow style
Behavioral style ENTITY and1 IS PORT (
a, b: IN STD_LOGIC;
Structural style (using only NAND gates)
o: OUT STD_LOGIC
Write a VHDL test bench to verify the operation of the
);
logic circuit. Provide a simulation waveform depicting all
END and1;
possible input cases.
ARCHITECTURE behavorial OF and1 IS
(a) Truth Table
SIGNAL F: STD_LOGIC;

BEGIN
(b) Karnaugh Map Simplification
 LIBRARY IEEE;
PROCESS (a,b,F) USE IEEE.STD_LOGIC_1164.ALL;

BEGIN ENTITY sop IS PORT (

F <= a NAND b; X1, X2, X3, X4: IN STD_LOGIC;
o <= F NAND F; Y: OUT STD_LOGIC
);
END PROCESS; END sop;

END behavorial; ARCHITECTURE structural OF sop IS

SIGNAL NX1, NX2, NX3, F: STD_LOGIC;
[sop_or.vhd] SIGNAL I1, I2, I3, I4: STD_LOGIC;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; COMPONENT not1 IS PORT (
a: IN STD_LOGIC;
ENTITY or1 IS PORT ( o: OUT STD_LOGIC
a,b: IN STD_LOGIC; );
o: OUT STD_LOGIC END COMPONENT;
);
END or1; COMPONENT and1 IS PORT (
a, b: IN STD_LOGIC;
ARCHITECTURE behavorial OF or1 IS o: OUT STD_LOGIC
SIGNAL G1,G2: STD_LOGIC; );
END COMPONENT;
BEGIN
COMPONENT or1 IS PORT (
PROCESS (a,b,G1,G2) a, b: IN STD_LOGIC;
o: OUT STD_LOGIC
BEGIN );
G1 <= a NAND a; END COMPONENT;
G2 <= b NAND b;
o <= G1 NAND G2; BEGIN
END PROCESS; N1: not1 PORT MAP (a => X1, o => NX1);
N2: not1 PORT MAP (a => X2, o => NX2);
END behavorial; N3: not1 PORT MAP (a => X3, o => NX3);

[sop_not.vhd] A1: and1 PORT MAP (a => NX1, b => X3,

LIBRARY IEEE; o => I1);
USE IEEE.STD_LOGIC_1164.ALL; A2: and1 PORT MAP (a => NX2, b =>
NX3, o => I2);
ENTITY not1 IS PORT ( A3: and1 PORT MAP (a => X1, b => X2,
a: IN STD_LOGIC; o => I3);
o: OUT STD_LOGIC A4: and1 PORT MAP (a => I3, b => X3,
); o => I4);
END not1;
O1: or1 PORT MAP (a => I1, b => I2,
ARCHITECTURE behavorial OF not1 IS o => F);
O2: or1 PORT MAP (a => F, b => I4, o
BEGIN => Y);

PROCESS (a) END structural;

BEGIN
o <= a NAND a; (d) Dataflow style (for F2)
END PROCESS; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
END behavorial;
ENTITY pos IS PORT (
[sop_structural.vhd] X1, X2, X3, X4: IN STD_LOGIC;
 Y: OUT STD_LOGIC LIBRARY IEEE;
); USE IEEE.STD_LOGIC_1164.ALL;
END pos;
ENTITY or1 IS PORT (
ARCHITECTURE dataflow OF pos IS a, b: IN STD_LOGIC;
o: OUT STD_LOGIC
BEGIN );
Y <= (X3 OR NOT X4) AND (X2 OR X3) END or1;
AND (NOT X1 OR NOT X2 OR NOT X4);
END dataflow; ARCHITECTURE behavorial OF or1 IS
SIGNAL G1, G2: STD_LOGIC;
(e) Behavioral style (for F2)
LIBRARY IEEE; BEGIN
USE IEEE.STD_LOGIC_1164.ALL;
PROCESS (a,b,G1,G2)
ENTITY pos IS PORT ( BEGIN
X1, X2, X3, X4: IN STD_LOGIC; G1 <= a NAND a;
Y: OUT STD_LOGIC G2 <= b NAND b;
); o <= G1 NAND G2;
END pos; END PROCESS;

ARCHITECTURE behavorial OF pos IS END behavorial;

BEGIN [pos_not.vhd]
LIBRARY IEEE;
PROCESS(X1,X2,X3,X4) USE IEEE.STD_LOGIC_1164.ALL;
BEGIN
Y <= (X3 OR NOT X4) AND (X2 OR X3) ENTITY not1 IS PORT (
AND (NOT X1 OR NOT X2 OR NOT X4); a: IN STD_LOGIC;
END PROCESS; o: OUT STD_LOGIC
);
END behavorial; END not1;

(f) Structural style (using only NAND gates) (for F2) ARCHITECTURE behavorial OF not1 IS
[pos_and.vhd]
LIBRARY IEEE; BEGIN
USE IEEE.STD_LOGIC_1164.ALL;
PROCESS (a)
ENTITY and1 IS PORT ( BEGIN
a, b: IN STD_LOGIC; o <= a NAND a;
o: OUT STD_LOGIC END PROCESS;
);
END and1; END behavorial;

ARCHITECTURE behavorial OF and1 IS [pos_structural.vhd]

SIGNAL F: STD_LOGIC; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
BEGIN
ENTITY pos IS PORT (
PROCESS (a,b,F) X1, X2, X3, X4: IN STD_LOGIC;
BEGIN Y: OUT STD_LOGIC
F <= a NAND b; );
o <= F NAND F; END pos;
END PROCESS;
ARCHITECTURE structural OF pos IS
END behavorial; SIGNAL NX1, NX2, NX4, F: STD_LOGIC;
SIGNAL I1, I2, I3, I4: STD_LOGIC;
[pos_or.vhd]
 COMPONENT not1 IS PORT (
a: IN STD_LOGIC; BEGIN
o: OUT STD_LOGIC uut: sop PORT MAP(
); X1 => input_vector(3),
END COMPONENT; X2 => input_vector(2),
X3 => input_vector(1),
COMPONENT and1 IS PORT ( X4 => input_vector(0),
a, b: IN STD_LOGIC; Y => output
o: OUT STD_LOGIC );
);
END COMPONENT; stim_proc: PROCESS

COMPONENT or1 IS PORT ( BEGIN

a, b: IN STD_LOGIC; FOR index IN 0 TO 15 LOOP
o: OUT STD_LOGIC input_vector <=
); std_logic_vector(to_unsigned(index,4));
END COMPONENT; WAIT FOR 50 ns;
END LOOP;
BEGIN END PROCESS;
N1: not1 PORT MAP (a => X1, o => NX1);
N2: not1 PORT MAP (a => X2, o => NX2); END behavioral;
N3: not1 PORT MAP (a => X4, o => NX4);
Discussion:
O1: or1 PORT MAP (a => X3, b => NX4,
o => I1); Output (for sum of product, F1):
O2: or1 PORT MAP (a => X2, b => X3,
o => I2);
O3: or1 PORT MAP (a => NX1, b => NX2,
o => I3);
O4: or1 PORT MAP (a => I3, b => NX4, Output (for product of sun, F2):
o => I4);

A1: and1 PORT MAP (a => I1, b => I2,

o => F);
A2: and1 PORT MAP (a => F, b => I4, V. ACTIVITY V
o => Y); Write VHDL code to implement a 2:1 MUX having inputs
x1 and x2, select line s and output y.
END structural; `TABLE – IV
TRUTH TABLE FOR 2:1 MULTIPLEXER
(g) Test Bench
Select Line Input Lines Output Line
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; S X2 X1 Y
USE IEEE.NUMERIC_STD.ALL; 0 0 0 0
0 0 1 1
ENTITY sop_tb IS
0 1 0 0
END sop_tb;
0 1 1 1
ARCHITECTURE behavioral OF sop_tb IS 1 0 0 0
COMPONENT sop 1 0 1 0
PORT(
1 1 0 1
X1, X2, X3, X4: IN STD_LOGIC;
Y: OUT STD_LOGIC 1 1 1 1
); Provide the following architectural implementation:
END COMPONENT; Using WITH-SELECT statement
Using WHEN-ELSE statement
SIGNAL input_vector: Using IF-THEN-ELSE statement
STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL output: STD_LOGIC:= '0';
 Write a VHDL test bench to verify the operation of the logic END IF;
circuit. Provide a simulation waveform depicting all possible END PROCESS;
input cases.
END behavioral;
(a) Using WITH-SELECT statement
LIBRARY IEEE; (d) Test Bench
USE IEEE.STD_LOGIC_1164.ALL; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux2to1 IS PORT ( USE IEEE.NUMERIC_STD.ALL;
S, X1, X2: IN STD_LOGIC;
Y: OUT STD_LOGIC ENTITY mux2to1_tb IS
); END mux2to1_tb;
END mux2to1;
ARCHITECTURE behavioral OF mux2to1_tb IS
ARCHITECTURE dataflow OF mux2to1 IS COMPONENT mux2to1
BEGIN PORT (
WITH (NOT S AND X1) OR (S AND X2) S, X1, X2: IN STD_LOGIC;
SELECT Y: OUT STD_LOGIC
Y <= '1' WHEN '1', );
'0' WHEN '0', END COMPONENT;
'0' WHEN OTHERS;
END dataflow; SIGNAL input: STD_LOGIC_VECTOR(2
DOWNTO 0):= "000";
(b) Using WHEN-ELSE statement SIGNAL output: STD_LOGIC;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; BEGIN
uut: mux2to1 PORT MAP (
ENTITY mux2to1 IS PORT ( S => input(2),
S, X1, X2: IN STD_LOGIC; X2 => input(1),
Y: OUT STD_LOGIC X1 => input(0),
); Y => output
END mux2to1; );

ARCHITECTURE dataflow OF mux2to1 IS stim_proc: PROCESS

BEGIN
Y <= '1' WHEN ((NOT S AND X1) OR (S BEGIN
AND X2)) = '1' ELSE FOR index IN 0 TO 7 LOOP
` '0'; input <= STD_LOGIC_VECTOR
END dataflow; (TO_UNSIGNED(index,3));
WAIT FOR 50 ns;
(c) Using IF-THEN-ELSE statement END LOOP;
LIBRARY IEEE; END PROCESS;
USE IEEE.STD_LOGIC_1164.ALL;
END behavioral;
ENTITY mux2to1 IS PORT (
S, X1, X2: IN STD_LOGIC; Discussion:
Y: OUT STD_LOGIC Output:
);
END mux2to1;
VI. ACTIVITY VI
ARCHITECTURE behavioral OF mux2to1 IS Write VHDL code to implement a 4-bit adder/subtracter
BEGIN using four 1-bit full adders

PROCESS (S,X1,X2)
BEGIN
IF ((NOT S AND X1) OR (S AND X2)) =
'1' THEN Y <= '1';
ELSE Y <= '0';
 END xor1;

ARCHITECTURE dataflow OF xor1 IS

BEGIN
o1 <= i1 XOR i2;
END dataflow;

[full_adder.vhd]
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

Fig. 4-bit adder/subtracter using 1-bit Full Adder ENTITY full_adder IS PORT (
i1, i2, cin: IN STD_LOGIC;
`TABLE – V sum, cout: OUT STD_LOGIC
TRUTH TABLE FOR 1-BIT FULL ADDER );
Input Bits Output END full_adder;
X Y Carry (Cin) Carry (Cout) Sum (S)
ARCHITECTURE dataflow OF full_adder IS
0 0 0 0 0 BEGIN
0 0 1 0 1 sum <= i1 XOR i2 XOR cin;
0 1 0 0 1 cout <= (i1 AND i2) OR ((i1 XOR i2)
AND cin);
0 1 1 1 0
END dataflow;
1 0 0 0 1
1 0 1 1 0 [add_sub_structural.vhd]
1 1 0 1 0 LIBRARY IEEE;
1 USE IEEE.STD_LOGIC_1164.ALL;
1 1 1 1
ENTITY add_sub IS PORT (
𝑺 = 𝑿 ⊕ 𝒀 ⨁ 𝑪𝒊𝒏 and 𝑪𝒐𝒖𝒕 = 𝑿𝒀 + (𝑿 ⊕ 𝒀) 𝑪𝒊𝒏 X3, X2, X1, X0: IN STD_LOGIC;
Y3, Y2, Y1, Y0, A_S: IN STD_LOGIC;
S4, S3, S2, S1, S0: OUT STD_LOGIC
);
END add_sub;

ARCHITECTURE structural OF add_sub IS

SIGNAL F0, F1, F2, F3: STD_LOGIC;
SIGNAL C1, C2, C3 : STD_LOGIC;

Fig. Logic Circuit for 1-bit Full Adder COMPONENT xor1 IS PORT (
i1, i2: IN STD_LOGIC;
Use structural architecture style with hierarchical design o1: OUT STD_LOGIC
approach. Use 1-bit adder as the basic building block. );
END COMPONENT;
Implement the 4-bit adder/subtracter using four 1-bit full
adders. Write a VHDL test bench to verify the operation of the
COMPONENT full_adder IS PORT (
4-bit adder/subtracter. Provide a simulation waveform
i1, i2, cin: IN STD_LOGIC;
depicting all possible input cases.
sum, cout: OUT STD_LOGIC
);
VHDL Code:
END COMPONENT;
[xor1.vhd]
LIBRARY IEEE; BEGIN
USE IEEE.STD_LOGIC_1164.ALL; A0: xor1 PORT MAP (i1 => A_S, i2 =>
Y0, o1 => F0);
ENTITY xor1 IS PORT ( A1: full_adder PORT MAP (i1 => X0,
i1, i2: IN STD_LOGIC; i2 => F0, cin => A_S, sum => S0, cout =>
o1: OUT STD_LOGIC C1);
);
 A2: xor1 PORT MAP (i1 => A_S, i2 =>
Y1, o1 => F1); S4 => output_vector(4),
A3: full_adder PORT MAP (i1 => X1, S3 => output_vector(3),
i2 => F1, cin => C1, sum => S1, cout => S2 => output_vector(2),
C2); S1 => output_vector(1),
S0 => output_vector(0)
A4: xor1 PORT MAP (i1 => A_S, i2 => );
Y2, o1 => F2);
A5: full_adder PORT MAP (i1 => X2, stim_proc: PROCESS
i2 => F2, cin => C2, sum => S2, cout =>
C3); BEGIN
FOR index1 IN 0 TO 15 LOOP
A6: xor1 PORT MAP (i1 => A_S, i2 => input_vector1 <=
Y3, o1 => F3); std_logic_vector(to_unsigned(index1,4));
A7: full_adder PORT MAP (i1 => X3, FOR index2 IN 0 TO 15 LOOP
i2 => F3, cin => C3, sum => S3, cout => input_vector2 <=
S4); std_logic_vector(to_unsigned(index2,4));
WAIT FOR 50 ns;
END structural; END LOOP;
END LOOP;
Test Bench END PROCESS;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; END behavioral;
USE IEEE.NUMERIC_STD.ALL;

ENTITY add_sub_tb IS Discussion:

END add_sub_tb;
Output:
ARCHITECTURE behavioral OF add_sub_tb IS
COMPONENT add_sub
PORT( For subtraction:
X3, X2, X1, X0: IN STD_LOGIC;
Y3, Y2, Y1, Y0: IN STD_LOGIC; VII. ACTIVITY VII
A_S: IN STD_LOGIC; Write VHDL code to implement a 4:1 MUX having inputs
S4,S3,S2,S1,S0: OUT STD_LOGIC (x1, x2, x3, and x4), select lines (s1, s0) and output (y) using
); three 2:1 multiplexers as the basic building blocks.
END COMPONENT;

SIGNAL addsub: STD_LOGIC := '0';

SIGNAL input_vector1:
STD_LOGIC_VECTOR( 3 DOWNTO 0) := "0000";
SIGNAL input_vector2:
STD_LOGIC_VECTOR( 3 DOWNTO 0) := "0000";
SIGNAL output_vector:
STD_LOGIC_VECTOR( 4 DOWNTO 0) := "00000";

BEGIN
uut: add_sub PORT MAP(
A_S => addsub,
X3 => input_vector1(3),
Use a hierarchical design approach. Create component
X2 => input_vector1(2),
definitions in separate (.vhd) files. Use either Dataflow or
X1 => input_vector1(1),
Behavioral or Structural design styles. Use structural design
X0 => input_vector1(0),
style for the 4:1 MUX architecture. Make use of 2:1 MUX
Y3 => input_vector2(3), component declaration. Make use of 2:1 MUX component
Y2 => input_vector2(2), instantiation. Write a VHDL test bench to verify the operation
Y1 => input_vector2(1), of the 4:1 MUX. Provide a simulation waveform depicting all
Y0 => input_vector2(0), possible input cases.
VHDL Code: ARCHITECTURE behavioral OF mux4to1_tb IS
[mux2to1_dataflow.vhd] COMPONENT mux4to1
LIBRARY IEEE; PORT(
USE IEEE.STD_LOGIC_1164.ALL; X1, X2, X3, X4: IN STD_LOGIC;
ENTITY mux2to1 IS PORT ( S0, S1: IN STD_LOGIC;
SEL, I1, I2: IN STD_LOGIC; Y: OUT STD_LOGIC
O: OUT STD_LOGIC );
); END COMPONENT;
END mux2to1;
SIGNAL select_vec:
ARCHITECTURE dataflow OF mux2to1 IS STD_LOGIC_VECTOR( 1 DOWNTO 0) := "00";
BEGIN SIGNAL input_vec:
WITH (NOT SEL AND I1) OR (SEL AND I2) STD_LOGIC_VECTOR( 3 DOWNTO 0) := "0000";
SELECT SIGNAL output: STD_LOGIC := '0';
O <= '1' WHEN '1',
'0' WHEN '0', BEGIN
'0' WHEN OTHERS; uut: mux4to1 PORT MAP(
END dataflow; S0 => select_vec(0),
S1 => select_vec(1),
[mux4to1_structural.vhd] X1 => input_vec(3),
LIBRARY IEEE; X2 => input_vec(2),
USE IEEE.STD_LOGIC_1164.ALL; X3 => input_vec(1),
X4 => input_vec(0),
ENTITY mux4to1 IS PORT ( Y => output
X1, X2, X3, X4, S0, S1: IN STD_LOGIC; );
Y: OUT STD_LOGIC
); stim_proc: PROCESS
END mux4to1;
BEGIN
ARCHITECTURE structural OF mux4to1 IS FOR selector IN 0 TO 3 LOOP
SIGNAL F1, F2: STD_LOGIC; select_vec <= std_logic_vector
(to_unsigned(selector,2));
COMPONENT mux2to1 IS PORT ( FOR index IN 0 TO 15 LOOP
I1, I2, SEL: IN STD_LOGIC; input_vec <=
O: OUT STD_LOGIC std_logic_vector(to_unsigned(index,4));
); WAIT FOR 50 ns;
END COMPONENT; END LOOP;
END LOOP;
BEGIN END PROCESS;
M0: mux2to1 PORT MAP (I1 => X1, I2 END behavioral;
=>
X2, SEL => S0, O => F1); Discussion:
M1: mux2to1 PORT MAP (I1 => X3, I2 Output:
=>
X4, SEL => S0, O => F2);
M2: mux2to1 PORT MAP (I1 => F1, I2 CONCLUSION
=>
F2, SEL => S1, O => Y);
END structural;

Test bench
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY mux4to1_tb IS
END mux4to1_tb;