Q No Question Answer Domain Subdomain Subdomain

1 what is magnet placemen PLACEMENT MAGNET PLACEM PLACEMENT

To perform magnet placement, use the magnet_placement command with a specification of th
2 is there a chance to hold no , becaz in place comboPLACEMENT PLACE
If width increases the resistance reduces, due to that delay reduces, as the delay and resistanc
3 In which way it is useful Placement Timing DRC's wrtCMOS
4 Max tran violations are thThe expected results will Placement Timing DRC's wrtAdvanced level t
2. Unconstrained Pins
5 What do you know about Placement Pre-Placement Sanity Checks
3. Un-driven
7. i/p Ports
High cell density.
6 What type of congestion Placement Congestion Analysis and debug
8. High local utilization.
7 Can we do a setup check Yes, we will check the se Placement
● (buffers are inserted for fixing fanout violations Timing Analysis and debug
and hence they reduce setup violation; ot
8 In A Reg to Reg Path If ● Near the capture path. Placement Timing Analysis and debug
Fixes:Because there may be other paths passing through or originating from the flop nearer to l
9 What are Timing DRV/'s, e●*We Placement Timing DRC's w.r.t data path
Max have
Tran:to take care by applying bounds and path groups based on the heirarchy communic
10 What should we do if ther*● Have
forto check
e.g. Let usheirarchy
assumePlacement
placement
that you start is done
setup
with properly
all timing
pathsand
inanalysis
a which
single are
pathcommunicating
group. to the int
11 *Let the tool have the right
What is a path group in VL● In this case the synthesis constraints at place
engine will spend
Placement Timingstage,
most and maybe optimizing the logic ofwith
give
of its timetechnique
optimization another round tim
the wor
●
● Post
Now Place
lookingOpt at the initial timing report you might have identified.
12 What placement optimizat Placement placement optimizations
● Incremental Opt
13 What is congestion? If the number of routing tPlacement congestion analysis and debug
● Pre-Cts = Jitter + Skew + Extra setup margin
14 What is Uncertainty? Why● collect all the nets from Placement SDC paths
FILE & re-route them incrementally on metal l
● Cts = Jitter + Extra setup the critical timing
margin
15 How do you fix DRC’s in a● We can apply cell padding Placementor module padding
DRC andblindly. But it may impact timing as it distur
Short violations
16 ● Finally
Relationship between timTiming try tois trim
window PG Placement
nothing straps by removing someAnalysis
Timing vias without impacting the IR drop limit giv
and debug
17 If you want to improve t Frequency. If you increas Placement Timing Analysis and debug
North and south pins should be in vertical metal layers (M2,4,6).
18 In which metal do you pre PLACEMENT Placement Overvi
East and west
2) Leakage pins consumption
power should be horizontal metal layers (M1,3,5)
19 What are the advantages PLACEMENT IR Drop , EM Ana
3) Performance degradation in terms of timing
20 What is Amoeba placemen Thebecause
No amoeba view to see tPLACEMENT
21 Can I add Spare cells inst • More static power consumption PLACEMENTof the spare cells compared to filler cells
•• Metal
Spare slot problems
cells are not will come.
available in all sizes.
22 Can I use number of FILL1 PLACEMENT
• Dishing
23 What is the difference b Timing-driven placement PLACEMENT (T
24 Could you place the standa No, we cannot place cell PLACEMENT Placement Qualit
25 Why standard cell width iTo get maximum metal routi PLACEMENT Physical Cells &
26 How much placement densi 65 to 75% is allowed. SomPLACEMENT Floor Plan Overv
27 If you have both IR drop aSpread macros, Spread sta Placement Congestion AnalyPDN
28 What are the placement oPreplace Opt, Inplace Optplacement Placement Optimizations
• timing ( drv’s and setup)
29 After placement what wil Placement Placement QualiPlacement Qualit
• core area utilization
30 What you mean by scan ch Answer1: Based on timing Placement
High standard cell density in particular area. Placement OptimPlacement Steps
31 If you are facing congesti High pin density in particular
• setPathGroupOptions area.-targetSlack
Placement
path1 Congestion
2 AnalyGlobal Route Con
32 If there are setup violati •Missing/Small
optDesignHalos near-incr
–preCTS macro cell.
Placement Timing Analysis Timing Analysis
33 If your congestion and ti iiThe. Module
definedconstraint
core areatechniques
is Placement : Congestion AnalyTiming Analysis
34 In my design I don’t have It may be due to over utilPlacement
2. Introduce the placement density screens Global
andRoute ConGlobal
placement Route(block
blockage Con halos)
35 How will you avoid the co3. RerunLogic
the optimization
fast placement if possible
Placement
with Congestion Congestion Analy
driven option Congestion
(Congestion Analyplacement)
driven
36 How you deal with the con 4. Module constraints
Modify physical constraints like fence,
Placement region and guide.
Congestion
such as adjust cell Analy
density in PD
congested areas. Because higher cell d
• Introduce the placement density i.e., Softscreens andHard
placement blockage (block halos)
37 How to do Congestion optUse/Modify proper blockages. Placement blockages,
Congestion blockages,
Analy PlacementMacro Padding
Optim are used pro
• Logic optimization if possible
 initial_place
initial_drc (performs
high fanout net
synthesis, buffering and
DRC fixes),
initial_opt (optimizes
the timing and
congestion)
final_place (performs
coarse placement)
final_opt (legalization
and optimization)
38 Placement? final_opt (legalization Placement Placement Steps
and optimization)
 . To view cell
density map, click on
view → map → cell
density
refine_opt

 check_legality
 report_congestion
 report_qor
 report_utilization
 report_constraints
–max_transition
 report_constraints
–max_capacitance
 timing reports
39 
Checks that have to be do report_constraints Placement Placement Quality Check
–all_violators

report_threshold_voltag
e_groups
 report_power
 check_mv_design
 After placement we will
check setup violations,
so while calculating
timing from in-to-reg
and reg- to-out paths it
requires external input
and output delays those
are mentioned in sdc
file. And also any path
exceptions like
40 why we use .sdc file in p multicycle path , false Placement Timing Analysis and debug
path and asynchronous
paths. And clock
definitions are required
for calculating timing.

At placement stage if
any std cells are placed
in macro channel , if we
didn’t get any
congestion issues then
we can place . if we are
getting congestion in
41 In between macros std cemacro channel then put Placement Placement Steps
any hard blockage to
avoid std cells
placement.

place_design optDesign
– preCTS
place_opt_desin
createPlacementBlockag
e checkPlace
refinePlace

report_utilization
42 What are all the placem (checkFPlan – Placement Placement Steps
reportUtil )
reportCongestion –
hotSpot report_timing

Congestion and timing

43 What issues you faced in violations Placement Congestion Analysis and debug
 path grouping can be
applied for in2reg paths,
reg2reg paths and
reg2out paths. The tool
will optimize these
paths based on the
weightage value given
to it.
Command:
• group_path -name
anyname(path1) -from
start point list –to end
point list – weight
integer value(1,2 ,3 etc)
• refine_opt -
path_group path1
44 what is path grouping? refine opt will do Placement Timing Analysis and debug
incremental
optimization. In path
grouping command we
have different sub
options. By using this
path grouping technique
we can optimize specific
paths or nets.

In pre-CTS Stage , by
upsizing or swapping the
cells in the data path we
3 Flops in Seris – Flop 1 tocan
flopfix2 this violations.
(-300ps slack) –flop2 and flop3 (+100ps slack)
45 Another method is using Placement Timing Analysis and debug
? pre CTS how you will fix?
Time borrowing
technique.

Mainly SVT cells are

allowed in the design at
placement stage. Yes,
46 What Vt cells you have ustiming was met in Placement Timing Analysis and debug
preroute stage.
 There are many reasons:
1. The starting points
and endpoints of flops
are placed far apart ,
then due to long routing
the path get violated.
This happens because of
scan chain reordering is
not done in optimization
stage.
2. During optimization if
some nets are not
optimized properly due
to
don’t touch constraint.
Take care:
47 If your setup slack is wo 1. Do scan chain Placement Timing Analysis and debug
reordering.
2. Observe nets are
optimized properly or
not, if not then look on
net
property and change it
to don’t touch as false.

In placement stage clock

is ideal that means the
skew is zero. Setup slack
is difference of required
path and arrival path.
Setup slack = RT – AT. If
RT value is less
compared to AT value
then we get the setup
48 Why setup violation occuviolation. In placement Placement Timing Analysis and debug
stage clock is ideal so
less delay is present in
clock path, so we get
setup violations.

Because clock tree is not

build at placement stage
that means clock is
ideal. Clock ideal
49 Why hold violation is not means , skew is zero, so Placement Timing Analysis and debug
we can’t get hold
violations.
 congestion occurs
mainly due to three
reasons. i. high cell
density ii. high pin
density iii. Bad
floorplan techniques for
reducing congestion are:
i. cell density : if
congestion is due to cell
density ,then apply
partial blockages at that
area to reduce cell
density in that region.
ii. Pin density : if
congestion is due to pin
density ,then apply cell
padding techniques. iii.
bad floorplan (notches) :
50 How do we reduce congesif we have congestion at Placement Congestion Analysis and debug
macro edges ,
then apply hard
blockages to reduce
congestion.
Other techniques are:
1. specify a maximum
density that controls
how densely the tool
can place cells in
uncongested areas
during wire-length-
driven placement.
place.coarse.max_densit
y ( default is 0 and the
tool spreads cells
uniformly by default)
2. Specify a
congestion-driven
icc2_lm_shell -f
51 What is the procedure to ndm_gen.tcl Placement Congestion Analysis and debug
 max_density: specify a
maximum density that
controls how densely
the tool can place cells
in uncongested areas
during wire-length-
driven placement.
place.coarse.max_densit
y ( default is 0 and the
tool spreads cells
uniformly by default)
max_util: Specify a
congestion-driven
maximum utilization
that controls how
densely the tool can
place cells in less
congested areas that
52 what is difference betwe surround highly Placement
congested areas, so that
the cells in the
congested areas can be
spread out to reduce
the congestion.
place.coarse.congestion
_driven_max_util
(Default is 0.93)
When specifying the
maximum density or
congestion-driven
maximum utilization,
choose a value between
1 and the overall
utilization of the block.
For example, if the
utilization of a block is
40 percent, you can
• netlist (.v)
• sdc
• lef
• FP.def
53 What are the inputs for • lib Placemet Inputs & Pre-Placement Sanity Ch
• captables,.TF & Scan
dft

54 How do you fix congestionChange

i max density valuePlacement
& placement
55 What measures do you take Placement reduce congesti Placement Congestion Analysis and debug
56 Icc vs extraction correlation
1. Make sure that the same Placement
57 Placement targets 1. Meeting timing (wns {worst negative slack},
Placement tns {total
Placement negative slack}, fep{failing end points)
Steps
58 Placement inputs 2.
1. Congestion
Fp completed in limit
design(0.5% h, v;
Placementlower tech hotspot: total < 10000,
Pre-Placement Sanity max < 200)
Checks
59 Placement results 2.
1. Sdc, mmmc
Legalized cell placement Placement Placement Optimizations
60 Placement checks. 2. Congestion
Legality of cell placementPlacement
timing module placement
Placementpath by path congestion congestion = (req
Steps
61 1: pin density is high and cell density
Design starting utilizatio This will have more cell d Placement is okayCongestion Analysis cond
keep_out_margin and debug
62 Placement output Timing congestion designPlacement Timing Analysis and debug
63 Why we are not checkingBefore CTS, clock is ideal Placement Timing Analysis and debug
64 Placement commands visual check on the databa Placement Placement Quality Check
65 What is need of early clo Early estimation of routing Placement Timing Analysis and debug
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ment Optimizations
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