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Midterm Project - Computer Architecture-1

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21 views

Midterm Project - Computer Architecture-1

Uploaded by

Islam
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© © All Rights Reserved
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Alamein University Course Name: Computer

Faculty of Computer Science & Architecture and Organization


Engineering Course Code: CSE132

Small-Project [Midterm]

The manager of the ALameinBank bank branch, located in a Alamein is proposing to install
an embedded system to monitor the client queue in front of the tellers. The proposed
system, called ABQM™, is to display various information about the status of the queue. The
detailed specification of ABQM™ is as follows:
1. Both queue ends are equipped with a photocell. Each photocell generates a logic ‘1’
signal if nobody interrupts a light beam generated at the corresponding queue end.
When the light beam is interrupted, the photocell output changes to logic ‘0’ and stays
at that value until it is no longer interrupted.
2. Clients are supposed to enter the queue only from the back end and leave only from
the front end.
3. The number of people standing in the queue (waiting to be served by a teller), Pcount,
and the expected waiting time in the queue before being served, Wtime, are to be
displayed on Seven Segment Display.
4. Pcount is to be incremented by only one when a client enters the queue and is to be
decremented by only one when a client leaves, even if a client stands in front of the
light beam for a long time period.
5. Wtime, in seconds, could approximately be given by the formulas:

Wtime (Pcount = 0) = 0,

Wtime (Pcount  0,Tcount) = 3*(Pcount+Tcount-1)/Tcount

where Tcount is the number of tellers currently in service (Tcount  {1,2,3}) and
Wtime is rounded by ignoring the fraction part.
6. ABQM™ maintains binary empty and full flags that reflect the status of the queue.
7. A responsible person should have the capability of resetting the system. Resetting the
system clears the full flag and Pcount, and the sets empty flag.

The design team has met few times to decide on the following for the ABQM™
architecture:

• Although the system could be modeled as one big FSM, it was decided to decompose
the system into smaller FSMs. Design reuse is also recommended. That is, one small
FSM model can be repeated multiple times in the overall system model.
• An n-bit up-down counter is to be used to generate Pcount. The maximum Pcount value
will be (2n - 1), with a default value of 7, where n is a generic value, with a default value
of 3.
• There will be an internal system clock.
• Although random logic can be used in calculating Wtime, it was decided to use a look-
up table to achieve a better runtime performance. The lookup table is to be realized as
a ROM.

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Alamein University Course Name: Computer
Faculty of Computer Science & Architecture and Organization
Engineering Course Code: CSE132

In this project, you are going to model the operation of ABQM™ and verify it via
simulation. Then, you will synthesize the model. Here is the list of deliverables:

a) In a table, identify ABQM™ inputs and outputs and briefly describe their meaning and
possible values.
b) Draw an icon for the ABQM™, clearly showing its input and output signals.
c) Draw a block diagram showing the ABQM™ structure.
d) Draw the necessary FSM diagram(s).
e) Model the up-down counter as a separate component using a Verilog behavioral
description.
f) Model the required FSM(s) in Verilog.
g) Model ABQM™ using a mixed architecture Verilog code. Use concurrent descriptions
for the binary flags. The model should issue an alarm if the queue is already full/empty
and somebody tries to enter/leave.
h) In a table, propose a test strategy to verify the operation of the ABQM™ model.
Carefully select an appropriate set of test cases that test various design aspects. For
example, you should test that the two flags reflect the correct status of the queue.
Additionally, you should ensure that the counter does not wrap around. That is, it does
not display ‘0’ when it gets an increment signal while the queue is full or ‘7’ when it
gets a decrement signal while the queue is empty.
i) Design a testbench to verify the operation of the ABQM™ model using the test strategy
proposed in the previous point. Provide simulation result snapshots.
Bonus
j) Synthesize the ABQM™ architecture in part (g).
k) Include a diagram of the synthesized output with your submission. [Use Quartus to get
the diagram]
l) In Lab, program the DE10-lite board and test your code.
Here are some hints:

• To apply hierarchy and modularity concepts, Try to decompose the ABQM™


architecture into a number of small procedures. Each procedure should be responsible
for updating some of the output signals. Avoid having multiple procedures updating
one single signal.
• The ROM could be declared as a one-dimension array of integers holding the Wtime
values. The index into this array could be constructed by concatenating Tcount and
Pcount. For example, for Pcount = 3 and Tcount = 2, the array index in binary will be
“10011”. ‘&’ is the concatenation operator in Verilog.
• ROM can be implemented using case-statement like decoder modeling.
• Adjust the Clock of the system to be 10 milliseconds.
• When testing on FPGA: Use push buttons to model the input for photocells.
• Use a Synchronizer Circuit to solve the problem of the Push-button (Bounce). The
synchronizer circuit is as follows:

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Alamein University Course Name: Computer
Faculty of Computer Science & Architecture and Organization
Engineering Course Code: CSE132

Figure.1 Synchronizer Circuit


Here are some Tips:
- In industry, typically the team is divided between designing and testing sub-teams;
they put the design document and agree on the interfaces. Then, they start to work
simultaneously to speed up the delivery. So, it is recommended to
o Create a design document before coding.
o Two team members work on the design development, while the other
member works on the testbench development.
o Once both sub-teams finish, they integrate the design and testbench and
verify the system’s functionality.

Note:
- FPGA part is bonus. The basic requirement is the simulation on ModelSim.
- Teams are 2 or 3 members Only. You can’t work alone; you can’t join team above
three members.

GOOD LUCK,
Dr. Ahmed Shalaby

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