06 Ads9817

ADS9817, ADS9815
SBASA81A – JANUARY 2023 – REVISED DECEMBER 2023
ADS981x 18-Bit, 2-MSPS/Ch, Dual, Simultaneous-Sampling ADC With Integrated

Analog Front-End
1 Features 3 Description
• 8-channel, 18-bit ADC with analog front-end: The ADS981x is an 8-channel data acquisition (DAQ)
– Dual, simultaneous sampling: 4 × 1 channels system based on a dual, simultaneous-sampling, 18-
– Constant 1-MΩ input impedance front-end bit successive approximation register (SAR) analog-
• Programmable analog input ranges: to-digital converter (ADC). The ADS981x features a
– ±12 V, ±10 V, ±7 V, ±5 V, ±3.5 V, and ±2.5 V complete analog front-end for each channel with an
– Single-ended and differential inputs input clamp protection circuit, 1-MΩ input impedance,
– ±12-V common-mode voltage range and a programmable gain amplifier (PGA) with
– Input overvoltage protection: Up to ±18 V user-selectable bandwidth options. The high input
• User-selectable analog input bandwidth: impedance allows direct connection with sensors and
– 21 kHz and 400 kHz transformers, thus eliminating the need for external
• Integrated low-drift precision references driver circuits. The ADS981x can be configured to
accept unipolar or bipolar inputs with up to a ±12-V
– ADC reference: 4.096 V
common-mode voltage.
– 2.5-V reference output for external circuits
• Excellent AC and DC performance at full- The device also features a 4.096-V reference for
throughput: the ADC and a 2.5-V reference output for use with
– DNL: ±0.3 LSB, INL: ±1.5 LSB external circuits. A digital interface supporting 1.2-V
– SNR: 92.2 dB, THD: –112 dB to 1.8-V operation enables the ADS981x to be used
• Power supply: without external voltage level translators.
– Analog and digital: 5 V and 1.8 V Package Information
– Digital interface: 1.2 V to 1.8 V PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
• Temperature range: –40°C to +125°C
ADS981x RSH (VQFN, 56) 7 mm × 7 mm
2 Applications
(1) For more information, see the Mechanical, Packaging, and
• Semiconductor tests Orderable Information.
(2) The package size (length × width) is a nominal value and
• Battery tests
includes pins, where applicable.
• Data acquisition (DAQ)
Device Information
PART NUMBER SPEED TOTAL POWER
ADS9817 2 MSPS/channel 232 mW
ADS9815 1 MSPS/channel 160 mW
Dynamic Input AVDD_5V = 4.75 V to 5.25 V VDD_1V8 = 1.75 V to 1.85 V REFIO IOVDD = 1.15 V to 1.85 V
Signal Support
AINxP and AINxM
Differential with AIN4P CHANNELS ADC Reference
Bipolar Differential Unipolar wide input AIN3P 1-4 4.096 V
common-mode AIN2P 1 M
voltage AIN1P Clamp User-
PGA selectable ADC
LPF 4:1
AIN1M Clamp A
AIN2M 1M
AIN3M
AIN4M DCLKOUT
FCLKOUT
Data D0
+12V Interface D1
Multiple analog input D2
+10V AIN5P CHANNELS
ranges D3
+7V AIN6P 5-8
+5V AIN7P 1 M
+3.5V
+2.5V AIN8P Clamp User-
Optimum PGA selectable ADC
SNR for LPF 4:1 CS
PGA AIN8M Clamp B
multiple User SCLK
ranges AIN7M 1 M Registers SDI
AIN6M
–2.5V AIN5M SDO
–3.5V 2.5 V
–5V
–7V
–10V
–12V REFOUT_2V5
Device Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS9817, ADS9815
SBASA81A – JANUARY 2023 – REVISED DECEMBER 2023 www.ti.com
Table of Contents
1 Features............................................................................1 6.5 Programming............................................................ 32
2 Applications..................................................................... 1 7 Register Map.................................................................. 36
3 Description.......................................................................1 7.1 Register Bank 0 ....................................................... 36
4 Pin Configuration and Functions...................................3 7.2 Register Bank 1 ....................................................... 39
5 Specifications.................................................................. 5 7.3 Register Bank 2 ....................................................... 53
5.1 Absolute Maximum Ratings........................................ 5 8 Application and Implementation.................................. 55
5.2 ESD Ratings............................................................... 5 8.1 Application Information............................................. 55
5.3 Recommended Operating Conditions.........................6 8.2 Typical Application.................................................... 55
5.4 Thermal Information....................................................6 8.3 Power Supply Recommendations.............................56
5.5 Electrical Characteristics.............................................7 8.4 Layout....................................................................... 57
5.6 Timing Requirements................................................ 10 9 Device and Documentation Support............................59
5.7 Switching Characteristics.......................................... 11 9.1 Receiving Notification of Documentation Updates....59
5.8 Timing Diagrams....................................................... 11 9.2 Support Resources................................................... 59
5.9 Typical Characteristics.............................................. 14 9.3 Trademarks............................................................... 59
6 Detailed Description......................................................21 9.4 Electrostatic Discharge Caution................................59
6.1 Overview................................................................... 21 9.5 Glossary....................................................................59
6.2 Functional Block Diagram......................................... 21 10 Revision History.......................................................... 59
6.3 Feature Description...................................................22 11 Mechanical, Packaging, and Orderable
6.4 Device Functional Modes..........................................30 Information.................................................................... 59
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: ADS9817 ADS9815

ADS9817, ADS9815
www.ti.com SBASA81A – JANUARY 2023 – REVISED DECEMBER 2023
4 Pin Configuration and Functions
SMPL_SYNC
SMPL_CLKM
SMPL_CLKP
AVDD_5V
VDD_1V8
VDD_1V8
VDD_1V8
AIN1M
REFIO
REFM
AIN1P
GND
NC
NC
53
56
51
50
49
48
47
46
45
44
43
55
54
52
AIN2P 1 42 IOGND
AIN2M 2 41 IOVDD
AIN3P 3 40 FCLKOUT
AIN3M 4 39 NC
AIN4P 5 38 NC
AIN4M 6 37 D3
GND 7 36 D2
Thermal
REFM 8 35 D1
Pad
AIN5P 9 34 D0
AIN5M 10 33 DCLKOUT
AIN6P 11 32 PWDN
AIN6M 12 31 RESET
AIN7P 13 30 IOVDD
AIN7M 14 29 IOGND
23
24
25
26
27
28
21
22
15
16
17
18
19
20
CS
SDI / EXTREF
VDD_1V8
VDD_1V8
GND
REFOUT_2V5
SDO
AIN8P
AIN8M
REFM
NC
SPI_EN
SCLK
AVDD_5V
Not to scale
Figure 4-1. RSH Package, 56-Pin VQFN (Top View)
Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
AIN1M 55 AI Analog input channel 1, negative input.
AIN1P 54 AI Analog input channel 1, positive input.
AVDD_5V 15, 56 P 5-V analog supply. Connect 1-µF and 0.1-µF decoupling capacitors to GND.
Chip-select input for SPI interface configuration; active low. This pin has an internal 100-kΩ
CS 25 DI
pullup resistor to IOVDD.
D0 34 DO Serial output data lane 0.
D1 35 DO Serial data output lane 1.
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

ADS9817, ADS9815
Table 4-1. Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NAME NO.
DCLKOUT 33 DO Clock output for data interface.
FCLKOUT 40 DO Frame synchronization output for data interface.
7, 23, 29, 42, Ground.
GND P
46
IOVDD 30, 41 P Digital I/O supply for data interface. Connect 1-µF and 0.1-µF decoupling capacitor to GND.
20, 38, 39, 50, Not connected. No external connection.
NC —
51
Power-down control; active low. PWDN has an internal 100-kΩ pullup resistor to the digital
PWDN 32 DI
interface supply.
REFIO acts as an internal reference output when the internal reference is enabled. REFIO
REFIO 52 AI/AO functions as an input pin for the external reference when the internal reference is disabled.
Connect a 10-µF decoupling capacitor to the REFM pins.
REFM 8, 18, 53 AI Reference ground potential. Connect to GND.
REFOUT_2V5 19 AO 2.5-V reference output. Connect a decoupling 10-µF capacitor to the REFM pins.
Reset input for the device; active low. RESET has an internal 100-kΩ pullup resistor to the
RESET 31 DI
digital interface supply.
Serial clock input for the configuration interface. SCLK has an internal 100-kΩ pulldown
SCLK 26 DI
resistor to the digital interface ground.
SDI is a multifunction logic input; pin function is determined by the SPI_EN pin. SDI has an
internal 100-kΩ pulldown resistor to GND.
SPI_EN = 0b: SDI is the logic input to select between the internal or external reference.
SDI 27 DI
Connect SDI to GND for the external reference. Connect SDI to IOVDD for the internal
reference.
SPI_EN = 1b: Serial data input for the configuration interface.
SDO 28 DO Serial data output for the configuration interface.
Single-ended ADC sampling clock input. SMPL_CLKP is the positive input for the differential
SMPL_CLKP 44 DI
sampling clock input to the ADC.
Connect SMPL_CLKM to GND for a single-ended ADC sampling clock input. SMPL_CLKM
SMPL_CLKM 43 DI
is the negative input for the differential sampling clock input to the ADC.
Synchronization input. See the Sample Synchronization section on how to use the
SMPL_SYNC 45 DI
SMPL_SYNC pin.
Logic input to enable the SPI interface configuration (CS, SCLK, SDI, and SDO). SPI_EN
SPI_EN 24 DI
has an internal 100-kΩ pullup resistor to the digital interface supply.
21, 22, 47, 48, 1.8-V power-supply. Connect 1-µF and 0.1-µF decoupling capacitors to GND.
VDD_1V8 P
49
Thermal pad — P Exposed thermal pad; connect to GND.
(1) I = input, O = output, I/O = input or output, G = ground, and P = power.

ADS9817, ADS9815
5 Specifications
5.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AVDD_5V to GND –0.3 6 V
VDD_1V8 to GND –0.3 2.1 V
IOVDD to GND –0.3 2.1 V
AINxP and AINxM to GND –18 18 V
REFIO to REFM REFM – 0.3 AVDD_5V + 0.3 V
REFM to GND GND – 0.3 GND + 0.3 V
Digital inputs to GND GND – 0.3 2.1 V
Input current to any pin except supply pins(2) –10 10 mA
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –60 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Pin current must be limited to 10 mA or less.
5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all V
±500
pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

ADS9817, ADS9815
5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
AVDD_5V Analog power supply AVDD_5V to GND, 5 V 4.75 5 5.25 V
VDD_1V8 Analog power supply VDD_1V8 to GND, 1.8 V 1.75 1.8 1.85 V
IOVDD Digital interface power supply IOVDD to GND 1.15 1.8 1.85 V
REFERENCE VOLTAGE
VREF Reference voltage to the ADC External reference 4.092 4.096 4.100 V
ANALOG INPUTS
RANGE_CHx = 0010b –2.5 2.5
RANGE_CHx = 0001b –3.5 3.5
RANGE_CHx = 0000b –5 5
VFSR Full-scale input range V
RANGE_CHx = 0011b –7 7
RANGE_CHx = 0100b –10 10
RANGE_CHx = 0101b –12 12
Operating input voltage,
AINxP –17 17 V
positive input
Operating input voltage,
AINxM –17 17 V
negative input
TEMPERATURE RANGE
TA Ambient temperature –40 25 125 °C
5.4 Thermal Information

ADS981x
THERMAL METRIC(1) RSH (VQFN) UNIT
56 PINS
RθJA Junction-to-ambient thermal resistance 23.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.5 °C/W
RθJB Junction-to-board thermal resistance 6.1 °C/W
ΨJT Junction-to-top characterization parameter 0.1 °C/W
ΨJB Junction-to-board characterization parameter 6.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

ADS9817, ADS9815
5.5 Electrical Characteristics

at AVDD_5V = 4.75 V to 5.25 V, VDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V, VREF = 4.096 V (internal or
external), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C;
typical values at TA = 25°C
ANALOG INPUTS
RIN Input impedance All input ranges 0.85 1 1.15 MΩ
Input impedance thermal drift All input ranges 10 25 ppm/°C
Input capacitance 10 pF
ANALOG INPUT FILTER
Low-bandwidth filter, all input ranges 21
Wide-bandwidth filter, input range = ±2.5 V 182
Wide-bandwidth filter, input range = ±3.5 V 240
Analog input LPF bandwidth
BW(-3 dB) Wide-bandwidth filter, input range = ±5 V 320 kHz
–3 dB
Wide-bandwidth filter, input range = ±7 V 400
DC PERFORMANCE
Resolution No missing codes 18 Bits
DNL Differential nonlinearity Wide-CM enabled and disabled, all ranges –0.99 ±0.5 0.99 LSB
Wide-CM enabled and disabled, all ranges, TA
–4 ±1.5 4 LSB
= 0℃ to 70℃
INL Integral nonlinearity
Wide-CM enabled and disabled, all ranges, TA
–4.5 ±1.5 4.5 LSB
= –40℃ to 125℃
Wide-CM disabled, RANGE = ±2.5 V –175 ±90 175
Wide-CM enabled, RANGE = ±2.5 V ±120
Wide-CM disabled, RANGE = ±3.5 V –100 ±60 100
Wide-CM enabled, RANGE = ±3.5 V ±80
Offset error Wide-CM disabled, RANGE = ±5 V –50 ±10 50 LSB
Wide-CM enabled, RANGE = ±5 V ±60
Wide-CM enabled, RANGE = ±7 V –100 ±35 100
Wide-CM disabled, RANGE = ±2.5 V 0 300 512
Wide-CM enabled, RANGE = ±2.5 V 0 450 750
Wide-CM disabled, RANGE = ±3.5 V 0 150 256
Wide-CM enabled, RANGE = ±3.5 V 0 300 512
Offset error matching Wide-CM disabled, RANGE = ±5 V 0 25 64 LSB
Wide-CM enabled, RANGE = ±5 V 0 175 296
Offset error thermal drift Wide-CM enabled and disabled, all ranges 0.5 1.5 ppm/°C
Wide-CM disabled, RANGE = ±2.5 V, ±3.5 V,
–130 ±48 130
and ±5 V
Wide-CM enabled, RANGE = ±2.5 V, ±3.5 V,
Gain error ±100 LSB
and ±5 V
Wide-CM enabled, RANGE = ±7V, ±10 V, ±12
–130 ±48 130
V

ADS9817, ADS9815
5.5 Electrical Characteristics (continued)

Wide-CM disabled, RANGE = ±2.5 V, ±3.5 V,
0 ±96 200
and ±5 V
Wide-CM enabled, RANGE = ±2.5 V, ±3.5 V,
Gain error matching 0 ±200 600 LSB
and ±5 V
Wide-CM enabled, RANGE = ±7V, ±10 V, ±12
0 ±96 200
V
Gain error thermal drift Wide-CM enabled and disabled, all ranges 0.7 3 ppm/°C
AC PERFORMANCE
Low-noise filter, fIN = 2 kHz, range = ±2.5 V 86.7 89.5
Low-noise filter, fIN = 2 kHz, range = ±5 V 88.5 91.4
Low-noise filter, fIN = 2 kHz, range = ±12 V 90 92
Wide-bandwidth filter, fIN = 2 kHz, range
79 82.5
= ±2.5 V
SNR Signal-to-noise ratio Wide-bandwidth filter, fIN = 2 kHz, range dBFS
80 83.5
= ±3.5 V
Wide-bandwidth filter, fIN = 2 kHz, range = ±5
80.5 84.5
V
81.5 83.5
V
83 85
V
83.5 85.5
V
Wide-bandwidth filter, fIN = 2 kHz, range
78.6 82.2
= ±2.5 V
SINAD Signal-to-noise + distortion ratio Wide-bandwidth filter, fIN = 2 kHz, range dB
79.5 83.2
= ±3.5 V
80.0 84.2
V
80.9 83.2
V
82.3 84.7
V
82.8 85.1
V
Low-noise filter, fIN = 2 kHz, all ranges –113
THD Total harmonic distortion dB
Wide-bandwidth filter, fIN = 2 kHz, all ranges –113
SFDR Spurious-free dynamic range fIN = 2 kHz 113 dB

ADS9817, ADS9815
5.5 Electrical Characteristics (continued)

CMRR at dc –70 dB
Isolation crosstalk at dc –100 dB
INTERNAL REFERENCE
Voltage on REFIO pin
VREF (1) 1-µF capacitor on REFIO pin, TA = 25°C 4.092 4.096 4.1 V
(configured as output)
Reference temperature drift 10 25 ppm/°C
DIGITAL INPUTS
VIL Input low logic level –0.3 0.3 IOVDD V
VIH Input high logic level 0.7 IOVDD IOVDD V
Input current –1 0.1 1 µA
Input capacitance 6 pF
LVDS SAMPLING CLOCK INPUT
VTH High-level input voltage 100 mV
VTL Low-level input voltage –100 mV
VICM Input common-mode voltage 0.3 1.2 1.4 V
DIGITAL OUTPUTS
VOL Output low logic level IOL = 500 µA sink 0 0.2 IOVDD V
VOH Output high logic level IOH = 500 µA source 0.8 IOVDD IOVDD V
POWER SUPPLY
Total power dissipation Maximum throughput 232 304 mW
Maximum throughput, internal reference 26 32
IAVDD_5V Supply current from AVDD_5V mA
Power-down 0.2 2
Maximum throughput, internal reference 50 70
IVDD_1V8 Supply current from VDD_1V8 mA
Power-down 0.2 8
Maximum throughput 7 10
IIOVDD Supply current from IOVDD mA
Power-down 0.1 2
(1) Does not include the variation in voltage resulting from solder shift effects.

ADS9817, ADS9815
5.6 Timing Requirements

at AVDD_5V = 4.75 V to 5.25 V, VDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V, and maximum throughput (unless
otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C
MIN MAX UNIT
CONVERSION CYCLE
fSMPL_CLK Sampling frequency 3.6 8 MHz
tSMPL_CLK Sampling time interval 1 / fSMPL_CLK ns
tPL_SMPL_CLK SMPL_CLK low time 0.45 tSMPL_CLK 0.55 tSMPL_CLK ns
tPH_SMPL_CLK SMPL_CLK high time 0.45 tSMPL_CLK 0.55 tSMPL_CLK ns
SPI INTERFACE TIMINGS (CONFIGURATION INTERFACE)
fSCLK Maximum SCLK frequency 20 MHz
tPH_CK SCLK high time 0.48 0.52 tCLK
tPL_CK SCLK low time 0.48 0.52 tCLK
thi_CS Pulse duration: CS high 220 ns
td_CSCK Delay time: CS falling to the first SCLK capture edge 20 ns
tsu_CKDI Setup time: SDI data valid to the SCLK rising edge 10 ns
tht_CKDI Hold time: SCLK rising edge to data valid on SDI 5 ns
tD_CKCS Delay time: last SCLK falling to CS rising 5 ns
CMOS DATA INTERFACE
tsu_SS Setup time: SMPL_SYNC rising edge to SMPL_CLK falling edge 10 ns
tht_SS Hold time: SMPL_CLK falling edge to SMPL_SYNC high 10 ns

ADS9817, ADS9815
5.7 Switching Characteristics

at AVDD_5V = 4.75 V to 5.25 V, VDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V, and maximum throughput (unless
otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
RESET
tPU Power-up time for device 25 ms
SPI INTERFACE TIMINGS (CONFIGURATION INTERFACE)
Delay time: 8th SCLK rising edge to data
tden_CKDO 22 ns
enable
Delay time: 24th SCLK rising edge to SDO
tdz_CKDO 50 ns
going Hi-Z
Delay time: SCLK falling edge to
td_CKDO 16 ns
corresponding data valid on SDO
Delay time: SCLK falling edge to previous
tht_CKDO 2 ns
data valid on SDO
CMOS DATA INTERFACE
DDR mode 10
tDCLK Data clock output ns
SDR mode 20
Clock duty cycle 45 55 %
Time offset: DCLK rising to corresponding
toff_DCLKDO_r DDR mode tDCLK / 4 – 1.5 tDCLK / 4 + 1.5 ns
data valid
Time offset: DCLK falling to corresponding
toff_DCLKDO_f DDR mode tDCLK / 4 – 1.5 tDCLK / 4 + 1.5 ns
data valid
Time delay: DCLK rising to corresponding
td_DCLKDO SDR mode –1 1 ns
data valid
Time delay: SMPL_CLK falling edge with
td_SYNC_FCLK SYNC signal to corresponding FCLKOUT 3 4 tSMPL_CLK
rising edge
5.8 Timing Diagrams

thi_CS
CS
td_CSCK td_CKCS
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tsu_CKDI tht_CKDI
A A A A A A A A D D D D D D D D D D D D D D D D
SDI 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tden_CKDO td_CKDO tht_SDO tdz_CKDO
Hi-Z DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO
SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDO is active only when reading registers; Hi-Z otherwise
Figure 5-1. SPI Configuration Interface

ADS9817, ADS9815
SMPL_SYNC
tht_SS
tsu_SS
SMPL_CLK
td_SYNC_FCLK 24 DCLKs
DCLKOUT
tFCLK
D[23:6] = 18-bit conversion result
FCLKOUT D[5:0] = 0
toff_DCLKDO_f 6 DCLK toff_DCLKDO_r
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
D3 23 21 19 13 11 9 1 23 21 19 13 11 9 1 23 21 19 13 11 9 1 23 21 19 13 11 9 1 23 21 19 13 11 9
Channel 1 Channel 2 Channel 3 Channel 4 Channel 1
D2 22 20 18 12 10 8 0 22 20 18 12 10 8 0 22 20 18 12 10 8 0 22 20 18 12 10 8 0 22 20 18 12 10 8
D1 23 21 19 13 11 9 1 23 21 19 13 11 9 1 23 21 19 13 11 9 1 23 21 19 13 11 9 1 23 21 19 13 11 9
D0 22 20 18 12 10 8 0 22 20 18 12 10 8 0 22 20 18 12 10 8 0 22 20 18 12 10 8 0 22 20 18 12 10 8
Figure 5-2. 4-SDO DDR CMOS Data Interface
SMPL_SYNC
tht_SS
tsu_SS
SMPL_CLK
td_SYNC_FCLK 48 DCLKs
DCLKOUT
tFCLK
FCLKOUT D[5:0] = 0
toff_DCLKDO_r 12 DCLK toff_DCLKDO_f
D3 23 22 21 12 11 10 0 23 22 21 12 11 10 0 23 22 21 12 11 10 0 23 22 21 12 11 10 0 23 22 21 12 11 10
D1 23 22 21 12 11 10 0 23 22 21 12 11 10 0 23 22 21 12 11 10 0 23 22 21 12 11 10 0 23 22 21 12 11 10
Figure 5-3. 2-SDO DDR CMOS Data Interface

ADS9817, ADS9815
SMPL_SYNC
tht_SS
tsu_SS
SMPL_CLK
td_SYNC_FCLK
48 DCLKs
DCLKOUT
tFCLK
D[5:0] = 0
FCLKOUT
td_DCLKDO
D3 D D D D D D D D D D D D D D D D
23 21 11 1 23 21 11 1 23 21 11 1 23 21 11 1
Channel 1 Channel 2 Channel 3 Channel 4
D D D D D D D D D D D D D D D D
D2 22 20 10 0 22 20 10 0 22 20 10 0 22 20 10 0
D1 D D D D D D D D D D D D D D D D
23 21 11 1 23 21 11 1 23 21 11 1 23 21 11 1
D D D D D D D D D D D D D D D D
D0 22 20 10 0 22 20 10 0 22 20 10 0 22 20 10 0
Figure 5-4. 4-SDO SDR CMOS Data Interface
SMPL_SYNC
tht_SS
tsu_SS
SMPL_CLK
td_SYNC_FCLK
96 DCLKs
DCLKOUT
tFCLK
D[5:0] = 0
FCLKOUT
td_DCLKDO
D3 D D D D
23 22 11 0
D1 D D D D
23 22 11 0
Figure 5-5. 2-SDO SDR CMOS Data Interface

ADS9817, ADS9815
5.9 Typical Characteristics

at TA = 25°C, AVDD_5V = 5 V, VDD_1V8 = 1.8 V, internal VREF = 4.096 V, ±5-V analog input range, and maximum
throughput (unless otherwise noted)
0.75 0.75
0.45 0.45
Integral Nonlinearity (LSB)

0.15 0.15
-0.15 -0.15
-0.45 -0.45
-0.75 -0.75
0 65536 131072 196608 262144 0 65536 131072 196608 262144
Output Code Output Code
Typical INL = ±0.75 LSB Typical INL = ±0.75 LSB

Figure 5-6. Typical INL With Low-Bandwidth LPF Figure 5-7. Typical INL With Wide-Bandwidth LPF
0.3 0.3
Differential Nonlinearity (LSB)
0.15 0.15
0 0
-0.15 -0.15
-0.3 -0.3
0 65536 131072 196608 262144 0 65536 131072 196608 262144
Output Code Output Code
Typical DNL = ±0.2 LSB Typical DNL = ±0.25 LSB

Figure 5-8. Typical DNL With Low-Noise LPF Figure 5-9. Typical DNL With Wide-Bandwidth LPF
0 0
-50 -50
Amplitude (dBFS)
Amplitude (dBFS)
-100 -100
-150 -150
-200 -200
0.1 1 10 100 1000 0.1 0.2 0.5 1 2 3 4 5 7 10 2030 50 100 200 500 1000
Frequency (kHz) Frequency (kHz)
SNR = 91.5 dBFS, THD = –113 dB at fIN = 2 kHz SNR = 83.7 dBFS, THD = –113 dB at fIN = 2 kHz
Figure 5-10. Typical FFT With Low-Bandwidth LPF, Figure 5-11. Typical FFT With Wide-Bandwidth LPF,
RANGE = ±5 V RANGE = ±5 V

ADS9817, ADS9815
5.9 Typical Characteristics (continued)

0 0
-50 -50
Amplitude (dBFS)
Amplitude (dBFS)
-100 -100
-150 -150
-200 -200
0.1 0.2 0.5 1 2 3 4 5 7 10 2030 50 100 200 500 1000 0.1 0.2 0.5 1 2 3 4 5 7 10 2030 50 100 200 500 1000
SNR = 92.1 dBFS, THD = –113 dB at fIN = 2 kHz SNR = 85.5 dBFS, THD = –113 dB at fIN = 2 kHz
Figure 5-12. Typical FFT With Low-Bandwidth LPF, Figure 5-13. Typical FFT With Wide-Bandwidth LPF,
RANGE = ±10 V RANGE = ±10 V
0 0
All input ranges
-6 -6
-12 -12
Amplitude (dB)
Amplitude (dB)
-18 -18
-24 -24
-30 -30 2.5 V range

3.5 V range
-36 -36 5 V range
7 V range
-42 -42 10 V range
12 V range
-48 -48
1 2 3 4 5 67 10 20 30 50 70100 200 500 1000 10 20 30 4050 70 100 200 300 500 1000 2000
Typical bandwidth (–3 dB) = 21.2 kHz

Figure 5-14. Low-Bandwidth LPF Frequency Response Across Figure 5-15. Wide-Bandwidth LPF Frequency Response Across
Input Ranges Input Ranges
94 88
±2.5 V ±5 V ±10 V
±3.5 V ±7 V ±12 V
92.5 86
SNR (dBFS)
SNR (dBFS)
91 84
89.5 82
±2.5 V ±5 V ±10 V
±3.5 V ±7 V ±12 V
88 80
0 6000 12000 18000 24000 30000 36000 42000 48000 0 6000 12000 18000 24000 30000 36000 42000 48000
Frequency (Hz) Frequency (Hz)
Figure 5-16. SNR vs Input Signal Frequency Across Input Figure 5-17. SNR vs Input Signal Frequency Across Input
Ranges With Low-Bandwidth LPF Ranges With Wide-Bandwidth LPF

ADS9817, ADS9815

-85 -85
-92 -92
-99 -99
THD (dB)
THD (dB)
-106 -106
±2.5 V ±2.5 V
±3.5 V ±3.5 V
±5 V ±5 V
-113 ±7 V -113 ±7 V
±10 V ±10 V
±12 V ±12 V
-120 -120
0 6000 12000 18000 24000 30000 36000 42000 48000 0 6000 12000 18000 24000 30000 36000 42000 48000
Figure 5-18. THD vs Input Signal Frequency Across Input Figure 5-19. THD vs Input Signal Frequency Across Input
94 88
±2.5 V ±5 V ±10 V
±3.5 V ±7 V ±12 V
86
92.5
SINAD (dB)
SINAD (dB)
84
91
82
89.5
80
±2.5 V ±5 V ±10 V
±3.5 V ±7 V ±12 V
88 78
0 6000 12000 18000 24000 30000 36000 42000 48000 0 6000 12000 18000 24000 30000 36000 42000 48000
Figure 5-20. SINAD vs Input Signal Frequency Across Input Figure 5-21. SINAD vs Input Signal Frequency Across Input
-96 -90
0 0
-99 50  50 
1 k -95 1 k
10 k 10 k
-102 50 k 50 k
-100
THD (dB)
THD (dB)
-105
-105
-108
-110
-111
-114 -115
-117 -120
0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50 0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50
Input Frequency (kHz) Input Frequency (kHz)
Figure 5-22. THD vs Input Frequency, Low-BW Mode, Figure 5-23. THD vs Input Frequency, High-BW Mode,
RANGE = ±5 V, ADS9817 RANGE = ±5 V, ADS9817

ADS9817, ADS9815

-90 -80
0 0
50  -85 50 
-95 1 k 1 k
10 k -90 10 k
50 k 50 k
-100
-95
THD (dB)
THD (dB)
-105 -100
-105
-110
-110
-115
-115
-120 -120
0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50 0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50
-100 -90
0 0
50  -95 50 
-105 1 k 1 k
10 k 10 k
50 k -100 50 k
-110
THD (dB)
THD (dB)
-105
-110
-115
-115
-120
-120
-125 -125
0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50 0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50
-90 -80
0 0
50  -85 50 
-95
1 k 1 k
10 k -90 10 k
-100 50 k 50 k
-95
THD (dB)
THD (dB)
-105 -100
-110 -105
-110
-115
-115
-120
-120
-125 -125
0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50 0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 30 50

ADS9817, ADS9815

-75
2 kHz Input Frequency, Wide-BW Mode
10 kHz Input Frequency, Wide-BW Mode
-85 2 kHz Input Frequency, Low-BW Mode
10 kHz Input Frequency, Low-BW Mode
-95
THD (dB)
-105
-115
-125
-135
-25 -20 -15 -10 -5 0
Input Amplitude (dB)
Input level = 0 dB; RIN = 0 Ω, 50 Ω, 1 kΩ, 10 kΩ, 50 kΩ, fIN =

40 Hz, 110 Hz, 1 kHz, 2 kHz, 10 kHz, 15 kHz, 24 kHz
Figure 5-30. THD vs Input Amplitude, RANGE = ±5 V Figure 5-31. THD vs Input Amplitude, RANGE = ±10 V
1.5 0.4
1
0.2
0.5
Maximum, Low-BW mode Maximum, Low-BW mode
0 Minimum, Low-BW mode Minimum, Low-BW mode
Maximum, High-BW mode Maximum, High-BW mode
0
Minimum, High-BW mode Minimum, High-BW mode
-0.5
-1
-0.2
-1.5
-2 -0.4
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)
Figure 5-32. INL vs Temperature Figure 5-33. DNL vs Temperature

64 40
56 Channel 2 Channel 6 Channel 2 Channel 6
Channel 3 Channel 7 32 Channel 3 Channel 7
48 Channel 4 Channel 8 Channel 4 Channel 8
Offset Error (LSB)
Offset Error (LSB)
40 24
32
24 16
16
8
8
0 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 5-34. Offset Error vs Temperature, RANGE = ±5 V Figure 5-35. Offset Error vs Temperature, RANGE = ±10 V

ADS9817, ADS9815

1750 96
Channel 1 Channel 5
Channel 2 Channel 6
1500 64 Channel 3 Channel 7
Channel 4 Channel 8
1250
32
Gain Error (LSB)

Number of Hits
1000
0
750
-32
500
250 -64
0 -96
0 0.3 0.6 0.9 1.2 1.5 -40 -20 0 20 40 60 80 100 120
Offset Error Drift (ppm/°C) Temperature (°C)
Figure 5-36. Offset Error Drift Histogram Figure 5-37. Gain Error vs Temperature, RANGE = ±5 V
64 1000
Channel 1 Channel 5
48 Channel 2 Channel 6
Channel 3 Channel 7 800
32 Channel 4 Channel 8
Gain Error (LSB)
Number of Hits
16 600
0
400
-16
-32
200
-48
-64 0
-40 -20 0 20 40 60 80 100 120 0 0.4 0.8 1.2 1.6 2 2.4
Temperature (°C) Gain Error Drift (ppm/°C)
Figure 5-38. Gain Error vs Temperature, RANGE = ±10 V Figure 5-39. Gain Error Drift Histogram
3000 3000
CH1 CH1
2700 CH2 2700 CH2
CH3 CH3
2400 2400
CH4 CH4
2100 CH5 2100 CH5
Number of Hits
Number of Hits
CH6 CH6
1800 CH7 1800 CH7
CH8 CH8
1500 1500
1200 1200
900 900
600 600
300 300
0 0
131055
131060
131065
131070
131075
131080
131085
131090
131095
131080
131085
131090
131095
131100
131100
131105
131120
131125
131110
131115
ADC Code ADC Code
Mean = 131073.8 LSB, standard deviation = 2.45 LSB, Mean = 131103.5 LSB, standard deviation = 2.49 LSB,
number of hits = 4096 number of hits = 4096
Figure 5-40. DC Histogram of Codes for AINxP = AINxM = GND, Figure 5-41. DC Histogram of Codes for VIN = 1 mV, Low-BW
Low-BW Mode, RANGE = ±5 V Mode, RANGE = ±5 V

ADS9817, ADS9815

1600 1600
CH1 CH1
1400 CH2 1400 CH2
CH3 CH3
1200 CH4 1200 CH4
CH5 CH5
Number of Hits
Number of Hits
1000 CH6 1000 CH6
CH7 CH7
CH8 CH8
800 800
600 600
400 400
200 200
0 0
131055
131060
131065
131070
131075
131080
131085
131090
131095
131080
131085
131090
131095
131100
131100
131105
131120
131125
131110
131115
ADC Code ADC Code
Mean = 131074.4 LSB, standard deviation = 5.47 LSB, Mean = 131102.3 LSB, standard deviation = 5.68 LSB,
number of hits = 4096 number of hits = 4096
Figure 5-42. DC Histogram of Codes for AINxP = AINxM = GND, Figure 5-43. DC Histogram of Codes for VIN = 1 mV, Wide-BW
Wide-BW Mode, RANGE = ±5 V Mode, RANGE = ±5 V
4.101 Reference Voltage on REFOUT_2V5 (V) 2.504
Reference Voltage on REFIO (V)
4.098 2.502
4.095 2.5
4.092 2.498
4.089 2.496
4.086 2.494
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 5-44. REFIO vs Temperature Figure 5-45. REFOUT_2V5 vs Temperature

60 280
Total Power Dissipation (mW)
45 IAVDD_5V (mA) 260

Supply Currents (mA)
IVDD_1V8 (mA)
IIOVDD (mA)
Total Power Dissipation (mW)
30 240
15 220
0 200
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
Figure 5-46. Supply Currents and Total Power Dissipation vs Temperature

ADS9817, ADS9815
6 Detailed Description
6.1 Overview
The ADS981x is an 18-bit data acquisition (DAQ) system with eight-channel analog inputs that can be
configured as either single-ended or differential. Each analog input channel consists of an input clamp protection
circuit, and a programmable gain amplifier (PGA) with user-selectable bandwidth options. The input signals
are digitized using an 18-bit analog-to-digital converter (ADC), based on the successive approximation register
(SAR) architecture. This overall system can achieve a maximum throughput of 2 MSPS/channel for all channels.
The device features a 4.096-V internal reference with a fast-settling buffer.
The device operates from 5-V and 1.8-V analog supplies and can accommodate true bipolar input signals. The
input clamp protection circuitry can tolerate voltages up to ±18 V. The device offers a constant 1-MΩ resistive
input impedance irrespective of the sampling frequency or the selected input range. The ADS981x offers a
simplified end solution without requiring external high-voltage bipolar supplies and complicated driver circuits.
6.2 Functional Block Diagram
AVDD_5V = 4.75 V to 5.25 V VDD_1V8 = 1.75 V to 1.85 V REFIO IOVDD = 1.15 V to 1.85 V
AIN4P CHANNELS ADC Reference

AIN3P 1-4 4.096 V
AIN2P 1 M
AIN1P Clamp User-
PGA selectable ADC
LPF 4:1
AIN1M Clamp A
AIN2M 1M
AIN3M
AIN4M DCLKOUT
FCLKOUT
Data D0
Interface D1
D2
AIN5P CHANNELS
5-8 D3
AIN6P
AIN7P 1 M
AIN8P Clamp User-
PGA selectable ADC
LPF 4:1 CS
AIN8M Clamp B
User SCLK
AIN7M 1 M Registers SDI
AIN6M
AIN5M SDO
2.5 V
REFOUT_2V5

ADS9817, ADS9815
6.3 Feature Description

6.3.1 Analog Inputs
The ADS981x incorporates dual, simultaneous-sampling, 18-bit successive approximation register (SAR)
analog-to-digital converters (ADCs). Each ADC is connected to four analog input channels through a multiplexer.
The device has a total of eight analog input pairs. The ADC digitizes the voltage difference between the analog
input pairs AINxP – AINxM. Figure 6-1 shows the simplified circuit schematic for each analog input channel,
including the input clamp protection circuit, PGA, low-pass filter, multiplexer, high-speed ADC driver, and a
precision 18-bit SAR ADC.
1M
AINxP Clamp
18 bit
PGA Prog. LPF MUX SAR
1M
ADC
AINxM Clamp
Figure 6-1. Front-End Circuit Schematic for the Selected Analog Input Channel
6.3.1.1 Input Clamp Protection Circuit

The ADS981x features an internal clamp protection circuit on each of the eight analog input channels, see
Figure 6-1. The input clamp protection circuit allows each analog input to swing up to a maximum voltage of
±18 V. Beyond an input voltage of ±18 V, the input clamp circuit turns on and still operates from the single 5-V
supply. Figure 6-2 shows a typical current versus voltage characteristic curve for the input clamp.
For input voltages above the clamp threshold, make sure that the input current never exceeds ±10 mA. A
resistor placed in series with the analog inputs is an effective way to limit the input current. In addition to limiting
the input current, the series resistor can also provide an antialiasing, low-pass filter (LPF) when coupled with a
capacitor. Matching the external source impedance on the AINxP and AINxM pins cancels any additional offset
error.
50
40
30
Input Clamp Current (mA)
20
10
0
-10
-20
-30
-40
-50
-20 -15 -10 -5 0 5 10 15 20
Input Voltage (V) D007
Figure 6-2. Input Protection Clamp Profile, Input Clamp Current vs Source Voltage
6.3.1.2 Programmable Gain Amplifier (PGA)

The ADS981x features a PGA at every analog input channel. The PGA supports single-ended and differential
inputs with a bipolar signal swing. Table 6-1 lists the supported analog input ranges. The analog input range can
be configured independently for each channel by using the RANGE_CHx register fields in address 0xC2 and
address 0xC3.

ADS9817, ADS9815
Table 6-1. Analog Input Ranges

DIFFERENTIAL INPUTS SINGLE-ENDED INPUTS RANGE_CHx CONFIGURATION
±12 V ±12 V 5
±10 V ±10 V 4
±7 V ±7 V 3
±5 V ±5 V 0
±3.5 V ±3.5 V 1
±2.5 V ±2.5 V 2
Each analog input channel features an antialiasing, low-pass filter (LPF) at the output of the PGA. Table 6-2
lists the various programmable LPF options available in the ADS981x corresponding to the analog input range.
Figure 5-14 and Figure 5-15 illustrate the frequency responses for low-bandwidth and wide-bandwidth LPF
configurations. The analog input bandwidth for the eight analog input channels can be can be selected using the
ANA_BW[7:0] bits in address 0xC0 of register bank 1.
Table 6-2. Low-Pass Filter Corner Frequency
LPF ANALOG INPUT RANGE CORNER FREQUENCY (–3 dB)
Low-bandwidth All input ranges 21.2 kHz
±12 V 375 kHz
±10 V 385 kHz
±7 V 400 kHz
Wide-bandwidth
±5 V 320 kHz
±3.5 V 240 kHz
±2.5 V 185 kHz
6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit

The ADS981x features a common-mode (CM) rejection circuit at the analog inputs that supports CM voltages
up to ±12 V. The CM voltage for differential inputs is given by Equation 1. On power-up or after reset, the
common-mode voltage range for the analog input channels is ±12 V (WIDE_CM_EN1 = 0b). Voltage at the
analog inputs, in all cases, must be within the Absolute Maximum Ratings.
Voltage on AINP + Voltage on AINM

Common mode voltage = 2 (1)
As described in Table 6-3, the CM voltage rejection circuit can be optimized for various CM voltages for
differential inputs.
Table 6-3. Wide Common-Mode Configuration for Differential Inputs
ADC A ADC B
COMMON-MODE (ANALOG INPUT CHANNELS 1–4) (ANALOG INPUT CHANNELS 5–8)
CM_CTRL_EN
(CM) RANGE CM_RNG_ADC_A CM_RNG_ADC_B
CM_EN_ADC_A CM_EN_ADC_B
[1:0] [1:0]
CM ≤ ±1 V 0 Don't care 0 Don't care
CM ≤ ±RANGE / 2 0 1 0
1
CM ≤ ±6 V 1 2 2
CM ≤ ±12 V 1 1
The CM voltage rejection circuit must be configured depending on the analog input range of the PGA when using
single-ended inputs as well. Table 6-4 lists the recommended configuration for single-ended inputs for various
analog input voltage ranges.

ADS9817, ADS9815
Table 6-4. Wide Common-Mode Configuration for Single-Ended Inputs

ADC A ADC B
PGA ANALOG (ANALOG INPUT CHANNELS 1–4) (ANALOG INPUT CHANNELS 5–8)
CM_CTRL_EN
INPUT RANGE CM_RNG_ADC_A CM_RNG_ADC_B
CM_EN_ADC_A CM_EN_ADC_B
[1:0] [1:0]
±2.5 V, ±3.5 V, and 0 Don't care 0 Don't care
±5 V
1
±7 V, ±10 V, and 1 0 1 0
±12 V
6.3.1.4 Gain Error Calibration

The ADS981x features calibration logic to minimize gain error from the analog inputs. Enable gain error
calibration for minimum gain error. Gain error calibration can be enabled by configuring the GE_CAL_EN1
(address = 0xD), GE_CAL_EN2, GE_CAL_EN3 (address = 0x33), and GE_CAL_EN4 (address = 0x34).
If gain error calibration is not enabled as shown in Table 6-5, the full-scale analog input ranges are increased by
a factor of 1.024.
Table 6-5. Analog Input Ranges vs Gain-Error Calibration
ANALOG INPUT RANGE WITH ANALOG INPUT RANGE WITHOUT
RANGE_CHx CONFIGURATION
CALIBRATION CALIBRATION
5 ±12 V ±12.288 V
4 ±10 V ±10.24 V
3 ±7 V ±7.168 V
0 ±5 V ±5.12 V
1 ±3.5 V ±3.584 V
2 ±2.5 V ±2.56 V

ADS9817, ADS9815
6.3.2 ADC Transfer Function

The ADS981x outputs 18 bits of conversion data in either straight-binary or binary two's-complement formats.
The format for the output codes is the same across all analog channels. The format for the output codes can be
selected using the DATA_FORMAT field in address 0xD in register bank 1. Figure 6-3 and Table 6-6 show the
transfer characteristics for the ADS981x. The LSB size depends on the analog input range selected, gain-error
calibration, and system gain error calibration as shown in Equation 2.
Analog input range

LSB = × 1 + G × 0.024 (2)
218
where:
• G is 0 when gain-error calibration is enabled, otherwise G is1; see the Gain Error Calibration section
Straight Twos
Binary Complement
0x3FFFF 0x1FFFF
0x3FFFE 0x1FFFE
ADC OUTPUT CODE
0x20001 0x00001
0x20000 0x00000
0x1FFFF 0x3FFFF
0x00002 0x20002
0x00001 0x20001
0x00000 0x20000
–FS+(0.5)LSB 0V–(0.5)LSB +FS–(1.5)LSB

ANALOG INPUT
Figure 6-3. Transfer Characteristics
Table 6-6. ADC Full-Scale Range and LSB Size

RANGE +FS MIDSCALE –FS LSB
±2.5 V 2.5 V 0V –2.5 V 19.07 µV
±3.5 V 3.5 V 0V –3.5 V 26.70 µV
±5 V 5V 0V –5 V 38.15 µV
±7 V 7V 0V –7 V 53.41 µV
±10 V 10 V 0V –10 V 76.29 µV
±12 V 12 V 0V –12 V 91.55 µV

ADS9817, ADS9815
6.3.3 ADC Sampling Clock Input

Use a low-jitter external clock with a high slew rate to maximize SNR performance. The ADS981x can be
operated with a differential or a single-ended clock input. Clock amplitude impacts the ADC aperture jitter
and consequently the SNR. For maximum SNR performance, provide a clock signal with fast slew rates that
maximizes swing between IOVDD and GND levels.
The sampling clock must be a free-running continuous clock. The ADC generates a valid output data, data clock,
and frame clock tPU_SMPL_CLK, as specified in the Switching Characteristics after a free-running sampling clock is
applied. The ADC output data, data clock, and frame clock are invalid when the sampling clock is stopped.
Figure 6-4 shows a diagram of the differential sampling clock input. For this configuration, connect the differential
sampling clock input to the SMPL_CLKP and SMPL_CLKM pins. Figure 6-5 shows a diagram of the single-
ended sampling clock input. In this configuration, connect the single-ended sampling clock to SMPL_CLKP and
connect SMPL_CLKM to ground.
IOVDD
SMPL_CLKP
SMPL_CLKP
5.4 k
0V
Differential +
100
sampling clock Bias

– ADS98XX
5.4 k
SMPL_CLKM
SMPL_CLKM
GND
Figure 6-4. AC-Coupled Differential Sampling
Clock Figure 6-5. Single-Ended Sampling Clock
6.3.4 Reference
The ADS981x has a precision, low-drift voltage reference internal to the device. For best performance, filter
the internal reference noise by connecting a 10-µF ceramic bypass capacitor to the REFIO pin. An external
reference can also be connected at the REFIO pin and the internal reference voltage can be disabled by writing
to PD_REF = 1b in address 0xC1 of register bank 1.
6.3.4.1 Internal Reference Voltage
The ADS981x features an internal reference voltage with a nominal output voltage of 4.096 V. On power-up, the
internal reference is enabled by default. As shown in Figure 6-6, place a minimum 10-µF decoupling capacitor
between the REFIO and REFM pins.
AVDD_5V
REFIO
ADC REF
External capacitor
10 μF for reference
1 k REFM noise reduction
PD_REF = 0
GND
User register bit
4.096 V GND
Figure 6-6. Internal Reference Voltage

ADS9817, ADS9815
6.3.4.2 External Reference Voltage

An external 4.096-V reference voltage, as shown in Figure 6-7, can be connected at the REFIO pin with
an appropriate decoupling capacitor placed between the REFIO and REFM pins. For improved thermal drift
performance, the REF7040 is recommended. To disable the internal reference, set PD_REF = 1b in address
0xC1 in register bank 1. The REFIO pin has ESD protection diodes connected to the AVDD_5V and REFM pins.
5V
VIN EN
OUTF
AVDD_5V
REF7040
OUTS
GND
REFIO
ADC REF
10 μF
1 k
REFM
PD_REF = 1
GND
User register bit
4.096 V GND
Figure 6-7. External Reference Voltage
6.3.5 Sample Synchronization

As illustrated in Figure 5-2, Figure 5-3, Figure 5-4, and Figure 5-5, the SMPL_SYNC pin can synchronize
multiple ADCs using an external SYNC signal. The SMPL_SYNC pin is latched in by the falling edge of the
sampling clock.
The synchronization signal is only required one time during power-up. As illustrated in Figure 5-2, Figure 5-3,
Figure 5-4, and Figure 5-5, the SYNC signal resets the internal analog channel selection logic and aligns the
FCLKOUT signal to the data frame. If no SYNC signal is given, the internal analog channel selection logic and
FCLKOUT are not synchronized, which can lead to a different alignment between the sequence of channel
output data and FCLKOUT. When using multiple ADCs with the same sampling clock, the SYNC signal makes
sure all ADCs sample the same respective analog input channel at the same time.
6.3.6 Data Interface
The ADS981x supports 2-lane and 4-lane mode with single-data-rate (SDR) and double-data-rate (DDR)
interface modes. The data interface can be selected using the configuration SPI as described in Table 6-7.
The ADC generates the data (D[3:0]), data clock (DCLKOUT), and frame clock (FCLKOUT) in response to the
sampling clock signal on the SMPL_CLK input pin. The 18-bit ADC conversion result is output MSB first in a
24-bit data packet and the last six bits are zeroes.
The data interface signals can be described as:
• D[3:0]: Data output from the ADC. In 4-lane mode all four lanes are used, whereas in 2-lane mode D3 and D1
are used to output ADC data.
• DCLKOUT: Data clock output from the ADC.
• FCLKOUT: Frame clock output from the ADC delimiting each set of 8-channel data. A SYNC pulse is required
on power-up or after device reset to align the rising edge of FCLKOUT with channel 0 data output, as
described in the Sample Synchronization section.
Use the registers in Table 6-7 to configure the data interface.

ADS9817, ADS9815
Table 6-7. Register Configurations For Interface Modes

DATA_RATE DATA_LANES
INTERFACE MODE FIGURE
(Address = 0xC1) (Address = 0xC1)
4-lane, DDR Figure 5-2 0 0
2-lane, DDR Figure 5-3 0 1
4-lane, SDR Figure 5-4 1 0
2-lane, SDR Figure 5-5 1 1
6.3.6.1 Data Clock Output

The ADS981x features a source-synchronous data interface where the ADC provides the output data and the
clock to capture the data. The clock to capture the data is output on the DCLKOUT pin. The clock frequency
depends on the sampling clock speed, data rate (SDR or DDR), and number of output lanes (4-lanes or 2-lanes)
and is given by Equation 3. The frame clock frequency is given by Equation 4.
24 bits/channel × 8 channels
Data clock frequency = × Sampling clock frequency (3)
Number of data lanes × Data rate SDR = 1, DDR = 2
Sampling clock frequency

Frame clock frequency = 4 (4)
Table 6-8 shows the data clock frequency for the maximum sampling rates for the ADS9817 and ADS9815 for
various interface modes.
Table 6-8. Data Clock Frequency for Interface Modes
ADS9815 ADS9817
INTERFACE MODE
(fSMPL_CLK = 4 MHz) (fSMPL_CLK = 8 MHz)
4-lane, DDR 24 MHz 48 MHz
2-lane, DDR 48 MHz 96 MHz
4-lane, SDR 48 MHz 96 MHz
2-lane, SDR 96 MHz Not supported
6.3.6.2 ADC Output Data Randomizer

As shown in Figure 6-8, the ADS981x features a data output randomizer. When enabled, the ADC conversion
result is bit-wise exclusive-ORed (XOR) with the LSB of the conversion result. The LSB of the ADC conversion
result has equal probability of being either 1 or 0. As a result of the XOR operation, the data output from
the ADS981x is randomized. The ground bounce created by the transmission of this randomized result over
the data interface is uncorrelated with the analog input voltage. This uncorrelated transmission helps minimize
interference between data transmission and analog performance of the ADC when the PCB layout does not
minimize ground bounce.
ADC Conversion Bit-wise Randomized
Result XOR Result
MSB MSB
MSB - 1 MSB - 1
MSB - 2 MSB - 2
LSB + 1 LSB + 1
LSB LSB
Figure 6-8. Bit-Wise XOR Operation

ADS9817, ADS9815
6.3.6.3 Test Patterns for Data Interface

The ADS981x features test patterns that can be used by the host for debugging and verifying the data interface.
The test patterns replace the ADC output data with predefined digital data. The test patterns can be enabled by
configuring the corresponding register addresses 0x13 through 0x1B in bank 1.
The ADS981x supports the following test patterns:
• User-defined output: User-defined, 24-bit pattern. Separate patterns for ADC A and ADC B; see the User-
Defined Test Pattern section.
• Ramp output: Digital ramp output with a user-defined increment between two steps. There are separate ramp
outputs for ADC A and ADC B; see the Ramp Test Pattern section.
• Alternate output: User-defined, 24-bit outputs that alternate between two user-defined patterns; see the
User-Defined Alternating Test Pattern section.
To disable the test patterns, set TEST_PAT_EN_CHA and TEST_PAT_EN_CHB to 0b.
6.3.6.3.1 User-Defined Test Pattern
The user-defined test pattern allows the host to specify a fixed 24-bit value that is output by the ADS981x.
Configure the registers in bank 1 to enable the user-defined test pattern:
• Configure the test patterns in TEST_PAT0_ADC_A (address = 0x15 MSB, 0x14 LSB) and
TEST_PAT0_ADC_B (address = 0x1A MSB, 0x19 LSB)
• Set TEST_PAT_EN_ADC_A = 1, TEST_PAT_MODE_ADC_A = 0 (address = 0x13) and TEST
PAT_EN_ADC_B = 1, TEST_PAT_MODE_ADC_B = 0 (address = 0x18)
The ADS981x outputs the TEST_PAT0_ADC_A (address 0x15 [7:0], address 0x14 [15:0]) and
TEST_PAT0_ADC_B (address 0x1A [7:0], address 0x19 [15:0]) register values in place of ADC A and ADC
B data, respectively.
6.3.6.3.2 User-Defined Alternating Test Pattern
The user-defined alternating test pattern allows the host to specify two fixed 24-bit values that are output by the
ADS981x alternately. Configure the registers in bank 1 to enable the user-defined alternating test pattern:
• Configure the test patterns in TEST_PAT0_CHA (address = 0x14, 0x15), TEST_PAT1_CHA (address = 0x15,
0x16) and TEST_PAT0_CHB (address = 0x19, 0x1A), TEST_PAT1_CHB (address = 0x1A, 0x1B)
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 3 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 3 (address = 0x18)
The ADS981x outputs the TEST_PAT0_CHA and TEST_PAT0_CHB register values in place of the ADC A and
ADC B data, respectively, in one output frame and the TEST_PAT1_CHA and TEST_PAT1_CHB register values
in the next frame.
6.3.6.3.3 Ramp Test Pattern
The ramp test pattern allows the host to specify a digital ramp that is output by the ADS981x. Configure the
registers in bank 1 to enable the ramp test pattern:
• Configure the increment value between two successive steps of the digital ramp in the RAMP_INC_CHA
(address = 0x13) and RAMP_INC_CHB (address = 0x18) registers, respectively. The digital ramp increments
by N + 1, where N is the value configured in these registers.
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 2 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 2 (address = 0x18).
The ADS981x outputs digital ramp values in place of the ADC A and ADC B data, respectively.

ADS9817, ADS9815
6.4 Device Functional Modes

6.4.1 Power-Down
The ADS981x can be powered-down by either a logic 0 on the PWDN pin or by writing 11b to the PD_CH field in
address 0xC0 in register bank 1. The device registers are initialized to the default values after power-up and the
device must be initialized with a sequence of register write operations; see the Initialization Sequence section.
6.4.2 Reset
The ADS981x can be powered down by either a logic 0 on the RESET pin or by writing 1b to the RESET field
in address 0x00 in register bank 0. The device registers are initialized to the default values after reset and the
device must be initialized with a sequence of register write operations; see the Initialization Sequence section.
6.4.3 Initialization Sequence
As shown in Table 6-9, the ADS981x must be initialized by a sequence of register writes after device power-
up or reset. A free-running sampling clock must be connected to the ADC before executing the initialization
sequence. The ADS981x registers are initialized with the default value after the initialization sequence is
complete.
Table 6-9. ADS981x Initialization Sequence
REGISTER
STEP NUMBER COMMENT
BANK ADDRESS VALUE[15:0]
1 0 0x03 0x0002 Select register bank 1
2 1 0xF6 0x0002 INIT_2 = 1
3 0 0x04 0x000B INIT_1 = 1011b
5 2 0x12 0x0040 INIT_3 = 1
6 2 0x13 0x8000 INIT_4 = 1
7 2 0x0A 0x4000 INIT_5 = 1
8 Wait 10 μs (min)
9 2 0x0A 0x0000 INIT_5 = 0
11 1 0xF6 0x0000 INIT_2 = 0
13 2 0x13 0x0000 INIT_5 = 0
14 2 0x12 0x0000 INIT_4 = 0
15 0 0x04 0x0000 INIT_1 = 0
17 1 0x33 0x0030 Write INIT_KEY
18 1 0xF4 0x0000 INIT = 0
19 1 0xF4 0x0002 INIT = 1
20 Wait 1 ms (min)
21 1 0xF4 0x0000 INIT = 0
22 Wait 1 ms (min)
23 1 0x33 0x0000 INIT_KEY = 0
Enable gain error calibration and select ADC
24 1 0x0D <user-defined>
output data format
25 1 0x33 0x2040 Enable gain error calibration
26 1 0x34 0x0010 Enable gain error calibration

ADS9817, ADS9815
As shown in Table 6-10, the default settings of the ADS981x can be changed for user-defined configuration:
• Analog inputs: analog input range, bandwidth, and common-mode voltage range
• Data interface: number of output lanes, single or double data rate
Table 6-10. ADS981x User-Configuration
REGISTER
STEP COMMENT
BANK ADDRESS VALUE[15:0]
Configure data interface
(data rate, number of
1 1 0xC1 <user-defined>
lanes) and select internal
or external reference
Select analog input
2 1 0xC2 and 0xC3 <user-defined>
ranges. See Table 6-1
Select analog input
3 1 0xC0 <user-defined>
bandwidth. See Table 6-2
Select common-mode
range for analog inputs.
4 1 0xC4 and 0xC5 <user-defined>
See Table 6-3 and Table
6-4
6.4.4 Normal Operation

After the ADS981x is initialized (see Table 6-9), the ADS981x converts analog input voltages to digital output. A
free-running sampling clock is required for normal device operation; see the ADC Sampling Clock Input section.

ADS9817, ADS9815
6.5 Programming
6.5.1 Register Write
Register write access is enabled by setting SPI_RD_EN = 0b. The 16-bit configuration registers are grouped in
three register banks and are addressable with an 8-bit register address. Register bank 1 and register bank 2
can be selected for read or write operation by configuring the PAGE_SEL0 and PAGE_SEL1 bits, respectively.
Registers in bank 0 are always accessible, irrespective of the PAGE_SELx bits because the register addresses
in bank 0 are unique and are not used in register banks 1 and 2.
As shown in Figure 6-9, steps to write to a register are:
1. Frame 1: Write to register address 0x03 in register bank 0 to select either register bank 1 or bank 2 for a
subsequent register write. This frame has no effect when writing to registers in bank 0.
2. Frame 2: Write to a register in the bank selected in frame 1. Repeat this step for writing to multiple registers
in the same register bank.
Frame 1 Frame 2
CS
24-bits
SCLK
{ addr[23:16] = 0x03, data[15:0] = 0x0002 or

SDI { addr[23:16] = REG_ADDR, data[15:0] = DATA }
0x0010 }
Register Write for Bank Selection (ADDR = 0x03)

Register Write
Not Required for Register Bank 0
Logic 0 (when SPI_MODE = 0b) and Hi-Z (when SPI_MODE = 1b)

SDO
Figure 6-9. Register Write
6.5.2 Register Read

Select the desired register bank by writing to register address 0x03 in register bank 0. Register read access
is enabled by setting SPI_RD_EN = 1b and SPI_MODE = 1b in register bank 0. As illustrated in Figure 6-10,
registers can be read using two 24-bit SPI frames after SPI_RD_EN and SPI_MODE are set. The first SPI frame
selects the register bank. The ADC returns the 16-bit register value in the second SPI frame corresponding to
the 8-bit register address.
As illustrated in Figure 6-10, steps to read a register are:
1. Frame 1: With SPI_RD_EN = 0b, write to register address 0x03 in register bank 0 to select the desired
register bank 0 for reading.
2. Frame 2: Set SPI_RD_EN = 1b and SPI_MODE = 1b in register address 0x00 in register bank 0.
3. Frame 3: Read any register in the selected bank using a 24-bit SPI frame containing the desired register
address. Repeat this step with the address of any register in the selected bank to read the corresponding
register.
4. Frame 4: Set SPI_RD_EN = 0 to disable register reads and re-enable register writes.
5. Repeat steps 1 through 4 to read registers in a different bank.

ADS9817, ADS9815
Frame 1 Frame 2 Frame 3 Frame 4

CS
24-bits
SCLK
{ addr[23:16] = 0x03, data[15:0] = 0x0002 or

SDI { addr[23:16] = 0x00, data[15:0] = 0x0006 } { addr[23:16] = REG_ADDR, data[15:0] = 0 } { addr[23:16] = 0x00, data[15:0] = 0x0004 }
0x0010 }
Register Write for Bank Selection (ADDR = 0x03)

Register Write for Read Enable (ADDR = 0x00) Register Read: 8-bit address of register to be read Register Write for Read Disable (ADDR = 0x00)
Not Required for Register Bank 0
Hi-Z (when SPI_MODE = 1b)

SDO Logic 0 (when SPI_MODE = 0b) 16-bit Register Data
Figure 6-10. Register Read
6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration

Figure 6-11 shows a typical connection diagram showing multiple devices in a daisy-chain topology.
SCLK
CS
SCLK CS SCLK CS SCLK CS SCLK CS

ADS98XX ADS98XX ADS98XX ADS98XX
HOST
ADC4 ADC3 ADC2 ADC1
SDO SDI SDO SDI SDO SDI SDO SDI
24-bit 24-bit 24-bit 24-bit PICO
POCI
Figure 6-11. Daisy-Chain Connections for SPI Configuration
The CS and SCLK inputs of all ADCs are connected together and controlled by a single CS and SCLK pin of
the controller, respectively. The SDI input pin of the first ADC in the chain (ADC1) is connected to the peripheral
IN controller OUT (PICO) pin of the controller, the SDO output pin of ADC1 is connected to the SDI input pin of
ADC2, and so on. The SDO output pin of the last ADC in the chain (ADC4) is connected to the peripheral OUT
controller IN (POCI) pin of the controller. The data on the PICO pin passes through ADC1 with a 24-SCLK delay,
as long as CS is active.
The daisy-chain mode must be enabled after power-up or after the device is reset. Set the daisy-chain length
in the DAISY_CHAIN_LENGTH register to enable daisy-chain mode. The daisy-chain length is the number of
ADCs in the chain excluding ADC1. In Figure 6-11, the DAISY_CHAIN_LENGTH = 3.

ADS9817, ADS9815
6.5.3.1 Register Write With Daisy-Chain

Writing to registers in a daisy-chain configuration requires N × 24-SCLKs in one SPI frame. A register write in a
daisy-chain containing four ADCs, as shown in Figure 6-12, requires 96 SCLKs.
CS
N x 24 bits
SCLK
PICO DADCN DADC3 DADC2 DADC1
POCI Logic 0 (when SPI_MODE = 0b)
Figure 6-12. Register Write With Daisy-Chain
Daisy-chain mode is enabled on power-up or after device reset. Configure the DAISY_CHAIN_LENGTH field
to enable daisy-chain mode. The waveform shown in Figure 6-12 must be repeated N times, where N is the
number of ADCs in the daisy-chain. Figure 6-13 provides the SPI waveform, containing N SPI frames, for
enabling daisy-chain mode for N ADCs.
DADC1[23:0] = DADC2[23:0] = DADC3[23:0] = DADCN[23:0] = { 0000 0001, 0000 0000, N-1, 00}
Frame 1 Frame 2 Frame 3 Frame N

CS
N x 24 bits
SCLK
PICO DADCN DADC3 DADC2 DADC1 DADCN DADC3 DADC2 DADC1 DADCN DADC3 DADC2 DADC1 DADCN DADC3 DADC2 DADC1
DAISY_CHAIN_LENGTH = 3 {ADC1} DAISY_CHAIN_LENGTH = 3 {ADC1 and ADC2} DAISY_CHAIN_LENGTH = 3 {ADC1, ADC2 and ADC3} DAISY_CHAIN_LENGTH = 3 {ADC1,
DAISY_CHAIN_LENGTH = 0 {ADC2, ADC3, and ADCN} DAISY_CHAIN_LENGTH = 0 {ADC3, ADCN} DAISY_CHAIN_LENGTH = 0 {ADCN} ADC2, ADC3 and ADCN}
POCI Logic 0 (when SPI_MODE = 0b)
Figure 6-13. Register Write to Configure Daisy-Chain Length
6.5.3.2 Register Read With Daisy-Chain

Figure 6-14 illustrates an SPI waveform for reading registers in a daisy-chain configuration. The steps for
reading registers from N ADCs connected in a daisy-chain are as follows:
1. Register read is enabled by writing to the following registers using the Register Write With Daisy-Chain:
a. Write to PAGE_SEL to select the desired register bank
b. Enable register read by writing SPI_RD_EN = 0b (default on power-up)
2. With the register bank selected and SPI_RD_EN = 0b, the controller can read register data in the following
two steps:
a. N × 24-bit SPI frame containing the 8-bit register address to be read: N-times {0xFE, 0x00, 8-bit register
address}
b. N × 24-bit SPI frame to read out register data: N-times {0xFF, 0xFF, 0xFF}

ADS9817, ADS9815
The 0xFE in step 2a configures the ADC for register read from the specified 8-bit address. At the end of step 2a,
the output shift register in the ADC is loaded with register data. The ADC returns the 8-bit register address and
corresponding 16-bit register data in step 2b.
CS
N x 24 bits N x 24 bits
SCLK
24 bits 24 bits
8-bit register
PICO 0xFE 0x00 0xFE 0xFF 0xFF 0xFF 0xFF
address
8-bit 8-bit
POCI 16-bit register data
address address
Figure 6-14. Register Read With Daisy-Chain

ADS9817, ADS9815
7 Register Map
7.1 Register Bank 0
Figure 7-1. Register Bank 0 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RESERVED SPI_MO SPI_RD RESET
00h DE _EN
01h RESERVED DAISY_CHAIN_LEN RESERVED
03h RESERVED REG_BANK_SEL
04h RESERVED INIT_1
06h REG_00H_READBACK
Table 7-1. Register Section/Block Access Type Codes

Access Type Code Description
R R Read
W W Write
R/W R/W Read or write
Reset or Default Value
-n Value after reset or the default value
7.1.1 Register 00h (offset = 0h) [reset = 0h]
Figure 7-2. Register 00h

15 14 13 12 11 10 9 8
RESERVED
W-0h
7 6 5 4 3 2 1 0
RESERVED SPI_MODE SPI_RD_EN RESET
W-0h W-0h W-0h W-0h
Figure 7-3. Register 00h Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED W 0h Reserved. Do not change from the default reset value.
Select between legacy SPI mode and daisy-chain SPI
mode for the configuration interface for register access.
2 SPI_MODE W 0h
0 : Daisy-chain SPI mode
1 : Legacy SPI mode
Enable register read access in legacy SPI mode. This bit
has no effect in daisy-chain SPI mode.
1 SPI_RD_EN W 0h
0 : Register read disabled
1 : Register read enabled
ADC reset control.
0 RESET W 0h 0 : Normal device operation
1 : Reset ADC and all registers

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED DAISY_CHAIN_LEN RESERVED
R/W-0h R/W-0h R/W-0h

15-7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
Configure the number of ADCs connected in daisy-chain for
the SPI configuration.
DAISY_CHAIN_L
6-2 R/W 0h 0 : 1 ADC
EN
1 : 2 ADCs
31 : 32 ADCs

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
REG_BANK_SEL
R/W-2h

Register bank selection for read and write operations.
0 : Select register bank 0
7-0 REG_BANK_SEL R/W 2h

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INIT_1
R/W-0h

INIT_1 field for device initialization. Write 1011b during the
3-0 INIT_1 R/W 0h
initialization sequence. Write 0000b for normal operation.

15 14 13 12 11 10 9 8
REG_00H_READBACK
R-0h
7 6 5 4 3 2 1 0
REG_00H_READBACK
R-5h

This register is a copy of the register address 0x00 for
REG_00H_READ readback. The register address 0x00 is write-only. The
15-0 R 2h
BACK default readback value is 2h because SPI_RD_EN in
address 0x00 must be set to 1 for register reads.

ADS9817, ADS9815
7.2 Register Bank 1

RESERVED DATA_F RESERVED GE_CAL_EN1 RESERVED
0Dh ORMAT
RESERVED XOR_EN RESERVED DATA_L
12h ANES
RESERVED RAMP_INC_ADC_A TEST_PAT_MODE_ TEST_P
ADC_A AT_EN_ RESERV
13h ADC_A ED
14h TEST_PAT0_ADC_A
15h TEST_PAT1_ADC_A TEST_PAT0_ADC_A
16h TEST_PAT1_ADC_A
RESERVED RAMP_INC_ADC_B TEST_PAT_MODE_ TEST_P
ADC_B AT_EN_ RESERV
18h ADC_B ED
19h TEST_PAT0_ADC_B
1Ah TEST_PAT1_ADC_B TEST_PAT0_ADC_B
1Bh TEST_PAT1_ADC_B
1Ch RESERVED USER_BITS_ADC_B RESERVED USER_BITS_ADC_A
RESERVED GE_CAL RESERVED GE_CAL INIT_KEY RESERVED
33h _EN3 _EN2
RESERVED GE_CAL RESERVED
34h _EN4
C0h RESERVED ANA_BW PD_CH
RESERVED PD_REF RESERV DATA_L DATA_R RESERVED
C1h ED ANES ATE
C2h RANGE_CH4 RANGE_CH3 RANGE_CH2 RANGE_CH1
C3h RANGE_CH8 RANGE_CH7 RANGE_CH6 RANGE_CH5
RESERVED CM_RNG_ADC_B CM_RNG_ADC_A RESERVED CM_EN_ CM_EN_ RESERV PD_CHI
C4h ADC_B ADC_A ED P
RESERVED CM_CT RESERVED
C5h RL_EN
RESERVED INIT RESERV
F4h ED
RESERVED INIT_2 RESERV
F6h ED

R R Read
W W Write

ADS9817, ADS9815
7.2.1 Register 0Dh (offset = Dh) [reset = 2002h]
Figure 7-13. Register 0Dh

15 14 13 12 11 10 9 8
RESERVED DATA_FORMAT RESERVED GE_CAL_EN1
R/W-0h R/W-1h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
GE_CAL_EN1 RESERVED
R/W-0h R/W-2h
Figure 7-14. Register 0Dh Field Descriptions

Select data format for the ADC conversion result.
13 DATA_FORMAT R/W 1h 0 : Straight binary format
1 : Two's-complement format
Global control for gain error calibration.
8-7 GE_CAL_EN1 R/W 0h 0 : Gain error calibration disabled for all channels
3 : Gain error calibration enabled for all channels

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED XOR_EN RESERVED

Enables XOR operation on ADC conversion result.
0 : XOR operation is disabled
3 XOR_EN R/W 0h
1 : ADC conversion result is bit-wise XOR with the LSB of
the ADC conversion result

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC_ADC_A TEST_PAT_MODE_ADC_A TEST_PAT_EN RESERVED
_ADC_A

Increment value for the ramp pattern output. The output
RAMP_INC_ADC
7-4 R/W 0h ramp increments by N+1, where N is the value configured
_A
in this register.
Select digital test pattern for analog input channels 1, 2, 3,
and 4.
0 : Fixed pattern as configured in the TEST_PAT0_ADC_A
register
TEST_PAT_MOD
3-2 R/W 0h 1 : Fixed pattern as configured in the TEST_PAT0_ADC_A
E_ADC_A
register
2 : Digital ramp output
3 : Alternate fixed pattern output as configured in the
TEST_PAT0_ADC_A and TEST_PAT1_ADC_A registers
Enable digital test pattern for data corresponding to
channels 1, 2, 3, and 4.
TEST_PAT_EN_A
1 R/W 0h 0 : ADC conversion result is launched on the data interface
DC_A
1 : Digital test pattern is launched corresponding to
channels 1, 2, 3, and 4 on the data interface
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

15 14 13 12 11 10 9 8
TEST_PAT0_ADC_A[15:0]
R/W-0h
7 6 5 4 3 2 1 0
R/W-0h

TEST_PAT0_ADC Lower 16 bits of test pattern 0 for channels 1, 2, 3, and 4
15-0 R/W 0h
_A[15:0] corresponding to ADC A.

ADS9817, ADS9815

15 14 13 12 11 10 9 8
R/W-0h
7 6 5 4 3 2 1 0
R/W-0h

TEST_PAT1_ADC Lower eight bits of test pattern 1 for channels 1, 2, 3, and 4
15-8 R/W 0h
TEST_PAT0_ADC Upper eight bits of test pattern 0 for channels 1, 2, 3, and 4
7-0 R/W 0h

15 14 13 12 11 10 9 8
R/W-0h
7 6 5 4 3 2 1 0
R/W-0h

TEST_PAT1_ADC Upper 16 bits of test pattern 1 for channels 1, 2, 3, and 4
15-0 R/W 0h

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC_ADC_B TEST_PAT_MODE_ADC_B TEST_PAT_EN RESERVED
_ADC_B

Increment value for the ramp pattern output. The output
RAMP_INC_ADC
7-4 R/W 0h ramp increments by N+1, where N is the value configured
_B
in this register.
Select digital test pattern for analog input channels 5, 6, 7,
and 8.
0 : Fixed pattern as configured in the TEST_PAT0_ADC_B
register
TEST_PAT_MOD
3-2 R/W 0h 1 : Fixed pattern as configured in the TEST_PAT0_ADC_B
E_ADC_B
register
2 : Digital ramp output
3 : Alternate fixed pattern output as configured in the
TEST_PAT0_ADC_B and TEST_PAT1_ADC_B registers
Enable digital test pattern for data corresponding to channel
5, 6, 7, and 8.
TEST_PAT_EN_A
1 R/W 0h 0 : ADC conversion result is launched on the data interface
DC_B
1 : Digital test pattern is launched corresponding to
channels 5, 6, 7, and 8 on the data interface

15 14 13 12 11 10 9 8
TEST_PAT0_ADC_B[15:0]
R/W-0h
7 6 5 4 3 2 1 0
R/W-0h

TEST_PAT0_ADC Lower 16 bits of test pattern 0 for channels 5, 6, 7, and 8
15-0 R/W 0h
_B[15:0] corresponding to ADC B.

ADS9817, ADS9815
7.2.9 Register 1Ah (offset = 1Ah) [reset = 0h]
Figure 7-29. Register 1Ah

15 14 13 12 11 10 9 8
R/W-0h
7 6 5 4 3 2 1 0
R/W-0h
Figure 7-30. Register 1Ah Field Descriptions

TEST_PAT1_ADC Lower eight bits of test pattern 1 for channels 5, 6, 7, and 8
15-8 R/W 0h
TEST_PAT0_ADC Upper eight bits of test pattern 0 for channels 5, 6, 7, and 8
7-0 R/W 0h
7.2.10 Register 1Bh (offset = 1Bh) [reset = 0h]
Figure 7-31. Register 1Bh

15 14 13 12 11 10 9 8
R/W-0h
7 6 5 4 3 2 1 0
R/W-0h
Figure 7-32. Register 1Bh Field Descriptions

TEST_PAT1_ADC Upper 16 bits of test pattern 1 for channels 5, 6, 7, and 8
15-0 R/W 0h

ADS9817, ADS9815
7.2.11 Register 1Ch (offset = 1Ch) [reset = 0h]
Figure 7-33. Register 1Ch

15 14 13 12 11 10 9 8
RESERVED USER_BITS_ADC_B
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED USER_BITS_ADC_A
R/W-0h R/W-0h
Figure 7-34. Register 1Ch Field Descriptions

USER_BITS_ADC User-defined bits appended to the ADC conversion result
15-8 R/W 0h
_B from channels 5, 6, 7, and 8.
USER_BITS_ADC User-defined bits appended to the ADC conversion result
7-0 R/W 0h
_A from channels 1, 2, 3, and 4.

15 14 13 12 11 10 9 8
RESERVED GE_CAL_EN3 RESERVED
7 6 5 4 3 2 1 0
RESERVED GE_CAL_EN2 INIT_KEY RESERVED

13 GE_CAL_EN3 R/W 0h 0 : Gain error calibration disabled for all channels
Device initialization sequence access key. Write 11b to
5-4 INIT_KEY R/W 0h access the device initialization sequence. Write 00b for
normal operation.

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED GE_CAL_EN4 RESERVED

7.2.14 Register C0h (offset = C0h) [reset = 0h]
Figure 7-39. Register C0h

15 14 13 12 11 10 9 8
RESERVED ANA_BW
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
ANA_BW PD_CH
R/W-0h R/W-0h
Figure 7-40. Register C0h Field Descriptions

Select analog input bandwidth for the respective analog
input channels.
MSB = BW control for channel 8.
9-2 ANA_BW R/W 0h
LSB = BW control for channel 1.
0 : Low-noise mode
1 : Wide-bandwidth mode
Power-down control for the analog input channels.
0 : Normal operation
1-0 PD_CH R/W 0h 1 : Channels 1, 2, 3, and 4 powered down
2 : Channels 5, 6, 7, and 8 powered down
3 : All channels powered down

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED PD_REF RESERVED DATA_LANES DATA_RATE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h

ADC reference voltage source selection.
0 : Internal reference enabled.
11 PD_REF R/W 0h
1 : Internal reference disabled. Connect the external
reference voltage to the REFIO pin.
Select number of output data lanes per ADC channel.
0 : 2-lane mode. ADC A data are output on pins D3 and D2.
9 DATA_LANES R/W 0h ADC B data are output on pins D1 and D0.
1 : 1-lane mode. ADC A data are output on pin D3. ADC B
data are output on pin D1.
Select data rate for the data interface.
8 DATA_RATE R/W 0h 0 : Double data rate (DDR)
1 : Single data rate (SDR)

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RANGE_CH4 RANGE_CH3
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RANGE_CH2 RANGE_CH1
R/W-0h R/W-0h

Select input voltage range for channel 4.
0 : ±5 V
1 : ±3.5 V
15-12 RANGE_CH4 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V
0 : ±5 V
1 : ±3.5 V
11-8 RANGE_CH3 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V
0 : ±5 V
1 : ±3.5 V
7-4 RANGE_CH2 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V
0 : ±5 V
1 : ±3.5 V
3-0 RANGE_CH1 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RANGE_CH8 RANGE_CH7
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RANGE_CH6 RANGE_CH5
R/W-0h R/W-0h

0 : ±5 V
1 : ±3.5 V
15-12 RANGE_CH8 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V
0 : ±5 V
1 : ±3.5 V
11-8 RANGE_CH7 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V
0 : ±5 V
1 : ±3.5 V
7-4 RANGE_CH6 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V
0 : ±5 V
1 : ±3.5 V
3-0 RANGE_CH5 R/W 0h 2 : ±2.5 V
3 : ±7 V
4 : ±10 V
5 : ±12 V

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED CM_RNG_ADC_B
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CM_RNG_ADC_A RESERVED CM_EN_ADC_ CM_EN_ADC_ RESERVED PD_CHIP
B A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Common-mode range for channels 5, 6, 7, and 8.
0 : CM range equal to ±RANGE / 2 for the respective
9-8 CM_RNG_ADC_B R/W 0h channels
1 : CM range equal to ±6 V for channels 5, 6, 7, and 8
Common-mode range for channels 1, 2, 3, and 4.
0 : CM range equal to ±RANGE / 2 for the respective
7-6 CM_RNG_ADC_A R/W 0h channels
Enable wide-common-mode range control for analog input
channels 1 to 4.
3 CM_EN_ADC_B R/W 0h 0 : Wide-common-mode range control disabled
1 : Wide-common-mode range control enabled for channels
1, 2, 3, and 4
Enable wide-common-mode range control for analog input
channels 5 to 8.
2 CM_EN_ADC_A R/W 0h 0 : Wide-common-mode range control disabled
1 : Wide-common-mode range control enabled for channels
5, 6, 7, and 8
Full chip power-down control.
0 PD_CHIP R/W 0h 0 : Normal device operation
1 : Full device powered-down

ADS9817, ADS9815

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED CM_CTRL_EN RESERVED

Enable wide-common-mode range control for all analog
input channels.
0 : CM range for all analog input channels is ±12 V
4 CM_CTRL_EN R/W 0h
1 : CM range is user-defined in the
CM_EN_ADC_A, CM_EN_ADC_B, CM_RNG_ADC_A, and
CM_RNG_ADC_B registers
7.2.20 Register F4h (offset = F4h) [reset = 0h]
Figure 7-51. Register F4h

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED CM_CTRL_EN RESERVED
Figure 7-52. Register F4h Field Descriptions

INIT field for device initialization. Write 1b during the
1 INIT R/W 0h

ADS9817, ADS9815
7.2.21 Register F6h (offset = F6h) [reset = 0h]
Figure 7-53. Register F6h

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED INIT_2 RESERVED
Figure 7-54. Register F6h Field Descriptions

1 INIT_2 R/W 0h

ADS9817, ADS9815
7.3 Register Bank 2

12h RESERVED INIT_3 RESERVED
13h INIT_4 RESERVED
RESERV INIT_2 RESERVED
0Ah ED

R R Read
W W Write

15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
Figure 7-57. Register 12 Field Descriptions

6-6 INIT_3 R/W 0h

15 14 13 12 11 10 9 8
INIT_4 RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Figure 7-59. Register 13 Field Descriptions

INIT_4 field for device initialization. Write 1b during
15-15 INIT_4 R/W 0h

ADS9817, ADS9815
7.3.3 Register 0Ah (offset = 0Ah) [reset = 0h]
Figure 7-60. Register 0Ah

15 14 13 12 11 10 9 8
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Figure 7-61. Register 0A Field Descriptions

INIT_5 field for device initialization. Write 1b during
14 INIT_5 R/W 0h

ADS9817, ADS9815
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

The following section gives an example circuit and recommendations for using the ADS9817 in a data
acquisition (DAQ) system. The ADS9817 includes an integrated analog front-end for each input channel and
an integrated precision reference with a buffer. As such, this device family does not require any additional
external circuits for driving the reference or analog input pins of the ADC.
8.2 Typical Application
8.2.1 Data Acquisition (DAQ) System
Analog supply 1.8 V Supply
(5 V)
Internal
reference
(4.096 V) C8 C2
C5
0.1 F 1 F
0.1 F
C7
10 F
Sync signal to select Ch1 and Ch5

ADC input Ch1
Sampling clock for ADC
U1
53
56
51
50
49
48
47
46
45
44
43
55
54
52
SMPL_CLKP
SMPL_SYNC
SMPL_CLKM
AIN1M
VDD_1V8
VDD_1V8
GND
REFM
REFIO
AIN1P
NC
NC
VDD_1V8
AVDD_5V
C10
0.1 F
1 AIN2P IOGND 42
ADC input Ch2
2 IOVDD 41 IO supply
AIN2M
(1.2 V to 1.8 V)
3 AIN3P FCLKOUT 40
ADC input Ch3
4 AIN3M NC 39
5 AIN4P NC 38
ADC input Ch4
6 AIN4M D3 37
Data
Interface
7 GND D2 36
Thermal
8 REFM Pad D1 35
9 AIN5P D0 34
ADC input Ch5
10 AIN5M DCLKOUT 33
11 AIN6P PWDN 32 Power-down control

ADC input Ch6
12 AIN6M ADS9817 RESET 31 Device reset
IO supply
13 AIN7P IOVDD 30 (1.2 V to 1.8 V)
ADC input Ch7
REFOUT_2V5
14 AIN7M IOGND 29
VDD_1V8
AVDD_5V
VDD_1V8
C11
SPI_EN
AIN8M
AIN8P
REFM
SCLK
0.1 F
SDO
GND
SDI
NC
CS
23
24
25
26
27
28
21
22
15
16
17
18
19
20
ADC input Ch8

Configuration
SPI
Interface
Enable
configuration SPI
interface
C6 1.8 V Supply
10 F
2.5 V reference
C1
output
0.1 F
Analog supply
(5 V)
C4 C3
0.1 F 1 F
Figure 8-1. Recommended Schematic

ADS9817, ADS9815
8.2.2 Design Requirements

The goal of this application is to design an 8-channel data acquisition system (DAQ) based on the ADS981x with
an internal reference. Table 8-1 lists the parameters for this design.
Table 8-1. Design Parameters
PARAMETER VALUE
Sampling rate Up to 2 MSPS/channel
ADC reference Internal, 4.096 V
ADC analog input type Differential
ADC analog input range –5 V to +5 V
Output impedance of the source driving the ADC analog inputs Up to 200 Ω
8.2.3 Detailed Design Procedure
8.2.3.1 CMOS Data Interface

The ADS981x features a high-speed CMOS serial interface for ADC data output. ADC data are launched on
D[3:0] and the corresponding data clock is launched on DCLKOUT. The DCLKOUT frequency is 192 MHz for 2
MSPS/channel sampling rate (24 SMPL_CLK bits and an 8-MHz SMPL_CLK rate).
High-speed CMOS switching can create ground bounce that adversely impacts the SNR of the ADC. Ground
bounce increments with increases in PCB trace capacitance. Minimize the PCB trace length for D[3:0] and
DCLKOUT. Place a CMOS buffer, with low input capacitance, close to the ADS981x to minimize the effect of
CMOS switching noise.
8.2.4 Application Curves
0 0.75
0.45
-50
Amplitude (dBFS)
0.15
-100
-0.15
-150
-0.45
-200 -0.75
0.1 1 10 100 1000 0 65536 131072 196608 262144
Frequency (kHz) Output Code
SNR = 91.5 dBFS, THD = –113 dB at fIN = 2 kHz Typical INL = ±0.75 LSB
Figure 8-2. Typical FFT With Low-Bandwidth LPF, Figure 8-3. Typical INL With Low-Bandwidth LPF
RANGE = ±5 V
8.3 Power Supply Recommendations

The ADS981x has three separate power supplies: AVDD_5V, VDD_1V8, and IOVDD. There is no requirement
for a specific power-up sequence. The data and configuration digital interfaces are powered by IOVDD. A
common 1.8-V supply powers the VDD_1V8 and IOVDD pins. Figure 8-4 illustrates the decoupling capacitor
connections for the respective power supplies. Each power-supply pin must have separate decoupling
capacitors.

ADS9817, ADS9815
Analog supply
(5 V)
AVDD_5V GND
0.1 F 1 F
Analog supply
(1.8 V)
VDD_1V8
(pins 47, 48, 49)
0.1 F 1 F IOGND
Digital supply
(1.8 V)
VDD_1V8
(pins 21, 22)
0.1 F 1 F
IO supply
(1.2 V to 1.8 V)
IOVDD
0.1 F 1 F
Figure 8-4. Power-Supply Decoupling
8.4 Layout
8.4.1 Layout Guidelines
Figure 8-5 illustrates a board layout example for the ADS981x. Avoid crossing digital lines with the analog signal
path and keep the analog input signals and the reference signals away from noise sources.
Use 0.1-μF ceramic bypass capacitors in close proximity to the AVDD_5V, VDD_1V8, and IOVDD power-supply
pins. Avoid placing vias between the power-supply pins and the bypass capacitors.
Place the reference decoupling capacitor close to the device REFIO and REFM pins. Avoid placing vias between
the REFIO pin and the bypass capacitors. Connect the GND, REFM, and IOGND pins to a ground plane using
short, low-impedance paths.

ADS9817, ADS9815
8.4.2 Layout Example
Figure 8-5. Example Layout

ADS9817, ADS9815
9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (January 2023) to Revision A (December 2023) Page

• Changed document status from Advance Information to Production Data ........................................................1
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 12-Dec-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
ADS9817RSHR ACTIVE VQFN RSH 56 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS9817 Samples
ADS9817RSHT ACTIVE VQFN RSH 56 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS9817 Samples
PADS9815RSHT ACTIVE VQFN RSH 56 250 TBD Call TI Call TI -40 to 125 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS9817RSHR VQFN RSH 56 2500 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2
ADS9817RSHT VQFN RSH 56 250 180.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS9817RSHR VQFN RSH 56 2500 367.0 367.0 35.0
ADS9817RSHT VQFN RSH 56 250 210.0 185.0 35.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

06 Ads9817

Uploaded by

Copyright:

Available Formats

06 Ads9817

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

06 Ads9817

Uploaded by

Copyright:

Available Formats

ADS9817, ADS9815

SBASA81A – JANUARY 2023 – REVISED DECEMBER 2023

ADS981x 18-Bit, 2-MSPS/Ch, Dual, Simultaneous-Sampling ADC With Integrated

Device Block Diagram

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ADS9817 ADS9815

4 Pin Configuration and Functions

Figure 4-1. RSH Package, 56-Pin VQFN (Top View)

Table 4-1. Pin Functions

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

Table 4-1. Pin Functions (continued)

(1) I = input, O = output, I/O = input or output, G = ground, and P = power.

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ADS9817 ADS9815

5.2 ESD Ratings

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5

5.3 Recommended Operating Conditions

5.4 Thermal Information

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ADS9817 ADS9815

5.5 Electrical Characteristics

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7

5.5 Electrical Characteristics (continued)

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ADS9817 ADS9815

5.5 Electrical Characteristics (continued)

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9

5.6 Timing Requirements

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ADS9817 ADS9815

5.7 Switching Characteristics

5.8 Timing Diagrams

tden_CKDO td_CKDO tht_SDO tdz_CKDO

Figure 5-1. SPI Configuration Interface

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11

toff_DCLKDO_f 6 DCLK toff_DCLKDO_r

Channel 1 Channel 2 Channel 3 Channel 4 Channel 1

Channel 8 Channel 7 Channel 6 Channel 5 Channel 8

Figure 5-2. 4-SDO DDR CMOS Data Interface

toff_DCLKDO_r 12 DCLK toff_DCLKDO_f

Channel 1 Channel 2 Channel 3 Channel 4 Channel 1

Channel 8 Channel 7 Channel 6 Channel 5 Channel 8

Figure 5-3. 2-SDO DDR CMOS Data Interface

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ADS9817 ADS9815

Channel 1 Channel 2 Channel 3 Channel 4

Channel 8 Channel 7 Channel 6 Channel 5

Figure 5-4. 4-SDO SDR CMOS Data Interface

Channel 1 Channel 2 Channel 3 Channel 4

Channel 8 Channel 7 Channel 6 Channel 5

Figure 5-5. 2-SDO SDR CMOS Data Interface

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13

5.9 Typical Characteristics

Integral Nonlinearity (LSB)

Typical INL = ±0.75 LSB Typical INL = ±0.75 LSB

Differential Nonlinearity (LSB)

Typical DNL = ±0.2 LSB Typical DNL = ±0.25 LSB

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ADS9817 ADS9815