ELCT-201 Digital Logic Design Name: Assignment 1 Tutorial #

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IET Faculty

Dr. Haitham Omran & Dr. Wassim Alexan

ELCT-201 Digital Logic Design Name:


Assignment 1 Tutorial #:

Problem I: Simplify the following expressions using K–maps:


i) F(A, B, C) = Π M(0, 1, 4, 5, 6)
ii) F(A, B, C, D) = A B C + B C D + B D + A B
iii) F(A, B, C, D) = Π M(0, 1, 2, 3, 6, 7, 8, 9, 10, 14, 15)
iv) F(A, B, C, D) = Σ m(1, 6, 7, 9, 11) + d(8, 10, 15)

Problem II: Using K–maps, simplify the following function and implement it once using NAND
gates only and once using NOR gates only:
F(A, B, C, D) = Σ(0, 2, 4, 5, 6, 9, 10) + d(7, 11, 12, 13, 14, 15)

Problem III: Given the following SOP form of a function:


F(w, x, y, z) = w ' x' y ' z' + w ' x' y z' + w ' x y ' z + w ' x y z + w ' x y z' + w x' y ' z' + w x' y z'
Fill out a 4–variable K–map based on it and then get the simplified function F(w, x, y, z)

Problem IV: Design a combinational logic circuit that computes the function F(x) = x2 + 2,
where x is a 3-bit input, x = {x2 , x1 , x0 }. Implement the function using NOR gates only.
Assume that the input variables are available in both complemented and uncomplemented
forms.

Problem V: Using full adders and basic logic gates only, design a multiplier (A ×B), where A
is a 4-bit number (A3 , A2 , A1 , A0 ) and B is a 3–bit number (B2 , B1 , B0 ).

Problem VI: A majority circuit is a combinational circuit whose output is equal to 1 if the input
variables have more 1s than 0s. Otherwise, the output is 0. Design a three–input majority
circuit by finding the circuit’s (a) truth table, (b) Boolean expression and (c) logic diagram.

Problem VII: Design a digital system whose output is defined as logically high if the 4–bit
input binary number is a multiple of 3; otherwise, the output will be logically low. The output is
defined if and only if the input binary number is greater than 5.

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Problem VIII: Write down the simplified Boolean expressions for the outputs F and G in
terms of the input variables in the following circuit:

Problem IX: Implement the following circuit using NAND gates only:

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