Electrical Eng. Dept.

Microprocessor and Computer Architecture I

Second Class Asst. Lec. Farah M. Ali

INTERNAL MICROPROCESSOR ARCHITECTURE

The Programming Model

The programming model of the 8086 through the Core2 is considered to be

program visible because its registers are used during application
programming and are specified by the instructions. Other registers, are
considered to be program invisible because they are not addressable
directly during applications programming, but may be used indirectly
during system programming. Only the 80286 and above contain the
program-invisible registers used to control and operate the protected
memory system and other features of the microprocessor.
Figure 2–1 illustrates the programming model of the 8086 through the
Core2 microprocessor including the 64-bit extensions. The earlier 8086,
8088, and 80286 contain 16-bit internal architectures, a subset of the
registers shown in Figure 2–1. The 80386 through the Core2
microprocessors contain full 32-bit internal architectures. The architectures
of the earlier 8086 through the 80286 are fully upward-compatible to the
80386 through the Core2. The shaded areas in this illustration represent
registers that are found in early versions of the 8086, 8088, or 80286
microprocessors and are provided on the 80386–Core2 microprocessors for
compatibility to the early versions.
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

The FS and GS segments are supplemental segment registers available in

the 80386–Core2 microprocessors to allow two additional memory
segments for access by programs. Windows uses these segments for
internal operations, but no definition of their usage is available. Other
difference exists: these additional 64-bit registers (R8 through R15) are
addressed as a byte, word, double-word, or quad-word, but only the
rightmost 8 bits is a byte. R8 through R15 have no provision for directly
addressing bits 8 through 15 as a byte.

REAL MODE MEMORY ADDRESSING

The 80286 and above operate in either the real or protected mode. Only the
8086 and 8088 operate exclusively in the real mode. In the 64-bit operation
mode of the Pentium 4 and Core2, there is no real mode operation. Real
mode operation allows the microprocessor to address only the first 1M
byte of memory space—even if it is the Pentium 4 or Core2
microprocessor. Note that the first 1M byte of memory is called the real
memory, conventional memory, or DOS memory system. The DOS
operating system requires that the microprocessor operates in the real
mode. Windows does not use the real mode.
Real mode operation allows application software written for the
8086/8088, which only contains 1M byte of memory, to function in the
80286 and above without changing the software. The upward compatibility
of software is partially responsible for the continuing success of the Intel
family of microprocessors. In all cases, each of these microprocessors
begins operation in the real mode by default whenever power is applied or
the microprocessor is reset. Note that if the Pentium 4 or Core2 operate in
the 64-bit mode, it cannot execute real mode applications; hence, DOS
applications will not execute in the 64-bit mode unless a program that
emulates DOS is written for the 64-bit mode.
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

Segments and Offsets

A combination of a segment address and an offset address accesses a

memory location in the real mode. The offset address selects any location
within the 64K byte memory segment. Segments in the real mode always
have a length of 64K bytes.
Figure 2–3 shows how the segment plus offset addressing scheme selects
a memory location. This illustration shows a memory segment that begins
at location 10000H and ends at location IFFFFH—64K bytes in length. It
also shows how an offset address, sometimes called a displacement.
The segment register in Figure 2–3 contains 1000H, yet it addresses a
starting segment at location 10000H. In the real mode, each segment
register is internally appended with a 0H on its rightmost end. This forms
a 20-bit memory address, allowing it to access the start of a segment.
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

INTRODUCTION TO PROTECTED MODE MEMORY

ADDRESSING

Protected mode memory addressing (80286 and above) allows access to

data and programs located above the first 1M byte of memory, as well as
within the first 1M byte of memory. Protected mode is where Windows
operates. In place of the segment address, the segment register contains a
selector that selects a descriptor from a descriptor table. The descriptor
describes the memory segment’s location, length, and access rights.
Because the segment register and offset address still access memory,
protected mode instructions are identical to real mode instructions. In fact,
most programs written to function in the real mode will function without
change in the protected mode. The difference between modes is in the way
that the segment register is interpreted by the microprocessor to access the
memory segment.
Another difference, in the 80386 and above, is that the offset address can
be a 32-bit number instead of a 16-bit number in the protected mode. A 32-
bit offset address allows the microprocessor to access data within a
segment that can be up to 4G bytes in length.
Indirectly, the segment register still selects a memory segment, but not
directly as in the real mode. For example, in the real mode, if CS=0008H,
the code segment begins at location 00080H. In the protected mode, this
segment number can address any memory location in the entire system for
the code segment.

Basic I/O Interface ( chapter 11)

A microprocessor is great at solving problems, but if it can’t communicate
with the outside world, it is of little worth. The instruction set contains one
type of instruction that transfers information to an I/O device (OUT) and
another to read information from an I/O device (IN). Instructions (INS and
OUTS, found on all versions except the 8086/8088) are also provided to
transfer strings of data between the memory and an I/O device.

Isolated and Memory-Mapped I/O

There are two different methods of interfacing I/O to the microprocessor:

isolated I/O and memory-mapped I/O. In the isolated I/O scheme, the
IN, INS, OUT, and OUTS instructions transfer data between the
microprocessor’s accumulator or memory and the I/O device. In the
memory-mapped I/O scheme, any instruction that references memory can
accomplish the transfer. The PC does not use memory-mapped I/O.
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

Isolated I/O. The most common I/O transfer technique used in the Intel
microprocessor-based system is isolated I/O. (Figure 11–1 illustrates both
the isolated and memory-mapped address spaces for any Intel 80X86 or
Pentium–Core2 microprocessor.) The addresses for isolated I/O devices,
called ports, are separate from the memory. Because the ports are separate,
the user can expand the memory to its full size without using any of
memory space for I/O devices. A disadvantage of isolated I/O is that the
data transferred between I/O and the microprocessor must be accessed by
the IN, INS, OUT, and OUTS instructions. 𝐼𝑂𝑅𝐶 ̅̅̅̅̅̅̅ and 𝐼𝑂𝑊𝐶
̅̅̅̅̅̅̅̅ are used as
control signals. An 8-bit port address is used to access devices located on
the system board, such as the timer and keyboard interface, while a 16-bit
port is used to access serial and parallel ports as well as video and disk
drive systems.

Memory-Mapped I/O. Unlike isolated I/O, memory-mapped I/O does not

use the IN, INS, OUT, or OUTS instructions. Instead, it uses any
instruction that transfers data between the microprocessor and memory. A
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

memory-mapped I/O device is treated as a memory location in the memory

map. The main advantage of memory-mapped I/O is that any memory
transfer instruction can be used to access the I/O device. The main
disadvantage is that a portion of the memory system is used as the I/O map.
This reduces the amount of memory available to applications. Another
̅̅̅̅̅̅̅ and 𝐼𝑂𝑊𝐶
advantage is that 𝐼𝑂𝑅𝐶 ̅̅̅̅̅̅̅̅ signals have no function in a memory
mapped I/O system and may reduce the amount of circuitry required for
decoding.

Personal Computer I/O Map

The personal computer uses part of the I/O map for dedicated functions.
Figure 11–2 shows the I/O map for the PC. Note that I/O space between
ports 0000H and 03FFH is normally reserved for the computer system and
the ISA bus. The I/O ports located at 0400H–FFFFH are generally
available for user applications, main-board functions, and the PCI bus.
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

Basic Input and Output Interfaces

The basic input device is a set of three-state buffers. The basic output
device is a set of data latches. The term IN refers to moving data from the
I/O device into the microprocessor and the term OUT refers to moving data
out of the microprocessor to the I/O device.

The Basic Input Interface. Three-state buffers are used to construct the
8-bit input port depicted in Figure 11–3. The external TTL [Transistor–
transistor logic is a logic family built from bipolar junction transistors. Its name signifies
that transistors perform both the logic function (the first "transistor") and the amplifying
function (the second "transistor")] data (simple toggle switches in this example)
are connected to the inputs of the buffers. The outputs of the buffers
connect to the data bus. The exact data bus connections depend on the
version of the microprocessor. For example, the 8088 has data bus
connections D7–D0, the 80386/80486 has connections D31–D0, and the
Pentium–Core2 have connections D63–D0. The circuit of Figure 11–3
allows the microprocessor to read the contents of the eight switches that
̅̅̅̅̅
connect to any 8-bit section of the data bus when the select signal 𝑆𝐸𝐿
becomes a logic 0. Thus, whenever the IN instruction executes, the
contents of the switches are copied into the AL register.

To interface 16 bits of data, the circuit in Figure 11–3 is doubled to include

two 74ALS244 buffers that connect 16 bits of input data to the 16-bit data
bus. To interface 32 bits of data, the circuit is expanded by a factor of 4.
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

The Basic Output Interface. The basic output interface receives data from
the microprocessor and usually must hold it for some external device. Its
latches or flip-flops, like the buffers found in the input device, are often
built into the I/O device.
Figure 11–4 shows how eight simple light-emitting diodes (LEDs) connect
to the microprocessor through a set of eight data latches. The latch stores
the number output by the microprocessor from the data bus so that the
LEDs can be lit with any 8-bit binary number. Latches are needed to hold
the data because when the microprocessor executes an OUT instruction,
the data are only present on the data bus for less than 1.0 μs. Without a
latch, the viewer would never see the LEDs illuminate. When the OUT
instruction executes, the data from AL, AX, or EAX are transferred to the
latch via the data bus.

Handshaking

Many I/O devices accept or release information at a much slower rate than
the microprocessor. Another method of I/O control, called handshaking
or polling, synchronizes the I/O device with the microprocessor. An
example of a device that requires handshaking is a parallel printer that
prints a few hundred characters per second (CPS). It is obvious that the
microprocessor can send more than a few hundred CPS to the printer, so a
way to slow the microprocessor down to match speeds with the printer
must be developed.
Electrical Eng. Dept. Microprocessor and Computer Architecture I
Second Class Asst. Lec. Farah M. Ali

Figure 11–5 illustrates the typical input and output connections found on a
printer. Here, data are transferred through a series of data connections (D7–
D0). BUSY indicates that the printer is busy. STB is a clock pulse used to
send data to the printer for printing.