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TUSB9261
SLLSE67I – MARCH 2011 – REVISED MARCH 2016

TUSB9261 USB 3.0 to SATA Bridge

1 Features 2 Applications
1• Universal Serial Bus (USB) • External HDD/SSD
– SuperSpeed USB 3.0 Compliant – TID • External DVD
340730020 • External CD
– Integrated Transceiver Supports SS/HS/FS • HDD-Based Portable Media Player
Signaling
– Best-in-Class Adaptive Equalizer 3 Description
– Allows for Greater Jitter Tolerance in the The TUSB9261 is an ARM® Cortex® M3
Receiver microcontroller based USB 3.0 to serial ATA bridge. It
provides the necessary hardware and firmware to
– USB Class Support implement a USB attached SCSI protocol (UASP)-
– USB Attached SCSI Protocol (UASP) compliant mass storage device suitable for bridging
– USB Mass Storage Class Bulk-Only hard disk drives (HDD), solid state disk drives (SSD),
Transport (BOT) optical drives, and other compatible SATA 1.5-Gbps
or SATA 3.0-Gbps devices to a USB 3.0 bus. In
– Support for Error Conditions Per the 13 addition to UASP support, the firmware implements
Cases (Defined in the BOT Specification) the mass storage class BOT and USB HID interfaces.
– USB Bootability Support
– USB Human Interface Device (HID) Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Supports Firmware Update Via USB, Using a
TI Provided Application TUSB9261 HTQFP (64) 7.00 × 7.00 mm

• SATA Interface (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Serial ATA Specification Revision 2.6
– Gen1i, Gen1m, Gen2i, and Gen2m
Simplified Schematic
– Support for Mass-Storage Devices Compatible
With the ATA/ATAPI-8 Specification ROM
ARM
GRSTz Power
and
TCK
TMS
Cortex M3 VDD3.3 JTAG TDO
Reset
• Integrated ARM Cortex M3 Core RAM
64 kB VDD1.1 Distribution
TDI
TRST

– Customizable Application Code Loaded from

EEPROM by SPI Interface Data Path
RAM
USB 3.0
Clock XI Device
80 kB
– Two Additional SPI Port Chip Selects for Generation X0 Controller

Peripheral Connection
SATA
– Up to 12 GPIOs for End-User Configuration AHCI

Watchdog Timer
– Two GPIOs have PWM Functionality for Timer

LED Blink Speed Control SATA II

PHY
USB SS
PHY
USB HS/FS
PHY
SCI GPIO
SPI
– Serial Communications Interface for Debug (UART) PWM
VBUS

USB_R1RTN
DATA_OUT

GPIO[11:0]

SATARX+
SATATX+

(UART)
PWM[1:0]

SATARX-
SATATX-
DATA_IN

USB_R1
CS[2:0]

SSRX+
UartRX

DP/DM
SSTX+
UartTX

SSRX-
SSTX-
SCLK

• General Features
– Integrated Spread Spectrum Clock Generation
Enables Operation from a Single Low-Cost
Crystal or Clock Oscillator
– Supports 40 MHz
– A JTAG Interface is Used for IEEE1149.1 and
IEEE1149.6 Boundary Scan
– Available in a Fully RoHS-Compliant Package

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB9261
SLLSE67I – MARCH 2011 – REVISED MARCH 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 10
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 13
3 Description ............................................................. 1 8 Application and Implementation ........................ 15
4 Revision History..................................................... 2 8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 7 9 Power Supply Recommendations...................... 19
9.1 Digital Supplies 1.1-V and 3.3-V ............................. 19
6.1 Absolute Maximum Ratings ...................................... 7
9.2 Analog Supplies 1.1-V and 3.3-V ........................... 19
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7 10 Layout................................................................... 19
6.4 Thermal Information .................................................. 7 10.1 Layout Guidelines ................................................. 19
6.5 DC Electrical Characteristics for 3.3-V Digital I/O..... 8 10.2 Layout Examples................................................... 20
6.6 SuperSpeed USB Power Consumption .................... 8 11 Device and Documentation Support ................. 22
6.7 High-Speed USB Power Consumption ..................... 8 11.1 Community Resources.......................................... 22
6.8 Oscillator Specification.............................................. 9 11.2 Trademarks ........................................................... 22
6.9 Crystal Specification.................................................. 9 11.3 Electrostatic Discharge Caution ............................ 22
7 Detailed Description ............................................ 10 11.4 Glossary ................................................................ 22
7.1 Overview ................................................................. 10 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 10 Information ........................................................... 22

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (July 2015) to Revision I Page

• Changed the CDM value in the ESD Ratings table From: 5000 To: ±1500 .......................................................................... 7

Changes from Revision G (October 2014) to Revision H Page

• Moved Tstg from Handling Ratings table to Absolute Maximum Ratings and renamed Handling Ratings to ESD Ratings ... 7
• Updated the frequency for the USB2 and USB3 to 5 Hz and 10 Hz, respectively ............................................................. 16

Changes from Revision F (March 2014) to Revision G Page

• Updated supported frequency to 40 MHz .............................................................................................................................. 1

• Updated supported frequency in Clock and Reset Signals table .......................................................................................... 4
• Updated the frequency for the clock to 40 MHz .................................................................................................................... 9
• Updated the frequency for the crystal to 40 MHz .................................................................................................................. 9
• Updated oscillation frequency and ESR equivalent series resistance .................................................................................. 9
• Updated Table 1 ................................................................................................................................................................... 12

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5 Pin Configuration and Functions

PVP Package
48-Pin HTQFP
Top View

USB_SSRXM

USB_SSTXM

USB_R1RTN
USB_SSRXP

USB_SSTXP

USB_DM
VDDA33

VDDA33

VDDA33
USB_DP
USB_R1
VDD

VDD

VDD
VSS

NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD 49 32 VDD
USB_VBUS 50 31 FREQSEL1
VDD33 51 30 FREQSEL0
XI 52 29 JTAG_TRSTz
VSSOSC 53 28 JTAG_TMS
XO 54 27 JTAG_TDO
VDD 55 26 JTAG_TDI
SATA_TXM 56 65 25 JTAG_TCK
SATA_TXP 57 VSS 24 VDD33
VSS 58 23 SPI_CS2 / GPIO11
SATA_RXM 59 22 SPI_CS1 / GPIO10
SATA_RXP 60 21 SPI_CS0
VDD 61 20 SPI_DATA_IN
VDDA33 62 19 VDD
VDD 63 18 SPI_DATA_OUT
NC 64 17 SPI_SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PWM0
PWM1
GRSTz
GPIO8 / UART_RX
GPIO9 / UART_TX

GPIO0
GPIO1
GPIO2
GPIO3

GPIO4
GPIO5
GPIO6
GPIO7
VDD

VDD33

VDD

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Signal Descriptions – I/O Definitions

I/O TYPE DESCRIPTION
I Input
O Output
I/O Input/output
PU Internal pullup resistor
PD Internal pulldown resistor
PWR Power signal

Clock and Reset Signals

PIN
I/O DESCRIPTION
NAME NO.
I Global power reset. This reset brings all of the TUSB9261 internal registers to their default
GRSTz 4
PU states. When GRSTz is asserted, the device is completely nonfunctional.
Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately
XI 52 I be driven by the output of an external oscillator. When using a crystal, a 1-MΩ feedback resistor
is required between X1 and XO.
Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an
XO 54 O external oscillator, this pin may be left unconnected. When using a crystal, a 1-MΩ feedback
resistor is required between X1 and XO.
Frequency select. These terminals indicate the oscillator input frequency and are used to
configure the correct PLL multiplier. The field encoding is as follows:
I
FREQSEL[1:0] 31, 30
PU FREQSEL[1] FREQSEL[0] INPUT CLOCK FREQUENCY
1 1 40 MHz

SATA Interface Signals (1)

PIN
I/O DESCRIPTION
NAME NO.
SATA_TXP 57 O Serial ATA transmitter differential pair (positive)
SATA_TXM 56 O Serial ATA transmitter differential pair (negative)
SATA_RXP 60 I Serial ATA receiver differential pair (positive)
SATA_RXM 59 I Serial ATA receiver differential pair (negative)

(1) Note that the default firmware and reference design for the TUSB9261 have the SATA TXP/TXM swapped for ease of routing in the
reference design. If you plan to use the TI default firmware please review the reference design in the TUSB9261 DEMO User’s Guide
(SLLU139) for proper SATA connection.

USB Interface Signals

PIN
I/O DESCRIPTION
NAME NO.
USB_SSTXP 43 O SuperSpeed USB transmitter differential pair (positive)
USB_SSTXM 42 O SuperSpeed USB transmitter differential pair (negative)
USB_SSRXP 46 I SuperSpeed USB receiver differential pair (positive)
USB_SSRXM 45 I SuperSpeed USB receiver differential pair (negative)
USB_DP 36 I/O USB high-speed differential transceiver (positive)
USB_DM 35 I/O USB high-speed differential transceiver (negative)
USB_VBUS 50 I USB bus power
USB_R1 38 O Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN.
USB_R1RTN 39 I Precision resistor reference return

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Serial Peripheral Interface (SPI) Signals

PIN
I/O DESCRIPTION
NAME NO.
O
SPI_SCLK 17 SPI clock
PU
O
SPI_DATA_OUT 18 SPI master data out
PU
I
SPI_DATA_IN 20 SPI master data in
PU
O
SPI_CS0 21 Primary SPI chip select for flash RAM
PU
SPI_CS2/ I/O SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used
23
GPIO11 PU as a general-purpose I/O.
SPI_CS1/ I/O SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used
22
GPIO10 PU as a general-purpose I/O.

JTAG, GPIO, and PWM Signals

PIN
I/O DESCRIPTION
NAME NO.
I
JTAG_TCK 25 JTAG test clock
PD
I
JTAG_TDI 26 JTAG test data in
PU
O
JTAG_TDO 27 JTAG test data out
PD
I
JTAG_TMS 28 JTAG test mode select
PU
I
JTAG_TRSTz 29 JTAG test reset
PD
I/O GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a
GPIO9/UART_TX 6
PU UART channel. This pin defaults to a general-purpose output.
I/O GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART
GPIO8/UART_RX 5
PU channel. This pin defaults to a general-purpose output.
I/O
GPIO7 16
PD
I/O
GPIO6 15
PD
I/O
GPIO5 14
PD
I/O
GPIO4 13
PD
Configurable as general-purpose input/outputs
I/O
GPIO3 11
PD
I/O
GPIO2 10
PD
I/O
GPIO1 9
PD
I/O
GPIO0 8
PD
O
PWM0 2
PD (1)
Pulse-width modulation (PWM). Can be used to drive status LEDs.
O
PWM1 3
PD (1)

(1) PWM pulldown resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down
resistors are enabled by default.

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Power and Ground Signals

PIN
I/O DESCRIPTION
NAME NO.
1
12
19
32
33
VDD 41 PWR 1.1-V power rail
47
49
55
61
63
7
VDD33 24 PWR 3.3-V power rail
51
34
40
VDDA33 PWR 3.3-V analog power rail
48
62
Oscillator ground. If using a crystal, this should not be connected to a PCB ground plane. If
VSSOSC 53 PWR using an oscillator, this should be connected to PCB ground. See Clock Source Requirements
for more details.
44
VSS PWR Ground
58
VSS 65 PWR Ground – Thermal pad
37
NC — No connect, leave floating
64

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
MIN MAX UNIT
VDD Steady-state supply voltage –0.3 1.4 V
VDD33/
Steady-state supply voltage –0.3 3.8 V
VDDA33
Tstg Storage temperature –55 150 °C

6.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 ±2000
VESD Electrostatic discharge V
Charged device model (CDM), per JESD22-C101 (2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Digital 1.1-V supply voltage 1.045 1.1 1.155 V
VDD33 Digital 3.3-V supply voltage 3 3.3 3.6 V
VDDA33 Analog 3.3-V supply voltage 3 3.3 3.6 V
VBUS Voltage at VBUS PAD 0 1.155 V
0 70
TA Operating free-air temperature range °C
Industrial version –40 85
TJ Operating junction temperature range –40 100 °C

6.4 Thermal Information

TUSB9261
THERMAL METRIC (1) PVP (HTQFP) UNIT
64 PINS
RθJA Junction-to-ambient thermal resistance 30.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.0 °C/W
RθJB Junction-to-board thermal resistance 6.1 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 6.1 °C/W
RJθC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 DC Electrical Characteristics for 3.3-V Digital I/O

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
TR Rise time 5 pF 1.5 ns
TF Fall time 5 pF 1.53 ns
IOL Low-level output current VDD33 = 3.3 V, TJ = 25°C 6 mA
IOH High-level output current VDD33 = 3.3 V, TJ = 25°C –6 mA
VOL Low-level output voltage IOL = 2 mA 0.4 V
VOH High-level output voltage IOL = –2 mA 2.4 V
VO Output voltage 0 VDD33 V
RECEIVER
VI Input voltage 0 VDD33 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2 V
Vhys Input hysteresis 200 mV
tT Input transition time (TR and TF) 10 ns
II Input current VI = 0 V to VDD33 5 µA
CI Input capacitance VDD33 = 3.3 V, TJ = 25°C 0.384 pF

6.6 SuperSpeed USB Power Consumption

POWER RAIL TYPICAL ACTIVE CURRENT (mA) (1) TYPICAL SUSPEND CURRENT (mA) (2)
VDD11 291 153
(3)
VDD33 65 28

(1) Transferring data by SS USB to a SSD SATA Gen II device. No SATA power management, U0 only.
(2) SATA Gen II SSD attached no active transfer. No SATA power management, U3 only.
(3) All 3.3-V power rails connected together.

6.7 High-Speed USB Power Consumption

POWER RAIL TYPICAL ACTIVE CURRENT (mA) (1) TYPICAL SUSPEND CURRENT (mA) (2)
VDD11 172 153
VDD33 (3) 56 28

(1) Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management.
(2) SATA Gen II SSD attached no active transfer. No SATA power management.
(3) All 3.3-V power rails connected together.

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6.8 Oscillator Specification

XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground
plane. A 40-MHz clock can be used.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CXI XI input capacitance TJ = 25°C 0.414 pF
VIL Low-level input voltage 0.7 V
VIH High-level input voltage 1.05 V
Ttosc_i Frequency tolerance Operational temperature –50 50 ppm
Tduty Duty cycle 45% 50% 55%
TR/TF Rise/fall time 20% to 80% 6 ns
RJ Reference clock JTF (1 sigma) (1) (2) 0.8 ps
TJ Reference clock JTF (total p-p) (2) (3) 25 ps
(4)
Tp-p Reference clock jitter (Absolute p-p) 50 ps

(1) Sigma value assuming Gaussian distribution

(2) After application of JTF
(3) Calculated as 14.1 × RJ + DJ
(4) Absolute phase jitter (p-p)

6.9 Crystal Specification

A parallel, 20-pF load capacitor should be used if a crystal source is used. VSSOSC should not be connected to the PCB
ground plane. A 40-MHz crystal can be used.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Oscillation mode Fundamental
ƒO Oscillation frequency 40 MHz
ESR Equivalent series resistance 40 MHz 50 Ω
Ttosc_i Frequency tolerance Operational temperature ±50 ppm
Frequency stability 1 year aging ±50 ppm
CL Load capacitance 12 20 24 pF
CSHUNT Crystal and board stray capacitance 4.5 pF
Drive level (max) 0.8 mW

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7 Detailed Description

7.1 Overview
The major functional blocks are as follows:
• Cortex M3 microcontroller subsystem including the following peripherals:
– Time interrupt modules, including watchdog timer
– Universal asynchronous receive/transmit (SCI)
– SPI
– General purpose input/output (GPIO)
– PWM for support of PWM outputs (PWM)
• USB 3.0 core (endpoint controller) and integrated USB 3.0 PHY
• AHCI-compliant SATA controller and integrated SATA PHY
– Supporting Gen1i, Gen1m, Gen2i, and Gen2m
• Chip level clock generation and distribution
• Support for JTAG 1149.1 and 1149.6

7.2 Functional Block Diagram

USB 3.0
(1)
SuperSpeed
PC
with
USB 3.0 SATA
Gen1/2 HDD
Support

USB 2.0
(1)
High-speed

TUSB9260
TUSB9261

A. USB connection is made at either SuperSpeed or high speed, depending on the upstream connection support.

7.3 Feature Description

7.3.1 Operation

7.3.1.1 General Functionality

The TUSB9261 ROM contains boot code that executes after a global reset, which performs the initial
configuration required to load a firmware image from an attached SPI flash memory to local RAM.
After the firmware is loaded, it configures the SATA advanced host controller interface host bus adapter (AHCI)
and the USB device controller. In addition, the configuration of the AHCI includes a port reset, which initiates an
out of band (OOB) TX sequence from the AHCI link layer to determine if a device is connected, and if so,
negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps).
The configuration of the USB device controller includes creation of the descriptors, configuration of the device
endpoints for support of UASP and USB mass storage class BOT, allocation of memory for the transmit request
blocks (TRBs), and creation of the TRBs necessary to transmit and receive packet data over the USB. In
addition, the firmware provides any other custom configuration required for application-specific implementation,
for example, a HID interface for user initiated backup.

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Feature Description (continued)

After the USB device controller configuration is complete, if a SATA device was detected during the AHCI
configuration, the firmware connects the device to the USB bus when VBUS is detected. According to the USB
3.0 specification, the TUSB9261 initially tries to connect at SuperSpeed USB. If successful, it enters U0;
otherwise, after the training time out, it enables the DP pullup and connects as a USB 2.0 high-speed or full-
speed device depending on the speed supported by host or hub port.
When connected, the firmware presents the BOT interface as the primary interface and the UASP interface as
the secondary interface. If the host stack is UASP aware, it can enable the UASP interface using a
SET_INTERFACE request for alternate interface 1.
Following speed negotiation, the device should transmit a device to host (D2H) FIS with the device signature.
This first D2H FIS is received by the link layer and copied to the port signature register. When firmware is notified
of the device connection, it queries the device for capabilities using the IDENTIFY DEVICE command. Firmware
then configures the device as appropriate for its interface and features supported, for example, an HDD that
supports native command queuing (NCQ).

7.3.1.2 Firmware Support

Default firmware support is provided for the following:
• SuperSpeed USB and USB 2.0 high speed and full speed
• USB attached SCSI protocol (UASP)
• USB mass storage class (MSC) bulk-only transport (BOT)
– Including the 13 error cases
• USB mass storage specification for bootability
• USB device class definition for HID
– Firmware update and custom functionality (for example, one-touch backup)
• Serial ATA advanced host controller interface (AHCI)
• GPIO
– LED control and custom functions (for example, one-touch backup control)
• PWM
– LED dimming control
• SPI
– Firmware storage and storing custom device descriptors
• Serial communications interface (SCI)
– Debug output only

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Feature Description (continued)

7.3.1.3 GPIO/PWM LED Designations
The default firmware provided by TI drives the GPIO and PWM outputs as listed in Table 1.

Table 1. GPIO/PWM LED Designations

GPIO DESCRIPTION DEFAULT
SETUP
Undefined. Can use HID commands to change to output low or high.
GPIO0 Input
[internal 100-µA PD]
GPIO1 USB 3.0 Link State if U1/U2 enabled, otherwise [input with 100-µA PD] Output
GPIO5 USB 3.0 Link State if U1/U2 enabled, otherwise [input with 100-µA PD] Output
U0: Off/Off
U1: On/Off
GPIO1/
USB3 power state (U0 to U3) U2: Off/On Output
GPIO5
U3: On/On
Other: Off/Off
GPIO2 HS/FS suspend Output
GPIO3 [INPUT with 100-µA PD] momentary push button Input
Bus- or self-powered indicator. (GPIO level should be HIGH when self-
GPIO4 Input
powered). [internal 100-µA PD]
Undefined. Can use HID commands to change to output low or high.
GPIO6 Input
[internal 100-µA PD]
GPIO7 SS connection Output
Undefined. Can use HID commands to change to output low or high.
GPIO10 Compile option to configure as SATA drive power enable output. Input
[internal 100-µA PU]
GPIO11 Power fault indicator. [internal 100-µA PU] Input
Disk activity (LED blink rate is faster when connected at USB
PWM0 SuperSpeed), USB connection (LED on), and USB suspend (fading Output
LED).
PWM1 SW heartbeat Output

The LEDs on the TUSB9261 product development kit (PDK) board are connected as in Table 1. See the
TUSB9261 PDK Guide for more information on GPIO LED connection and usage. This EVM is available for
purchase. Contact TI for ordering information.

7.3.1.4 Power-Up and Reset Sequence

The core power (VDD) must be present and at its minimum high level prior to, or at the same time that, the I/O
power (VDD33).
In addition, meet the following constraints:
• All maximum ratings and recommended operating conditions are observed.
• All warnings about exposure to maximum rated and recommended conditions are observed, particularly
junction temperature. These apply to power transitions as well as normal operation.
• Bus contention while VDD33 is powered up must be limited to 100 hours over the projected lifetime of the
device.
• Bus contention while VDD33 is powered down may violate the absolute maximum ratings.
A supply bus is powered up when the voltage is within the recommended operating range. It is powered down
when it is below that range, either stable or in transition.
A minimum reset duration of 2 ms is required. This is defined as the time when the power supplies are in the
recommended operating range to the deassertion of GRSTz.

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7.3.2 Clock Connections

7.3.2.1 Clock Source Requirements

The TUSB9261 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a
crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is
used, the connection needs to follow these guidelines.
Because XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as
possible and away from any switching leads. TI also recommends to minimize the capacitance between XI and
XO. This can be accomplished by connecting the VSSOSC lead to the two external capacitors CL1 and CL2 and
shielding them with the clean ground lines. The VSSOSC should not be connected to PCB ground when using a
crystal.
Load capacitance (Cload) of the crystal (varies with the crystal vendor) is the total capacitance value of the entire
oscillation circuit system as seen from the crystal. It includes two external capacitors, CL1 and CL2, in Figure 1.
The trace length between the decoupling capacitors and the corresponding power pins on the TUSB9261 must
be minimized. TI also recommends that the trace length from the capacitor pad to the power or ground plane be
minimized.
CL1

XI

VSSOSC

Crystal

XO

CL2

Figure 1. Typical Crystal Connections

7.3.2.2 Clock Source Selection Guide

Reference clock jitter is an important parameter. Jitter on the reference clock degrades both the transmit eye and
receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing system performance.
Additionally, a particularly jittery reference clock may interfere with the PLL lock detection mechanism, forcing the
lock detector to issue an Unlock signal. A good-quality, low-jitter reference clock is required to achieve
compliance with supported USB3.0 standards. For example, USB3.0 specification requires the random jitter (RJ)
component of either RX or TX to be 2.42 ps (random phase jitter calculated after applying jitter transfer function
(JTF)). As the PLL typically has a number of additional jitter components, the reference clock jitter must be
considerably below the overall jitter budget.

7.4 Device Functional Modes

7.4.1 VBUS Power
Power can be supplied by a USB cable on the terminal VBUS. When using power from VBUS, both the
TUSB9261 and the SATA device are allowed to draw only up to 500 mA from VBUS when operating.

7.4.2 External Power

Power can be supplied from an external power source. When using an external power source, both the
TUSB9261 and the SATA interface can draw all their current from the external supply.

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Device Functional Modes (continued)

7.4.3 External Voltage Regulator
Because the TUSB9261 requires two voltage supplies (1.1 V and 3.3 V), TI recommends a multi-channel voltage
regulator. The TPS650061 or TPS65024x are good choices. The TPS650061 uses a DC-DC converter and two
LDO regulators in a single package. The DC-DC converter can supply 1-A nominal current while the two LDOs
can supply 300-mA nominal current. Because the 1.1-V supply can consume upwards of 340 mA of current, the
DC-DC converter is ideal for supplying the 1.1-V current while the two LDOs can be used to supply 3.3-V current.
Likewise the TPS65024x uses three DC-DC converters and three LDOs. Both devices also have a built-in
supervisor circuit that can be connected to GRST on the TUSB9261.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device serves as a bridge between a downstream USB 3.0 host port and a SATA device such as a hard disk
drive. A crystal or oscillator supplies the required clock source. A SPI flash device contains the firmware that is
loaded into the TUSB9261 after the deassertion of RESET. Push buttons or any other desired logic can be
connected to the TUSB9261 GPIO pins. The TUSB9261 can also output a pulse-width modulated signal that can
be used to drive an activity LED.

8.2 Typical Application

Optional
SPI
JTAG
FLASH Header

TUSB9261
SPI JTAG

USB 3.0
SuperSpeed

PC with SATA
Serial ATA Device
USB 3.0 Gen 1/2
Support
USB 2.0
High-speed

CLOCK GPIO/PWM

HDD
Crystal or
Activity
Oscillator LED

Figure 2. Typical Application Schematic

8.2.1 Design Requirements

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDD supply 1.1 V
VDD33 supply 3.3 V
Upstream port USB support SS, HS, FS
Main supply VBUS
USB_VBUS resistor values 90.9 kΩ, 10 kΩ
Crystal frequency 40 MHz
SATA device SSD

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8.2.2 Detailed Design Procedure

8.2.2.1 PWM Terminals

The TUSB9261 has two pulse-width modulated output terminals.
Table 3 shows the default firmware configuration of PWMs.

Table 3. Default Firmware Configuration of PWMs

PWM USAGE
0 Primary Indicator LED:
ON when there is a USB connection. OFF when there is no connection.
Blinks during disk activity (Frequency: 5 Hz for USB2 or 10 Hz for USB3).
Fades when USB is in Suspend or U3 state.
1 Power indicator LED

PWM duty cycle will be 0% when the LED should be fully ON.

8.2.2.2 JTAG Interface

The TUSB9261 supports JTAG for board-level test and debug support. Typically, these terminals are left
unconnected or routed to a header to plug in an external JTAG controller. Table 4 shows the JTAG terminal
names and internal resistor connection. The JTAG interface should be left unconnected if JTAG support is not
required.

Table 4. Internal JTAG Resistor Termination

NAME PULL UP OR PULL DESCRIPTION
DOWN
JTAG_TCK Pull down JTAG test clock
JTAG_TDI Pull up JTAG test data in
JTAG_TDO Pull down JTAG test data out
JTAG_TMS Pull up JTAG test mode select
JTAG_RSTZ Pull down JTAG reset

8.2.2.3 Voltage Regulator Schematic

VDD_1P1V

L2

2.2 µH R30 0402

BOARD_5V
400 kΩ 1%
C46
R31 C72 22 µF
475 kΩ
U4
0402
1%
8 7 SW_1.1V
10 VINDCDC SW 11 FB_DCDC 30 pF R32
MODE 9 EN_DCDC FB_DCDC 5 A BOARD_3P3V
C57 R39 MODE PG#
22 µF MR# 1 2 TRST 4.7 kΩ
19 MR# TRST 20 0402
RSTSNS RST# GRST#
4.7 kΩ 5%
0402 15 14
3 VINLDO1 VLDO1 13
EN_LDO1 FB_LDO1 6
SW2 18 PGND 17
PB_SWITCH 4 VINLDO2 VLDO2 16 BOARD_1P8V C60
EN_LDO2 FB_LDO2 12 C68 22 µF
1 4 AGND 21
2 3 PWR_PAD 0.1 µF
N.O.
A TPS650061
A

STAR GROUND AGND TO GND

A C63
22 µF

8.2.2.4 SPI
A SPI system consists of one master device and one or more slave devices. The TUSB9261 is a SPI master
providing the SPI clock, data-in, data-out, and up to three chip-select terminals.

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The SPI has a 4-wire synchronous serial interface. Data communication is enabled with an active-low chip select
terminal (SPI_CS[2:0]#). Data is transmitted with a 3-terminal interface consisting of terminals for serial data
input (SPI_DATA_IN), serial data output (SPI_DATA_OUT) and serial clock (SPI_SCLK).
All SPI terminals have integrated pullup resistors. No external components are required to connect the SPI
interface to an external SPI flash device. See Figure 3 for an example implementation of the SPI interface using
one SPI slave device.

BOARD_3P3V

R2 R3
4.7K 4.7K
TUSB9261 U2
1 8
2 CE# VCC 7
3 SO HOLD# 6
4 WP# SCK 5
GND SI

Pm25LV512A C11
SPI_SO_J SOIC_8S 0.1uF

17 SPI_SCK
SPI_SCLK 18 SPI_SO
SPI_DATA_OUT 20 SPI_SI J13
SPI_DATA_IN 21 SPI_CE# 1 2 SPI ENABLE
SPI_CS0
HDR2X1 M .1

Figure 3. SPI Connection

The SPI_CLK is running at a fixed frequency of 18.75 MHz and its clocking mode is configured with a POLARITY
of 0 and a PHASE of 1, this means that the SPI sends the data output one half-cycle before the first rising edges
of SPI_CLK and on subsequent falling edges. Meanwhile, the input data is latched on the rising edge of
SPI_CLK (see Figure 4 and Table 5 for a detailed timing description).
The flash memory is erased by the bootloader prior to programming and must use a word size of 8 bits with an
address length of 24 bits and its program instruction must allow 256 bytes to be written in one operation. TI
recommends a minimum flash size of 512 kb (64 k × 8). Table 5 shows SPI flash devices that have been tested
with the TUSB9261.

Figure 4. SPI Characterization

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Table 5. SPI Characterization Time

NO. TIME REFERENCE THEORETICAL VALUE
1 Cycle time SPICLK 53.3 ns
2 Positive SPI_CLK slope 2 ns
3 Negative SPI_CLK slope 3 ns
MIN: 53.3 ns
4 SPISCS – SPICLK edge(PHASE = 1) TYP: 80 ns
MAX: 93.3 ns
5 Output delay time, SPICLK TX edge to SPISIMO valid 260 ps
6 Output hold time, SPICLK RX edge to SPISIMO valid 26.7 ns
7 Setup time 22 ns
8 Hold time 500 ps
9 "SPICLK -SPISCS Phase = 1, Master" 13.3 ns

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9 Power Supply Recommendations

9.1 Digital Supplies 1.1-V and 3.3-V

The TUSB9261 requires a 1.1-V and 3.3-V digital power source.
The 1.1-V terminals are named VDD11. These terminals supply power to the digital core. The 1.1-V core allows
for a significant reduction in both power consumption and logic switching noise.
The 3.3-V terminals are named VDD33 and supply power to most of the input and output cells. Both VDD11 and
VDD33 supplies must have 0.1-μF bypass capacitors to VSS (ground) to ensure proper operation. One capacitor
per power terminal is sufficient and should be placed as close to the terminal as possible to minimize trace
length. TI also recommends smaller value capacitors like 0.01-μF on the digital supply terminals.
When placing and connecting all bypass capacitors, follow high-speed board design rules.

9.2 Analog Supplies 1.1-V and 3.3-V

TI recommends a Pi filter on all analog power terminals to minimize circuit noise. These filters can be combined
on a per-rail basis for a total of two (VDDA11 / VDDA11_USB2) + (VDDA33).
Analog power terminals must have a 1-μF and a 10-μF bypass capacitor connected to VSSA (ground) to ensure
proper operation. Place the capacitor as close as possible to the associated terminal to minimize trace length. TI
also recommends smaller value capacitors such as 0.1-μF and 0.01-μF on the analog supply terminals.

10 Layout

10.1 Layout Guidelines

10.1.1 High-Speed Differential Routing
The high-speed differential pair (USB_DM and USB_DP) is connected to a USB type B connector. The
differential pair traces should be routed with 90-Ω, ±15% differential impedance. The high-speed signal pair
should be trace length matched. Maximum trace length mismatch between high-speed USB signal pairs should
be no greater than 150 mils. Keep total trace length to a minimum. Route differential traces first. Route the
differential pairs on the top or bottom layers with the minimum amount of vias possible. No termination or
coupling capacitors are required. If a common-mode choke is required, then place the choke as close as possible
to the USB connector signal pins. Likewise, ESD clamps should also be placed as close as possible to the USB
connector signal pins (closer than the choke).
To minimize crosstalk on the USB2/3 differential signal pairs, TI recommends that the spacing between the two
interfaces be five times the width of the trace (5W rule). For instance, if the SS USB TX/RX differential pair trace
widths are 5 mils, then there should be 25 mils of space (air gap) between the TX and RX differential pairs and
the DP/DM differential pair. If this 5W rule cannot be implemented, then the space between the TX/RX differential
pairs and DP/DM differential pairs should be maximized as much as possible and ground-fill should be placed
between the two. In this case, it is better to route each differential pair on opposite sides of the board with a
ground plane between them.

10.1.2 SuperSpeed Differential Routing

SuperSpeed consists of two differential routing pairs, a transmit pair (USB_SSTXM and USB_SSTXP) and a
receive pair (USB_SSRXM and USB_SSRXP). Each differential pair’s traces should be routed with 90-Ω, ±15%
differential impedance. The high-speed signal pair should be trace length matched. Maximum trace length
mismatch between SuperSpeed USB signal pairs should be no greater than 2.5 mils. The transmit differential
pair does not have to be the same length as the receive differential pair. Keep total trace length to a minimum.
Route differential traces first. Route the differential pairs on the top or bottom layers with the minimum amount of
vias possible. The transmitter differential pair requires 0.1-uF coupling capacitors for proper operation. The
package/case size of these capacitors should be no bigger than 0402. C-packs are not allowed. The capacitors
should be placed symmetrically as close as possible to the USB connector signal pins. If a common mode choke
is required, then place the choke as close as possible to the USB connector signal pins (closer than the
transmitter capacitors). Likewise ESD clamps should also be placed as close as possible to the USB connector
signal pins (closer than the choke and transmitter capacitors).

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Layout Guidelines (continued)

It is permissible to swap the plus and minus on either or both of the SuperSpeed differential pairs. This may be
necessary to prevent the differential traces from crossing over one another. However, it is not permissible to
swap the transmitter differential pair with receive differential pair. To minimize crosstalk on the SS USB
differential signal pairs, TI recommends that the spacing between the TX and RX signal pairs be five times the
width of the trace (5W rule). For instance, if the SS USB TX/RX differential pair trace widths are 5 mils, then
there should be 25 mils of space (air gap) between the TX and RX differential pairs.
If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs should be
maximized as much as possible and ground-fill should be placed between the two. In this case, it is better to
route each differential pair on opposite sides of the board with a ground plane between them.

10.1.3 SATA Differential Routing

The SATA traces (SATA_TXP and SATA_TXM) should be routed with 100-Ω, ±15% differential impedance.
Maximum trace length mismatch between SATA signal pairs should be no greater than 2.5 mils. The transmit
differential pair does not have to be the same length as receive differential pair. Keep total trace length to a
minimum. Route differential traces first. Route the differential pairs on the top or bottom layers with the minimum
amount of vias possible. Each SATA trace requires a coupling capacitor be placed inline. The package/case size
of these capacitors should be no bigger than 0402. C-packs are not allowed. The capacitors should be placed
symmetrically as close as possible to the SATA connector signal pins.
It is permissible to swap the plus and minus on the SATA differential pair. This may be necessary to prevent the
differential traces from crossing over one another. However, it is not permissible to swap the transmitter
differential pair with the receive differential pair.
To minimize crosstalk on the SATA differential signal pairs, TI recommends that the spacing between the TX and
RX signal pairs for each interface be five times the width of the trace (5W rule). For instance, if the SATA TX/RX
differential pair trace widths are 5 mils, then there should be 25 mils of space (air gap) between the TX and RX
differential pairs. If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs
should be maximized as much as possible and ground-fill should be placed between the two. In this case, it is
better to route each differential pair on opposite sides of the board with a ground plane between them.

10.2 Layout Examples

Figure 5. SuperSpeed Differential Routing

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Layout Examples (continued)

Figure 6. SATA Differential Routing

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11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.2 Trademarks
E2E is a trademark of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Ltd.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TUSB9261IPVP ACTIVE HTQFP PVP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TUSB9261I

TUSB9261PVP ACTIVE HTQFP PVP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TUSB9261

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

OTHER QUALIFIED VERSIONS OF TUSB9261 :

• Automotive: TUSB9261-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
TUSB9261IPVP PVP HTQFP 64 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TUSB9261PVP PVP HTQFP 64 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25

Pack Materials-Page 1
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