19EC4DCHDL HDL Programming

Question Bank

Unit I
1. Show the typical design flow for VLSI IC and explain all the blocks. [Jun’19] 07

2. With a neat block diagram, explain the typical VLSI IC design flow. [Jun’18, Aug’18] 06, 08

3. Show the typical design flow for VLSI IC and explain all the blocks. Also recall the different
levels of abstraction in Verilog. [Jul’17] 07

4. Differentiate between the following: [Aug’18] 06

(a) Register and wire data types
(b) $monitor and $display system tasks
(c) $finish and $stop

5. Explain the Verilog data types with syntax. [Jun’16] 06

6. Discuss different data types in HDL. [May’17] 06

7. What is a module? What are the basic components of a module? Explain with an example.
[Aug’18] 06

8. List the various components of a Verilog module. [Jun’18] 04

9. Explain the different types of modeling in Verilog. [Jul’16] 07

10. Discuss the rules to be followed while connecting the Verilog ports with an example code. [Jul’19] 06

11. Model the Verilog code for D flipflop with asynchronous active low input (reset). [Jul’17] 05

12. Apply the concept of top-down design methodology to develop a 4-bit ripple carry counter using
Verilog. [Jun’17] 08

13. Deduce the design block for the given Verilog code and draw the waveforms for the stimulus given:
module example(out, a, b, c); [Jul’17] 05
input a, b, c;
output out;
and #5 a1(e, a, b);
or #4 a2(out, e, c);
endmodule
module stimulus;
reg A, B, C;
wire OUT;
example ex1(OUT, A, B, C);
initial
begin

1
 A = 1’b0, B = 1’b0, C = 1’b0;
#10 A = 1’b1, B = 1’b1, C = 1’b1;
#10 A = 1’b1, B = 1’b0, C = 1’b0;
#20 $finish;
end
endmodule

14. Explain how ports are connected to external signals in Verilog description with an example pro-
gram definition. [Jun’18] 10

15. Design and implement 16:1 multiplexer using 4:1 multiplexer using Verilog. [Jun’17] 06

16. Design and implement 16:1 Multiplexer using two 8:1 MUX in Verilog HDL. [Jul’16] 08

17. Illustrate the components of simulation using 4 bit ripple carry adder as an example. [Jul’17] 08

Unit II
13. Design full-adder based 3-bit comparator using Verilog HDL gate-level modeling. [Jun’19] 07

14. Implement the 4×1 MUX using Verilog gate-level modeling. Also write the testbench. [Jul’19] 08

15. Write the Verilog gate level implementation of S-R flip flop. [May’16] 06

16. Develop a positive edge triggered D flip-flop using Verilog gate level Implementation. Also write
the test bench to test the code. [May’16] 08

17. Design and implement a full adder using Verilog HDL in the following design methodologies:
(a) Gate-level modeling
(b) Using two half-adders [Jul’16] 06

18. Implement edge triggered D flip-Flop by instantiating D-latch module. Write the code for the
D-latch using gate-level description. [Jul’19] 08

19. Design a 2-to-1 multiplexer using bufif0 and bufif1 gates as shown below. The delay specification
for gates b1 and b2 are as follows:

Write the verilog code and apply stimulus to test the output values. [Jun’16] 10

20. Implement the Verilog gate level description for the positive edge triggered D flip-flop. Also write
test bench. [May’18] 10

21. Design and implement the 2-to-4 decoder using gate-level description. Also write the simulation
block. [Jun’17] 06

2
22. Apply the concept of module instantiations in Verilog for a full subtractor using 2 half subtractors.
Use gate-level modeling for half subtractors. [Jul’17] 07

23. Using gate-level description style, write a Verilog HDL model for the following logic circuit shown
in Figure 1. Use the specified delays. Apply stimulus to test the output values. [Jun’19] 08

Figure 1: Question 23

24. Explain the Verilog gate primitives of inverter and buffer with symbol and truth table. [May’18] 04

25. Write the Verilog code and analyze effect of given gate delays with waveform for the module given
below in Figure 2. Write the test bench. [May’18] 06

a
#5
b
#4 out
c

Figure 2: Question 25

26. Design 4-bit ripple carry adder using top-down design methodology with stimulus. [Jun’18] 10

27. Illustrate the components of simulation using 4-bit ripple carry adder as an example. [Jul’17] 08

28. Briefly describe gate delays. [Aug’18] 05

29. Briefly explain different delays specified in Verilog code. [Jul’16, May’17] 05, 06

30. Identify the errors in the below given Verilog HDL code and write the correct code: [Jun’19] 06
module mult_array(a, b, P)
input [1:0] a, b;
output (3:0) P;
P[0] = a[0] & b[0];
assign P[1] = a[1] and b[1];
endmodule

31. Explain the following operators in Verilog HDL: [Jun’19] 06

(a) Logical Operators
(b) Concatenation Operator
(c) Bitwise Operators

32. Find the value of Y = ((&A) | (B>>2) | (A ˆ B)); if A = 1011 and B = 1111.
[Jun’16] 04

33. Find the value of Y = ((&A) | (B<<2) | (A | B)), if A = 1101 and B = 1001.
[May’18, Jul’19] 04

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34. Find the value of y, if y = ((A+B) && (|C)) + (A<<<2); A = 1101, B = 1010
and C = 0111. [May’16] 06

35. Find the value of y, if y = ((A ˆ B) && (∼ˆ C))+((A>>>3)|(C<<2)); A = 1101,

B = 1010 and C = 0111. [Jun’17] 06

36. Write the Verilog data flow description of RS latch with the stimulus for RS latch. [Aug’18] 07

37. Design a 2-bit unsigned multiplier using dataflow description. Assume 5 ns delay for each gate.
Determine the total delay for the output lines. [Jun’17] 08

38. Write a note on operator types in Verilog use necessary examples. [Aug’18] 08

39. Explain the different operator types in Verilog HDL. [May’17] 06

40. Explain equality operators with example. [Jun’18] 08

41. Explain concatenation and replication operator in Verilog HDL. [Jul’16] 06

42. Distinguish the following lexical conventions based on number of operands, type of operation and
results of operation: [Jul’17] 08
(a) Logical, Bitwise and Reduction operators
(b) Precedence of operators
(c) System tasks and compiler directives

43. Develop a dataflow description for the 3-bit parallel adder that has carry propagate and carry
generate block. Find the worst case delay if the propagation delay of each gate is 4 ns. Also write
the test bench to test the function of the adder. [May’18] 10

44. Design a 2-to-4 decoder using Verilog HDL data flow modeling. Consider an enable input to
activate the circuit. [Jun’19] 06

45. Model a D latch at gate-level and describe a flipflop from the developed D latch in dataflow model
by using the instance of D-Latch. [Jun’16] 10

46. Design and Implement a full subtractor using Verilog HDL: [May’17] 08
(a) Dataflow modeling
(b) Structural modeling

47. Design a logic system that has three 1-bit inputs: a1, a2 and a3; and 1-bit output b. The LSB bit
is a1; and b is one only when a1a2a3 = 1,3,6 and 7 (all in decimal), otherwise b is 0. Write the
Verilog data flow description to implement the design. [Jul’19] 08

48. Develop a verilog code for a 3 - bit ripple carry adder using data flow description. Calculate the
final delay for it, if 4ns delay is assumed for all gates. [May’16] 08

49. Write a program for a 4 to 1 multiplexer using [May’17] 08

(a) Dataflow modeling
(b) Conditional Operator

50. Develop a Verilog dataflow description to implement the following function that has five inputs
D0, D1, D2, S0 and S1; and one data output Y. The value of output Y is determined as follows:
Y = D0 if S0 = 0 and S1 = 0
Y = D1 if S0 = 1 and S1 = 0
Y = D2 if S1 = 1 (the value of S0 doesn’t matter)
Also write the testbench. [May’18] 06

4
51. Design and implement dataflow modeling of 4-bit ripple carry counter using T-Flip flop.
[Jul’16, May’17] 08, 06

52. Design a full subtractor which has 3, 1-bit inputs and 2, 1-bit output using data flow modeling and
verily the truth table by test bench code. [May’16] 08

53. Analyze the below given Verilog code, find the values s1 and s2 as per the timing units given in
table. [May’16, Jun’17, Jul’19] 04, 06
module ex(a, b, s1, s2);
input a, b;
output s1, s2;
assign #10 s1 = a ˆ b;
assign #10 s2 = a | s1;
endmodule
T=100 T=150 T=165 T=200 T=250 T=300
a 1 0 0 1 0 1
b 1 1 1 0 0 1
s1 0
s2 0

54. In the description below

module TEST1(A,B,C,G,Y);
input A,B,C,G;
output Y;
wire S1,S2,S3,S4,S5;
assign #7 Y = S4 | S5;
assign #7 S4 = A & S2 & S1;
assign #7 S5 = B & S3 & S1;
assign #7 S2 = ∼C;
assign #7 S3 = ∼S2;
assign #7 S1 = ∼G;
endmodule
Initial values of inputs are A=1, B=0, C=0 and G=0. If A changes from 1 to 0 and B changes from
0 to 1 at time T0. C changes from 0 to 1 at T1. G changes from 0 to 1 at T2. Given T0 = 100 ns,
T1 = 200 ns, T2 = 300 ns. Y will have changes @T0+∆1, T1+∆2, T2+∆3. Find ∆1, ∆2, ∆3 in
ns. [Jun’16] 10

55. Write Verilog code for a 4-bit shift register to perform shift left and shift right operation and also
write the stimulus. [Aug’18] 10

Unit III
56. Explain the three methods of timing control used in procedural statements with example.
[Jul’19] 10

57. Explain various timing control constructs that are available in Verilog HDL programming.
[Jun’19] 06

58. Explain the three types of delay modules used in Verilog. [May’18] 06

59. Explain delay-based timing control and event-based timing control Verilog constructs with exam-
ple. [Jun’17] 06

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60. An inhibited toggle Flip-Flop has inputs I0,I1,T and Reset, and outputs Q and QN. Reset is active
high and overrides the action of the other inputs. The Flip-Flop works as follows. If I0=1,the
Flip-Flop changes state on rising edge of T; if I1=1, the Flip- Flop changes state on the falling
edge of T. If I0=I1=0,no state change occurs (except on reset). Assume propagation delay from T
to output is 8 ns and from reset to output is 5 ns. Write the complete Verilog description of this
flip-flop. [Jul’16, May’18] 10, 08

61. Design a clock generator using forever statement with 20 ns time period and duty cycle of 75%.
Initial value of clock is 0. [Jul’19] 04

62. Design a clock generator using forever statement with 10 ns time period and duty cycle of 75%.
Initial value of clock is 0. [May’18] 06

63. Explain clock generation using forever loop. [Aug’18] 04

64. Implement a clock generator in Verilog with time period 40 ns and a duty cycle of 25% by using
always and initial statements. The value of clock at 0 ns time should be initialized to zero.
[Jun’17] 06

65. Explain the Verilog loop statements with example. [Jul’19] 05

66. Give Verilog HDL program examples for the following Verilog constructs: [Jun’19] 06
(a) for loop
(b) while loop
(c) repeat

67. Distinguish between all the looping statements in Verilog with examples. [Jul’17] 08

68. Explain blocking and non-blocking assignments with example statements. [Jun’16, Jun’17] 04, 05

69. Following Verilog code contains statements with nested blocks. Analyze: [May’18] 06
(a) When does the block finish?
(b) What is the order of execution of events?
(c) At what simulation times does each statement finish execution?

initial
begin
x = 1’b0;
#5 y = 1’b1;
fork
#20 a = x;
#15 b = y;
join
#40 x = 1’b1;
fork
#10 p = x;
begin
#10 a = y;
#30 b = x;
end
#5 m = y;
join
end

6
70. Below is a block with nested sequential and parallel blocks. When does the block finish and what
is the order of execution of events? At what simulation time does each statement finish execution?
always [Jun’19] 08
begin
#4 Dry = 5;
fork
#6 Cun = 7;
begin
Exe = Box;
#5 Jap = Exe;
end
#2 Dop = 3;
#4 Gos = 2;
#8 Pas = 4;
join
#8 Bax = 1;
#2 Zoom = 52;
#6 $stop;
end

71. How does Casex statement differ from the Casez statement? Explain with the help of an example.
[Jul’17] 08

72. Discuss the Verilog case statements with syntax. Apply the concept of Verilog case on output Q
for a JK flip-flop to describe its behavior. Write the stimulus to test the code. [Jun’17] 10

73. Design a 4-bit up/down counter with synchronous reset using Verilog behavioral modeling.
[Jun’19] 06

74. Design an 8-bit counter by using a forever loop, named block, and disabling of named block. The
counter starts counting at count = 4 and finishes at count = 60. The count is incremented at positive
edge of clock. The clock has a time period of 10. The counter counts through the loop only once
and then is disabled. [Jul’16] 10

75. Develop a Verilog code to implement the logic encoder that assigns a highest priority to LSB bit
using suitable case statement. Also write the test code. [Jun’16] 10

76. Develop an 8-bit counter by using a forever loop, named block, and disabling of named block.
The counter starts counting at count = 5 and finishes at count = 67. The count is incremented at
positive edge of clock. The clock has a time period of 10. The counter counts through the loop
only once and then is disabled. [Jun’17] 08

77. Find the values of variables in the following examples: [Jul’17] 06

(a) always @(posedge clk)
y1 <= in;
always @(posedge clk)
y2 <= y1;
(b) always
begin
a =3; a = 4; a = 5; b = a; #5; end

78. Given below is an initial block with blocking procedural assignments. At what simulation
time each statement is executed? What are the intermediate and final values of a, b, c, d and e if

7
 a = 0, b = 1, c = 0 and d = 1 at time t = 0. [Aug’18] 06
initial
begin
a = 1’b0;
b = #20 1’b0;
c = #15 1’b1;
d = #30 1’b0;
e = #35 {a, b, c, d};
end

79. Write an RTL code for a 4 bit adder. [Jul’17] 06

80. Implement a positive edge triggered JK flip-flop using if-else-if statement. [Jul’19] 05

81. Write a Verilog HDL program for positive edge triggered JK flipflop using case statements and
apply stimulus to test the same. [Jun’19] 06

82. Develop a 4×1 multiplexer using if-else statements. [May’16] 05

83. Explain repeat loop and forever loop with example. [Jun’18] 06

84. Explain sequential block and parallel block with example. [Jun’18] 06

85. Explain the conditional statements and loop statements with an example. [May’17] 06

86. Explain the generate blocks with an example to each. [May’17] 06

87. Write a Verilog code for a 4-bit priority encoder using casex behavioral statement. [May’16] 05

88. Write a Verilog code for 8:3 priority encoder using casex statement. [May’17] 08

89. Develop a traffic signal controller using Verilog behavioral description. [May’16] 10

90. Implement serial-in parallel-out right shift register triggered by the positive edge of clock. Write
the stimulus to test the functioning. [May’18] 07

91. Construct a 4 bit parallel adder using generate block. [Jul’17] 06

92. Write Verilog code for 1-bit full adder/subtractor. Design a 3-bit binary subtractor using 1-bit full
adders and generate construct. [May’17] 08

93. Develop the logic diagram that takes two N-bit inputs for comparison using adders and logic gates
and implement by using the concept of verilog generate statement. [Jul’19] 10

94. Write a Verilog code to implement N-bit adder using a generate case block. [Aug’18] 07
Hint Q94 : Use CLA
95. Design an N-bit asynchronous down counter with JK flip-flop using generate statement. Also test
the function of the design using test bench. [May’18] 08

96. Design an 8-function ALU that takes 4-bit input signals A, B and 3-bit input signal select. [Jun’18] 08

97. Develop a signed binary to integer converter using a Verilog task. [Jul’19] 06

98. Explain $setup , $hold and $width tasks with syntax. [Jul’16] 06

99. Develop a signed binary to integer converter using a Verilog task. [Jun’16] 06

100. Design 4:1 multiplexer with stimulus using Verilog task in behavioral description. [Jun’18] 08

8
101. Define task called bitwise oper, which computes the bitwise and, bitwise or, and bitwise ex-or
of two 16-bit numbers. The two 16-bit numbers a and b are inputs and the three outputs are 16-bit
numbers ab and, ab or and ab xor. [Aug’18] 07

102. Compare task and function. [May’17] 04

103. List any four difference between Verilog task and Verilog function. [Jun’18] 04

104. Distinguish between tasks and functions. [May’18] 05

105. List the limitations of functions over task in Verilog HDL programming. Write a program to
determine factorial of a number using function. [Jun’19] 08

106. Write a Verilog function to find greatest of two signed numbers. [Aug’18] 06

107. Define a recursive function. Write a Verilog description to calculate the factorial of a 4-bit number
using recursive function. [Jun’18] 08

108. Construct an automatic function to find the sum of squares of ‘n’ natural numbers. [Jul’17] 06

109. Develop a Verilog function to find the factorial of a number. [Jun’17] 05

110. Analyze the below given function fn, complete the Verilog code and write the logic circuit.
function ...fn; [May’18] 08
.........
.........
begin
if (a <= 4)
fn = 2*a + 5;
end
endfunction

111. Bring out the differences between the following: [May’17] 08

(a) casex and casez
(b) initial and always
(c) Blocking and Non-blocking
(d) Automatic function and Constant Function

Unit IV
112. Construct a flow graph for computer aided Logic Synthesis process. Explain briefly.
[May’16, Jul’17] 06, 07

113. Explain the synthesis design flow from RTL to gates. [Jun’18] 10

114. What is Logic synthesis? Explain the typical steps of RTL to Gates logic synthesis flow.
[Jun’16, May’17] 08, 07

115. With flow diagram, explain the RTL to gate level logic synthesis flow. [Jul’19] 09

116. Explain how the ‘if’ statement can be synthesized. Give an example for with and without storage.
[Jun’16] 04

117. Explain how logic synthesis tools interpret the following Verilog constructs: [Jun’18] 06

9
 (a) assign (b) if-else (c) case

118. Write a short note on synthesizable Verilog constructs. [Aug’18] 04

119. Classify ‘Synthesizable’ Verilog constructs and ‘Simulatable’ constructs. [Jul’17, Jun’19] 07, 06

120. Give the logic synthesis of the following: [May’17] 06

(a) if (a)
y = m;
else
y = n;
(b) always @(posedge clk)
y <= a;

121. Analyze the below given code, Write the complete Verilog code and Synthesized logic circuit.
always @(inp) [May’16] 08
begin
if (inp[0] == 1’b1)
outp = 3’d7;
else if (inp[1] == 1’b1)
outp = 3’d6;
else if (inp[2] == 1’b1)
outp = 3’d5;
else
outp = 3’d0;
end

122. Analyze the below given code, write the complete Verilog code and Synthesized logic circuit.
always @(a, c) [Jul’19] 11
begin
for (i=0; i<=3; i=i+1)
begin
if (a[i] == 1)
result = result + 2**i;
end
if (result > c)
begin
for (i=0; i<=3; i=i+1)
begin
j = (i + 2) % 4;
b[j] = a[i];
end
end
else
begin
for (i=0; i<=3; i=i+1)
begin
j = (i + 1) % 4;
b[j] = a[i];
end
end
end

10
123. Analyze the function fn given below. Complete the Verilog code and write the logic circuit.
function fn; [May’18] 08
.........
begin
if (a <= 4)
fn = 2*a + 5;
end
endfunction

124. Analyze the below given code, write the synthesized logic circuit. [May’18] 06
module Ex(a, b, ct, d);
input [3:0] a, b;
input ct;
output [4:0] d;
reg [4:0] d;
always @(a, b, ct)
begin
case(ct)
1’b0: d = a + b;
1’b1: d = a - b;
endcase
end
endmodule

125. Write the complete code and synthesized logic diagram for the below given code. [Jul’16] 06
always @ (a, b, ct)
begin
case (ct)
1’b0: d = a + b;
1’b1: ;
endcase
end

126. Analyze the below given code, write the complete Verilog code and Synthesized logic circuit.
always @ (a, c) [Jun’17] 10
begin
for (i=0; i<=3; i=i+1)
begin
if(a[i] = =1)
result= result + 2**i;
end
if (result > c)
begin
for (i=0; i<=3; i=i+1)
begin
j = (i + 2) % 4;
b[j] = a[i];
end
end
else
begin
for (i=0; i<=3; i=i+1)

11
 begin
j = (i + 1) % 4;
b[j] = a[i];
end
end
end

127. Write the complete code and synthesized logic diagram from the code given below: [Jun’19] 08
always @(PB)
begin
if (PB <= 2)
HD = 15;
else if (PB <= 5)
HD = 0;
else
HD = PB*(-5) + 25;
end

128. Write the complete code and synthesized logic diagram for the below given code. [Jul’16] 08
function [3:0] fn;
input [2:0] x;
begin
if (x <= 4)
fn = 2*x+5;
end
endfunction

129. Explain horizontal and vertical partitioning with an example. [Jun’17, Jun’19] 06

130. Write a note on horizontal and vertical partitioning. [Aug’18] 06

Unit V
131. Explain a Mealy FSM with an example. Mention the state transition diagram for it. [May’17] 10

132. Differentiate Moore and Mealy type FSMs. [Jul’17] 10

133. With a neat block diagram, explain Mealy and Moore model. [Jun’16] 06

134. Explain One-Hot encoding in FSM designing. [Jun’16] 04

135. Design a Moore-type FSM in Verilog to detect the sequence 110. [Jun’19] 12

136. Design a Mealy circuit to detect an overlapping sequence of 1011 in Verilog. [May’18] 10

137. Design a Moore type FSM for the following: For a serial single-bit input, if two 1’s or two 0’s
comes one after another, output should go high. Otherwise output should be low. [Jul’17] 10

138. Develop a FSM that has input w and output z. The machine is a sequence detector that produces
z=1 when the previous two values of w were 00 or 11; otherwise z=0 and implement using Verilog
HDL. [Jun’16] 10

139. Design a clocked synchronous sequential circuit which detects the following sequence 0110 using
D-flip-flop and implement using Verilog HDL. [Jun’16] 10

12
140. Develop Verilog Mealy-type FSM that detects 110 and 101 (with overlaps) and sets output Z=1.
[Jul’19] 10

141. Design a synchronous sequential circuit that meets the following specifications using D-flip flop
and one-hot encoding. Write the code for the FSM is Verilog. [Jul’16, Jun’17] 14, 12
(a) The circuit has one input w and one output z.
(b) All changes in the circuit occur on the positive edge of a clock signal.
(c) The output z is equal to 1 if during two immediately preceding clock cycles the input w was
equal to 1. Otherwise, the value of z is equal to 0.

142. Develop a Verilog mealy sequence detector for the following specifications. [May’16] 08
(a) The circuit has one input w and one output z.
(b) All changes in the circuit occur on the positive edge of a clock signal.
(c) The output z is equal to 1 if during two immediately preceding clock cycles the input w was
equal to 1. Otherwise, the value of z is equal to 0.

143. Explain the Moore-type FSM with state diagram and circuit diagram to design serial adder.
[Jun’18] 10

144. Explain the Mealy-type FSM with state diagram and circuit diagram to design serial adder.
[Jun’18] 10

145. Design serial adder using Moore machine. Write state diagram, transition excitation table and
logic realization for the same. [May’17] 10

146. Design a serial binary adder as a Mealy network with D-flip flop and implement using Verilog
HDL. [Jun’16] 10

147. Develop a Moore type FSM for the serial adder and implement using Verilog code.
[Jul’16, Aug’18] 10

148. Develop a BCD to excess-3 code converter using state diagram and Verilog programming.
[Jun’17, May’18, Aug’18] 08, 10, 10

149. Design a Verilog Mealy-type BCD to Ex-3 code convertor. [May’16, Jul’19] 10

150. Design a counter that counts 0,2,3,5,7,0 with D Flipflop using FSM and hence describe using
Verilog HDL. [May’16] 12

151. Apply the concept of FSM, design a 3-bit counter that counts 0, 2, 7, 5, 0 with T-flip flop and hence
describe using Verilog HDL. [Jul’16] 10

152. Design an FSM to swap the contents of registers R1 and R2 using temporary register R3 . Control
signals for the process are as follows: [Jun’19] 08
R2out = 1 and R3in = 1 Contents of R2 are loaded into R3
R1out = 1 and R2in = 1 Contents of R1 are loaded into R2
R3out = 1 and R1in = 1 Contents of R3 are loaded into R1
Done = 1 Swap task is completed

153. Write a verilog code for the state diagram shown in Figure 3. [May’16] 10

154. Write the Verilog code for the state diagram shown in Figure 4. [Jul’16] 06

13
 w=0 w=0 w=0 w=0

w=1 w=1 w=1

A/0 B/1 C/2 D/3

w=1 w=1

H/7 G/6 F/5 E/4

w=1 w=1 w=1

w=0 w=0 w=0 w=0

Figure 3: Question 153

0 0 0

1 1
0 1 2

1 1

5 4 3
1 1

0 0 0

Figure 4: Question 154

14