NUP4202W1

ESD Protection Diode, Low

Clamping Voltage
The NUP4202W1 surge protection is designed to protect high speed
data lines from ESD, EFT, and lightning.

Features www.onsemi.com
• Low Clamping Voltage
• Stand−Off Voltage: 5 V SC−88 LOW CAPACITANCE
• Low Leakage DIODE SURGE PROTECTION
• Protection for the Following IEC Standards: ARRAY
IEC 61000−4−2 Level 4 ESD Protection 500 WATTS PEAK POWER
• UL Flammability Rating of 94 V−0 6 VOLTS
• This is a Pb−Free Device
PIN CONFIGURATION
Typical Applications AND SCHEMATIC
• High Speed Communication Line Protection
• USB 1.1 and 2.0 Power and Data Line Protection I/O 1 6 I/O
• Digital Video Interface (DVI) and HDMI
• Monitors and Flat Panel Displays VN 2 5 VP
• MP3
I/O 3 4 I/O
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Peak Power Dissipation Ppk 500 W
8 x 20 mS @ TA = 25°C (Note 1)
1
Operating Junction Temperature Range TJ −40 to +125 °C
SC−88
Storage Temperature Range Tstg −55 to +150 °C CASE 419B
PLASTIC
Lead Solder Temperature − TL 260 °C
Maximum (10 Seconds)
MARKING DIAGRAM
Human Body Model (HBM) ESD 16000 V
Machine Model (MM) 400 6
IEC 61000−4−2 Air (ESD) 20000
IEC 61000−4−2 Contact (ESD) 20000 63 MG
G
IEC 61000−4−4 (5/50 ns) EFT 40 A
Stresses exceeding those listed in the Maximum Ratings table may damage the 1
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected. 63 = Specific Device Code
1. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2). M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)

See Application Note AND8308/D for further description of

survivability specs. ORDERING INFORMATION

Device Package Shipping

NUP4202W1T2G SC−88 3000/Tape & Reel

(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

October, 2017 − Rev. 4 NUP4202W1/D
 NUP4202W1

ELECTRICAL CHARACTERISTICS I
(TA = 25°C unless otherwise noted)
IF
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VC Clamping Voltage @ IPP
VRWM Working Peak Reverse Voltage VC VBR VRWM
V
IR Maximum Reverse Leakage Current @ VRWM IR VF
IT
VBR Breakdown Voltage @ IT
IT Test Current
IF Forward Current
IPP
VF Forward Voltage @ IF
Ppk Peak Power Dissipation
C Capacitance @ VR = 0 and f = 1.0 MHz Uni−Directional
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.

ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM (Note 2) 5.0 V
Breakdown Voltage VBR IT = 1 mA, (Note 3) 6.0 V
Reverse Leakage Current IR VRWM = 5 V 5.0 mA
Clamping Voltage VC IPP = 5 A (Note 4) 8.5 12.5 V
Clamping Voltage VC IPP = 8 A (Note 4) 8.9 20 V
Maximum Peak Pulse Current IPP 8x20 ms Waveform (Note 4) 28 A
Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 3.0 5.0 pF
Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins 1.5 3.0 pF
Clamping Voltage VC @ IPP = 1 A (Notes 5 and 6) 14.5 V
Clamping Voltage VC Per IEC 61000−4−2 (Note 7) Figure 1 and 2 V
2. Rurge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater
than the DC or continuous peak operating voltage level.
3. VBR is measured at pulse test current IT.
4. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2).
5. Nonrepetitive current pulse per Figure 5 (Any I/O Pins).
6. Surge current waveform per Figure 5.
7. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Figure 1. ESD Clamping Voltage Screenshot Figure 2. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2 Negative 8 kV Contact per IEC61000−4−2

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 NUP4202W1

IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
First Peak
Test Volt- Current Current at Current at 100%
Level age (kV) (A) 30 ns (A) 60 ns (A) 90%
1 2 7.5 4 2
2 4 15 8 4 I @ 30 ns
3 6 22.5 12 6
4 8 30 16 8 I @ 60 ns

10%

tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

ESD Gun Oscilloscope

50 W
Cable 50 W

Figure 4. Diagram of ESD Test Setup

The following is taken from Application Note systems such as cell phones or laptop computers it is not
AND8308/D − Interpretation of Datasheet Parameters clearly defined in the spec how to specify a clamping voltage
for ESD Devices. at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the protection diode over the time domain of an ESD pulse in the
voltage that an IC will be exposed to during an ESD event form of an oscilloscope screenshot, which can be found on
to as low a voltage as possible. The ESD clamping voltage the datasheets for all ESD protection diodes. For more
is the voltage drop across the ESD protection diode during information on how ON Semiconductor creates these
an ESD event per the IEC61000−4−2 waveform. Since the screenshots and how to interpret them please refer to
IEC61000−4−2 was written as a pass/fail spec for larger AND8307/D.

100
tr PEAK VALUE IRSM @ 8 ms
90
% OF PEAK PULSE CURRENT

80 PULSE WIDTH (tP) IS DEFINED

AS THAT POINT WHERE THE
70 PEAK CURRENT DECAY = 8 ms
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0 20 40 60 80
t, TIME (ms)
Figure 5. 8 X 20 ms Pulse Waveform

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 NUP4202W1

TYPICAL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

100

PEAK POWER DISSIPATION (%)

90
80
70
60
50
40
30
20
10
0
0 25 50 75 100 125 150 175 200
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Pulse Derating Curve

5.0 20
4.5 18
JUNCTION CAPACITANCE (pF)

4.0 16
CLAMPING VOLTAGE (V)

3.5 14
3.0 I/O−Ground 12
2.5 10
2.0 8
1.5 I/O lines 6
1.0 4
0.5 2
0.0 0
0 1 2 3 4 5 0 10 20 30 40 50
VBR, REVERSE VOLTAGE (V) PEAK PULSE CURRENT (A)
Figure 7. Junction Capacitance vs Reverse Voltage Figure 8. Clamping Voltage vs. Peak Pulse Current
(8 x 20 ms Waveform)

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 NUP4202W1

APPLICATIONS INFORMATION

The new NUP4202W1 is a low capacitance surge Option 2

protection diode array designed to protect sensitive Protection of four data lines with bias and power supply
electronics such as communications systems, computers, isolation resistor.
and computer peripherals against damage due to ESD events
or transient overvoltage conditions. Because of its low I/O 1
capacitance, it can be used in high speed I/O data lines. The I/O 2
integrated design of the NUP4202W1 offers surge rated, low VCC
capacitance steering diodes and a surge protection diode 1 6
integrated in a single package (SC−88). If a transient 10 k
condition occurs, the steering diodes will drive the transient 2 5
to the positive rail of the power supply or to ground. The
surge protection device protects the power line against 3 4
overvoltage conditions to avoid damage to the power supply
and any downstream components. I/O 3
I/O 4
NUP4202W1 Configuration Options
The NUP4202W1 is able to protect up to four data lines The NUP4202W1 can be isolated from the power supply
against transient overvoltage conditions by driving them to by connecting a series resistor between pin 5 and VCC. A
a fixed reference point for clamping purposes. The steering 10 kW resistor is recommended for this application. This
diodes will be forward biased whenever the voltage on the will maintain a bias on the internal surge protection and
protected line exceeds the reference voltage (Vf or VCC + steering diodes, reducing their capacitance.
Vf). The diodes will force the transient current to bypass the
sensitive circuit. Option 3
Data lines are connected at pins 1, 3, 4 and 6. The negative Protection of four data lines using the internal surge
reference is connected at pin 2. This pin must be connected protection diode as reference.
directly to ground by using a ground plane to minimize the
I/O 1
PCB’s ground inductance. It is very important to reduce the
I/O 2
PCB trace lengths as much as possible to minimize parasitic
inductances.
1 6
Option 1
Protection of four data lines and the power supply using 2 5 NC
VCC as reference.
3 4
I/O 1
I/O 2 I/O 3
I/O 4

1 6 In applications lacking a positive supply reference or

those cases in which a fully isolated power supply is
2 5 VCC required, the internal surge protection can be used as the
reference. For these applications, pin 5 is not connected. In
3 4 this configuration, the steering diodes will conduct
I/O 3
whenever the voltage on the protected line exceeds the
working voltage of the surge protection plus one diode drop
I/O 4
(Vc = Vf + VRWM).
For this configuration, connect pin 5 directly to the
positive supply rail (VCC), the data lines are referenced to ESD Protection of Power Supply Lines
the supply voltage. The internal surge protection diode When using diodes for data line protection, referencing to
prevents overvoltage on the supply rail. Biasing of the a supply rail provides advantages. Biasing the diodes
steering diodes reduces their capacitance. reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:

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 NUP4202W1

Power
Even with good board layout, some disadvantages are still
Supply IESDpos present when discrete diodes are used to suppress ESD
VCC events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
D1 IESDpos therefore higher capacitance. This capacitance becomes
Protected Data Line IESDneg problematic as transmission frequencies increase. Reducing
Device capacitance generally requires reducing die size. These
D2
small die will have higher forward voltage characteristics at
IESDneg VF + VCC typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.
−VF
The ON Semiconductor NUP4202W1 was developed to
Looking at the figure above, it can be seen that when a overcome the disadvantages encountered when using
positive ESD condition occurs, diode D1 will be forward discrete diodes for ESD protection. This device integrates a
biased while diode D2 will be forward biased when a surge protection diode within a network of steering diodes.
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:
D1 D3 D5 D7
For positive pulse conditions:
Vc = VCC + VfD1
For negative pulse conditions:
Vc = −VfD2 D2 D4 D6 D8
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.
0
Power Figure 9. NUP4202W1 Equivalent Circuit
Supply IESDpos
During an ESD condition, the ESD current will be driven
VCC
to ground through the surge protection diode as shown
D1 IESDpos below.
Protected IESDneg
Device
Data Line
Power
D2 VC = VCC + Vf + (L diESD/dt) Supply
IESDneg
VCC

D1 IESDpos

VC = −Vf − (L diESD/dt) Protected

An approximation of the clamping voltage for these fast Device
Data Line
transients would be: D2
For positive pulse conditions:
Vc = VCC + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = −Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not The resulting clamping voltage on the protected IC will
only depends on the Vf of the steering diodes but also on the be:
L diESD/dt factor. A relatively small trace inductance can Vc = VF + VRWM.
result in hundreds of volts appearing on the supply rail. This The clamping voltage of the surge protection diode is
endangers both the power supply and anything attached to provided in Figure 8 and depends on the magnitude of the
that rail. This highlights the importance of good board ESD current. The steering diodes are fast switching devices
layout. Taking care to minimize the effects of parasitic with unique forward voltage and low capacitance
inductance will provide significant benefits in transient characteristics.
immunity.

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 NUP4202W1

TYPICAL APPLICATIONS

UPSTREAM
USB PORT

VBUS
VBUS
VBUS
RT VBUS
D+ D+
RT DOWNSTREAM
D− D− USB PORT
VBUS USB VBUS
GND Controller NUP4202W1
GND
CT CT

VBUS

VBUS
NUP2202W1 RT
D+ DOWNSTREAM
RT USB PORT
D−
GND
CT CT

Figure 10. ESD Protection for USB Port

RJ45
Connector

TX+ TX+

TX−
TX−
Coupling
PHY Transformers
Ethernet RX+
RX+
(10/100)

RX−

RX−

NUP4202W1
VCC

GND
N/C N/C

Figure 11. Protection for Ethernet 10/100 (Differential Mode)

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 NUP4202W1

R1
RTIP

R3
R2
RRING
T1
VCC

T1/E1
TRANCEIVER
NUP4202W1

R4
TTIP

R5
TRING
T2

Figure 12. TI/E1 Interface Protection

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 NUP4202W1

PACKAGE DIMENSIONS

SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE W
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
D 2. CONTROLLING DIMENSION: INCH.
3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.
e
MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
A 0.80 0.95 1.10 0.031 0.037 0.043
A1 0.00 0.05 0.10 0.000 0.002 0.004
6 5 4 A3 0.20 REF 0.008 REF
b 0.10 0.21 0.30 0.004 0.008 0.012
HE −E− C 0.10 0.14 0.25 0.004 0.005 0.010
D 1.80 2.00 2.20 0.070 0.078 0.086
1 2 3 E 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 BSC 0.026 BSC
L 0.10 0.20 0.30 0.004 0.008 0.012
HE 2.00 2.10 2.20 0.078 0.082 0.086
b 6 PL
0.2 (0.008) M E M

SOLDERING FOOTPRINT*
A3
0.50
C 0.0197
A

A1 L
0.65
0.025

0.65
0.025
0.40
0.0157

1.9
0.0748
SCALE 20:1 ǒinches
mm Ǔ

SC−88/SC70−6/SOT−363
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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