CADENCE TUTORIAL

Written by Shawn Chen for EGCP 4250 CMOS VLSI Design

APRIL 2, 2019
CEDARVILLE UNIVERSITY
School of Engineering and Computer Science
This is a tutorial for EGCP 4250 CMOS VLSI:

Start Xming, and then start Putty, enable X11 and connect to barnabas.cedarville.edu. Login with your
user name and password.

Once you login, you should be in your home directory, you may double check using “pwd” command.

Type “virtuoso&” to start Cadence.

Once Cadence is started, go to Tools-> Library Manager, you shall see a window like this:

Go to File->New -> Library, this will be a new library you create, you may choose your own name here,
for example, you want to name it Lab4250, click OK, a window will pop up, choose “Attach to an existing
technology library”,

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Choose “gpdk045”, this is the general purpose design kit from Cadence, click OK.

Go back to Library Manager, now you should be able to see “Lab4250” in the library list. Click on
“Lab4250”, and then go to File-> New -> Cell View:

We will create a cell view called “inverter”, make sure the library chosen here is Lab4250:

Click OK.

A Virtuoso Schematic Editor window will pop up, this is one of the schematic editors of Cadence, we will
use this one as the schematic editor for our lab. This is similar to the LT-Spice, with which you are
familiar.

Next, we will start editing the schematic of an inverter. Press “i” on keyboard, or click on “Create
Instance” from the Virtuoso Schematic Editor as shown below:

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Both ways should work.

In the “Add Instance” window, choose the library to be “gpdk045”, cell to be nmos1v_3”, and view
should be “symbol”. Leave the “Names” blank as it is.

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Set the width and length properly. Click on “ Hide” and you shall see an NMOS following your mouse
now, click wherever you want to place it. Add PMOS using the same way.

You can scroll your mouse to zoon in and zoom out.

Click on “Create Narrow Wire” and connect the NMOS and PMOS and build an inverter circuit. Please
note, when you wire two terminals, click and release on the terminal where you want to start, then click
and release on the second terminal you want to end. Or simply click and release anywhere and click and
release at a different spot and hit “Enter”, you can draw a wire.

Connec the NMOS and PMOS in this way:

Any time if you want the circuit to automatically Zoom in or Zoom out so it can fit the design space you
have, press “f”.

Next, we will add input and output pins in the schematic, click “Create Pin” .

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First create an input pin called “In”, make sure the direction is set to be input, type name “In”,

Click “Hide”, place the pin to the input wire of the inverter. Similarly , create an output pin called “Out”,
remember to set the direction to be output for this pin, the circuit should look like this：

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We also need to add vdd and gnd for this circuit. Click on “Create Wire Name”:

First create “gnd!” by typing “gnd!” in “Names”, “!” means this is a global ground, everything named
“gnd!” is automatically connected.

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Click on the wire for ground and “gnd!” shall be marked on the wire. Do the same to name the vdd wire,
and this is how the circuit should look like:

Till now, the circuit of an inverter is finished.

Next step will be creating a symbol for this circuit.

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Go to Create-> Cellview -> From Cellview, in the pop up window, keep everything as default, note that
the library and cell name should be exactly the same with the inverter cellview you just created. Click Ok
and another window pops up.

We are creating a symbol now, This window shows the location of the pins in the symbol you are going
to create. The default one is pin “In” on the left, and pin “Out” on the right, you may change it if you
want, however you can not change the names of the pins. They have to be exactly the same with the pin
names in the schematic you just draw and they are case sensitive.

Click Ok and the Virtuoso Symbol Editor window pops up. You may leave the pins and delete the rest:

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You can choose from the top of the symbol editor to draw lines and circles and make a symbol as shown
below:

Save it and close the symbol editor window. You just create a symbol for the inverter schematic. You
should be able to see it now in the library manager.

Next, we will simulate the inverter we just created.

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Create a new cellview by File-> New-> Cell View in Library Manager, you can name it “inverter_tb”.

Click OK, and a schematic editor will pop up, add instance by press “i”, choose inverter in library
“Lab4250”:

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This is the symbol of the inverter we just created. Click on the symbol and press “e” and choose click OK,
you can descend your view one level lower, which will be the inverter circuit. Press “Ctrl+e” you can go
up one level.

Now we will add power and signal to this inverter. Press “i”, choose “vdc” from library “analoglib”, set
DC voltage to be 1 v,

Click “Hide”, place it next to the inverter, also add “vdd”, “gnd”, and “vpulse” and connect the circuit as
shown below:

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Click on the “vpulse” symbol and press “q” on the keyboard. You can use “q” any time during your
design and it will show the properties of an instance. Set the parameters of “vpulse” as below:

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Add output pin named “Y” to the inverter output. The finished circuit looks like this:

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Next, we will start the simulator by Launch-> ADEL,

In the ADE window, go to Setup->Model Libraries, make sure the gpdk045.scs file is selected, this file
includes all the mathematic models of instances.

Go to Analyses-> Choose, choose “tran” to do a transient analysis, set the stop time to be 4n, and select
“Enabled”,

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Click “OK” and then click “Netlist and Run” in the ADE window,

Wait till simulation is done. Go to Results-> Direct Plot -> Main Form, choose “tran” and “Voltage” in the
pop up window,

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Keep this window open and switch to the inverter_tb schematic window, choose to plot the voltage by
clicking on the corresponding wires. Suppose we want to plot the input and output of the inverter, click
on the input wire first and input wave form will be plotted, do the same on the output wire and output
waveform will be plotted.

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In the plot window, go to Graph-> Split All Strips, you can separate the input plot from the output plot,

Next, we want to calculate the rise and fall time of the inverter output. Click on the output plot which is
the purple one in my case, the plot will become bold, click on the calculator symbol,

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The calculator should pop up,

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Clip the output waveform so that we are only looking at the section of interest. This helps to avoid
sections of waveforms that are still settling and not stable. Find the function panel at the bottom of the
calculator window, search for the clip function, and this is how you should set the clip function and click
OK after setting it properly:

To calculate rise time, search for a function called “ riseTime” in the function panel and set the riseTime

function and click OK, click Evaluate to calculate the result as shown below.

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Do the same to calculate the fall time using “fallTime” function.

As a practice, also calculate the rise and fall time of input signal.

Now we will calculate the propagation delay of the inverter. We will calculate the delay from the mid

point of the input waveform to the midpoint of the output waveform.

Close all calculator windows. Find the waveform plot window (Virtuoso Visualization & Analysis XL), click
on output plot and then press “ctrl” and click on input waveform, both waveform should be selected
and be bold now, start the calculator, and find “delay” function from function panel and this is how you
should set it:

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Click “Evaluate” to calculate the result.

Next, we will calculate power consumption of this inverter.

Go to ADE window, choose Outputs-> To Be Plotted -> Select on Design, in the schematic window, click
on the positive node (not wire) of dc power supply, and it will be circled once selected, “V0/PLUS” will
also be shown in the output section in ADE window. Then click on the wire connecting to that node, vdd!
will be shown in the output section in ADE window. Please note that you need to select a node in order
to plot the current and a wire in order to plot voltage. Also select “save” option for both. The schematic
window shall look like this once all is set:

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We will also choose to save all the voltage and current information all nodes in the schematic, go to
Outputs-> Save All, check the save options shown below and click OK:

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Also go to Outputs -> To Be Plotted ->Select on Design, click on the Vdc node for current and wire for
voltage, once you click on the node, it should be circled.

This is how the ADE window looks like:

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Start the simulation and both the current and voltage of the dc power supply will be plotted in a popup
window. The popup window looks like this:

To calculate the power, select both by clicking on the first one and pressing “ctrl” and clicking on the
second one. Start calculator, power should be voltage times current. You can do this easily by click on
the multiply symbol in the calculator.

This will be the instant power of the inverter, to calculate the total power in one period we still need to
use a function called “Integ”, this is how to set the function:

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Click OK and then start the evaluation and the power shall be calculated.

To calculate average power, you can just use the equation to calculate total power divided by 2n which
is the period.

We have talked about creating a schematic and simulation of it. Next, we will work on the layout.

Go to Library Manager, File -> New -> Cell View, create a layout view of an inverter by typing “layout” for
view,

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Press OK and the layout editor window (Virtuoso Layout Suite L) shall pop up, add NMOS and PMOS into
the editor by pressing “i”, the NMOS and PMOS you choose including their names and sizes should be
exactly the same with the ones in your inverter schematic. It may look like this when NMOS and PMOS
are initially added into the layout editor:

Press “shift+f” and it shall show the actual layout of NMOS and PMOS, read carefully to see whether you
can recognize the different layers in them.

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We will now start PVS which is the design check software for layout. We will do a design rule check
(DRC) to makes sure our design does not violate any design rules. It’s generally a good habit to start the
DRC right at the beginning at the design so you can find the design rule violations and correct them as
you continue your design.

To start DRC check, in layout editor, go to PVS -> Run DRC, first you need to set your “Run Directory”, set
it as below:

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You may choose to run the DRC check by multiple CPUS if you want, it can substantially increase the
check speed for a large layout. For this layout we are checking, it makes no big difference.

You need to manually set the path for the “Technology mapping file” as shown below, once you set it,
you can choose the technology from the dropdown menu.

Click “Submit” and the DRC result viewer window will pop up once it’s done. The design rule violations
or also called DRC errors are listed in the viewer. Click on one of it and all DRC errors of this same type
will be listed on the right part of the viewer. Click on one of it and detailed information will be shown
below in the viewer and also marked in the layout in the layout editor.

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Next we will connect the gate of the NMOS and PMOS, to draw a wire in the layout editor, you need to
choose the layer by clicking on the layer listed on the left side of the layout editor, choose “Poly drw”,
press “r” to draw a rectangular wire. Also use “Metal1 drw” to connect the output of the inverter,

Extend the gate polysilicon a little bit and add a “M1_PO” via and place it on the gate, as shown below:

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Run DRC one more time. As you can see, there are a lot of errors related with latchup and nwell, that is
because we do not have the PMOS source connect to NWELL and NMOS source connect to P-substrate.
We will do that now. Press “o”, and choose via “M1_NWELL”, 1 row, 2 columns. Connect the
“M1_NWELL” via with the source of the PMOS and save it,

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Run DRC one more time, if there are new DRC errors, read through the information, the most two
common ones are the minimum distance between two layers is too short and the minimum area of a
layer is too small. You just need to increase the space between them or increase the area. For your
convenience, if you want to only show a certain layer and make the rest invisible, you can click on the
layer you want to show and then click NV which is shown below:

Do not be discouraged if there are too many DRC errors, it’s pretty normal. Some times, you solve one
error and many others will be gone with that error.

Besides connecting PMOS source to NWELL, we also need to connect NMOS source to P-substrate. To do
that, you can add via “M1_PSUB”, make it 2 rows and 2 columns, place it under the NMOS and connect
it with NMOS source with “M1 drw”,

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There should be less DRC errors now, check whether there are new errors or not. One common error
here is that the space between polysilicon the gate and the active area in the “M1_PSUB” via has to be
0.05 um, if this is one of the errors, you may just move the via to increase the space. For other errors,
check them one by one and see how you can fix them.

After fixing all the DRC errors, the layout looks like this:

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Next, we need to add pin, power, and ground names to the layout so that the layout can match the
schematic exactly. Remember that your layout should match your schematic in transistor sizes,
connections, pin names, and power & ground names.

The pin name should be on the same layer where you want to place your pin, and for each layer, “drw”
is for wire connections, and “lbl” is for creating labels. For example, if you want to draw a metal1 wire,
you use “M1 drw”, however, if you want to create a gnd label, you will find for the ground connection,
metal 1 is used, so you will use “M1 lbl”.

Press “l”, type “gnd!” for the label name, then choose “Select layer”, select “M1 lbl” which is also called
“Metal1 label” from the drop down list, set the label height to be 0.2, click hide and place the label to
the ground wire.

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Similarly, add label “vdd!”, “In”, “Out”. Check DRC one more time and it’s error free!

Till now, we have finished the layout of an inverter. You may close the DRC check window now.

The next step is to run LVS, which means to compare the layout vs schematic to see whether they match
exactly. It’s an important step in the design to make sure your layout is actually the same and functions
the same as your schematic design.

To run LVS, in the layout editor. Go to PVS -> Run LVS, first set the “Run Data”,

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Then set the “Rules”,

Then the “Input”,

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Then the “Output”,

It will report match once you click “Submit”. Here I purposely added some mismatch by deleting the
“Out” pin in layout, here is the LVS result,

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It shows “Unmatched Schematic Pin Label” and once you click on in, it will show which pins don’t match.
You can then debug the LVS error.

Finally, we have designed the schematic and layout, and also verified that that layout matches design
rules and also matches the schematic. Next, we will extract the parasitic resistors and capacitors from
the layout and then run simulation taking those patristics into consideration.

To extract the layout, in the layout editor, go to Quantus -> Run PVS – Quantus,

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Quantus QRC Parastic Extraction Run Form will open. Now, check the “Setup” tab and make sure the
following circled ones are correct,

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Also set the Extraction tab as below,

Click OK and once it’s done, it will show you a message like this:

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If you go back to Library Manger now, you should be able to see the “av_extracted” view of the inverter
now.

Next, we want to run the post-layout simulation, which means the simulation based on the extracted
layout. To do this, go to library manager, File -> New – Cell View, set it as below,

Click OK and the “New Configuration” window will pop up, set the view to be “schematic”, click “Use
Template”, choose “AMS” and click OK, this is the correct setting,

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Click Ok and the “Virtuoso Hierarchy Editor” pops up, right click on the inverter’s “View Found” , Set Cell
View to be “av_extracted”,

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Leave the “Virtuoso Hierarchy Editor” open, go to Library Manager and open the “config” view of the
“inverter_tb” by double clicking it.

It looks exactly the same with the schematic view of your “inverter_tb”, but when you check the sub-
circuit of the inverter symbol by pressing “e”, the circuit is actually the extracted layout with resistors
and capacitors,

You can launch ADE, run the simulation, calculate the rise time, fall time, delay time and power just like
you did on the schematic. Compare the difference.

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